Imaging device and electronic equipment

Abstract

[Problem] To provide an imaging device and an electronic apparatus that can be downsized and are capable of high-speed readout, and with which degradation of captured images does not occur. [Solution] The imaging device comprises a pixel for outputting a photoelectrically converted signal that corresponds to the incident light quantity, and a comparator for comparing the photoelectrically converted signal with a reference signal. The comparator is provided with a differential circuit for outputting a signal that corresponds to a signal difference between the photoelectrically converted signal and the reference signal, and a differential control circuit for setting an operation point of the differential circuit within a signal reset period before the operation to compare the photoelectrically converted signal with the reference signal begins.

Description

Technical Field

[0001] The present disclosure relates to an imaging device and an electronic device.

Background Art

[0002] There is known an imaging device using a column AD method in which pixel signals photoelectrically converted by a plurality of pixels arranged in the column direction are AD-converted in column units. In an imaging device using the column AD method, after a photoelectric conversion signal photoelectrically converted by a photodiode is transferred to a floating diffusion (hereinafter, FD), it is generally converted into a voltage signal by a source follower circuit and input to an AD converter through a signal line extending in the column direction.

[0003] However, since the source follower circuit has a long settling time, it takes time for the voltage level on the signal line to stabilize, making it difficult to perform high-speed reading.

[0004] In order to achieve high-speed reading, a method has been proposed in which a photoelectric conversion signal is read out and AD-converted without using a source follower circuit (see Patent Document 1).

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In the method of Patent Document 1, a differential circuit is formed by a transistor that amplifies the photoelectric conversion signal transferred to FD and another transistor to which a ramp wave voltage is input, and conversion into a voltage signal is performed based on a signal corresponding to the difference in current flowing through these transistors.

[0007] However, because the transistor characteristics and FD voltage levels within each pixel vary from pixel to pixel, generating a voltage signal using the differential circuit described above can cause fluctuations in the voltage level, potentially leading to degradation of the captured image.

[0008] Therefore, this disclosure provides an imaging device and electronic equipment that are miniaturized, enable low power consumption and high-speed readout, and do not cause degradation of captured images. [Means for solving the problem]

[0009] To solve the above problems, according to this disclosure, a pixel that outputs a photoelectric conversion signal corresponding to the amount of incident light, The system includes a comparator that compares the photoelectric conversion signal with a reference signal, The aforementioned comparator is A differential circuit that outputs a signal corresponding to the signal difference between the photoelectric conversion signal and the reference signal, An imaging device is provided, comprising a differential control circuit that sets the operating point of the differential circuit within a signal reset period before the comparison operation between the photoelectric conversion signal and the reference signal begins.

[0010] The comparator has a first current source connected to the differential circuit, The pixel has a first transistor that generates a current corresponding to the photoelectric conversion signal, The differential circuit has a second transistor that generates a current corresponding to the reference signal, The differential circuit outputs a signal corresponding to the difference between the current flowing through the first transistor and the current flowing through the second transistor. The first current source may supply a current that is the sum of the current flowing through the first transistor and the current flowing through the second transistor.

[0011] The differential circuit includes a third transistor that is cascode-connected to the first transistor and turns on when reading out the pixel to be read out. The first current source may supply a current that is the sum of the currents flowing through the first transistor and the third transistor and the current flowing through the second transistor.

[0012] The differential control circuit is The system includes a second current source and a third current source connected in series between a first reference voltage node and a second reference voltage node. The second current source has a fourth transistor and a fifth transistor that are cascode-connected between the first reference voltage node and the input node of the third current source. The connection nodes of the fourth and fifth transistors may be connected to the second transistor.

[0013] The differential control circuit has an output node that outputs a signal corresponding to the signal difference from the connection nodes of the second current source and the third current source, The differential control circuit may use negative feedback control to control the voltage level of the output node during the signal reset period.

[0014] The comparator has a sixth transistor that switches whether or not to short-circuit the gate of the second transistor and the output node. The sixth transistor may be turned on during the signal reset period to short-circuit the gate of the second transistor and the output node.

[0015] A capacitor is connected between the gate of the second transistor and the input node of the reference signal, While the sixth transistor is turned on, the input node of the reference signal may be set to a predetermined voltage level.

[0016] The gate voltages of the fourth and fifth transistors may be adjusted so that the voltage level of the output node reaches a predetermined voltage level within the signal reset period.

[0017] The voltage levels of the gate voltages of the fourth transistor and the fifth transistor may be maintained after the setting of the operating point.

[0018] The gate voltages of the fourth transistor and the fifth transistor may be set to voltage levels at which the fourth transistor and the fifth transistor operate in a saturation state.

[0019] Both the fourth transistor and the fifth transistor are P-type MOS transistors, The gate of the fifth transistor may be set to a lower voltage level than the gate of the fourth transistor.

[0020] A seventh transistor and an eighth transistor that are cascode-connected between the first reference voltage node and the second reference voltage node are provided, A predetermined bias signal is supplied to the gate of the seventh transistor, The output node may be connected to the gate of the eighth transistor.

[0021] A ninth transistor that is connected in parallel with the fourth transistor and is cascode-connected to the second transistor may be provided.

[0022] When the gate voltage of the first transistor decreases, the gate voltage of the ninth transistor may be adjusted so that the same current as that before the gate voltage of the first transistor decreases flows through the first current source.

[0023] A tenth transistor that is connected in parallel with the second transistor is provided, The output node may be connected to the gate of the tenth transistor.

[0024] The differential circuit may compare the sum of the currents flowing through the plurality of first transistors provided in the plurality of pixels with the current flowing through the second transistor and output a signal corresponding to the signal difference.

[0025] The system includes a selector that selects at least one of the multiple first transistors provided within the multiple pixels, The differential circuit may compare the sum of the currents flowing through the first transistor selected by the selector with the current flowing through the second transistor and output a signal corresponding to the signal difference.

[0026] A first substrate on which a plurality of the aforementioned pixels are arranged, The system may also include a second substrate laminated on the first substrate, on which the comparator is arranged.

[0027] A pixel having a photoelectric conversion element and an amplification transistor, A differential circuit comprising the aforementioned amplification transistor, a first transistor that receives a reference signal, and a first current source, A second current source and a third current source are connected in series between the first reference voltage node and the second reference voltage node, It has a second transistor provided between the second current source and the third current source, The node between the second current source and the second transistor may be connected to the first transistor.

[0028] According to this disclosure, a solid-state imaging device that outputs an imaging pixel signal obtained by photoelectric conversion at multiple pixels, An electronic device comprising a signal processing device that performs signal processing based on the aforementioned image pixel signal, The solid-state imaging device is It includes a comparator that compares a photoelectric conversion signal with a reference signal, The aforementioned comparator is A differential circuit that outputs a signal corresponding to the signal difference between the photoelectric conversion signal and the reference signal, An electronic device is provided, comprising a differential control circuit that sets the operating point of the differential circuit within a signal reset period before the comparison operation between the photoelectric conversion signal and the reference signal begins. [Brief explanation of the drawing]

[0029] [Figure 1] A block diagram showing one embodiment of an imaging device to which this technology is applied. [Figure 2] A circuit diagram showing an example of the internal configuration of a pixel located in the pixel section. [Figure 3] A circuit diagram showing an example of the internal configuration of the comparator in Figure 1. [Figure 4] Circuit diagram of the comparator with an added initialization circuit for initializing the voltage level of output node n1 in Figure 3. [Figure 5] Figure 3 shows the operating timing diagram of the comparator. [Figure 6] Circuit diagram of a comparator based on one comparative example. [Figure 7] Circuit diagram of the first modified example of the comparator shown in Figure 3. [Figure 8] Circuit diagram of the second modified example of the comparator shown in Figure 3. [Figure 9] Circuit diagram of the third modified example of the comparator shown in Figure 3. [Figure 10] Circuit diagram of the fourth modified example of the comparator shown in Figure 3. [Figure 11] Circuit diagram of the imaging device equipped with the comparator shown in Figure 9. [Figure 12A] Layout diagram of the first circuit board. [Figure 12B] Layout diagram of the second circuit board. [Figure 13] A block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system. [Figure 14] A diagram showing an example of the installation location of the imaging unit. [Modes for carrying out the invention]

[0030] The following description will focus on the main components of the imaging device and electronic equipment, but there may be components and functions that are not shown or described. The following description does not exclude any components or functions that are not shown or described.

[0031] <Example of image sensor configuration> Figure 1 is a block diagram showing one embodiment of an imaging device 100 to which this technology is applied.

[0032] The imaging device 100 includes a pixel unit 101, a timing control circuit 102, a vertical scanning circuit 103, a DAC (digital-to-analog converter) 104, an ADC (analog-to-digital converter) group 105, a horizontal transfer scanning circuit 106, an amplifier circuit 107, and a signal processing circuit 108.

[0033] The pixel section 101 has a matrix arrangement of unit pixels (hereinafter simply referred to as pixels) that include a photoelectric conversion element that converts incident light into an electric charge corresponding to the amount of light. The specific circuit configuration of the unit pixels will be described later with reference to Figure 2. In addition, for each row of the matrix-like pixel array in the pixel section 101, pixel drive lines 109 are wired along the left-right direction in the figure (the pixel array direction of the pixel row / horizontal direction), and vertical signal lines 110 are wired along the up-down direction in the figure (the pixel array direction of the pixel column / vertical direction). One end of each pixel drive line 109 is connected to the output terminal of the vertical scanning circuit 103 corresponding to each row. In Figure 1, one pixel drive line 109 is shown for each pixel row, but two or more pixel drive lines 109 may be provided for each pixel row.

[0034] The timing control circuit 102 includes a timing generator (not shown) that generates various timing signals. Based on control signals provided from an external source, the timing control circuit 102 controls the drive of the vertical scanning circuit 103, DAC 104104, ADC group 105, and horizontal transfer scanning circuit 106, etc., based on the various timing signals generated by the timing generator.

[0035] The vertical scanning circuit 103 is composed of components such as a shift register and an address decoder. While the specific configuration is not shown in the diagram here, the vertical scanning circuit 103 includes both a read-out scanning system and a sweep-out scanning system.

[0036] The readout scanning system performs a sequential selective scan of each unit pixel in a row, from which the signal is read out. On the other hand, the sweep scanning system performs a sweep scan on each readout row, preceding the readout scan by the shutter speed, to sweep out (reset) unwanted charges from the photoelectric conversion elements of the unit pixels in that readout row. This sweeping out (resetting) of unwanted charges by the sweep scanning system performs what is known as an electronic shutter operation. Here, electronic shutter operation refers to the operation of discarding the photoelectric charge of the photoelectric conversion element and starting a new exposure (starting the accumulation of photoelectric charge). The signal read out by the readout operation of the readout scanning system corresponds to the amount of light incident since the previous readout operation or electronic shutter operation. The period from the readout timing of the previous readout operation or the sweep timing of the electronic shutter operation to the readout timing of the current readout operation becomes the photoelectric charge accumulation time (exposure time) at the unit pixel.

[0037] The pixel signal VSL output from each unit pixel of the pixel row selected and scanned by the vertical scanning circuit 103 is supplied to the ADC group 105 via the vertical signal line 110 of each column.

[0038] DAC104 generates a reference signal RAMP, which is a linearly increasing ramp waveform signal, and supplies it to ADC group 105.

[0039] The ADC group 105 comprises comparators 121-1 to 121-n, counters 122-1 to 122-n, and latches 123-1 to 123-n. Hereafter, when it is not necessary to distinguish between comparators 121-1 to 121-n, counters 122-1 to 122-n, and latches 123-1 to 123-n, they will simply be referred to as comparator 121, counter 122, and latch 123.

[0040] The comparator 121, counter 122, and latch 123 are each provided one at a time for each row of the pixel section 101, thus constituting an ADC. In other words, the ADC group 105 has an ADC for each row of the pixel section 101.

[0041] The comparator 121 compares the pixel signal VSL output from each pixel with the reference signal RAMP and supplies an output signal indicating the comparison result to the counter 122.

[0042] Based on the output signal of comparator 121, counter 122 converts an analog pixel signal into a digital pixel signal represented by a count value by counting the time until the signal obtained by adding the pixel signal VSL and the reference signal RAMP via a capacitor exceeds a predetermined reference voltage. Counter 122 supplies the count value to latch 123.

[0043] Latch 123 holds the count value supplied from counter 122. Latch 123 also performs CDS (Correlated Double Sampling) by taking the difference between the D-phase count value corresponding to the signal level pixel signal and the P-phase count value corresponding to the reset level pixel signal.

[0044] The horizontal transfer scanning circuit 106 is composed of a shift register, an address decoder, and the like, and sequentially selects and scans the circuit portions corresponding to the pixel rows of the ADC group 105. Through this selective scanning by the horizontal transfer scanning circuit 106, the digital pixel signals held in the latch 123 are sequentially transferred to the amplifier circuit 107 via the horizontal transfer line 111.

[0045] The amplifier circuit 107 amplifies the digital pixel signal supplied from the latch 123 and supplies it to the signal processing circuit 108.

[0046] The signal processing circuit 108 performs predetermined signal processing on the digital pixel signals supplied from the amplifier circuit 107 to generate two-dimensional image data. For example, the signal processing circuit 108 may correct vertical line defects or point defects, clamp the signal, or perform digital signal processing such as parallel-to-serial conversion, compression, encoding, addition, averaging, and intermittent operation. The signal processing circuit 108 outputs the generated image data to a subsequent device.

[0047] <Example of pixel configuration> Figure 2 is a circuit diagram showing an example of the internal configuration of a pixel 150 provided in the pixel section 101.

[0048] Pixel 150 includes a photoelectric conversion element and a readout circuit. The photoelectric conversion element is, for example, a photodiode 151. The readout circuit includes, for example, a transfer transistor 152, an amplification transistor 154, a selection transistor 155, and a reset transistor 156. Figure 2 shows an example in which these transistors are made up of N-type MOS transistors.

[0049] The photodiode 151 converts incident light into an amount of electric charge (in this case, electrons) corresponding to the amount of light.

[0050] The transfer transistor 152 is connected between the photodiode 151 and the FD (floating diffusion) 153. When the transfer transistor 152 is turned on by the drive signal TX supplied from the vertical scanning circuit 103, it transfers the charge stored in the photodiode 151 to the FD 153.

[0051] The gate of the amplification transistor 154 is connected to FD153. The amplification transistor 154 is connected to the vertical signal line 110 via the selection transistor 155 and, together with the current source 157 outside the pixel unit 101, forms a source follower circuit. When the selection transistor 155 is turned on by the drive signal SEL supplied from the vertical scanning circuit 103, the amplification transistor 154 amplifies the potential of FD153 and outputs a pixel signal indicating a voltage corresponding to that potential to the vertical signal line 110. The pixel signals output from each pixel 150 are then supplied to each comparator 121 of the ADC group 105 via the vertical signal line 110.

[0052] In this embodiment, as will be described later, the amplifying transistor 154 and the selecting transistor 155 are used as part of the comparator 121, thereby eliminating the need for the current source 157 and the source follower circuit.

[0053] The reset transistor 156 is connected between the power supply VDD and FD153. When the reset transistor 156 is turned on by the drive signal RST supplied from the vertical scanning circuit 103, the potential of FD153 is reset to the potential of the power supply VDD.

[0054] <Example of comparator configuration> Figure 3 is a circuit diagram showing an example of the internal configuration of the comparator 121 in Figure 1. The comparator 121 in Figure 3 has a differential circuit 11 and a differential control circuit 12.

[0055] The differential circuit 11 outputs a signal corresponding to the signal difference between the photoelectric conversion signal and the reference signal. The photoelectric conversion signal is the signal obtained by amplifying the potential of FD153 with the amplification transistor 154. The specific circuit configuration of the differential circuit 11 will be described later.

[0056] The differential control circuit 12 sets the operating point of the differential circuit 11 during the signal reset period before starting the comparison operation between the photoelectric conversion signal and the reference signal.

[0057] The differential circuit 11 outputs a signal corresponding to the difference in current flowing through the first transistor Q1 and the second transistor Q2, which constitute the differential pair. The first transistor Q1 is the amplification transistor 154 within the pixel 150. In a typical pixel 150, as shown in Figure 2, a selection transistor (third transistor Q3) 155 is cascode-connected to the amplification transistor 154. Therefore, the differential circuit 11 outputs a signal corresponding to the difference between the current flowing through the first transistor Q1 and the third transistor Q3 and the current flowing through the second transistor Q2. A reference signal is supplied to the gate of the second transistor Q2 via capacitor C1.

[0058] Thus, the differential circuit 11 according to this embodiment directly compares the currents flowing through the amplification transistor 154 and the selection transistor 155 within the pixel 150 with the current flowing through the second transistor Q2, to which the reference signal is supplied to the gate. This expands the dynamic range and enables high-speed readout compared to the case where the current flowing through the first transistor Q1 is converted into a voltage signal by a source follower circuit before being compared with the reference signal. This effect will be described in detail later.

[0059] The comparator 121 in Figure 3 has a first current source 13 connected to the differential circuit 11. The first current source 13 carries the sum of the current flowing through the first transistor Q1 and the current flowing through the second transistor Q2. The first current source 13 is, for example, an N-type MOS transistor. A bias signal BIAS_N1 is supplied to the gate of this transistor. By controlling the voltage of the bias signal BIAS_N1, the total amount of current flowing through the first transistor Q1 and the second transistor Q2 in the differential circuit 11 can be adjusted.

[0060] The differential control circuit 12 has a second current source 14 and a third current source 15 connected in series between the power supply voltage node (first reference voltage node) VDDH and the ground node (second reference voltage node). The second current source 14 has a fourth transistor Q4 and a fifth transistor Q5 cascode-connected between the power supply voltage node VDDH and the output node n1 of the comparator 121. The fourth transistor Q4 and the fifth transistor Q5 are, for example, P-type MOS transistors. A bias signal BIAS_P1 is supplied to the gate of the fourth transistor Q4, and a bias signal BIAS_P2 is supplied to the gate of the fifth transistor Q5.

[0061] The connection node between the fourth transistor Q4 and the fifth transistor Q5 is connected to the drain of the second transistor Q2. The current flowing through the second current source 14 is determined taking into account the characteristics of the pixel 150 and the variations of each transistor within the pixel 150. In this embodiment, when the signal is reset, the signal voltage of the output node n1 of the comparator 121 is negatively feedback controlled to adjust the bias signals BIAS_P1 and BIAS_P2 of the fourth transistor Q4 and the fifth transistor Q5 so that the output node n1 of the comparator 121 reaches a desired voltage level.

[0062] Furthermore, the bias signals BIAS_P1 and BIAS_P2 are set to voltage levels such that the fourth transistor Q4 and the fifth transistor Q5 operate in a saturated state. The method for setting the bias signals BIAS_P1 and BIAS_P2 will be described later.

[0063] In Figure 3, the connection node n1 between the second current source 14 and the third current source 15 is the output node n1 of the comparator 121. However, a circuit to increase the gain may be connected to the connection node n1 between the second current source 14 and the third current source 15, and this connection node n1 may not necessarily be the output node n1 of the comparator 121. However, in this specification, the connection node between the second current source 14 and the third current source may be referred to as the output node n1 of the comparator 121.

[0064] The third current source 15 has, for example, an N-type MOS transistor. This transistor is connected between the output node n1 of the comparator 121 and the ground node. A bias signal BIAS_N2 is supplied to the gate of this transistor.

[0065] The comparator 121 has a sixth transistor Q6 that switches whether or not to short-circuit the gate of the second transistor Q2 with the output node n1 of the comparator 121. The sixth transistor Q6 is, for example, a P-type MOS transistor. An AZP signal is supplied to the gate of the sixth transistor Q6. The AZP signal temporarily goes low when the signal is reset. When the AZP signal goes low, the sixth transistor Q6 turns on, and the gate of the second transistor Q2 is short-circuited with the output node n1 of the comparator 121. When the sixth transistor Q6 is turned on, the operation to set the operating point of the differential circuit 11 is performed.

[0066] The comparator 121 in this embodiment performs an operation to compare the signal with a reference signal when a signal reset is performed without photoelectric conversion (P-phase operation), and then performs an operation to compare the photoelectric conversion signal with the reference signal (D-phase operation).

[0067] Figure 4 is a circuit diagram of comparator 121 with an added initialization circuit 20 for initializing the voltage level of output node n1 in Figure 3. The initialization circuit 20 in Figure 4 has, for example, an N-type MOS transistor, and the initialization signal PAC is supplied to the gate of this transistor. When the initialization signal PAC becomes high logic, the initialization circuit 20 sets the voltage VOU1 of output node n1 to the initialization potential.

[0068] Figure 5 is an operation timing diagram of the comparator 121 in Figures 3 and 4. The operation of the comparator 121 in Figures 3 and 4 will be explained below with reference to Figure 5. First, time t1 to t3 is the signal reset period. During this period, the DAC 104 outputs a reference signal at a predetermined voltage level. Also, as shown in Figure 2, during the signal reset period, the reset transistor in the pixel 150 turns on and then off, and the FD 153 is fixed at the reset potential.

[0069] During the period from time t1 to t2, the AZP signal becomes low. This turns on the sixth transistor Q6, and the gate of the second transistor Q2 becomes at the same potential as the output node n1 of the comparator 121. During the period from time t1 to t2, the operating point of the differential circuit 11 is set. More specifically, negative feedback control is performed by adjusting the bias signals BIAS_P1 and BIAS_P2 of the fourth transistor Q4 and the fifth transistor Q5 so that the output node n1 of the comparator 121 reaches a predetermined voltage level. At this time, the bias signals BIAS_P1 and BIAS_P2 are adjusted so that the fourth transistor Q4 and the fifth transistor Q5 operate in the saturation region. This sets the operating point of the differential circuit 11. The voltage levels of the bias signals BIAS_P1 and BIAS_P2 corresponding to the set operating point are held in a capacitance not shown. From time t2 onward, comparator 121 performs a comparison operation between the photoelectric conversion signal and the reference signal. While comparator 121 is performing this comparison operation, the bias signals BIAS_P1 and BIAS_P2 are maintained at the voltage levels set during the period from time t1 to t2.

[0070] At time t2, when the AZP signal reaches a high level, the sixth transistor Q6 turns off. Therefore, from time t2 onward, the gate voltage of the second transistor Q2 becomes a voltage that changes according to the voltage level of the reference signal.

[0071] At time t3, the initialization signal PAC goes high logic, and the voltage VOU1 at output node n1 drops to the initialization potential. Also, DAC104 raises the reference signal to the initial voltage level and holds that voltage level until time t4. As a result, the current flowing through the second transistor Q2 in the differential circuit 11 becomes greater than the current flowing through the first transistor Q1, and the voltage at output node n1 of comparator 121 drops.

[0072] DAC104 continuously or stepwise lowers the voltage level of the reference signal between times t4 and t6. Between times t4 and t6, pixel 150 has not yet performed photoelectric conversion, and FD153 maintains its reset potential. Between times t4 and t5, the voltage level of the reference signal is higher than the reset potential of FD153, so the current flowing through the second transistor Q2 in the differential circuit 11 is greater than the current flowing through the first transistor Q1, and the output node n1 of comparator 121 maintains a low potential. When the voltage level of the reference signal crosses the reset potential at time t5, from time t5 onward, the current flowing through the first transistor Q1 in the differential circuit 11 becomes greater than the current flowing through the second transistor Q2. As a result, the output node n1 of comparator 121 transitions from a low potential to a high potential.

[0073] The counter 122 counts the time from time t4, when the voltage level of the reference signal begins to decrease, to time t5, when the potentials of the reference signal and FD153 intersect. The count value of the counter 122 is held by latch 123. The count value held by latch 123 is the P-phase count value.

[0074] Subsequently, at times t6-t7, the transfer transistor 152 in Figure 2 is turned on by the charge converted photoelectrically by the photodiode 151, causing the FD153 to drop to a potential corresponding to the amount of incident light. Between times t8-t9, the DAC104 raises the reference signal to its initial voltage level, and then from time t9 to time t10, it continuously or stepwise lowers the voltage level of the reference signal. While the voltage level of the reference signal is higher than the voltage level of FD153 (times t9-t10), no current flows through the first transistor Q1 in the differential circuit 11, but current flows through the second transistor Q2. At time t10, when the voltage level of the reference signal crosses the voltage level of FD153, current flows through the first transistor Q1 in the differential circuit 11, but no current flows through the second transistor Q2. As a result, the output node n1 of the comparator 121 is at a low potential between times t8-t10 and at a high potential between times t10-t11.

[0075] The counter 122 counts the time from time t9, when the voltage level of the reference signal begins to decrease, to time t10, when the potentials of the reference signal and FD153 intersect. The count value of the counter 122 is held by latch 123. The count value held by latch 123 is the D-phase count value.

[0076] Latch 123 performs CDS (Cardion-Digital Sequencing) by taking the difference between the P-phase count value and the D-phase count value to generate an AD conversion signal.

[0077] Figure 6 is a circuit diagram of comparator 121z based on one comparative example. Comparator 121z in Figure 6 has a differential amplifier 16 and a current source 17.

[0078] The differential amplifier 16 has transistors Q11 to Q17 and capacitors C11 and C12. Transistors Q11 to Q13 are N-type MOS transistors, and transistors Q14 to Q17 are P-type MOS transistors. Transistors Q11 and Q12 form a differential circuit. Transistor Q13 is a current source connected to the sources of transistors Q11 and Q12. Transistors Q14 and Q15 form a current mirror circuit and are connected to the drains of transistors Q11 and Q12. Transistor Q16 switches whether or not to short-circuit the gate and drain of transistor Q11. Transistor Q17 switches whether or not to short-circuit the gate and drain of transistor Q12. The gate of transistor Q11 is connected to the output node of pixel 150 and the input node of current source 18 via capacitor C11. The gate of transistor Q12 is input to the reference signal RAMP via capacitor C12.

[0079] The current source 17 comprises N-type MOS transistors Q21 to Q23, a capacitor C13, and a constant current source 18. The current source 17 is connected to the selection transistor 155 in the pixel 150, forming a source follower circuit.

[0080] The comparator 121z in Figure 6 has a more complex circuit configuration than the comparator 121 in Figure 3. In particular, the comparator 121z in Figure 6 has a separate transistor Q11 from the amplifying transistor 154 and the selecting transistor 155 in the pixel 150, and outputs a signal corresponding to the difference between the current flowing through transistor Q11 and the current flowing through transistor Q12, to which the reference signal is input to the gate. The comparator 121z in Figure 6 also has a current source 17 connected to the output node of the pixel 150. The amplifying transistor 154 and the selecting transistor 155 in the pixel 150 in Figure 3 are source follower circuits, and it takes time for the potential of the output node of the pixel 150 to stabilize. For this reason, the comparator 121z in Figure 6 must perform the comparison operation after the potential of the output node of the pixel 150 has stabilized, making high-speed operation difficult. In addition, because the circuit configuration of the comparator 121z in Figure 6 is more complex than that of the comparator 121 in Figure 3, the circuit area cannot be reduced and power consumption increases. Furthermore, in comparator 121z shown in Figure 6, the dynamic range is narrowed because transistors Q14 and Q15 connected to the power supply voltage node are P-type MOS transistors.

[0081] Thus, the comparator 121 in Figure 3 can operate at higher speeds, be made smaller, and achieve lower power consumption compared to the comparator 121z in Figure 6. Various modifications to the circuit configuration of the comparator 121 in Figure 3 are possible.

[0082] (First modified example of comparator 121) Figure 7 is a circuit diagram of the first modified version of comparator 121 in Figure 3. Comparator 121a in Figure 7 has an output amplifier 21 in addition to the circuit configuration of comparator 121 in Figure 3. The output amplifier 21 has, for example, a seventh transistor Q7 and an eighth transistor Q8 that are cascode-connected between a power supply voltage node VDDH and a ground node. A bias signal BIAS_P3 is supplied to the gate of the seventh transistor Q7, and the drain of the fifth transistor Q5 is connected to the gate of the eighth transistor Q8. The output amplifier 21 is a common-source circuit and can increase the gain of the signal output from the drain of the fifth transistor Q5. The output voltage VOUT2 of comparator 121a is input to a counter 122, which is a digital circuit (logic circuit). By outputting a signal with increased gain from the output amplifier 21, a signal at the allowable input level of the digital circuit (logic circuit) can be input to the counter 122.

[0083] (Second modified example of comparator 121) When photographing a subject with a white pattern on a black background, it is possible to obtain an image that includes streaking, where white lines appear to stand out on the black background.

[0084] Figure 8 is a circuit diagram of a second modified example of comparator 121 in Figure 3, showing a circuit configuration that prevents streaking when imaging a subject with a white pattern on a black background.

[0085] Comparator 121b in Figure 8 has a ninth transistor Q9 in addition to the circuit configuration in Figure 2. The ninth transistor Q9 is, for example, an N-type MOS transistor. The ninth transistor Q9 is connected in parallel with the fourth transistor Q4 and is also cascode-connected to the second transistor Q2. That is, the ninth transistor Q9 and the second transistor Q2 are cascode-connected between the power supply voltage node and the input node n2 of the first current source 13. A bias signal BIAS_N3 is supplied to the gate of the ninth transistor Q9.

[0086] When starting D-phase photoelectric conversion after signal reset, if a bright pixel 150 is photoelectrically converted, the potential of FD153 drops significantly, reducing the current flowing through the first transistor Q1 of the differential circuit 11 in comparator 121b in Figure 8. The differential circuit 11 operates so that the current flowing through the first current source 13 is always constant. Therefore, it attempts to increase the current flowing through the second transistor Q2 by the amount by which the current flowing through the first transistor Q1 decreases. However, since the voltage levels of the bias signals BIAS_P1 and BIAS_P2 supplied to the gate voltages of the fourth transistor Q4 and fifth transistor Q5 are kept constant, it is not possible to compensate for the decrease in the current flowing through the first transistor Q1, resulting in streaking. Therefore, a ninth transistor Q9 is newly provided so that current can flow from the power supply voltage node through the ninth transistor Q9 to the first current source 13. This makes it possible to keep the current flowing from the power supply voltage node to the first current source 13 always constant, and suppresses streaking when imaging subjects with a white pattern on a black background.

[0087] (Third modified example of comparator 121) Figure 9 is a circuit diagram of a third modified example of comparator 121 in Figure 3, showing a circuit configuration that prevents streaking when imaging a subject with a black pattern on a white background.

[0088] Comparator 121c in Figure 9 has a 10th transistor Q10 in addition to the circuit configuration in Figure 2. The 10th transistor Q10 is connected in parallel with the 2nd transistor Q2. The 10th transistor Q10 is, for example, an N-type MOS transistor. The drain of the 10th transistor Q10 is connected to the connection node n3 of the 4th transistor Q4 and the 5th transistor Q5. The source of the 10th transistor Q10 is connected to the input node n2 of the 1st current source 13. The gate of the 10th transistor Q10 is connected to the output node n1 of comparator 121c (or the drain of the 5th transistor Q5).

[0089] When switching from acquiring P-phase count values ​​to acquiring D-phase count values, if the potential of FD153 is high, a large current flows to the first transistor Q1. The voltage level of the reference signal decreases over time, and when the voltage level of the reference signal falls below the potential of FD153, almost no current flows to the second transistor Q2, and most of the current flows to the first transistor Q1. In this case, the voltage level of the power supply voltage node on the pixel 150 side may cause a voltage drop due to IR (hereinafter referred to as IR drop).

[0090] The comparator 121c in Figure 9 has a tenth transistor Q10 connected in parallel with the second transistor Q2. Therefore, the decrease in current flowing through the second transistor Q2 can be compensated for by the tenth transistor Q10, thereby suppressing the current flowing through the first transistor Q1. Consequently, the IR drop at the power supply voltage node on the pixel 150 side can be suppressed, and streaking when imaging subjects with a black pattern on a white background can be suppressed.

[0091] (Fourth modified example of comparator 121) The ADC in this embodiment is basically provided for each pixel row in the column direction, but variations such as providing one ADC for each of multiple pixel rows, or performing AD conversion by adding multiple adjacent pixels 150 in the row direction, are conceivable.

[0092] Figure 10 is a circuit diagram of a fourth modified example of comparator 121 in Figure 3. Comparator 121d in Figure 10 compares the photoelectric conversion signal of at least one of a plurality of pixels 150 arranged in a row with a reference signal. Comparator 121d in Figure 10 has a selector 22. The selector 22 is connected between the source of a third transistor Q3 (selection transistor 155) in the differential circuit 11 and the input node of the first current source 13. For each pixel 150, the selector 22 has a plurality of switches SW0, SW1 that switch whether or not to connect the source of the third transistor Q3 in the corresponding pixel 150 to the input node of the first current source 13. This allows the photoelectric conversion signal of any one of the plurality of pixels 150 to be compared with the reference signal, as well as the sum of the photoelectric conversion signals of any two or more of the plurality of pixels 150 to be compared with the reference signal.

[0093] In Figure 10, only one pixel 150 is shown in the column direction, but multiple pixels 150 may be arranged in the column direction. By providing the selector 22 as shown in Figure 10, it is possible to provide fewer comparators 121d than the number of pixel rows in the column direction, thereby reducing the circuit area of ​​the imaging device 100.

[0094] Figure 11 is a circuit diagram of the imaging device 100 equipped with the comparator 121d of Figure 10. The imaging device 100 of Figure 11 is equipped with fewer comparators 121d than the number of pixel rows in the column direction. The pixel section 101 has multiple pixel rows extending in the column direction arranged in the row direction. The comparator 121d has selectors (multiplexers) 22, and each selector 22 can select any one or more pixel rows from the multiple pixel rows arranged in the row direction. The photoelectric conversion signal in the pixel row selected by each selector 22 is compared with a reference signal in the corresponding comparator 121d.

[0095] According to the imaging device 100 in Figure 11, one or more pixel sequences can be selected for each selector 22, and the type of pixel sequence selected by each selector 22 can be arbitrarily set for each selector 22. This allows the object that each comparator 121d compares with the reference signal to be changed for each comparator 121d.

[0096] (Multilayer chips) Each component within the imaging device 100 according to this embodiment can be arranged on multiple substrates, and these substrates may be stacked. Figure 12A is a layout diagram of the first substrate 31, and Figure 12B is a layout diagram of the second substrate 32. The first substrate 31 and the second substrate 32 are stacked together, and various signals are transmitted and received by Cu-Cu junctions, vias, bumps, conductive pads, etc.

[0097] The first substrate 31 in Figure 12A is positioned on the side to which light is incident. The first substrate 31 has a pixel section 101 and a plurality of junctions 33. The junctions 33 have Cu-Cu junctions, vias, bumps, etc., for transmitting and receiving various signals between the first substrate 31 and the second substrate 32. The junctions 33 are positioned around the pixel section 101.

[0098] The second circuit board 32 in Figure 12B contains a timing control circuit 102, a vertical scanning circuit 103, a DAC 104, an ADC 105, a horizontal transfer scanning circuit 106, an amplifier circuit 107, and a signal processing circuit 108. The ADC 105 includes a comparator 121, a counter 122, and a latch 123. Near the signal processing circuit 108, there is an interface section (I / F) 34 for outputting the processed signal and for inputting external signals to various parts of the second circuit board 32.

[0099] Furthermore, multiple pads 35 are provided along the edges of the first substrate 31 and the second substrate 32. Bonding wires are connected to these pads 35 to connect to various parts within each substrate.

[0100] In Figure 3, the first transistor Q1 (amplifier transistor 154) and the third transistor Q3 (selection transistor 155) in the comparator 121 are located in the pixel area 101 on the first substrate 31, while the rest are located in the dashed area on the second substrate 32.

[0101] The arrangement of components on the first substrate 31 and the second substrate 32 is arbitrary, and at least some of the components other than the first transistor Q1 and the third transistor Q3 in the comparator 121 may be placed on the first substrate 31.

[0102] (Effects of this embodiment) Thus, in the imaging device 100 according to this embodiment, the operating point of the differential circuit 11 is set during the signal reset period before the comparison operation between the photoelectric conversion signal and the reference signal is started, and a reference signal whose voltage level changes based on the operating point is supplied to the differential circuit 11. More specifically, during the signal reset period, the gate of the second transistor Q2 to which the reference signal is supplied to the gate is short-circuited with the output node n1 of the comparator 121, and the voltage level of the output node is negatively feedback controlled to adjust and maintain the bias signals BIAS_P1 and BIAS_P2 of the fourth transistor Q4 and the fifth transistor Q5 that constitute the second current source 14 connected to the output node. As a result, when the photoelectric conversion operation is started thereafter, the comparison operation by the comparator 121 can be performed without depending on the characteristics and variations of the pixels 150, and degradation of the image quality of the captured image can be suppressed.

[0103] Furthermore, the comparator 121 outputs a signal corresponding to the difference between the current flowing through the amplifying transistor 154 (first transistor Q1) in the pixel 150 and the current flowing through the second transistor Q2, to which the reference signal is supplied to the gate. This allows the comparator 121 to perform comparison operations at high speed, and the photoelectric conversion signal to be read out at high speed. In particular, in the imaging device 100 according to this disclosure, the output of the source follower circuit in the pixel 150 is not input to the comparator 121, and the current flowing through the amplifying transistor 154 (first transistor Q1) is directly compared with the current flowing through the second transistor Q2. This eliminates the problem of not being able to perform comparison operations until the output voltage of the source follower circuit stabilizes, thus enabling high-speed operation. In addition, conventional pixels 150 were equipped with a current source connected to the source follower circuit, but this current source is also unnecessary, allowing for a simpler internal configuration of the imaging device 100 compared to conventional devices, resulting in miniaturization and lower power consumption.

[0104] <Examples of applications to mobile devices> The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein may be implemented as a device mounted on any type of mobile vehicle, such as an automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility device, airplane, drone, ship, or robot.

[0105] Figure 13 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0106] The vehicle control system 12000 comprises multiple electronic control units connected via a communication network 12001. In the example shown in Figure 13, the vehicle control system 12000 includes a drivetrain control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0107] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0108] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0109] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0110] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0111] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0112] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking system based on information from inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0113] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0114] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0115] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 13, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0116] Figure 14 shows an example of the installation position of the imaging unit 12031. In Figure 14, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0117] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0118] Figure 14 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0119] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels 150 for phase difference detection.

[0120] For example, the microcomputer 12051, based on distance information obtained from imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to vehicle 12100). In particular, it can extract the nearest object on the vehicle 12100's path that is traveling in approximately the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0121] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, heavy vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0122] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0123] The above describes an example of a vehicle control system to which the technology described herein may be applied. The technology described herein may be applied to the imaging unit 12031 of the configuration described above. By applying the technology described herein to the imaging unit 12031, a display with superior display quality can be obtained, resulting in easier-to-view captured images and reducing driver fatigue.

[0124] Furthermore, this technology can take the following configuration. (1) A pixel that outputs a photoelectric conversion signal corresponding to the amount of incident light, The system includes a comparator that compares the photoelectric conversion signal with a reference signal, The aforementioned comparator is A differential circuit that outputs a signal corresponding to the signal difference between the photoelectric conversion signal and the reference signal, An imaging device comprising: a differential control circuit that sets the operating point of the differential circuit within a signal reset period before starting the comparison operation between the photoelectric conversion signal and the reference signal. (2) The comparator has a first current source connected to the differential circuit, The pixel has a first transistor that generates a current corresponding to the photoelectric conversion signal, The differential circuit has a second transistor that generates a current corresponding to the reference signal, The differential circuit outputs a signal corresponding to the difference between the current flowing through the first transistor and the current flowing through the second transistor. The imaging apparatus according to (1), wherein the first current source supplies a current obtained by adding the current flowing through the first transistor and the current flowing through the second transistor. (3) The differential circuit includes a third transistor that is cascode-connected to the first transistor and turns on when reading out the pixel to be read out, The imaging apparatus according to (2), wherein the first current source supplies a current obtained by adding the currents flowing through the first transistor and the third transistor and the current flowing through the second transistor. (4) The differential control circuit is The system includes a second current source and a third current source connected in series between a first reference voltage node and a second reference voltage node. The second current source has a fourth transistor and a fifth transistor that are cascode-connected between the first reference voltage node and the input node of the third current source. The imaging apparatus according to (2) or (3), wherein the connection nodes of the fourth transistor and the fifth transistor are connected to the second transistor. (5) The differential control circuit has an output node that outputs a signal corresponding to the signal difference from the connection nodes of the second current source and the third current source, The imaging apparatus according to (4), wherein the differential control circuit negatively feedback controls the voltage level of the output node during the signal reset period. (6) The comparator has a sixth transistor that switches whether or not to short-circuit the gate of the second transistor and the output node, The imaging apparatus according to (5), wherein the sixth transistor is turned on during the signal reset period to short-circuit the gate of the second transistor and the output node. (7) A capacitor is connected between the gate of the second transistor and the input node of the reference signal, The imaging apparatus according to (6), wherein while the sixth transistor is turned on, the input node of the reference signal is set to a predetermined voltage level. (8) The imaging apparatus according to any one of (5) to (7), wherein the gate voltages of the fourth transistor and the fifth transistor are adjusted so that the voltage level of the output node becomes a predetermined voltage level during the signal reset period. (9) The imaging apparatus according to (8), wherein the voltage levels of the gate voltages of the fourth transistor and the fifth transistor are held after the setting of the operating point. (10) The imaging apparatus according to (8) or (9), wherein the gate voltages of the fourth transistor and the fifth transistor are set to a voltage level at which the fourth transistor and the fifth transistor operate in a saturated state. (11) Both the fourth transistor and the fifth transistor are P-type MOS transistors, The imaging apparatus according to any one of (8) to (10), wherein the gate of the fifth transistor is set to a lower voltage level than the gate of the fourth transistor. (12) comprising a seventh transistor and an eighth transistor cascode-connected between the first reference voltage node and the second reference voltage node, A predetermined bias signal is supplied to the gate of the seventh transistor. The imaging apparatus according to any one of (5) to (11), wherein the output node is connected to the gate of the eighth transistor. (13) The imaging apparatus according to any one of (5) to (11), further comprising a ninth transistor connected in parallel to the fourth transistor and cascode-connected to the second transistor. (14) The imaging apparatus according to (13), wherein the gate voltage of the 9th transistor is adjusted so that when the gate voltage of the first transistor decreases, the same current as before the gate voltage of the first transistor decreases flows to the first current source. (15) comprising a tenth transistor connected in parallel with the second transistor, The imaging apparatus according to any one of (5) to (14), wherein the output node is connected to the gate of the tenth transistor. (16) The imaging apparatus according to any one of (2) to (15), wherein the differential circuit compares the sum of the currents flowing through a plurality of first transistors provided in a plurality of pixels with the current flowing through the second transistor and outputs a signal corresponding to the signal difference. (17) A selector is provided which selects at least one of the multiple first transistors provided in the multiple pixels, The imaging apparatus according to any one of (2) to (15), wherein the differential circuit compares the sum of the currents flowing through the first transistor selected by the selector with the current flowing through the second transistor and outputs a signal corresponding to the signal difference. (18) A first substrate on which a plurality of the aforementioned pixels are arranged, The imaging apparatus according to (1), comprising: a second substrate laminated on the first substrate and on which the comparator is arranged. (19) A pixel having a photoelectric conversion element and an amplifying transistor, A differential circuit comprising the aforementioned amplification transistor, a first transistor that receives a reference signal, and a first current source, A second current source and a third current source are connected in series between the first reference voltage node and the second reference voltage node, It has a second transistor provided between the second current source and the third current source, The node between the second current source and the second transistor is connected to the first transistor. Imaging device. (20) A solid-state imaging device that outputs an imaging pixel signal obtained by photoelectric conversion at multiple pixels, An electronic device comprising a signal processing device that performs signal processing based on the aforementioned image pixel signal, The solid-state imaging device is It includes a comparator that compares a photoelectric conversion signal with a reference signal, The aforementioned comparator is A differential circuit that outputs a signal corresponding to the signal difference between the photoelectric conversion signal and the reference signal, An electronic device comprising: a differential control circuit that sets the operating point of the differential circuit within a signal reset period before starting the comparison operation between the photoelectric conversion signal and the reference signal.

[0125] The aspects of this disclosure are not limited to the individual embodiments described above, but include various modifications that a person skilled in the art could conceive, and the effects of this disclosure are not limited to those described above. In other words, various additions, modifications, and partial deletions are possible, as long as they do not depart from the conceptual idea and spirit of this disclosure derived from the claims and their equivalents. [Explanation of Symbols]

[0126] 11 Differential circuit, 12 Differential control circuit, 13 First current source, 14 Second current source, 15 Third current source, 16 Differential amplifier, 17 Current source, 18 Current source, 18 Constant current source, 21 Output amplifier, 22 Selector (multiplexer), 31 First board, 32 Second board, 33 Junction, 34 Interface section (I / F), 35 Pad, 100 Imaging device, 101 Pixel section, 102 Timing control circuit, 103 Vertical scanning circuit, 105 ADC group, 105 (Analog-to-digital converter) group, 106 Horizontal transfer scanning circuit, 107 Amplifier circuit, 108 Signal processing circuit, 109 Pixel drive line, 110 Vertical signal line, 111 Horizontal transfer line, 121 Comparator, 121-1 Comparator, 121a Comparator, 121b Comparator, 121c comparator, 121d comparator, 121-n comparator, 121z comparator, 122 counter, 122-1 counter, 122-n counter, 123 latch, 123-1 latch, 123-n latch, 150 pixel, 151 photodiode, 152 transfer transistor, 154 amplification transistor, 155 selection transistor (3rd transistor Q3), 155 selection transistor, 156 reset transistor, 157 constant current source, 12000 vehicle control system, 12001 communication network, 12010 drive system control unit, 12020 body system control unit, 12030 external information detection unit, 12030 body system control unit, 12031 imaging unit, 12040 in-vehicle information detection unit, 12041 driver status detection unit, 12050 Integrated control unit, 12051 microcomputer, 12052 audio / image output unit, 12061 audio speaker, 12062 display unit, 12063 instrument panel, 12100 vehicle, 12101 imaging unit

Claims

1. A pixel that outputs a photoelectric conversion signal corresponding to the amount of incident light, The system includes a comparator that compares the photoelectric conversion signal with a reference signal, The aforementioned comparator is A differential circuit that outputs a signal corresponding to the signal difference between the photoelectric conversion signal and the reference signal, A differential control circuit that sets the operating point of the differential circuit during a signal reset period before the comparison operation between the photoelectric conversion signal and the reference signal begins, Equipped with, The differential control circuit is A second current source and a third current source are connected in series between the first reference voltage node and the second reference voltage node, The system includes an output node that outputs a signal corresponding to the signal difference from the connection nodes of the second current source and the third current source, The second current source has two transistors that are cascode-connected between the first reference voltage node and the connection node of the third current source. The connection nodes of the two transistors are connected to the comparator. The differential control circuit, during the signal reset period, negatively feedbacks the signal voltage of the output node and adjusts the gate voltages of the two transistors so that the output node reaches a predetermined voltage level. Imaging device.

2. A pixel that outputs a photoelectric conversion signal corresponding to the amount of incident light, The system includes a comparator that compares the photoelectric conversion signal with a reference signal, The aforementioned comparator is A differential circuit that outputs a signal corresponding to the signal difference between the photoelectric conversion signal and the reference signal, A differential control circuit that sets the operating point of the differential circuit during a signal reset period before the comparison operation between the photoelectric conversion signal and the reference signal begins, Equipped with, The differential control circuit is A second current source and a third current source are connected in series between the first reference voltage node and the second reference voltage node, The system includes an output node that outputs a signal corresponding to the signal difference from the connection nodes of the second current source and the third current source, The comparator has a first current source connected to the differential circuit, The pixel has a first transistor that generates a current corresponding to the photoelectric conversion signal, The differential circuit has a second transistor that generates a current corresponding to the reference signal, The second current source includes a fourth transistor and a fifth transistor cascode-connected between the first reference voltage node and the connection node of the third current source, and a ninth transistor connected in parallel to the fourth transistor and cascode-connected to the second transistor. The connection nodes of the fourth transistor and the fifth transistor are connected to the second transistor. The differential circuit outputs a signal corresponding to the difference between the current flowing through the first transistor and the current flowing through the second transistor. The first current source supplies a current which is the sum of the current flowing through the first transistor and the current flowing through the second transistor. When the gate voltage of the first transistor decreases, the bias voltage applied to the gate of the ninth transistor is adjusted so that the same current flows through the first current source as before the gate voltage of the first transistor decreased. Imaging device.

3. The comparator has a first current source connected to the differential circuit, The pixel has a first transistor that generates a current corresponding to the photoelectric conversion signal, The differential circuit has a second transistor that generates a current corresponding to the reference signal, The differential circuit outputs a signal corresponding to the difference between the current flowing through the first transistor and the current flowing through the second transistor. The first current source supplies a current which is the sum of the current flowing through the first transistor and the current flowing through the second transistor. The imaging apparatus according to claim 1.

4. The differential circuit includes a third transistor that is cascode-connected to the first transistor and turns on when reading out the pixel to be read out. The first current source supplies a current which is the sum of the currents flowing through the first transistor and the third transistor and the current flowing through the second transistor. The imaging device according to claim 3.

5. The two transistors mentioned above are the fourth transistor and the fifth transistor. The connection nodes of the fourth transistor and the fifth transistor are connected to the second transistor. The imaging apparatus according to claim 3 or 4.

6. The comparator has a sixth transistor that switches whether or not to short-circuit the gate of the second transistor and the output node. The sixth transistor is turned on during the signal reset period to short-circuit the gate of the second transistor and the output node. The imaging apparatus according to claim 5.

7. A capacitor is connected between the gate of the second transistor and the input node of the reference signal, While the sixth transistor is on, the input node of the reference signal is set to a predetermined voltage level. The imaging device according to claim 6.

8. The gate voltages of the fourth and fifth transistors are adjusted so that the voltage level of the output node reaches a predetermined voltage level within the signal reset period. The imaging apparatus according to claim 6 or 7.

9. The voltage levels of the gate voltages of the fourth and fifth transistors are maintained after the setting of the operating point. The imaging apparatus according to claim 8.

10. The gate voltages of the fourth and fifth transistors are set to a voltage level at which the fourth and fifth transistors operate in a saturated state. The imaging device according to claim 8 or 9.

11. The fourth and fifth transistors are both P-type MOS transistors. The imaging apparatus according to any one of claims 8 to 10.

12. The system comprises a seventh transistor and an eighth transistor that are cascode-connected between the first reference voltage node and the second reference voltage node, A predetermined bias signal is supplied to the gate of the seventh transistor. The output node is connected to the gate of the eighth transistor. The imaging apparatus according to any one of claims 2 to 11.

13. The device comprises a ninth transistor connected in parallel to the fourth transistor and cascode-connected to the second transistor, The imaging apparatus according to claim 2, or any one of claims 5 to 11.

14. When the gate voltage of the first transistor decreases, the bias voltage applied to the gate of the ninth transistor is adjusted so that the same current flows through the first current source as before the gate voltage of the first transistor decreased. The imaging device according to claim 13.

15. The system includes a tenth transistor connected in parallel to the second transistor, The output node is connected to the gate of the 10th transistor. The imaging apparatus according to any one of claims 2 to 14.

16. The imaging apparatus according to any one of claims 2 to 15, wherein the differential circuit compares the sum of the currents flowing through a plurality of first transistors provided in a plurality of pixels with the current flowing through a second transistor and outputs a signal corresponding to the signal difference.

17. The system includes a selector that selects at least one of the multiple first transistors provided within the multiple pixels, The imaging apparatus according to any one of claims 2 to 15, wherein the differential circuit compares the sum of the currents flowing through the first transistor selected by the selector with the current flowing through the second transistor and outputs a signal corresponding to the signal difference.

18. A first substrate on which a plurality of the aforementioned pixels are arranged, The system comprises a second substrate laminated on the first substrate, on which the comparator is arranged, The imaging apparatus according to claim 1.

19. A pixel having a photoelectric conversion element and an amplification transistor, A differential circuit having the amplification transistor, a first transistor having a gate into which a reference signal is input, and a first current source connected to the amplification transistor and the first transistor, A differential control circuit that sets the operating point of the differential circuit during a signal reset period before starting the comparison operation between the photoelectric conversion signal output from the photoelectric conversion element and the reference signal, A second current source and a third current source are connected in series between the first reference voltage node and the second reference voltage node, A second transistor that switches whether or not to short-circuit the connection nodes of the second current source and the third current source with the reference voltage node, The system includes a third transistor that switches whether or not to short-circuit the connection node and the gate of the first transistor, The differential control circuit is The second current source and the third current source have output nodes that output a signal corresponding to the signal difference between the photoelectric conversion signal and the reference signal, The second current source has a fourth transistor and a fifth transistor that are cascode-connected between the first reference voltage node and the connection node of the third current source. The connection nodes of the fourth transistor and the fifth transistor are connected to the second transistor. The differential control circuit performs negative feedback control during the signal reset period so that the output node reaches a predetermined voltage level. Imaging device.

20. A solid-state imaging device that outputs an imaging pixel signal obtained by photoelectric conversion at multiple pixels, An electronic device comprising a signal processing device that performs signal processing based on the aforementioned image pixel signal, The solid-state imaging device is It includes a comparator that compares a photoelectric conversion signal with a reference signal, The aforementioned comparator is A differential circuit that outputs a signal corresponding to the signal difference between the photoelectric conversion signal and the reference signal, A differential control circuit that sets the operating point of the differential circuit during a signal reset period before the comparison operation between the photoelectric conversion signal and the reference signal begins, Equipped with, The differential control circuit is A second current source and a third current source are connected in series between the first reference voltage node and the second reference voltage node, The system includes an output node that outputs a signal corresponding to the signal difference from the connection nodes of the second current source and the third current source, The second current source has two transistors that are cascode-connected between the first reference voltage node and the connection node of the third current source. The connection nodes of the two transistors are connected to the comparator. The differential control circuit performs negative feedback control during the signal reset period so that the output node reaches a predetermined voltage level. electronic equipment.

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