Degradation suppression circuit

Abstract

To suppress degradation of MOS transistor characteristics due to BTI without causing an increase in circuit scale.SOLUTION: A degradation suppressing circuit 1 for suppressing characteristics degradation of a pair of MOS transistors provided in a differential pair circuit 2 for outputting an output signal corresponding to a difference of a pair of input signals respectively inputted through a non-inverted input terminal and an inverted input terminal comprises a changeover circuit 3. The changeover circuit 3 is capable of changeover between a normal application state in which a first voltage higher by a threshold voltage relative to an intermediate voltage is applied to a gate of a first transistor which is an MOS transistor whose gate is connected to the non-inverted input terminal of the pair of MOS transistors and a second voltage lower by the threshold voltage relative to the intermediate voltage is applied to a gate of a second transistor which is an MOS transistor whose gate is connected to the inverted input terminal of the pair of MOS transistors, and an inverted phase application state in which the second voltage is applied to the gate of the first transistor and the first voltage is applied to the gate of the second transistor.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a deterioration suppression circuit that suppresses deterioration of characteristics of a pair of MOS transistors included in a differential pair circuit that outputs an output signal according to a difference between a pair of input signals.

Background Art

[0002] Conventionally, there has been a differential pair circuit configured using P-channel MOS transistors. In this specification, a P-channel MOS transistor may sometimes be referred to as a PMOS transistor. It is known that a PMOS transistor particularly suffers from characteristic deterioration due to NBTI, specifically, the gate threshold voltage fluctuates. Note that NBTI is an abbreviation for Negative Bias Temperature Instability. Characteristic deterioration due to NBTI occurs during a period when a DC potential difference exists between the gate and the back gate of the MOS transistor, and particularly appears significantly when used at a high temperature for a long time. However, characteristic deterioration due to NBTI does not occur during a period when no DC potential difference exists between the gate and the back gate of the MOS transistor.

[0003] For example, when a receiving circuit of a communication device is configured using a differential pair circuit, if characteristic deterioration of the MOS transistors constituting the differential pair circuit occurs, it may affect the reception operation of the communication signal by the receiving circuit. Therefore, conventionally, various countermeasures against characteristic deterioration due to NBTI of MOS transistors have been devised. Patent Document 1 discloses a differential pair circuit in which an output stage is configured using N-channel MOS transistors, which are less likely to suffer from characteristic deterioration due to NBTI, instead of PMOS transistors, which are more likely to suffer from characteristic deterioration due to NBTI. In this specification, an N-channel MOS transistor may sometimes be referred to as an NMOS transistor.

[0004] Patent Document 2 discloses a differential pair circuit equipped with a control circuit that sets the gate and back gate of a PMOS transistor to the same potential in order to suppress the occurrence of characteristic degradation due to NBTI as much as possible. Patent Document 3 discloses a technique for adjusting the gate threshold voltage fluctuation using a function to adjust the back gate voltage of a finFET configuration. In the following description, the prior art disclosed in Patent Documents 1, 2, and 3 will be referred to as the first prior art, the second prior art, and the third prior art, respectively. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2018-129627 [Patent Document 2] Japanese Patent Publication No. 2012-199664 [Patent Document 3] U.S. Patent No. 8049214 [Overview of the project] [Problems that the invention aims to solve]

[0006] According to the first prior art, while the use of an NMOS transistor makes characteristic degradation due to NBTI less likely, characteristic degradation due to PBTI will occur, although its impact is smaller than that of NBTI. PBTI is an abbreviation for Positive Bias Temperature Instability. Furthermore, in this specification, since both NBTI and PBTI involve fluctuations in the gate threshold voltage during the period when a DC potential difference exists between the gate and back gate of a MOS transistor, they may be collectively referred to as BTI when there is no need to distinguish between them.

[0007] According to the second prior art, it is possible to suppress characteristic degradation due to PBTI by operating the control circuit when the differential pair circuit is not operating to make the gate and back gate of the PMOS transistor at the same potential. However, since the control circuit cannot be operated when the differential pair circuit is operating, some characteristic degradation due to PBTI will inevitably occur. Therefore, with the second prior art, the characteristic degradation due to PBTI may become significant, especially when used for long periods at high temperatures, such as in automotive applications. According to the third prior art, even if the gate threshold voltage fluctuates, adjustments can be made to compensate for these fluctuations. However, the circuit size increases because an analog circuit is required to perform such adjustments.

[0008] This invention has been made in view of the above circumstances, and its purpose is to provide a degradation suppression circuit that can suppress the degradation of MOS transistor characteristics due to BTI without increasing the circuit size. [Means for solving the problem]

[0009] The degradation suppression circuit according to claim 1 is a pair of inputs input via the first input terminal and the second input terminal, respectively. Voltage Degradation of the characteristics of a pair of MOS transistors (Q1, Q2) in a differential pair circuit (2) that outputs an output signal corresponding to the difference. In-phase variation of bias temperature instability fluctuations caused by this fluctuation This is a circuit that suppresses the process and includes a switching circuit (3, 3A, 3B, 3H, 3L) that can switch between a normal application state and a reverse-phase application state. Here, if the MOS transistor whose gate is connected to the first input terminal of the pair of MOS transistors is designated as the first transistor (Q1), and the MOS transistor whose gate is connected to the second input terminal of the pair of MOS transistors is designated as the second transistor (Q2), then the normal application state and the reverse-phase application state are as follows.

[0010] In other words, the normal application state is the first Input terminals to As the aforementioned input voltage Applying the first voltage and the second Input terminals to As the aforementioned input voltageThis is the state in which a second voltage is applied. The reverse-phase application state is the first Input terminals to As the aforementioned input voltage Apply the second voltage and the second Input terminals to As the aforementioned input voltage This is the state in which the first voltage is applied. The first voltage is a voltage that is higher by a predetermined threshold voltage than the intermediate voltage, which is the voltage between the circuit's power supply voltage and a reference potential, and the second voltage is a voltage that is lower by the threshold voltage than the intermediate voltage. The differential pair circuit constitutes the receiving circuit of a communication device that communicates with another device. The pair of input signals are differential communication signals representing transmission data transmitted from the other device. The switching circuit switches between the normal application state and the reverse-phase application state each time it receives one frame of the transmission data.

[0011] In this case, the characteristic degradation of a MOS transistor due to BTI, that is, the BTI fluctuation, is caused by a fluctuation in the gate threshold voltage during the period when a DC potential difference exists between the gate and back gate of the MOS transistor. Therefore, the focus is on the fact that the degradation is improved by creating a reverse bias between the gate and back gate of the MOS transistor. With the above configuration, in addition to the normal application state in which a positive-sequence voltage is applied to the input of the differential pair circuit, a reverse-sequence application state in which an inverse-sequence voltage is applied is provided, thereby canceling out the in-phase fluctuation of the BTI fluctuation.

[0012] In other words, the above configuration makes it possible to minimize the DC potential difference between the gate and back gate of the pair of MOS transistors in the differential pair circuit, thereby suppressing fluctuations in the characteristics of the MOS transistors. Furthermore, in the above configuration, the switching circuit can be switched to an inverse phase applied state even when the differential pair circuit is operating, thus suppressing characteristic degradation due to BTI even when the differential pair circuit is operating. Moreover, since the above configuration does not require an analog circuit like the third prior art, the circuit size can be kept smaller. Therefore, the above configuration provides the excellent effect of suppressing characteristic degradation of MOS transistors due to BTI without increasing the circuit size. [Brief explanation of the drawing]

[0013] [Figure 1] This figure schematically shows the configuration of the degradation suppression circuit and differential pair circuit according to the first embodiment. [Figure 2] This figure shows a specific configuration example of a differential pair circuit according to the first embodiment. [Figure 3]Diagram schematically showing input voltages of differential pair circuits in normal application state and reverse-phase application state according to the first embodiment [Figure 4] Diagram showing a specific first configuration example of the switching circuit according to the first embodiment [Figure 5] Diagram showing a specific second configuration example of the switching circuit according to the first embodiment [Figure 6] Diagram showing a specific first timing example in which the switching circuit according to the first embodiment switches between the normal application state and the reverse-phase application state [Figure 7] Diagram showing a specific second timing example in which the switching circuit according to the first embodiment switches between the normal application state and the reverse-phase application state [Figure 8] Diagram showing a specific third timing example in which the switching circuit according to the first embodiment switches between the normal application state and the reverse-phase application state [Figure 9] Diagram schematically showing input voltages of differential pair circuits according to the comparative example [Figure 10] Diagram schematically showing the configuration of the degradation suppression circuit and the differential pair circuit according to the second embodiment [Figure 11] Diagram showing a specific timing example in which the switching circuit according to the second embodiment switches between the normal application state and the reverse phase state and explaining the operation by the inverter circuit

Embodiments for Carrying Out the Invention

[0016] The degradation suppression circuit 1 includes a switching circuit 3 that can switch between a normal applied state and an inverted phase applied state, and a control circuit 4 that controls the operation of the switching circuit 3. As will be described in detail later, the operation of the switching circuit 3 is controlled based on the signals VSW and VSW bars generated by the control circuit 4. Note that in Figure 1 and other figures, the VSW bar signal is indicated by adding a "-" above VSW. The differential pair circuit 2 outputs an output signal Vout corresponding to the difference between a pair of input signals VinP_i and VinN_i, ​​which are input via a non-inverting input terminal that functions as the first input terminal and an inverting input terminal that functions as the second input terminal. In other words, the differential pair circuit 2 functions as a comparator.

[0017] In this embodiment, the pair of input signals VinP_i and VinN_i are differential communication signals representing transmission data sent from another device. The pair of input signals VinP_i and VinN_i are input via a pair of signal lines L1 and L2, and then supplied to the differential pair circuit 2 via the switching circuit 3 provided by the degradation suppression circuit 1. In this case, the voltage at the non-inverting input terminal of the differential pair circuit 2 is referred to as the input voltage VinP, and the voltage at its inverting input terminal is referred to as the input voltage VinN. The differential pair circuit 2 operates by receiving a power supply voltage Vcc supplied via power supply lines L3 and L4.

[0018] The differential pair circuit 2, as shown in Figure 2 for example, has a configuration that includes a pair of MOS transistors Q1 and Q2 and a current source 5 that outputs a constant current as its input stage. MOS transistors Q1 and Q2 are NMOS transistors, and their sources are connected to a power line L4 via the current source 5 to which the circuit's reference potential Vss is supplied. The back gates of MOS transistors Q1 and Q2 are each supplied with the reference potential Vss. Although not shown in the figure, the drains of MOS transistors Q1 and Q2 are connected to a power line L3 via an active load to which the power supply voltage Vcc is supplied.

[0019] The gate of MOS transistor Q1 is supplied with an input voltage VinP. The gate of MOS transistor Q2 is supplied with an input voltage VinN. In the following description, the MOS transistor Q1 whose gate is connected to the non-inverting input terminal of differential pair circuit 2 will be referred to as the first transistor Q1, and the MOS transistor Q2 whose gate is connected to the inverting input terminal of differential pair circuit 2 will be referred to as the second transistor Q2.

[0020] Of the switching states by the switching circuit 3, the normal application state is a state in which the first voltage V1 is applied to the gate of the first transistor Q1, that is, the input voltage VinP is set to the first voltage V1, and the second voltage V2 is applied to the gate of the second transistor Q2, that is, the input voltage VinN is set to the second voltage V2. Of the switching states by the switching circuit 3, the reverse phase application state is a state in which the second voltage V2 is applied to the gate of the first transistor Q1, that is, the input voltage VinP is set to the second voltage V2, and the first voltage V1 is applied to the gate of the second transistor Q2, that is, the input voltage VinN is set to the first voltage V1.

[0021] The first voltage V1 is a voltage that is higher than the intermediate voltage Vm by a predetermined threshold voltage VTH, as shown in (1) below. However, the intermediate voltage Vm is half the power supply voltage Vcc, as shown in equation (2) below. V1 = Vm + VTH …(1) Vm = Vcc / 2 …(2)

[0022] The second voltage V2 is a voltage that is lower than the intermediate voltage Vm by the threshold voltage VTH, as shown by equation (3) below. V2 = Vm - VTH …(3)

[0023] As shown in Figure 3, during the period Ta when the switching circuit 3 switches to the normal applied state, the input voltage VinP becomes the first voltage V1, which is higher than the intermediate voltage Vm by the threshold voltage VTH, and the input voltage VinN becomes the second voltage V2, which is lower than the intermediate voltage Vm by the threshold voltage VTH. Furthermore, during the period Tb when the switching circuit 3 switches to the reverse-phase applied state, the input voltage VinP becomes the second voltage V2, and the input voltage VinN becomes the first voltage V1.

[0024] In the above configuration, by switching between the normal application state and the reverse-phase application state, the differential voltage ΔVd of the input voltages VinP and VinN of the differential pair circuit 2 becomes "0", as expressed by equation (4) below. ΔVd=(Vm+VTH-(Vm-VTH))+(Vm-VTH-(Vm+VTH)) =(2×VTH)+(-2×VTH)=0 …(4) Thus, with the above configuration, BTI fluctuations are canceled by switching between the normal application state and the reverse-phase application state.

[0025] <Specific configuration of the switching circuit> As for the specific configuration of the switching circuit 3, for example, the first configuration example shown in Figure 4 or the second configuration example shown in Figure 5 can be adopted. [1] First configuration example As shown in Figure 4, the switching circuit 3A of the first configuration example includes a first resistor R1, a second resistor R2, current sources I1a, I1b, I2a, I2b, I3a, I3b, I4a, I4b, switches S1a, S1b, S2a, S2b, S3a, S3b, S4a, S4b, and so on.

[0026] The first resistor R1 has one terminal connected to the non-inverting input terminal of the differential pair circuit 2, and the other terminal connected to the signal line L1. The second resistor R2 has one terminal connected to the inverting input terminal of the differential pair circuit 2, and the other terminal connected to the signal line L2. The eight current sources I1a to I4b are all configured as constant current sources that output a constant current.

[0027] One terminal of the first resistor R1 is connected to the power line L3 via switch S1a and current source I1a. The other terminal of the first resistor R1 is connected to the power line L4 via switch S1b and current source I1b. The other terminal of the first resistor R1 is connected to the power line L3 via switch S2a and current source I2a. One terminal of the first resistor R1 is connected to the power line L4 via switch S2b and current source I2b.

[0028] One terminal of the second resistor R2 is connected to the power line L3 via switch S3a and current source I3a. The other terminal of the second resistor R2 is connected to the power line L4 via switch S3b and current source I3b. The other terminal of the second resistor R2 is connected to the power line L3 via switch S4a and current source I4a. One terminal of the second resistor R2 is connected to the power line L4 via switch S4b and current source I4b.

[0029] In the above configuration, during the period when switches S1a and S1b are turned on, current flows from one terminal of the first resistor R1 to the other terminal, corresponding to the respective current values ​​of current sources I1a and I1b. In this case, the resistance value of the first resistor R1 and the respective current values ​​of current sources I1a and I1b are set such that during the period when switches S1a and S1b are turned on, the voltage at the other terminal of the first resistor R1 becomes the intermediate voltage Vm and the voltage drop across the first resistor R1 becomes the threshold voltage VTH, in other words, a first voltage V1 is generated at one terminal of the first resistor R1. In the above configuration, switches S1a and S1b and current sources I1a and I1b function as a first current circuit 11 that can perform the operation of generating a first voltage V1 at one terminal of the first resistor R1 by flowing current through the first resistor R1.

[0030] In the above configuration, during the period when switches S2a and S2b are turned on, current flows from the other terminal of the first resistor R1 to the other terminal, according to the respective current values ​​of current sources I2a and I2b. In this case, the resistance value of the first resistor R1 and the respective current values ​​of current sources I2a and I2b are set such that during the period when switches S2a and S2b are turned on, the voltage at the other terminal of the first resistor R1 becomes the intermediate voltage Vm and the voltage drop across the first resistor R1 becomes the threshold voltage VTH, in other words, a second voltage V2 is generated at one terminal of the first resistor R1. In the above configuration, switches S2a and S2b and current sources I2a and I2b function as a second current circuit 12 that can perform the operation of generating a second voltage V2 at one terminal of the first resistor R1 by flowing current through the first resistor R1.

[0031] In the above configuration, during the period when switches S3a and S3b are turned on, current flows from one terminal of the second resistor R2 to the other terminal, corresponding to the respective current values ​​of current sources I3a and I3b. In this case, the resistance value of the second resistor R2 and the respective current values ​​of current sources I3a and I3b are set such that during the period when switches S3a and S3b are turned on, the voltage at the other terminal of the second resistor R2 becomes the intermediate voltage Vm and the voltage drop across the second resistor R2 becomes the threshold voltage VTH, in other words, a first voltage V1 is generated at one terminal of the second resistor R2. In the above configuration, switches S3a and S3b and current sources I3a and I3b function as a third current circuit 13 that can perform the operation of generating a first voltage V1 at one terminal of the second resistor R2 by flowing current through the second resistor R2.

[0032] In the above configuration, during the period when switches S4a and S4b are turned on, current flows from the other terminal of the second resistor R2 to the other terminal, corresponding to the respective current values ​​of current sources I4a and I4b. In this case, the resistance value of the second resistor R2 and the respective current values ​​of current sources I4a and I4b are set such that during the period when switches S4a and S4b are turned on, the voltage at the other terminal of the second resistor R2 becomes the intermediate voltage Vm and the voltage drop across the second resistor R2 becomes the threshold voltage VTH, in other words, a second voltage V2 is generated at one terminal of the second resistor R2. In the above configuration, switches S4a and S4b and current sources I4a and I4b function as a fourth current circuit 14 that can generate a second voltage V2 at one terminal of the second resistor R2 by flowing current through the second resistor R2.

[0033] Switches S1a, S1b, S4a, and S4b are turned on and off based on the binary signal VSW provided by the control circuit 4. Switches S2a, S2b, S3a, and S3b are turned on and off based on the signal VSW bar provided by the control circuit 4. Both the VSW signal and the VSW bar are binary signals. In this specification, for binary signals such as the VSW signal and the VSW bar, a relatively high level is referred to as a high level, and a relatively low level is referred to as a low level.

[0034] Specifically, switches S1a, S1b, S4a, and S4b are turned on when the signal VSW is at a high level and turned off when the signal VSW is at a low level. Switches S2a, S2b, S3a, and S3b are turned on when the signal VSW bar is at a high level and turned off when the signal VSW bar is at a low level. In this case, the signal VSW bar is the inverted signal of the signal VSW. Therefore, in the above configuration, switches S1a, S1b, S4a, and S4b are turned on and off complementaryly to switches S2a, S2b, S3a, and S3b.

[0035] When the switching state by the switching circuit 3A is set to the normal applied state, the control circuit 4 sets the signal VSW to a high level. As a result, in the normal applied state, switches S1a, S1b, S4a, and S4b are turned on, while switches S2a, S2b, S3a, and S3b are turned off. In other words, in the normal applied state, the control circuit 4 causes the operation of the first current circuit 11 and the fourth current circuit 14 to proceed, while stopping the operation of the second current circuit 12 and the third current circuit 13. As a result, in the normal applied state, the input voltage VinP becomes the first voltage V1, and the input voltage VinN becomes the second voltage V2.

[0036] When the switching state by the switching circuit 3A is set to the reverse phase application state, the control circuit 4 sets the signal VSW bar to a high level. As a result, in the reverse phase application state, switches S2a, S2b, S3a, and S3b are turned on, while switches S1a, S1b, S4a, and S4b are turned off. In other words, in the reverse phase application state, the control circuit 4 causes the operation of the second current circuit 12 and the third current circuit 13 to proceed, while stopping the operation of the first current circuit 11 and the fourth current circuit 14. As a result, in the reverse phase application state, the input voltage VinP becomes the second voltage V2, and the input voltage VinN becomes the first voltage V1.

[0037] [2] Second configuration example As shown in Figure 5, the switching circuit 3B of the second configuration example includes MOS transistors Q3 and Q4, switches S11, S12, S13, S14, etc. In this case, the differential pair circuit 2 includes two current sources 15 and 16. The source of the first transistor Q1 is connected to the power line L4 via the current source 15, and the source of the second transistor Q2 is connected to the power line L4 via the current source 16. The drains of the first transistor Q1 and the second transistor Q2 are connected to the power line L3 via an active load 17 consisting of a current mirror circuit made of two PMOS transistors.

[0038] MOS transistors Q3 and Q4 are NMOS transistors. The source of MOS transistor Q3 is connected to power line L4 via current source 15, and the source of MOS transistor Q4 is connected to power line L4 via current source 16. A reference potential Vss is applied to the back gates of MOS transistors Q3 and Q4. The drains of MOS transistors Q3 and Q4 are connected to power line L3 via active load 17.

[0039] In the above configuration, MOS transistor Q3 functions as a third transistor that forms a current mirror circuit together with the first transistor Q1. Also in the above configuration, MOS transistor Q4 functions as a fourth transistor that forms a current mirror circuit together with the second transistor Q2. In the following description, MOS transistor Q3 will also be referred to as the third transistor Q3, and MOS transistor Q4 will also be referred to as the fourth transistor Q4.

[0040] The gate of the third transistor Q3 is connected to voltage line 18 to which the first voltage V1 is supplied via switch S11, and to voltage line 19 to which the second voltage V2 is supplied via switch S12. The gate of the fourth transistor Q4 is connected to voltage line 18 via switch S13, and to voltage line 19 via switch S14.

[0041] Switches S11 and S14 are turned on and off based on the signal VSW provided by the control circuit 4. Switches S12 and S13 are turned on and off based on the signal VSW bar provided by the control circuit 4. Signals VSW and VSW bar are the same signals as those described in the first configuration example. Switches S11 and S14 are turned on when signal VSW is at a high level and turned off when signal VSW is at a low level. Switches S12 and S13 are turned on when signal VSW bar is at a high level and turned off when signal VSW bar is at a low level. In the above configuration, switches S11 and S14 and switches S12 and S13 are turned on and off complementaryly.

[0042] When the switching state by the switching circuit 3B is set to the normal applied state, the control circuit 4 sets the signal VSW to a high level. As a result, in the normal applied state, switches S11 and S14 are turned on, and switches S12 and S13 are turned off. In other words, in the normal applied state, the control circuit 4 controls the operation of the switching circuit 3B so that the first voltage V1 is applied to the gate of the third transistor Q3 and the second voltage V2 is applied to the gate of the fourth transistor Q4.

[0043] When the switching state by the switching circuit 3B is set to the reverse phase application state, the control circuit 4 sets the signal VSW bar to a high level. As a result, in the reverse phase application state, switches S12 and S13 are turned on, and switches S11 and S14 are turned off. In other words, in the reverse phase application state, the control circuit 4 controls the operation of the switching circuit 3B so as to apply the second voltage V2 to the gate of the third transistor Q3 and the first voltage V1 to the gate of the fourth transistor Q4.

[0044] [3] Characteristics of each configuration example According to the first configuration example, regardless of the current value of the current source 5 which becomes the operating current of the differential pair circuit 2, the threshold voltage VTH can be set to any value by the resistance values ​​of the first resistor R1 and the second resistor R2 and the current values ​​of the current sources I1a to I4b, so that the first voltage V1 and the second voltage V2 can be applied to each input terminal of the differential pair circuit 2 with high precision. However, the first configuration example has the disadvantage that the input range of the differential pair circuit 2 is reduced.

[0045] In the second configuration example, although the accuracy of the first voltage V1 and second voltage V2 applied to each input terminal of the differential pair circuit 2 is reduced compared to the first configuration example, the degradation suppression circuit 1 does not affect the input range of the differential pair circuit 2, and its input range can be sufficiently secured. Furthermore, according to the second configuration example, the circuit size can be kept smaller compared to the first configuration example because fewer current sources are required.

[0046] <Specific switching timing for each state by the switching circuit> The specific timing at which the switching circuit 3 switches between the normal application state and the reverse-phase application state can be, for example, the first timing example shown in Figure 6, the second timing example shown in Figure 7, or the third timing example shown in Figure 8.

[0047] [1] Example of the first timing As shown in Figure 6, the switching circuit 3 can switch between a normal application state and a reverse-phase application state each time it receives one frame of transmission data transmitted from another device. Specifically, the switching circuit 3 can change the switching state each time it receives one frame of transmission data, such as switching to the normal application state during the period when it receives communication frame n+1, switching to the reverse-phase application state during the period when it receives the next communication frame n+2, and then switching back to the normal application state during the period when it receives the next communication frame n+3.

[0048] [2] Example of second timing The second timing example, like the first timing example, changes the switching state each time a frame of transmitted data is received, but the timing of the switching is more specific. That is, in this case, as shown in Figure 7, the switching circuit 3 can switch between the normal applied state and the reversed phase applied state at the timing t1 when the frame data is finalized. In Figure 7 and other examples, the differential voltage corresponds to the difference between the input signals VinP_i and VinN_i, ​​and the digital value corresponds to the digital value obtained from the output signal Vout of the differential pair circuit 2.

[0049] In the second timing example, we assume that communication frames are transmitted periodically. In this case, as shown in Figure 7, the switching circuit 3 can change the switching state at the timing when the frame data is determined, such as by receiving the periodically transmitted communication frames and waiting for the frame data to be determined before switching from the normal applied state to the reverse-phase applied state.

[0050] [3] Example of the third timing The third timing example assumes that communication signals are transmitted continuously. In this case, as shown in Figure 8, the switching circuit 3 can switch between the normal applied state and the reversed phase applied state each time a communication signal is received. Specifically, the switching circuit 3 can change the switching state at the timing when the data is finalized after receiving the communication signal. In Figure 8, the timing when the data is finalized is indicated by a black arrow.

[0051] [4] Characteristics of each timing example According to the first and second timing examples, the switching state is changed each time a frame of transmitted data is received. As a result, the number of switching operations is reduced compared to the third timing example, and consequently, the complexity of the control related to switching can be suppressed. On the other hand, the third timing example can be applied even when communication signals are transmitted continuously, which has the advantage of increasing the versatility of applications compared to the first and second timing examples.

[0052] According to the embodiment described above, the following effects can be obtained. The switching circuit 3 of the degradation suppression circuit 1 has two states: a normal application state in which a first voltage V1, which is a voltage higher by a threshold voltage VTH than the intermediate voltage Vm, is applied to the non-inverting input terminal of the differential pair circuit 2, i.e., the gate of the first transistor Q1, and a second voltage V2, which is a voltage lower by a threshold voltage VTH than the intermediate voltage Vm, is applied to the inverting input terminal of the differential pair circuit 2, i.e., the gate of the second transistor Q2; and a state in which the second voltage V2 is applied to the gate of the first transistor Q1 and It is possible to switch between a reverse-phase application state, where the first voltage V1 is applied to the gate of the second transistor Q2, and another state.

[0053] In this embodiment, the characteristic degradation of MOS transistors Q1 and Q2 due to BTI, that is, the BTI fluctuation, is caused by a fluctuation in the gate threshold voltage during the period when a DC potential difference exists between the gate and back gate of MOS transistors Q1 and Q2. Therefore, the focus is on the fact that the degradation is improved by creating a reverse bias between the gate and back gate of MOS transistors Q1 and Q2. With the above configuration, in addition to the normal application state in which a positive-sequence voltage is applied to the input of the differential pair circuit 2, a reverse-sequence application state in which an inverse-sequence voltage is applied is provided, thereby canceling out the in-phase fluctuation of the BTI fluctuation.

[0054] In other words, with the above configuration, it is possible to prevent a DC potential difference from occurring between the gate and back gate of the pair of MOS transistors Q1 and Q2 in the differential pair circuit 2, and as a result, fluctuations in the characteristics of MOS transistors Q1 and Q2 are suppressed. Furthermore, with the above configuration, the switching circuit 3 can be switched to an inverse phase applied state even when the differential pair circuit 2 is operating, so characteristic degradation due to BTI can be suppressed even when the differential pair circuit 2 is operating. Moreover, since the above configuration does not require an analog circuit like the third prior art, the circuit size can be kept smaller.Therefore, according to this embodiment, the excellent effect of suppressing characteristic degradation of MOS transistors Q1 and Q2 due to BTI is obtained without increasing the circuit size.

[0055] Furthermore, the effects obtained by this embodiment become even clearer when compared with a comparative example corresponding to the prior art. That is, as shown in Figure 9, in the comparative example, the input voltage VinP is always a first voltage V1 which is higher than the intermediate voltage Vm by a threshold voltage VTH, and the input voltage VinN is always a second voltage V2 which is lower than the intermediate voltage Vm by a threshold voltage VTH.

[0056] In the comparative example, the differential voltage ΔVd between the input voltages VinP and VinN of the differential pair circuit 2 is "2 × VTH" as shown in equation (5) below. ΔVd=(Vm+VTH)-(Vm-VTH)=2×VTH…(5)

[0057] As can be seen in the comparative example, BTI fluctuations occur. In contrast, according to the configuration of this embodiment, as shown in Figure 3 and equation (4), the differential voltage ΔVd of the input voltages VinP and VinN of the differential pair circuit 2 is "0". In other words, according to the configuration of this embodiment, BTI fluctuations are canceled by switching between the normal application state and the reverse-phase application state.

[0058] (Second Embodiment) The second embodiment will be described below with reference to Figures 10 and 11. As shown in Figure 10, this embodiment assumes that the communication device has two receiving circuits, and two of the same configurations as the switching circuit 3 and differential pair circuit 2 of the first embodiment are provided. The communication device of this embodiment is configured to perform communication using Manchester codes.

[0059] In this case, of the two switching circuits 3, the one corresponding to the upper threshold is referred to as switching circuit 3H, and the one corresponding to the lower threshold is referred to as switching circuit 3L. Also, in this case, of the two differential pair circuits 2, the one corresponding to the upper threshold is referred to as differential pair circuit 2H, and the one corresponding to the lower threshold is referred to as differential pair circuit 2L. In this embodiment, the degradation suppression circuit 22 is composed of switching circuits 3H, 3L, a control circuit 4, and an inverting circuit 21, which will be described later.

[0060] In this case, the voltage at the non-inverting input terminal of differential pair circuit 2H is referred to as the input voltage VinPa, and the voltage at its inverting input terminal is referred to as the input voltage VinNb. Similarly, the voltage at the non-inverting input terminal of differential pair circuit 2L is referred to as the input voltage VinPc, and the voltage at its inverting input terminal is referred to as the input voltage VinNd. Differential pair circuit 2H outputs an output signal VoutP corresponding to the difference between a pair of input signals VinP_i and VinN_i. Differential pair circuit 2L outputs an output signal VoutN corresponding to the difference between a pair of input signals VinP_i and VinN_i. Output signals VoutP and VoutN are input to the inverting circuit 21.

[0061] The inverting circuit 21 inverts the logic represented by the output signals VoutP and VoutN during the period when it is switched to an inverse phase applied state by the switching circuits 3H and 3L, and includes switches S21, S22, S23, and S24. The inverting circuit 21 includes an input node N21 that receives the output signal VoutP, an input node N22 that receives the output signal VoutN, an output node N23 that outputs the output signal VoutP_o corresponding to the output signal VoutP, and an output node N24 that outputs the output signal VoutN_o corresponding to the output signal VoutN.

[0062] Switch S21 is connected between input node N21 and output node N23. Switch S22 is connected between input node N22 and output node N23. Switch S23 is connected between input node N21 and output node N24. Switch S24 is connected between input node N22 and output node N24. Switches S21 and S24 are turned on and off based on the signal VSW provided by the control circuit 4. Switches S22 and S23 are turned on and off based on the signal VSW bar provided by the control circuit 4.

[0063] Switches S21 and S24 are turned on when the signal VSW is at a high level and turned off when the signal VSW is at a low level. Switches S22 and S23 are turned on when the signal VSW bar is at a high level and turned off when the signal VSW bar is at a low level. In the above configuration, switches S21 and S24 and switches S22 and S23 are turned on and off complementaryly.

[0064] As a result, the inverting circuit 21 outputs output signal VoutP_o, which represents the same logic as output signal VoutP, and output signal VoutN_o, which represents the same logic as output signal VoutN, during the period when it is switched to the normal applied state by the switching circuits 3H and 3L. Also, during the period when the inverting circuit 21 is switched to the reverse phase applied state by the switching circuits 3H and 3L, it outputs output signal VoutP_o, which represents the opposite logic of output signal VoutP, and output signal VoutN_o, which represents the opposite logic of output signal VoutN. In this case, output signals VoutP_o and VoutN_o become the outputs of the receiving circuit.

[0065] In this embodiment, the second timing example shown in Figure 7 is adopted as the specific timing for switching circuits 3H and 3L to switch between the normal application state and the reverse-phase application state. Therefore, as shown in Figure 11, the switching circuits 3H and 3L change their switching state each time they receive one frame of transmitted data. Specifically, the switching circuits 3H and 3L can change their switching state each time they receive one frame of transmitted data, such as switching to the normal application state during the period when they receive communication frame n, and switching to the reverse-phase application state during the period when they receive the next communication frame n+1. In this case, the switching between the normal application state and the reverse-phase application state occurs at the timing when the frame data is finalized.

[0066] Here, we assume that communication frame n and communication frame n+1 represent the same data. In the above configuration, the Manchester code logic of the output signals VoutP and VoutN of the differential pair circuits 2H and 2L becomes inverted between communication frame n and communication frame n+1. However, in the above configuration, the Manchester code logic of the output signals VoutP and VoutN of the inverting circuit 21 does not become inverted between communication frame n and communication frame n+1, and represents the same logic.

[0067] As described above, the degradation suppression circuit 22 of this embodiment is applicable when the communication device has two receiving circuits, and includes an inverting circuit 21 that inverts the logic represented by the output signals VoutP and VoutN during the period when the switching circuits 3H and 3L are switched to the reverse-phase applied state. In a configuration without the inverting circuit 21, in the reverse-phase applied state, the receiving threshold voltage is in the opposite phase to that of the normal applied state, so the Manchester code logic of the output voltages VoutP and VoutN, which are the outputs of the receiving circuit, is inverted.

[0068] With such a configuration, there is a risk that the communication device may not be able to communicate correctly. In contrast, with the configuration of this embodiment, even in the reverse-phase applied state, the Manchester code logic of the output voltages VoutP and VoutN, which are the outputs of the receiving circuit, is not inverted due to the action of the inverting circuit 21, and represents the same logic as in the normal applied state, and as a result, the communication device can communicate normally.

[0069] (Other embodiments) It should be noted that the present invention is not limited to the embodiments described above and shown in the drawings, and can be arbitrarily modified, combined, or expanded without departing from its essence. The numerical values ​​and other figures shown in each of the above embodiments are illustrative examples and are not limiting.

[0070] The degradation suppression circuits 1 and 22 are not limited to differential pair circuits 2 used in receiving circuits of communication devices applicable to automotive and industrial equipment, but can be used with various differential pair circuits to suppress the characteristic degradation of the pair of MOS transistors they comprise. Furthermore, although the above embodiments illustrate a configuration in which a pair of NMOS transistors, namely MOS transistors Q1 and Q2, are used as the differential pair circuit, a configuration in which a pair of PMOS transistors are used as the differential pair circuit may also be used.

[0071] This disclosure is described in accordance with the embodiments, but it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the equivalence. In addition, various combinations and forms, as well as other combinations and forms that include only one, more, or fewer of those elements, fall within the scope and concept of this disclosure. [Explanation of Symbols]

[0072] 1, 22... Degradation suppression circuit, 2... Differential pair circuit, 3, 3A, 3B, 3H, 3L... Switching circuit, 11... First current circuit, 12... Second current circuit, 13... Third current circuit, 14... Fourth current circuit, 21... Inverting circuit, Q1... First transistor, Q2... Second transistor, Q3... Third transistor, Q4... Fourth transistor, R1... First resistor, R2... Second resistor.

Claims

1. A degradation suppression circuit that suppresses the amount of in-phase fluctuation of bias temperature instability fluctuations caused by characteristic degradation of a pair of MOS transistors (Q1, Q2) in a differential pair circuit (2) that outputs an output signal corresponding to the difference between a pair of input voltages input via a first input terminal and a second input terminal, respectively, The aforementioned pair of input voltages are voltages corresponding to a pair of input signals, If we define the MOS transistor whose gate is connected to the first input terminal as the first transistor (Q1) and the MOS transistor whose gate is connected to the second input terminal as the second transistor (Q2), The system includes a switching circuit (3, 3A, 3B, 3H, 3L) that can switch between a normal application state in which a first voltage is applied to the first input terminal as the input voltage and a second voltage is applied to the second input terminal as the input voltage, and a reverse-phase application state in which the second voltage is applied to the first input terminal as the input voltage and the first voltage is applied to the second input terminal as the input voltage. The first voltage is a voltage that is higher by a predetermined threshold voltage than the intermediate voltage, which is the voltage between the power supply voltage of the circuit and the reference potential. The second voltage is a voltage that is lower than the intermediate voltage by the threshold voltage. The differential pair circuit constitutes the receiving circuit of a communication device that communicates with other devices. The pair of input signals are differential communication signals representing transmission data transmitted from the other device. The switching circuit is a degradation suppression circuit that switches between the normal application state and the reverse-phase application state each time the transmitted data is received for one frame.

2. The degradation suppression circuit according to claim 1, wherein the switching circuit switches between the normal application state and the reverse-phase application state at the timing when the frame data is determined.

3. Furthermore, the degradation suppression circuit according to claim 1 or 2, further comprising an inverting circuit (21) that inverts the logic represented by the output signal during the period when the switching circuit (3H, 3L) is switched to the reverse phase application state.

4. A degradation suppression circuit that suppresses the amount of in-phase fluctuation of bias temperature instability fluctuations caused by characteristic degradation of a pair of MOS transistors (Q1, Q2) in a differential pair circuit (2) that outputs an output signal corresponding to the difference between a pair of input voltages input via a first input terminal and a second input terminal, respectively, The aforementioned pair of input voltages are voltages corresponding to a pair of input signals, If we define the MOS transistor whose gate is connected to the first input terminal as the first transistor (Q1) and the MOS transistor whose gate is connected to the second input terminal as the second transistor (Q2), The system includes a switching circuit (3, 3A, 3B, 3H, 3L) that can switch between a normal application state in which a first voltage is applied to the first input terminal as the input voltage and a second voltage is applied to the second input terminal as the input voltage, and a reverse-phase application state in which the second voltage is applied to the first input terminal as the input voltage and the first voltage is applied to the second input terminal as the input voltage. The first voltage is a voltage that is higher by a predetermined threshold voltage than the intermediate voltage, which is the voltage between the power supply voltage of the circuit and the reference potential. The second voltage is a voltage that is lower than the intermediate voltage by the threshold voltage. The aforementioned switching circuit (3A) is A first resistor (R1) whose one terminal is connected to the first input terminal, A second resistor (R2) has one terminal connected to the second input terminal, A first current circuit (11) is capable of performing the operation of generating the first voltage at one terminal of the first resistor by passing current through the first resistor, A second current circuit (12) is capable of performing the operation of generating the second voltage at one terminal of the first resistor by passing current through the first resistor, A third current circuit (13) is capable of performing the operation of generating the first voltage at one terminal of the second resistor by passing current through the second resistor, A fourth current circuit (14) is capable of performing the operation of generating the second voltage at one terminal of the second resistor by passing current through the second resistor, Equipped with, In the normal current application state, the operation of the first current circuit and the fourth current circuit is performed, while the operation of the second current circuit and the third current circuit is stopped. In the reverse-phase application state, the degradation suppression circuit causes the second current circuit and the third current circuit to operate while stopping the operation of the first current circuit and the fourth current circuit.

5. The differential pair circuit constitutes the receiving circuit of a communication device that communicates with other devices. The pair of input signals are differential communication signals representing transmission data transmitted from the other device. The degradation suppression circuit according to claim 4, wherein the switching circuit switches between the normal application state and the reverse phase application state each time the communication signal is received.

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