modulator
The modulator addresses noise and offset issues in ΔΣ modulators by integrating a continuous integrator with chopping switches, enhancing noise reduction and performance.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- DENSO CORP
- Filing Date
- 2023-01-30
- Publication Date
- 2026-07-08
AI Technical Summary
Existing ΔΣ modulators using discrete integrators face issues with noise due to sampling, while those using continuous integrators are susceptible to jitter noise and offset, which are not adequately addressed by chopping.
A modulator design incorporating a continuous integrator with high-frequency and low-frequency chopping switches to reduce noise and offset, utilizing an amplifier, input capacitor, integrating capacitor, quantizer, D/A converter, and DAC capacitor with specific chopping switch configurations.
The design effectively reduces sampling noise and offset by integrating the input signal in continuous time and employing chopping techniques, achieving balanced noise reduction and improved performance.
Smart Images
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Abstract
Description
Technical Field
[0001] The present invention relates to a modulator.
Background Art
[0002] As shown in FIGS. 11 and 12, Non-Patent Document 1 discloses a ΔΣ modulator using a discrete integrator. In order to reduce offset, chopping is performed before and after the integration capacitor Cint1 in the input section, output section, and discrete integrator. Further, Patent Document 1 discloses a ΔΣ modulator using a continuous integrator.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Non-Patent Documents
[0004]
Non-Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0005] The configuration in Non-Patent Document 1 uses a discrete integrator, which has the problem that noise (kT / C1) generated by sampling becomes the rate-limiting factor. Here, k is Boltzmann's constant, T is the absolute temperature, and C1 is the sampling capacitance. The configuration in Patent Document 1 uses a continuous integrator, so it does not have the same problem as Non-Patent Document 1, but it is susceptible to jitter noise, and because chopping is not performed on the input, output, or integrating capacitance as in Non-Patent Document 1, the offset is not reduced. The present invention has been made in view of the above circumstances, and its object is to provide a modulator that can reduce offset in a configuration using a continuous integrator. [Means for solving the problem]
[0006] The modulator according to claim 1 comprises an amplifier (1), an input capacitor (Cin), an integrating capacitor (Cint) connected to the output side of the amplifier, a first integrator (11, 11A, 11B) that integrates the input signal in continuous time, a quantizer (6) that quantizes the output value of the first integrator, a D / A converter (8) that D / A converts the data output from the quantizer and feeds it back to the input of the first integrator, a DAC capacitor (CDAC) connected to the output of the D / A converter, first to third high-frequency chopping switches (3, 4, 10) arranged between the input terminal and the input capacitor, the output section of the amplifier, and between the D / A converter and the DAC capacitor, respectively, and all operating at the same frequency, and first to third low-frequency chopping switches (2, 5, 9) arranged between the input terminal and the first high-frequency chopping switch, between the second high-frequency chopping switch and the integrating capacitor, and between the output of the D / A converter and the third high-frequency chopping switch, respectively, and all operating at the same frequency lower than the high-frequency chopping switches.
[0007] With this configuration, since the first integrator integrates the input signal in continuous time, sampling noise is not generated, and noise does not become the rate-limiting factor. Furthermore, the offset can be reduced by performing chopping using the first to third high-frequency chopping switches. In addition, the offset caused by switching can be reduced by performing chopping using the first to third low-frequency chopping switches at the input side of the first high-frequency chopping switch, the output side of the second high-frequency chopping switch, and the input side of the third high-frequency chopping switch, respectively. [Brief explanation of the drawing]
[0008] [Figure 1] This is the first embodiment, and the diagram shows the configuration of the modulator. [Figure 2] Operation timing chart [Figure 3] This diagram illustrates the configuration and operation of a 4-tap FIR type DAC unit. [Figure 4] Diagram showing a modulator in a differential configuration. [Figure 5] Diagram showing chopping switches in a differential configuration. [Figure 6] This is a second embodiment, and the diagram shows the configuration of the modulator. [Figure 7] Operation timing chart [Figure 8] This is a third embodiment, and the diagram shows the configuration of the modulator. [Figure 9] Operation timing chart [Figure 10] This is the fourth embodiment, and the diagram shows the configuration of the modulator. [Figure 11] Diagram showing the modulator configuration disclosed in Non-Patent Document 1 [Figure 12] Operation timing chart [Modes for carrying out the invention]
[0009] (First Embodiment) The modulators dealt with in the following embodiments are differential types as shown in Fig. 4. However, for ease of explanation, as shown in Fig. 1, there are cases where the single-ended type positive and negative switches, etc. are illustrated together. As shown in Fig. 4, the configurations of the inverting side and non-inverting side are symmetric. The signs of the inverting side and negative side configurations are denoted by "m", and the signs of the non-inverting side and positive side configurations are denoted by "p". However, when there is no particular need to distinguish between the two, the signs may not be denoted by "m" and "p".
[0010] As shown in Fig. 4, an input voltage is applied to each input terminal of the differential amplifier 1 via the first low-frequency chopping switch 2, the first high-frequency chopping switch 3, and the coupling capacitor Cin which is an input capacitor. A second high-frequency chopping switch 4 is arranged at the output stage inside the differential amplifier 1. The input terminal of the quantizer 6 is connected to the output terminal of the switch 4 via the second low-frequency chopping switch 5. An integrating capacitor Cint is connected to the output terminal of the switch 5. Note that the amplifier 1 is a so-called gm-C type amplifier that performs voltage / current conversion internally and receives the converted current with a capacitor and outputs it.
[0011] The input terminal of the D / A converter; DAC8 is connected to the output terminal of the quantizer 6. A series circuit of the third low-frequency chopping switch 9, the third high-frequency chopping switch 10, and the DAC capacitor C DAC is connected to the output side of the DAC8. The output terminal of the DAC8 is connected to the input terminal of the differential amplifier 1 via the above series circuit. The combination of the switches 9 and 10 and the DAC capacitor C DAC constitutes the DAC unit 7.
[0012] The switches 3, 4, and 10 for high-frequency chopping operate in a chopping manner by a common chopping signal CHH. The switches 2, 5, and 9 for low-frequency chopping operate in a chopping manner by a common chopping signal CHL. As shown in FIG. 2, assuming the sampling frequency of the DAC8 is fs, the frequency of the chopping signal CHH is set to, for example, fs / 4, and the frequency of the chopping signal CHL is set to, for example, fs / 256, which is sufficiently smaller than the frequency of the signal CHH. In this embodiment, a signal and its frequency are denoted by the same name.
[0013] In FIG. 1, the chopping switches 2 to 5, 9, and 10 symbolically shown are composed of two switches CHL1p connected in series to the inverting side and the non-inverting side respectively, and two switches CHL1m connected in a bridging state between the inverting side and the non-inverting side, as shown in FIG. 5. The switch CHL1 corresponds to a capacitive chopping input switch, and the switch CHL2 corresponds to a capacitive chopping output switch. Each switch is composed of, for example, an N-channel MOSFET or the like.
[0014] Also, as shown in FIG. 3, the DAC unit 7 may actually be configured in a FIR (Finite Impulse Response) type with a tap number n = 4. A 4-input selector (not shown) is inserted between the output of the quantizer 6 and the input terminals of each of the DAC units 7(1) to 7(4). A 4-input selector (not shown) is inserted between the output terminals of each of the DAC units 7(1) to 7(4) and the input terminal of the amplifier 1. The input selection of the selector is switched at the frequency fs.
[0015] As shown in Figure 3, if the data sequence output from the quantizer 6 is, for example, "100101111" and the DAC unit 7 has 4 taps, then the outputs of DAC units 7(1), 7(2), 7(3), and 7(4) will correspond to the values four, three, two, and one positions prior to the data sequence, respectively. For example, if the four data points immediately preceding the data sequence are 1001, then the outputs of DAC8 within DAC units 7(1), 7(2), 7(3), and 7(4) will output values corresponding to "1", "0", "0", and "1", respectively. Therefore, if the data sequence is, for example, "100101111", then the outputs of DAC8 within DAC units 7(1) to 7(4) will output values corresponding to "1001", "0010", "0101", "1011", "0111", and "1111", respectively, in chronological order. Thus, the output data from the quantizer 6 will be output a total of four times by each of the DAC units 7(1) to 7(4).
[0016] Since the polarity of the high-frequency chopping signal CHH reverses every two times, the output data of the quantizer 6 is output a total of two times when the chopping polarity is positive and a total of two times when it is negative, resulting in a balanced state of positive and negative chopping polarity. In this configuration, the input capacitor Cin, amplifier 1, and integrating capacitor Cint constitute the first integrator 11, and the modulator 12 is formed by adding other peripheral circuits to the first integrator 11.
[0017] As described above, according to this embodiment, the modulator 12 includes an amplifier 1, an input capacitance Cin, an integrating capacitance Cint connected to the output side of the amplifier 1, a first integrator 11 that integrates the input signal in continuous time, a quantizer 6 that quantizes the output value of the first integrator 11, a DAC 8 that performs D / A conversion on the data output from the quantizer 6 and feeds it back to the input of the first integrator 11, and a DAC capacitance C connected to the output of the DAC 8. DAC , between the input terminal and input capacitance Cin, the output section of amplifier 1, DAC8 and DAC capacitance C DACThe DAC8 is equipped with first to third high-frequency chopping switches 3, 4, and 10, each positioned between the high-frequency chopping switches and operating at the same frequency, and first to third low-frequency chopping switches 2, 5, and 9, each positioned between the input terminal and the first high-frequency chopping switch 3, between the second high-frequency chopping switch 4 and the integrating capacitor Cint, and between the output of the DAC8 and the third high-frequency chopping switch 10, each operating at the same frequency but lower than the high-frequency chopping switches.
[0018] With this configuration, since the first integrator 11 integrates the input signal in continuous time, sampling noise (kT / Cin) is not generated, and the noise is not limited by sampling noise. Furthermore, the offset can be reduced by performing chopping with the first to third high-frequency chopping switches 3, 4 and 10. In addition, the offset caused by switching can be reduced by performing chopping with the first to third low-frequency chopping switches 2, 5 and 9 at the input side of the first high-frequency chopping switch 3, the output side of the second high-frequency chopping switch 4, and the input side of the third high-frequency chopping switch 10, respectively.
[0019] Furthermore, if the DAC unit 7 is an FIR type with 4 taps, and the sampling frequency of the DAC 8 is set to fs, the chopping frequencies of the high-frequency chopping switches 3, 4, and 10 are set to fs / 4. As a result, the output of the quantizer 6 is output twice for each case of positive and negative chopping polarity of the high-frequency chopping switches 3, 4, and 10, resulting in proper balance. By employing an FIR type DAC unit 7 with a tap count greater than 1, the output value of the amplifier 1 can be reduced, and by relating the chopping frequency to the tap count, the positive and negative polarities can be canceled out by the chopping operation.
[0020] (Second Embodiment) In the following description, parts identical to those in the first embodiment are denoted by the same reference numerals and their descriptions are omitted, while the differences are described. As shown in Figure 6, the modulator 21 of the second embodiment has a configuration in which a deadband switch 13, which corresponds to a path interruption switch, is inserted between the output terminal of the amplifier 1 and the switch 5. Note that only one DAC unit 7 is shown. The same applies to subsequent embodiments.
[0021] Switch 13S is connected between the output terminal of amplifier 1 and switch 5, and switch 13G is connected between the output terminal of amplifier 1 and ground, which is the reference potential. The deadband switch 13 is controlled on and off by signal DB. If signal DB is high level, switch 13G is on and switch 13S is off; if it is low level, switch 13G is off and switch 13S is on. The first integrator 11A is formed by adding the deadband switch 13 to the first integrator 11 of the first embodiment.
[0022] Next, the operation of the second embodiment will be described. As shown in Figure 7, the signal DB becomes high level in synchronization with the rising edge of the sampling signal fs. As a result, the output terminal of amplifier 1 is disconnected from the chopping switch 5 and the integrating capacitor Cint and connected to the reference potential point, so the integration operation is stopped. The DAC unit 7 introduces transient noise when the output switches at the timing of the switching of the sampling signal fs, but the deadband switch 13 operates at the timing of the switching of the output of the DAC unit 7, so that transient noise caused by the switching of the DAC unit 7 is not introduced into the integrating capacitor Cint.
[0023] (Third embodiment) As shown in Figure 8, the modulator 22 of the third embodiment has a series circuit of resistor element 14a, switch 15, and resistor element 14b connected between the input terminal of amplifier 1 and the reference potential point, compared to the configuration of the second embodiment. The addition of the above series circuit constitutes the first integrator 11B. The on / off state of switch 15 controls the signal f RES It is controlled by [the specified method / system].
[0024] As shown in Figure 9, the signal f RES The frequency of the signal CHH is set to twice the frequency of the signal, and when switch 15 is turned on, the input terminal of amplifier 1 is biased to a predetermined potential within the operable range, so it does not become floating. This stabilizes the operation of amplifier 1.
[0025] (Fourth Embodiment) As shown in Figure 10, the modulator 23 of the fourth embodiment has a configuration in which a series circuit of a fourth low-frequency chopping switch 16, a second integrator 17 corresponding to the second integrator, and a fifth low-frequency chopping switch 18 is connected between the switch 5 and the quantizer 6, compared to the configuration of the first embodiment. The second integrator 17 is discrete, and similar to the first integrator 11, the output of the quantizer 6 is fed back to the input via a D / A converter (not shown). This makes it possible to move the quantization noise to a higher frequency band and reduce the noise level.
[0026] Note that switches 16 and 18 are located at the input and output sections of the quadratic integrator 17, respectively. However, the terms "input section" and "output section" here also include cases where switches 16 and 18 are located inside the quadratic integrator 17. For example, this includes cases where they are located immediately before the sampling capacitor on the input side, or where they are included in a feedback path that includes a feedback capacitor on both the input and output sides.
[0027] (Other embodiments) The number of taps is not limited to "4". D / A converters are not limited to FIR type. The relationship between the sampling frequency and the high-frequency chopping frequency is not necessarily 4:1. Furthermore, the relationship between the sampling frequency and the low-frequency chopping frequency is not necessarily 256:1. The second integrator is not limited to discrete types.
[0028] This disclosure is described in accordance with the embodiments, but it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the equivalence. In addition, various combinations and forms, as well as other combinations and forms that include only one, more, or fewer of those elements, fall within the scope and concept of this disclosure. [Explanation of Symbols]
[0029] In the diagram, 1 is a differential amplifier, 2 is a switch for the first low-frequency chopping, 3 is a switch for the first high-frequency chopping, 4 is a switch for the second high-frequency chopping, 5 is a switch for the second low-frequency chopping, 6 is a quantizer, 7 is a DAC unit, 8 is a DAC, 11 is a first integrator, 12 is a modulator, Cin is a coupling capacitance, Cint is a coupling capacitance, C DAC This indicates the DAC capacity.
Claims
1. The first integrator (11, 11A, 11B) comprises an amplifier (1), an input capacitor (Cin) connected to the input side of the amplifier, and an integrating capacitor (Cint) connected to the output side of the amplifier, and integrates the input signal in continuous time. A quantizer (6) that quantizes the output value of this first integrator, A D / A converter (8) performs D / A conversion on the data output from this quantizer and feeds it back to the input of the first integrator, The DAC capacitor (C) connected to the output of this D / A converter is connected to the output of this D / A converter. ＤＡＣ )and, First to third high-frequency chopping switches (3, 4, 10) are positioned between the input terminal and the input capacitor, between the output section of the amplifier and between the D / A converter and the DAC capacitor, and all operate at the same frequency. A modulator comprising: first to third low-frequency chopping switches (2, 5, 9) positioned between the input terminal and the first high-frequency chopping switch, between the second high-frequency chopping switch and the integrating capacitor, and between the output of the D / A converter and the third high-frequency chopping switch, all of which operate at the same frequency lower than the high-frequency chopping switch.
2. The D / A converter is further equipped with a DAC unit (7) which includes a third high-frequency chopping switch (10) and a third low-frequency chopping switch (9). The DAC unit is a Finite Impulse Response (FIR) type with n taps. The modulator according to claim 1, wherein the sampling frequency of the D / A converter is fs, and the chopping frequency of the high-frequency chopping switch is set to fs / n.
3. The modulator according to claim 2, wherein the number of taps n is "4".
4. A path interruption switch (13) is provided between the output of the amplifier and the integrating capacitor. The modulator according to claim 2, wherein the path interruption switch is turned off at the timing when the output value of the D / A converter is input to the DAC capacitor.
5. The amplifier comprises a series circuit of a potential-applying switch (15) and resistive elements (14a, 14b) connected between the input terminal of the amplifier and a reference potential. The modulator according to claim 4, wherein the potential application switch is turned on at the timing when the on / off state of the high-frequency chopping switch and the low-frequency chopping switch are switched.
6. The modulator according to any one of claims 1 to 5, further comprising a second integrator (17) connected between the first integrator and the quantizer.
7. The modulator according to claim 6, wherein the second integrator is of discrete type.
8. The modulator according to claim 7, further comprising a fourth and fifth low-frequency chopping switch (16, 18) operating at the same frequency as the low-frequency chopping switch at the input and output sections of the second integrator, respectively.