Semiconductor equipment

Abstract

To provide a semiconductor device capable of reducing a switching loss.SOLUTION: A semiconductor device includes a first electrode, a second electrode, a first region, and a second region. The first region includes: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type; a plurality of third semiconductor regions of the first conductivity type; a gate electrode; a conductive part; a fourth semiconductor region of the second conductivity type; a fifth semiconductor region of the first conductivity type; and a sixth semiconductor region of the second conductivity type. The gate electrode faces one of the plurality of third semiconductor regions via a gate insulating layer. The conductive part faces the other one of the plurality of third semiconductor regions via an insulating layer and is electrically connected to the second electrode. The fourth semiconductor region is located on the one of the plurality of third semiconductor regions. The sixth semiconductor region is located on the other one of the plurality of third semiconductor regions. A length of the sixth semiconductor region in a third direction is greater than a length of the fourth semiconductor region in the third direction.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] One type of semiconductor device used for power conversion and other applications is the Reverse Conducting Insulated Gate Bipolar Transistor (RC-IGBT), which incorporates a diode into an Insulated Gate Bipolar Transistor (IGBT). There is a need for technologies that can reduce switching losses in this type of semiconductor device. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-59429 [Overview of the project] [Problems that the invention aims to solve]

[0004] The problem that this invention aims to solve is to provide a semiconductor device capable of reducing switching losses. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment comprises a first electrode, a second electrode, a first region, and a second region. The second electrode is separated from the first electrode. The first region is located between the first electrode and the second electrode and is provided on a portion of the first electrode. The first region includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a plurality of third semiconductor regions of a first conductivity type, a gate electrode, a conductive portion, a fourth semiconductor region of a second conductivity type, a fifth semiconductor region of a first conductivity type, and a sixth semiconductor region of a second conductivity type. A portion of the second semiconductor region is provided on the first semiconductor region. The plurality of third semiconductor regions are provided on the portion of the second semiconductor region. The gate electrode faces one of the plurality of third semiconductor regions via a gate insulating layer in a second direction perpendicular to a first direction toward the second electrode. The conductive portion faces another of the plurality of third semiconductor regions via an insulating layer in the second direction and is electrically connected to the second electrode. The fourth semiconductor region is provided on one of the plurality of third semiconductor regions. The fifth semiconductor region is provided on one of the plurality of third semiconductor regions and has a higher impurity concentration of the first conductivity type than one of the plurality of third semiconductor regions. The sixth semiconductor region is provided on another of the plurality of third semiconductor regions. The length of the sixth semiconductor region in the third direction perpendicular to the first and second directions is longer than the length of the fourth semiconductor region in the third direction. The second region is provided on another part of the first electrode between the first electrode and the second electrode. The second region includes a seventh semiconductor region of the second conductivity type, another part of the second semiconductor region, and an eighth semiconductor region of the first conductivity type. The seventh semiconductor region has a higher impurity concentration of the second conductivity type than the second semiconductor region. The other part of the second semiconductor region is provided on the seventh semiconductor region. The eighth semiconductor region is provided on another part of the second semiconductor region. [Brief explanation of the drawing]

[0006] [Figure 1]Figure 1 is a plan view of a semiconductor device according to an embodiment. [Figure 2] Figure 2 is an enlarged plan view of part A of Figure 1. [Figure 3] Figure 3 is a cross-sectional view of the line B1-B2 in Figure 2. [Figure 4] Figure 4 is a cross-sectional view of the line C1-C2 in Figure 2. [Figure 5] Figure 5 is a cross-sectional view taken along the line D1-D2 in Figure 2. [Figure 6] Figure 6 is a plan view showing a part of a semiconductor device according to a reference example. [Figure 7] Figure 7 is a plan view showing a part of a semiconductor device according to a modified example of the embodiment. [Figure 8] Figure 8 is a plan view showing a part of a semiconductor device according to a modified embodiment. [Figure 9] Figure 9 is a plan view showing a part of a semiconductor device according to a modified example of the embodiment. [Figure 10] Figure 10 is a plan view showing a part of a semiconductor device according to a modified example of the embodiment. [Figure 11] Figure 11 is a plan view showing a part of a semiconductor device according to a modified example of the embodiment. [Modes for carrying out the invention]

[0007] The embodiments of the present invention will be described below with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes of the parts, etc., are not necessarily the same as those of reality. Even when representing the same part, the dimensions and ratios may be represented differently in the drawings. In this specification and each drawing, elements similar to those already described are denoted by the same reference numerals, and detailed explanations are omitted as appropriate. In the following explanation, n + , n, n - and p + The notation p represents the relative levels of impurity concentrations in each conductivity type. That is, n + The concentration of n-type impurities is relatively higher in n than in n. -indicates that the impurity concentration of the n-type is relatively lower than that of the n-shaped. Also, p + indicates that the impurity concentration of the p-type is relatively higher than that of the p-shaped. For each embodiment described below, each embodiment may be implemented by reversing the p-type and n-type of each semiconductor region.

[0008] FIG. 1 is a plan view of a semiconductor device according to an embodiment. FIG. 2 is an enlarged plan view of part A in FIG. 1. FIG. 3 is a cross-sectional view taken along the line B1 - B2 in FIG. 2. FIG. 4 is a cross-sectional view taken along the line C1 - C2 in FIG. 2. FIG. 5 is a cross-sectional view taken along the line D1 - D2 in FIG. 2. FIG. 2 corresponds to a cross-sectional view taken along the line E1 - E2 in FIGS. 3 to 5. The semiconductor device according to the embodiment is an RC-IGBT. As shown in FIGS. 1 to 5, the semiconductor device 100 according to the embodiment includes a p + -type (first conductivity type) collector region 1 (first semiconductor region), an n - -type (second conductivity type) base region 2 (second semiconductor region), a p-type base region 3 (third semiconductor region), an n + -type emitter region 4 (fourth semiconductor region), a p + -type contact region 5 (fifth semiconductor region), an n + -type semiconductor region 6 (sixth semiconductor region), an n + -type cathode region 7 (seventh semiconductor region), a p-type anode region 8 (eighth semiconductor region), a p + -type anode region 9, a gate electrode 20, a conductive portion 21, an insulating layer 25, a collector electrode 31 (first electrode), an emitter electrode 32 (second electrode), and a gate pad 33.

[0009] In the description of the embodiment, an XYZ orthogonal coordinate system is used. The direction from the collector electrode 31 to the emitter electrode 3२ is defined as the Z direction (first direction). Two directions that are perpendicular to the Z direction and perpendicular to each other are defined as the X direction (third direction) and the Y direction (second direction). Also, for the sake of explanation, the direction from the collector electrode 31 to the emitter electrode 32 is referred to as "up", and the opposite direction is referred to as "down". These directions are based on the relative positional relationship between the collector electrode 31 and the emitter electrode 32 and are independent of the direction of gravity.

[0010] As shown in Figure 1, emitter electrodes 32 and gate pads 33 are provided on the upper surface of the semiconductor device 100. The emitter electrodes 32 and gate pads 33 are spaced apart from each other. For example, multiple emitter electrodes 32 are provided in the X direction. Gate wiring 33a is provided around each emitter electrode 32. A portion of the gate wiring 33a extends in the Y direction between the emitter electrodes 32. The gate wiring 33a is electrically connected to the gate pads 33.

[0011] As shown in Figures 1 and 2, the semiconductor device 100 includes an IGBT region R1 (first region) and a diode region R2 (second region). In the example shown in Figure 1, multiple IGBT regions R1 and diode regions R2 are provided in the X and Y directions, respectively. In the Y direction, IGBT regions R1 and diode regions R2 are provided alternately.

[0012] As shown in Figures 3 to 5, a collector electrode 31 is provided on the lower surface of the semiconductor device 100. The collector electrode 31 and the emitter electrode 32 are separated from each other, and multiple IGBT regions R1 and multiple diode regions R2 are located between the collector electrode 31 and the emitter electrode 32.

[0013] As shown in Figures 2 to 5, each IGBT region R1 contains p + Shape collector region 1, n - Part of the base region 2, p-type base region 3, n + Shape emitter region 4, p + Shape Contact area 5, n + A shaped semiconductor region 6, a gate electrode 20, and a conductive portion 21 are provided.

[0014] As shown in Figures 3 to 5, p + The collector region 1 is provided on a portion of the collector electrode 31 and is electrically connected to the collector electrode 31. - Part of the shape base region 2 is p + It is located on top of the p-shaped collector region 1. The p-shaped base region 3 is n - A portion of the shaped base region 2 is provided, p+ It is located above the shape collector area 1.

[0015] Multiple p-shaped base regions 3 are provided in the Y direction. Each p-shaped base region 3 extends in the X direction. When viewed from the Z direction, the multiple p-shaped base regions 3 are arranged in a striped pattern. As shown in Figures 3 and 4, the multiple p-shaped base regions 3 include p-shaped base regions 3a and p-shaped base regions 3b. P-shaped base region 3a is one of the multiple p-shaped base regions 3. P-shaped base region 3b is another of the multiple p-shaped base regions 3.

[0016] The gate electrode 20 faces the p-type base region 3a in the Y direction via the gate insulating layer 20a. The conductive portion 21 faces the p-type base region 3b in the Y direction via the insulating layer 21a. + Shape emitter region 4 and p + The shaped contact region 5 is provided on the p-shaped base region 3a. + The p-type impurity concentration in the contact region 5 is higher than the p-type impurity concentration in the p-type base region 3. + The p-type semiconductor region 6 is located on top of the p-type base region 3b.

[0017] n + Shape emitter region 4, p + Shape Contact area 5, n + Multiple p-shaped semiconductor regions 6, gate electrodes 20, and conductive portions 21 are provided in the Y direction. Specifically, multiple gate electrodes 20 face multiple p-shaped base regions 3a in the Y direction. + The p-type emitter region 4 is located on top of multiple p-type base regions 3a. + The contact region 5 is located on top of each of the p-shaped base regions 3a. The conductive parts 21 face each of the p-shaped base regions 3b in the Y direction. + The p-type semiconductor region 6 is located on top of multiple p-type base regions 3b. As shown in the diagram, another multiple p +The shaped contact region 5 may be provided on each of the multiple p-shaped base regions 3b.

[0018] In the illustrated example, multiple p + The shape of the contact area 5 is p + Shaped contact areas 5a and p + Includes contact area 5b. + The contact area 5a is composed of multiple p + It is one of the contact areas 5. + The contact area 5b is composed of multiple p + This is another type of contact region 5. Each gate electrode 20 and each conductive part 21 extends in the X direction. When viewed from the Z direction, the multiple gate electrodes 20 and multiple conductive parts 21 are arranged in a stripe pattern. On one p-shaped base region 3a, n + Shape emitter region 4 and p + The p-shaped contact regions 5a are arranged alternately in the X direction. On one p-shaped base region 3b, + Multiple contact regions 5b are provided in the X direction. + The p-type semiconductor region 6 is located on one p-type base region 3b, along the XY plane (first plane), with each p + It is provided around the contact area 5b.

[0019] As shown in Figure 2, n + The length L2 of the semiconductor region 6 in the X direction is n + The length of the emitter region 4 in the X direction is longer than L1. In the XY plane, n per unit area + The area of ​​the semiconductor region 6 is n per unit area. + It is larger than the area of ​​the emitter region 4.

[0020] p + The length L4 of the contact region 5b in the Y direction is p + The length of the contact region 5a in the Y direction is shorter than L3. In the XY plane, p per unit area + The area of ​​the contact region 5b is p per unit area. +It is smaller than the area of ​​contact region 5a.

[0021] For example, as shown in Figures 2 to 4, the IGBT region R1 includes the first part P1 and the second part P2. p-type base regions 3a, n + Shape emitter region 4, p + The p-shaped contact region 5a and the gate electrode 20 are provided in the first portion P1. p-shaped base region 3b, p + Shaped contact area 5b, n + The shaped semiconductor region 6 and the conductive portion 21 are provided in the second portion P2.

[0022] In the illustrated example, in the IGBT region R1, the first portion P1 and the second portion P2 are alternately arranged in the Y direction. Near the boundary between the IGBT region R1 and the diode region R2, one second portion P2 is located between one first portion P1 and one diode region R2. Note that the position of the boundary between the IGBT region R1 and the diode region R2 in the XY plane is the position of the p in the XY plane. + Shape collector area 1 and n + This corresponds to the position of the boundary with the cathode region 7.

[0023] The emitter electrode 32 is located in the IGBT region R1, with a p-type base region 3 and n + Shape emitter region 4, p + Shape Contact area 5, n + It is electrically connected to the p-type semiconductor region 6 and the conductive portion 21. More specifically, the emitter electrode 32 includes contact portions 32a to 32d that protrude toward the collector electrode 31. In Figure 2, the contact portions 32a to 32d are shown by dashed lines. The contact portion 32a is located on the p-type base region 3a, and n + Shape emitter region 4 and p + It contacts the p-shaped contact area 5a. The contact portion 32b is located on the p-shaped base area 3b, and p + Shaped contact areas 5b and n + The contact portion 32c is located on the conductive portion 21 and is in contact with the conductive portion 21.

[0024] The end of the gate electrode 20 in the X direction is electrically connected to the gate wiring 33a. The gate electrode 20 is electrically connected to the gate pad 33 via the gate wiring 33a. An insulating layer 25 is provided between the gate electrode 20 and the emitter electrode 32. The insulating layer 25 electrically isolates the gate electrode 20 and the emitter electrode 32 from each other.

[0025] Each diode region R2 has n + Shape of cathode region 7, n - Another part of the base region 2, p-shaped anode region 8, p + A shaped anode region 9 and a conductive portion 21 are provided.

[0026] n + The cathode region 7 is located on another part of the collector electrode 31 and is electrically connected to the collector electrode 31. - Another part of the shape base region 2 is n + It is located on top of the cathode region 7. + The concentration of n-type impurities in the cathode region 7 is n - The n-type impurity concentration is higher than that of the base region 2. The p-type anode region 8 is n - Provided on the other part of the shaped base region 2, n + It is located above the cathode region 7.

[0027] The conductive portion 21 faces the p-type anode region 8 in the Y direction via the insulating layer 21a. + The p-shaped anode region 9 is located on top of the p-shaped anode region 8. + The p-type impurity concentration in anode region 9 is higher than that in p-type anode region 8.

[0028] The emitter electrode 32 is in the diode region R2, p-type anode region 8, p + The p-type anode region 9 and the conductive part 21 are electrically connected. The contact portion 32c of the emitter electrode 32 is in contact with the conductive part 21. The contact portion 32d is connected to the p-type anode region 8 and p + It is in contact with the shape of the anode region 9.

[0029] In one diode region R2, p-type anode region 8, p + Multiple p-shaped anode regions 9 and conductive portions 21 are provided in the Y direction. Each p-shaped anode region 8 and each conductive portion 21 extends in the X direction. When viewed from the Z direction, the multiple p-shaped anode regions 8 and multiple conductive portions 21 are arranged in a stripe pattern. + Multiple p-shaped anode regions 9 are provided in the X direction on top of a single p-shaped anode region 8.

[0030] The operation of the semiconductor device 100 will be described. With a positive voltage applied to the collector electrode 31 relative to the emitter electrode 32, a voltage above a threshold is applied to the gate electrode 20. This forms a channel (inversion layer) in the p-type base region 3. Electrons pass through the channel, + Shape emitter region 4 to n - The holes flow into the base region 2, p + Shape collector area 1 to n - It flows into the base region 2. - The carrier density accumulated in the base region 2 increases, causing conductivity modulation. As a result, n - The electrical resistance of the p-type base region 2 decreases significantly, and the IGBT region R1 turns on. Subsequently, when the voltage applied to the gate electrode 20 falls below a threshold, the channel in the p-type base region 3 disappears, and the IGBT region R1 switches to the off state.

[0031] After the IGBT region R1 is switched to the off state, electrons accumulated in the n-type base region 2 are discharged to the collector electrode 31 through the p+-type collector region 1. Holes are discharged to the emitter electrode 32 through the p-type base region 3.

[0032] For example, a bridge circuit is formed by a plurality of semiconductor devices 100. When one semiconductor device 100 switches from an on state to an off state, an induced electromotive force is applied to the emitter electrode 32 of another semiconductor device 100 due to the inductance component of the bridge circuit. As a result, in the said another semiconductor device 100, the diode region R2 operates. Holes flow from the p-type anode region 8 to the n - type base region 2, and electrons flow from the n + type cathode region 7 to the n - type base region 2. The diode region R2 functions as a freewheel diode (FWD).

[0033] As shown in FIGS. 3 to 5, an n-type channel stopper region 10 may be provided between the p + type collector region 1 and the n - type base region 2, and between the n + type cathode region 7 and the n - type base region 2. The n-type impurity concentration of the n-type channel stopper region 10 is lower than the n-type impurity concentration of the n + type cathode region 7 and higher than the n-type impurity concentration of the n - type base region 2. By providing the n-type channel stopper region 10, the spread of the depletion layer in the n - type base region 2 can be more reliably suppressed by the n-type channel stopper region 10.

[0034] An example of the material of each component of the semiconductor device 100 will be described. p + type collector region 1, n - type base region 2, p-type base region 3, n + type emitter region 4, p + type contact region 5, n + type semiconductor region 6, n + type cathode region 7, p-type anode region 8, p +The n-type anode region 9 and the n-type channel stopper region 10 contain silicon, silicon carbide, gallium nitride, or gallium arsenide as semiconductor materials. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as n-type impurities. Boron can be used as p-type impurities.

[0035] The gate electrode 20 and the conductive part 21 contain a conductive material such as polysilicon. The gate insulating layer 20a, insulating layer 21a, and insulating layer 25 contain an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The collector electrode 31, emitter electrode 32, gate pad 33, and gate wiring 33a contain a metal such as titanium or aluminum.

[0036] Figure 6 is a plan view showing a part of a semiconductor device according to a reference example. The semiconductor device 100r shown in Figure 6, in the reference example, is p + Shaped contact area 5 and n + Instead of the shaped semiconductor region 6, p + Shaped contact area 5r and n + A shaped semiconductor region 6r is provided. + Shaped contact area 5r and n + The p-shaped semiconductor region 6r is provided on the p-shaped base region 3b (not shown in Figure 6) facing the conductive portion 21. + The length of the contact region 5r in the X direction is p + It is the same as the length of the contact region 5 in the X direction. + The length of the semiconductor region 6r in the X direction is n + It is the same length as the emitter region 4 in the X direction.

[0037] The advantages of the embodiment will be explained. The semiconductor device 100r is p + Shape collector region 1, n - Shape base region 2, p-shaped base region 3, and n +The device includes a parasitic thyristor consisting of a p-type emitter region 4. When the IGBT region R1 switches to the off state, holes flow into the p-type base region 3. When the potential of the p-type base region 3 rises due to the flow of holes, the parasitic thyristor may activate. When the parasitic thyristor activates, a large current flows through the semiconductor device 100r, destroying the semiconductor device 100r.

[0038] In semiconductor device 100r, in order to suppress the operation of the parasitic thyristor, p + Shaped contact area 5 and p + A contact area 5r is provided. + Shaped contact area 5 and p + The p-type impurity concentration in each contact region 5r is higher than the p-type impurity concentration in the p-type base region 3. When a hole flows into the p-type base region 3, the hole becomes p + Shaped contact area 5 and p + The gas is more easily discharged to the emitter electrode 32 through the contact region 5r. This suppresses the operation of the parasitic thyristor. In other words, the latch-up tolerance of the semiconductor device 100r can be improved.

[0039] On the other hand, the IGBT region R1 is n - It also includes a parasitic diode consisting of a p-type base region 2 and a p-type base region 3. When diode region R2 is ON, the operation of the parasitic diode in IGBT region R1 causes n to be emitted from the emitter electrode 32. - Holes can flow into the base region 2. In particular, p + The electrical resistance between the contact area 5 and the emitter electrode 32, and p + Because the electrical resistance between the contact region 5r and the emitter electrode 32 is low, more holes are n - It flows into the base region 2. As a result, n - The carriers accumulated in the base region 2 increase. When the diode region R2 switches to the off state, n -It takes a longer time to discharge the carriers accumulated in the base region 2. As a result, the switching of the diode region R2 from the on state to the off state becomes slower. The operating speed of the diode region R2 decreases, and the switching loss of the semiconductor device 100r increases.

[0040] Regarding this issue, in the semiconductor device 100 according to the embodiment, in a part of the IGBT region R1, n + Replace the semiconductor region 6r with n + A semiconductor region 6 is provided. + The length L2 of the semiconductor region 6 is n + The length of the emitter region 4 is longer than the length of the diode region R2. - Electrons injected into the p-type base region 2 are directed to the p-type anode region 8 and p + In addition to the shape anode region 9, n + It is also emitted from the semiconductor region 6. + n is longer than the emitter region 4. + When a semiconductor region 6 is provided, n + More electrons can be discharged to the emitter electrode 32 through the semiconductor region 6. Therefore, when the diode region R2 is operating, n - The carrier density accumulated in the base region 2 can be reduced. As a result, the operating speed of the diode region R2 can be improved, and the switching loss of the semiconductor device 100 can be reduced.

[0041] Furthermore, when the diode region R2 is operating, n + Electrons are also emitted from the emitter region 4. + By lengthening the emitter region 4, when the diode region R2 is operating, n - The density of carriers accumulated in the base region 2 can be reduced. However, p + n for contact area 5 + If the emitter region 4 is made longer, n + The potential near the emitter region 4 tends to rise. As a result, the latch-up tolerance of the semiconductor device 100 decreases. +The p-type semiconductor region 6 is located on the p-type base region 3b facing the conductive portion 21. That is, when the IGBT region R1 is ON, no channel is formed in the p-type base region 3b. Therefore, even if the potential of the p-type base region 3b rises when the IGBT region R1 is turned off, the parasitic thyristor does not operate. + The shape emitter region is n, not 4. + By making the semiconductor region 6 longer, the switching loss of the semiconductor device 100 can be reduced while suppressing the decrease in the latch-up withstand capability of the semiconductor device 100.

[0042] As shown in Figure 2, p + The length L4 of the contact area 5b is p + It is preferable that the length of the contact region 5a is shorter than the length L3. When the diode region R2 is operating, the parasitic diode of the IGBT region R1 has p + Holes are injected through the contact region 5. By making length L4 shorter than length L3, p + This suppresses the injection of holes through the contact region 5b. - The density of carriers accumulated in the base region 2 can be further reduced. Also, p + The p-type contact region 5b is located on top of the p-type base region 3b. If the length L4 is short, the potential of the p-type base region 3b tends to rise when the IGBT region R1 is turned off. However, as mentioned above, the parasitic thyristor does not operate even if the potential of the p-type base region 3b rises. By making the length L4 shorter than the length L3, the decrease in latch-up tolerance can be further suppressed while further reducing the switching loss of the semiconductor device 100.

[0043] In at least one of the IGBT region R1 and the diode region R2, n - One or more elements selected from the group consisting of hydrogen, helium, and platinum may be ion-implanted into the shape base region 2. - By being injected into the shape base region 2, n -The lifetime in the base region 2 can be shortened. This further reduces the switching loss of the semiconductor device 100. Instead of element injection, n - The base region 2 may be irradiated with an electron beam. Due to the irradiation of the electron beam, n - Crystal defects are formed in the shape base region 2. The higher the density of crystal defects, the more n - The lifetime in the shape-based region 2 is shortened.

[0044] Figures 7 to 11 are plan views showing a part of a semiconductor device according to a modified embodiment. The arrangement of the first part P1 and the second part P2 is not limited to the examples shown in Figures 2 to 4 and can be changed as appropriate. For example, in the semiconductor device 110 shown in Figure 7, the first part P1 is located between the second part P2 and the diode region R2 near the boundary between the IGBT region R1 and the diode region R2. Regardless of the positions of the first part P1 and the second part P2, n is located on the p-type base region 3b. + n is longer than the emitter region 4. + A semiconductor region 6 is provided. This makes it possible to reduce the switching loss of the semiconductor device 110 while suppressing a decrease in the latch-up withstand capability of the semiconductor device 110.

[0045] However, as shown in Figure 2, it is more preferable that the second portion P2 is located between the first portion P1 and the diode region R2. The closer the second portion P2 is to the diode region R2, the better n + The emission of electrons through the semiconductor region 6 can be made larger. Also, the further the first part P1 moves away from the diode region R2, p + This suppresses the injection of holes through the contact region 5a. - The density of carriers accumulated in the shape-based region 2 can be further reduced.

[0046] The number of p-type base regions 3a and gate electrodes 20 provided in one first portion P1 is arbitrary. The number of p-type base regions 3a and gate electrodes 20 may differ for each first portion P1. Similarly, the number of p-type base regions 3b and conductive parts 21 provided in one second portion P2 is arbitrary. The number of p-type base regions 3b and conductive parts 21 may differ for each second portion P2. In the semiconductor device 120 shown in Figure 8, more conductive parts 21 are provided in one second portion P2 compared to the semiconductor device 100 shown in Figure 2.

[0047] Preferably, the length L5 of the second portion P2 in the Y direction is longer than the distance D1 (shown in Figure 4) in the Z direction between the collector electrode 31 and the emitter electrode 32. When the length L5 is longer than the distance D1, the first portion P1 can be sufficiently separated from the diode region R2. The longer the distance between the first portion P1 and the diode region R2, the greater the distance from the parasitic diode of the first portion P1 to the diode region R2. + The flow of holes into the cathode region 7 becomes difficult. When the diode region R2 is operating, p + Shaped contact area 5a to n - The injection of holes into the base region 2 can be suppressed. Also, by providing the second portion P2 to be sufficiently long, when the diode region R2 is operating, n + This promotes the emission of electrons through the semiconductor region 6. This further reduces the switching loss of the semiconductor device 120.

[0048] As shown in Figure 9, semiconductor device 130, p + Shaped contact areas 5b and n + The type semiconductor region 6 may be different from that of the semiconductor device 100. In the semiconductor device 130, on the p-type base region 3b (not shown), + Shaped contact areas 5b and n + The semiconductor regions 6 and shaped are alternately arranged in the X direction. However, n + The length L2 of the semiconductor region 6 in the X direction is n +The shape is longer than the length L1 in the X direction of the emitter region 4. According to the semiconductor device 130, similar to the semiconductor device 100, switching losses can be reduced while suppressing a decrease in latch-up tolerance.

[0049] More preferably, as in the semiconductor device 100 shown in Figure 2, each p + One large n around the contact area 5b + A semiconductor region 6 is provided. According to the structure shown in Figure 2, in the XY plane, n per unit area + The area of ​​the semiconductor region 6 can be made larger, and p per unit area + The area of ​​the contact region 5b can be made smaller. + The larger the area of ​​the semiconductor region 6, or p + The smaller the area of ​​the contact region 5b, the less n is required when the diode region R2 is operating. - The carriers accumulated in the base region 2 can be reduced. Therefore, the structure of semiconductor device 100 can further reduce switching losses compared to the structure of semiconductor device 130.

[0050] As shown in Figure 10, in the semiconductor device 140, in the second part P2, p + The p-type contact region 5b may be omitted. In semiconductor device 140, the entire area above the p-type base region 3b is n + A semiconductor region 6 is provided. Compared to the structure of semiconductor device 100, the switching loss can be further reduced with semiconductor device 140.

[0051] As shown in Figure 11, in the semiconductor device 150, in the diode region R2, the entire surface of the p-type anode region 8 is p + A shaped anode region 9 may be provided. + The larger the area of ​​the anode region 9, the more carriers are present during the operation of the diode region R2. - It is injected into the base region 2. Compared to the structure of semiconductor device 120, the on-resistance of the diode region R2 during operation can be reduced with semiconductor device 150.

[0052] On the other hand, n - As carrier injection into the shape-based region 2 increases, n - The carriers accumulated in the base region 2 also increase. As a result, the switching loss of the semiconductor device 150 may increase. However, according to an embodiment of the present invention, during the operation of the diode region R2, n + More electrons can be discharged to the emitter electrode 32 through the semiconductor region 6. + Even if the area of ​​the anode region 9 increases, the increase in switching loss of the semiconductor device 150 can be suppressed.

[0053] Embodiments of the present invention include the following configurations. (Composition 1) First electrode and, A second electrode separated from the preceding first electrode, A first region provided between the first electrode and the second electrode, on a part of the first electrode, The first semiconductor region of the first conductivity type, A second semiconductor region of a second conductivity type, a portion of which is provided on the first semiconductor region, A plurality of third semiconductor regions of a first conductivity type are provided on a portion of the second semiconductor region, In a second direction perpendicular to the first direction toward the second electrode from the first electrode, a gate electrode faces one of the plurality of third semiconductor regions via a gate insulating layer, In the second direction, a conductive portion faces another of the plurality of third semiconductor regions via an insulating layer and is electrically connected to the second electrode, A fourth semiconductor region of a second conductivity type is provided on one of the plurality of third semiconductor regions, A fifth semiconductor region of a first conductivity type is provided on one of the plurality of third semiconductor regions and has a higher impurity concentration of the first conductivity type than one of the plurality of third semiconductor regions, A sixth semiconductor region of a second conductivity type is provided on one of the plurality of third semiconductor regions, and its length in the third direction perpendicular to the first and second directions is longer than that of the fourth semiconductor region. The first region including, A second region provided between the first electrode and the second electrode, on another part of the first electrode, A seventh semiconductor region of the second conductivity having a higher impurity concentration of the second conductivity than the aforementioned second semiconductor region, Another part of the second semiconductor region provided on the seventh semiconductor region, An eighth semiconductor region of a first conductivity type is provided on another part of the second semiconductor region, The second region including, A semiconductor device equipped with the following features. (Configuration 2) The semiconductor device according to configuration 1, wherein the fourth semiconductor region and the fifth semiconductor region are arranged alternately in the third direction. (Composition 3) The fifth semiconductor region is provided on each of the plurality of third semiconductor regions, The semiconductor device according to configuration 1 or 2, wherein the length in the second direction of the fifth semiconductor region located on one of the plurality of third semiconductor regions is longer than the length in the second direction of one of the plurality of fifth semiconductor regions located on one of the plurality of third semiconductor regions. (Composition 4) The fifth semiconductor region is provided in multiple locations in the third direction on one of the plurality of third semiconductor regions. The semiconductor device according to configuration 3, wherein the sixth semiconductor region is provided around each of the plurality of fifth semiconductor regions along a first plane perpendicular to the first direction. (Composition 5) The first region is, The plurality of third semiconductor regions, one of the fourth semiconductor region, the fifth semiconductor region, and the first portion on which the gate electrode is provided, The plurality of third semiconductor regions, one of the others, the sixth semiconductor region, and the second portion provided with the conductive part, Includes, The second part is a semiconductor device according to any one of configurations 1 to 4, located between the first part and the second region. (Composition 6) The semiconductor device according to configuration 5, wherein the length of the second portion in the second direction is longer than the distance between the first electrode and the second electrode in the first direction.

[0054] According to each embodiment described above, a semiconductor device capable of reducing switching losses is provided.

[0055] The relative levels of impurity concentrations between semiconductor regions in each embodiment can be confirmed, for example, using an SCM (Scanning Capacitive Microscope). The carrier density in each semiconductor region can be considered equal to the concentration of activated impurities in that region. Therefore, the relative levels of carrier densities between semiconductor regions can also be confirmed using an SCM. Furthermore, the impurity concentration in each semiconductor region can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry).

[0056] Although several embodiments of the present invention have been illustrated above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. Furthermore, the embodiments described above can be implemented in combination with each other. [Explanation of Symbols]

[0057] 1:p + Collector area, 2:n - Shape base region, 3,3a,3b: p-shaped base region, 4: n + Shape emitter region, 5,5a,5b,5r:p + Shape of contact area, 6,6r:n + Semiconductor region, 7:n + 8:p-type cathode region, 8:p-type anode region, 9:p +10: n-type anode region, 20: n-type channel stopper region, 20: gate electrode, 20a: gate insulating layer, 21: conductive part, 21a: insulating layer, 25: insulating layer, 31: collector electrode, 32: emitter electrode, 32a~32d: contact area, 33: gate pad, 33a: gate wiring, 100, 100r, 110~140: semiconductor device, D1: distance, P1: first part, P2: second part, R1: IGBT region, R2: diode region

Claims

1. First electrode and A second electrode separated from the first electrode, A first region provided between the first electrode and the second electrode, on a part of the first electrode, The first semiconductor region of the first conductivity type, A second semiconductor region of a second conductivity type, a portion of which is provided on the first semiconductor region, A plurality of third semiconductor regions of a first conductivity type are provided on a portion of the second semiconductor region, In a second direction perpendicular to the first direction toward the second electrode from the first electrode, a gate electrode faces one of the plurality of third semiconductor regions via a gate insulating layer, In the second direction, a conductive portion faces another of the plurality of third semiconductor regions via an insulating layer and is electrically connected to the second electrode, A fourth semiconductor region of a second conductivity type is provided on one of the plurality of third semiconductor regions, A fifth semiconductor region of a first conductivity type provided on one of the plurality of third semiconductor regions, having a higher impurity concentration of the first conductivity type than one of the plurality of third semiconductor regions, wherein the fourth semiconductor region and the fifth semiconductor region are alternately provided in a third direction perpendicular to the first and second directions, A sixth semiconductor region of a second conductivity type is provided on one of the plurality of third semiconductor regions, and its length in the third direction is longer than that of the fourth semiconductor region. The first region including, A second region provided between the first electrode and the second electrode, on another part of the first electrode, A seventh semiconductor region of the second conductivity having a higher impurity concentration of the second conductivity than the second semiconductor region, Another part of the second semiconductor region provided on the seventh semiconductor region, An eighth semiconductor region of a first conductivity type is provided on another part of the second semiconductor region, The second region including, A semiconductor device equipped with the following features.

2. First electrode and A second electrode separated from the first electrode, A first region provided between the first electrode and the second electrode, on a part of the first electrode, The first semiconductor region of the first conductivity type, A second semiconductor region of a second conductivity type, a portion of which is provided on the first semiconductor region, A plurality of third semiconductor regions of a first conductivity type are provided on a portion of the second semiconductor region, In a second direction perpendicular to the first direction toward the second electrode from the first electrode, a gate electrode faces one of the plurality of third semiconductor regions via a gate insulating layer, In the second direction, a conductive portion faces another of the plurality of third semiconductor regions via an insulating layer and is electrically connected to the second electrode, A fourth semiconductor region of a second conductivity type is provided on one of the plurality of third semiconductor regions, A fifth semiconductor region of a first conductivity type is provided on one of the plurality of third semiconductor regions and has a higher impurity concentration of the first conductivity type than one of the plurality of third semiconductor regions, A sixth semiconductor region of a second conductivity type is provided on one of the plurality of third semiconductor regions, and its length in the third direction perpendicular to the first and second directions is longer than that of the fourth semiconductor region. The first region including, A second region provided between the first electrode and the second electrode, on another part of the first electrode, A seventh semiconductor region of the second conductivity having a higher impurity concentration of the second conductivity than the second semiconductor region, Another part of the second semiconductor region provided on the seventh semiconductor region, An eighth semiconductor region of a first conductivity type is provided on another part of the second semiconductor region, The second region including, Equipped with, The first region is, The plurality of third semiconductor regions, one of the fourth semiconductor region, the fifth semiconductor region, and the first portion on which the gate electrode is provided, The plurality of third semiconductor regions, one of the others, the sixth semiconductor region, and the second portion provided with the conductive part, Includes, The second portion is a semiconductor device located between the first portion and the second region.

3. First electrode and A second electrode separated from the first electrode, A first region provided between the first electrode and the second electrode, on a part of the first electrode, The first semiconductor region of the first conductivity type, A second semiconductor region of a second conductivity type, a portion of which is provided on the first semiconductor region, A plurality of third semiconductor regions of a first conductivity type are provided on a portion of the second semiconductor region, In a second direction perpendicular to the first direction toward the second electrode from the first electrode, a gate electrode faces one of the plurality of third semiconductor regions via a gate insulating layer, In the second direction, a conductive portion faces another of the plurality of third semiconductor regions via an insulating layer and is electrically connected to the second electrode, A fourth semiconductor region of a second conductivity type is provided on one of the plurality of third semiconductor regions, A fifth semiconductor region of a first conductivity type provided on one of the plurality of third semiconductor regions, having a higher impurity concentration of the first conductivity type than one of the plurality of third semiconductor regions, wherein the fourth semiconductor region and the fifth semiconductor region are alternately provided in a third direction perpendicular to the first and second directions, A sixth semiconductor region of a second conductivity type is provided on one of the plurality of third semiconductor regions and has a higher impurity concentration of the second conductivity type than that of the plurality of third semiconductor regions. The first region includes, and in a first plane perpendicular to the first direction, the area of ​​the sixth semiconductor region per unit area is greater than the area of ​​the fourth semiconductor region per unit area, A second region provided between the first electrode and the second electrode, on another part of the first electrode, A seventh semiconductor region of the second conductivity having a higher impurity concentration of the second conductivity than the second semiconductor region, Another part of the second semiconductor region provided on the seventh semiconductor region, An eighth semiconductor region of a first conductivity type is provided on another part of the second semiconductor region, The second region including, A semiconductor device equipped with the following features.

4. First electrode and A second electrode separated from the first electrode, A first region provided between the first electrode and the second electrode, on a part of the first electrode, The first semiconductor region of the first conductivity type, A second semiconductor region of a second conductivity type, a portion of which is provided on the first semiconductor region, A plurality of third semiconductor regions of a first conductivity type are provided on a portion of the second semiconductor region, In a second direction perpendicular to the first direction toward the second electrode from the first electrode, a gate electrode faces one of the plurality of third semiconductor regions via a gate insulating layer, In the second direction, a conductive portion faces another of the plurality of third semiconductor regions via an insulating layer and is electrically connected to the second electrode, A fourth semiconductor region of a second conductivity type is provided on one of the plurality of third semiconductor regions, A fifth semiconductor region of a first conductivity type is provided on one of the plurality of third semiconductor regions and has a higher impurity concentration of the first conductivity type than one of the plurality of third semiconductor regions, A sixth semiconductor region of a second conductivity type is provided on one of the plurality of third semiconductor regions and has a higher impurity concentration of the second conductivity type than that of the plurality of third semiconductor regions. The first region includes, and in a first plane perpendicular to the first direction, the area of ​​the sixth semiconductor region per unit area is greater than the area of ​​the fourth semiconductor region per unit area, A second region provided between the first electrode and the second electrode, on another part of the first electrode, A seventh semiconductor region of the second conductivity having a higher impurity concentration of the second conductivity than the second semiconductor region, Another part of the second semiconductor region provided on the seventh semiconductor region, An eighth semiconductor region of a first conductivity type is provided on another part of the second semiconductor region, The second region including, Equipped with, The first region is, The plurality of third semiconductor regions, one of the fourth semiconductor region, the fifth semiconductor region, and the first portion on which the gate electrode is provided, The plurality of third semiconductor regions, one of the others, the sixth semiconductor region, and the second portion provided with the conductive part, Includes, The second portion is a semiconductor device located between the first portion and the second region.

5. The semiconductor device according to claim 2 or 4, wherein the fourth semiconductor region and the fifth semiconductor region are alternately provided in a third direction perpendicular to the first and second directions.

6. The semiconductor device according to claim 2 or 4, wherein the length of the second portion in the second direction is longer than the distance between the first electrode and the second electrode in the first direction.

7. The fifth semiconductor region is provided on each of the plurality of third semiconductor regions, The semiconductor device according to any one of claims 1 to 4, wherein the length in the second direction of the fifth semiconductor region located on one of the plurality of third semiconductor regions is shorter than the length in the second direction of another fifth semiconductor region located on one of the plurality of third semiconductor regions.

8. The fifth semiconductor region is provided in multiple locations in the third direction on one of the plurality of third semiconductor regions. The semiconductor device according to claim 7, wherein the sixth semiconductor region is provided around each of the plurality of fifth semiconductor regions along a first plane perpendicular to the first direction.

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