Power semiconductor module

Abstract

The present disclosure relates to a power semiconductor module (1), comprising at least two groups (2, 3; 31, 32, 33, 34) of semiconductor switches (4) connected in parallel, the semiconductor switches (4) of each group being connected in parallel within the group (2, 3; 31, 32, 33, 34), a module gate contact (5), group gate contacts (6, 7) of each group, a first branch point (8) connected to the module gate contact (5) and the group gate contact (6, 7), a gate path between the module gate contact (5) and the first branch point (8) shared for the at least two groups (2, 3; 31, 32, 33, 34) of semiconductor switches, and a compensation structure (9; 39) for increasing an inductance of a connection path in the connection path between the first branch point (8) and a gate terminal (10) of a semiconductor switch (4) of at least one group (3) of the semiconductor switches (4).

Description

Technical Field

[0001] Description The present disclosure relates to a power semiconductor module including at least two parallel groups of semiconductor switches, with the semiconductor switches in each group being connected in parallel. From European Patent Application Publication No. 3113223, power semiconductor modules are known in which several power semiconductor switches are connected using separate substrate metallizations arranged in a stacked manner.

Background Art

[0002] To obtain lower switching losses in a power module, it is an option in principle to use wide-bandgap semiconductors with a high-speed switching operation. However, the use of high-speed switching semiconductors poses new challenges to the design of the module. In addition, the area of a typical wide-bandgap semiconductor device is considerably smaller than the area of today's Si devices, and thus, when aiming for a higher current rating, many of them need to be connected in parallel.

[0003] U.S. Patent Application Publication No. 2011 / 233608 discloses a switching device having a balancing unit arranged outside a semiconductor module. Japanese Unexamined Patent Application Publication No. 2005-129826 shows a switching configuration having a compensating resistor. U.S. Patent Application Publication No. 2020 / 185359 targets a semiconductor module having compensating means. U.S. Patent Application Publication No. 2018 / 123478 discloses a switching configuration having an artificially extended connection path. European Patent Application Publication No. 3113223 shows a power semiconductor module having a stacked configuration of several layers.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The objective is to provide a power semiconductor module that is based on a wide-bandgap semiconductor, equipped with a large number of semiconductor switches connected in parallel, and having high-speed switching operation. [Means for solving the problem]

[0005] According to one embodiment, this objective is achieved by a semiconductor module, and the semiconductor module is - At least two groups of semiconductor switches connected in parallel, wherein the semiconductor switches in each group are connected in parallel within the group, - Module gate contacts, -Group gate contacts for each group, - A first inner branch point connected to a module gate contact and a group gate contact, - A connection path between the external gate contact and the internal branch point, which is shared for at least two groups of semiconductor switches. - A compensation structure for increasing the inductance of the connection path between a first branch point and the gate terminal of at least one group of semiconductor switches, It is equipped with.

[0006] The described embodiment has an improved gate connection, which allows the proposed compensation structure to better match the gate inductances of different groups of semiconductor switches. Even for multiple semiconductor switches connected in parallel, improved switching operation can be achieved with shorter switching times, less oscillation, and lower power loss.

[0007] The compensation structure results in an artificial extension of the gate path. This artificial extension means the connection is longer than required for the electrical connection and is suitable for a substantial effect on the inductance of the path between the first branch point and the gate terminals of at least one group of semiconductor switches. A substantial effect means the inductance increases by, for example, more than 5%, more than 10%, or more than 20% compared to the gate path section without such an artificial extension. If higher compensation is required, the extension can also exceed 50%, 100%, or 150%.

[0008] An advantage of this embodiment is that the connection between the module gate contact and the branch point can be used to connect all gate terminals, and therefore the space required within the module is minimized.

[0009] In addition, the connection between the group gate contact and the gate terminal of the semiconductor switch can also be configured without additional corrective measures. To obtain better switching performance, it is primarily important to adjust the connection between the branch point and the group gate contact.

[0010] Another advantage of the proposed embodiment is that, while it is not necessary to minimize the absolute value of the inductance, improvements can be achieved simply by reducing the difference in inductance across the connection paths to different groups of semiconductor switches.

[0011] A further advantage of the proposed embodiment is that resistors typically used to dampen vibrations between semiconductor switches can be omitted or at least reduced. This improves switching operation, for example, by reducing losses.

[0012] By sufficiently reducing vibration, it is at least possible to replace thick-film resistors with semiconductor-based resistors, which simplifies module manufacturing and reduces manufacturing costs.

[0013] According to a more detailed embodiment, the compensation structure comprises a meandering structure formed within the metallization layer, a helical structure formed within the metallization layer, and / or meandering wires connecting islands formed within the metallization layer, or this can be a separate device such as an inductor. All of these techniques enable good adjustment of inductance without requiring much additional space within the module.

[0014] In a further embodiment, at least one group gate contact is configured as a compensation structure. Such a group gate contact is often provided with a relatively large surface area sufficient to form the compensation structure. Therefore, no additional space is required within the module.

[0015] In an alternative embodiment, the compensation structure is located between the first branch point and at least one group gate contact, allowing for a flexible configuration without changing the group gate contact configuration.

[0016] In a further embodiment, the compensation structure is implemented only for groups of semiconductor switches where the geometric distance to the branch point is shorter than that of other groups. This means that the inductance of the shorter connection path is adjusted to better match that of the longer connection path.

[0017] In further embodiments, essentially the same compensation structure is applied to the group gate contacts of several groups of semiconductor switches. The compensation effect is selective, i.e., it is individual for each of the relevant groups that is attenuated or neutralized by at least partially excluding the compensation structure from the gate path. For example, a shortcut by bond wire can neutralize or attenuate the compensation effect depending on where the group of semiconductor switches is located within the module. Since the structure of the metallization layer of the group gate contacts is the same for all groups, manufacturing costs can be reduced.

[0018] In the embodiments described, it is advantageous to use at least one of a MOSFET, MISFEST, JFET, or IGBT based on a wide bandgap material such as Si, SiC, or GaN as the semiconductor switch.

[0019] This disclosure includes further embodiments of gate connection improvements, which involve reducing the inductance of connections within a module. According to this embodiment, bond wire connections of gate and source paths are replaced by interconnect bridges in which conductive layers are used for the gate and source paths. The proposed layer structure comprises insulating layers placed between conductive layers. The gate and source paths belong to the same control loop, and the inductance can be reduced according to the physics of parallel conductors. The thickness of the insulating layer is less than 150 μm, and more preferably less than 80 μm.

[0020] This embodiment can be applied in addition to the inductance increase described above. This reduces the inductance in some gate connections and increases the inductance in some other gate connections, thereby reducing the overall gate inductance. This makes it possible to bring the difference between the maximum and minimum inductance to almost zero. However, reducing the inductance difference is also a very effective means of avoiding vibration and enabling high-speed switching operation. In very good cases, gate resistors provided to suppress vibration can be omitted. This further improves the performance of the power semiconductor module.

[0021] Even if each feature is not explicitly mentioned in the context of a particular embodiment, all features described in relation to one embodiment are also disclosed herein in relation to other embodiments.

[0022] The attached drawings are included to provide further understanding. In the drawings, elements of the same structure and / or function may be referred to by the same reference numerals. Please understand that the embodiments shown in the drawings are illustrative and not necessarily drawn to a specific scale.

Brief Description of the Drawings

[0023] [Figure 1] It is a schematic diagram of a first embodiment of a power semiconductor module. [Figure 2] It is a diagram showing the effect on the gate inductance of the first embodiment. [Figure 3] A second exemplary embodiment is shown. [Figure 4] The vertical structure of the embodiment of FIG. 3 is shown. [Figure 5] An exemplary embodiment of a compensation structure is shown. [Figure 6] An exemplary embodiment of a compensation structure is shown. [Figure 7] An exemplary embodiment of a compensation structure is shown. [Figure 8] An embodiment of a compensation structure with attenuation of the compensation effect is shown. [Figure 9] It is a schematic diagram of a further embodiment of a power module. [Figure 10] A compensation structure having two compensation outputs is shown. [Figure 11] It is a further embodiment having an additional interconnection bridge. [Figure 12] An interconnection bridge is shown. [Figure 13] It is a diagram showing the details of the interconnection bridge of FIG. 12.

Modes for Carrying Out the Invention

[0024] FIG. 1 is a schematic diagram of a power module 1 including two groups 2, 3 of semiconductor switches 4. The gate terminals 10 of the semiconductor switches 4 are connected to the module gate contact 5. The length of the conduction path between the module gate contact 5 and the gate terminals 10 of the semiconductor switches 4 depends on the geometric arrangement of the components within the module. For example, when providing two or more groups of semiconductor switches, it is not possible to make the lengths of the connection paths equal for each group of semiconductor switches.

[0025] The unequal lengths of the conductive paths became a problem when the use of wide-bandgap semiconductors such as silicon carbide (SiC) or gallium nitride (GaN) became more common to overcome the limitations of silicon-based power semiconductor devices. Exemplarily, silicon carbide and gallium nitride-based devices are attractive due to their high-speed switching capability and resulting low switching losses. When many wide-bandgap semiconductor switches were used in modules, strong vibrations within the module were observed. To dampen such vibrations, resistors are commonly used in the gate path. In many cases, a 5Ω resistor is sufficient to suppress the vibrations. However, providing such resistors requires the use of thick-film technology, which means additional manufacturing steps are necessary. While it is possible to suppress vibrations in this way, the initial advantage of wide-bandgap semiconductors, namely their high-speed switching capability, cannot be fully utilized.

[0026] According to this disclosure, the objective is not to suppress vibration, but to avoid vibration by providing an improved design. Thus, this approach equalizes inductance in connection paths rather than minimizing them, which is difficult with limited design options. The switching capability of a power semiconductor module also depends on the total inductance of the gate path, but vibration strongly depends on the inductance differences in the paths to different groups of semiconductor switches.

[0027] In other words, in order to enable high-speed switching, the module's stray inductance must be low enough to avoid critical voltage overshoot, and the inductance imbalance must be low enough to avoid oscillations between semiconductor switches.

[0028] The inductance of the gate path of the first group 2 can be expressed as shared inductance L_shared + interconnection inductance L_interconnection + inductance L1, and the inductance of the second gate path can be expressed as shared inductance L_shared + L2. As can be seen from Figure 1, the path to the second group 3 includes a compensation structure 9 used to increase the inductance of this connection path in order to equalize the total inductance of the gate path to the first group 2 and the gate path to the second group 3.

[0029] Assuming that a typical 1 mm bond wire increases the gate path inductance by approximately 1 nH, the difference in gate inductance between semiconductor switches can easily exceed 10 nH. In certain module designs, for example, the difference in inductance within a group of semiconductor switches may be negligible, while shared inductance may be dominant. This means that for a more balanced inductance situation, the focus should be on interconnect inductance.

[0030] The proposed features are beneficial, for example, in the design of complex high-power modules based on many silicon carbide or gallium nitride devices arranged in parallel on several substrates. However, they can also be implemented in other smaller power modules, such as those shown in Figure 1.

[0031] In the schematic diagram of Figure 1, group gate contacts 6 and 7 are mounted. In the context of this application, a group gate contact is a common point of connection to the gate terminals of semiconductor switches belonging to this group. When multiple similar semiconductor switches are arranged on a common substrate, each substrate has a common group gate contact. It is also possible to combine several substrates into a submodule. The geometric arrangement of group gate contacts with respect to the semiconductor switches of a group is often similar for all groups included in the power semiconductor module 1, but the length of the connection path from the module gate contact to the group gate contact may differ between groups. The shared inductance L_shared mentioned above means that the first portion of the connection path to the gate terminal is used in common up to the branching point where the paths to different groups diverge.

[0032] In Figure 1, the connection path to the first group 2 is much longer than the connection path to the second group 3; therefore, the total inductance of the first group 2 is higher than the total inductance of the second group 3. As a result, a compensation structure 9 is implemented in the connection path between the branch point 8 and the gate terminal of the semiconductor switch 4 of the second group 3. In this embodiment, the compensation structure 9 comprises a serpentine structure formed in the metallization layer.

[0033] Figure 2 shows the effect of the compensation structure in such an embodiment. For example, 10 semiconductor switches (4) on one substrate of the module and another 10 semiconductor switches (4) on the other substrate of the module can be grouped together. The 20 semiconductor devices (4) located on both substrates are connected in parallel. In a half-bridge module configuration, the two such substrates represent either the upper or lower side of the module. Two other such substrates connected in parallel form the other semiconductor switches of this half-bridge module. Thus, in such an embodiment, there are 40 semiconductor switches arranged in four groups (two and two connected in parallel).

[0034] In Figure 2, the maximum relative gate inductance (%) is shown for each semiconductor switch placed on one of two parallel-connected substrates. Semiconductor switches 1 to 10 belong to the first group and are placed on one substrate in this embodiment, while semiconductor switches 11 to 20 belong to the second group and are placed on the other substrate. As can be seen from the dashed line 17 showing the gate inductance of the power semiconductor module without the compensation structure, the maximum difference in gate inductance is 22%, but the difference within the group is only 7%. By using the compensation structure 9, as can be seen from the solid line 18, the inductance of the gate path of the second group increases. In the arrangement with the compensation structure, the maximum difference in gate inductance is only 11 nH, which is about half the difference in gate inductance without the compensation structure.

[0035] A further benefit is the reduction of vibration, which in turn increases the switching speed. The applicant's measurements show that the amplitude of gate voltage vibration can be reduced by approximately 70%. Because vibration is reduced, power loss over the switching time can also be reduced.

[0036] Another positive effect of using the concepts of this disclosure is that the resistor can be reduced to a value of at least less than 2Ω. Such resistors can be implemented as semiconductor-based resistors and do not require additional manufacturing steps during module assembly.

[0037] Figure 3 shows a more detailed view of the semiconductor switch group 4. The semiconductor switch 4 is located on a metallization layer 12 of a common substrate 11. The first metallization layer 12 is used as a drain connection. In the stacked configuration of this embodiment, a second substrate 20 having a second metallization layer 21 is located on the first metallization layer 12 or the first substrate 11. The source terminal 22 of the semiconductor switch 4 is connected to the second metallization layer 21 by a bond wire 25.

[0038] A third substrate 23 having a third metallization layer 24 is placed on the metallization layer 21. The third metallization layer 24 is used as a busbar for connecting the gate terminal 10 of the semiconductor switch 4. The connection between the gate terminal 10 and the metallization layer is made by bond wire 26. Smaller portions of the third metallization layer 24 are isolated to form a group gate contact 6. The third metallization layer 24 is connected to the group gate contact 6 via a resistor 29 and bond wire.

[0039] The second group 3 is substantially the same as the first group 2. The difference is that the first group 2 does not have a structural component, while the group gate contact 7 of the second group 3 is modified by a compensation structure 9. Details of the compensation structure are shown in Figures 5 to 9.

[0040] The vertical structure of the configuration in Figure 3 is shown in Figure 4. This exemplary embodiment relates to a MOSFET-based configuration using SiC. For such wide-bandgap semiconductors, the main advantages are assumed. However, this solution may also be beneficial and considered for Si-based power modules and other types of semiconductor switches when an improved balance of gate inductance is required.

[0041] A substrate 11 having a metallization layer 12 on its upper surface is provided on the bottom surface. A semiconductor switch 4 having a source terminal 22 and a gate terminal 10 is arranged on the metallization layer 12. The source terminal 22 is connected to a second metallization layer 21 by a bond wire 25, and the gate terminal 10 is connected to a metallization layer 24 by a bond wire 26.

[0042] Figures 5, 6, and 7 show different configurations of the compensation structure 9 that can be applied to the group gate contact 7 of Figure 3. The metallization layer 24 on the third substrate 23 is designed to form a meandering structure. As is clear from Figure 5, the current path from the first contact 27 to the second contact 28 is much longer than the straight line from point 27 to point 28. The configuration of Figure 5 can be easily used as a replacement or modification for the group gate contact 6 or 7. Traces coming from the module gate contact 5 are connected to contact 27 of the compensation structure 9, but contact 28 is connected to a resistor 29 via another bond wire, and then to the third metallization layer 24, or, if no resistor is used, contact 28 is in direct contact with the metallization layer 24.

[0043] Figure 6 shows another embodiment. In this embodiment, the island 16 is provided on the substrate 23, and the incoming contact 27 is connected to the island via bond wire 15, for example, in a meandering configuration.

[0044] In another alternative embodiment shown in Figure 7, a helical configuration is used for the same purpose to increase the inductance of the path between contacts 27 and 28. Contact 27 is connected to the center point of the helix by a bond wire 17.

[0045] Furthermore, the inductance of the gate path can also be increased by adding discrete devices that increase inductance.

[0046] It should be noted that the configurations in Figures 5, 6, and 7 can be combined in further embodiments.

[0047] In further embodiments, the effect of the compensation structure can be attenuated or neutralized by excluding or partially excluding the compensation structure from the gate path. This is shown in Figure 8, where the bond wire 18 is connected to approximately the center of the helical path rather than the center point of the helical compensation structure, and as a result, the connection path through the compensation structure is still longer than the straight line between points 27 and 28, but not as long as possible. Such a configuration can be used, for example, when essentially the same structure in the metallization layer should be applied to several group gate contacts, but the increase in inductance must vary depending on the location of the group of semiconductor switches in the module and the length of the conductive path to the gate contacts of the module.

[0048] Another embodiment is shown in Figure 9. According to this embodiment, four semiconductor groups 31 to 34 are provided. Two groups each form submodules 35 and 36. Additional groups of semiconductor switches can be arranged on the back surface of the submodules. In such an embodiment, eight groups of semiconductor switches are used. Similar configurations can be used for power semiconductors with fewer or more groups.

[0049] In the embodiment shown in Figure 9, two levels of branching points are provided. Between the module gate contact 5 and the first branching point 8, the gate path is shared for all semiconductor switches. At the first branching point 8, the gate path is divided for the first submodule 35 and the second submodule 36. At the left branch, a second branching point 37 is provided, and the gate path is divided for the first group of semiconductor switches 31 and the second group 32. The same applies to the second submodule 36, where a third branching point 38 is provided. The third branching point 38 is a simple connection point, while the second branching point 37 is formed as a configuration structure 39 that is effective in increasing the gate inductance of the first and second groups 31 and 32.

[0050] The configuration of the compensation structure 39 is shown in detail in Figure 10. This shows a meandering structure having an "incoming" contact 40 connected to the module gate contact 5 and two "departing" contacts 41 and 42 connected to the second group 32 or the first group 31, respectively. As is clear from Figure 10, the connection path from contact 40 to contact 41 is shorter than the connection path from contact 40 to contact 42. In this way, the different lengths of the paths from the branch point 37 to the group gate contact 6 can be compensated individually, that is, the additional inductance can be configured to be higher in the second group 32 than in the first group 31.

[0051] Figure 11 shows an embodiment including a second aspect of the present disclosure described above. Groups 51 and 52 of semiconductor switches are integrated within a submodule 53. Two additional groups 54 and 55 of semiconductor switches are integrated within a second submodule 56. Each of the submodules 53 and 56 has connections between groups via an interconnect bridge 57, as described later in relation to Figures 12 and 13. The gate and source connections between submodules 53 and 56 can also be implemented as an interconnect bridge 57. The technical background for using the interconnect bridge 57 is that compensation structures may not be able to adequately equalize the gate inductance. In some cases, it is possible to increase the inductance to achieve this goal, but this can result in the total inductance becoming too high and oscillating, or the switching time becoming very slow.

[0052] The interconnect bridge makes it possible to reduce the inductance of several gate paths, thereby increasing some low inductances and reducing some high inductances. For the functionality of the interconnect bridge, it is important that a source path, i.e., the path between the module source contact 19 and the source terminal of the semiconductor switch, must be included. If other types of semiconductor switches are used instead of MOESFETs, the source terminal may have a different name, but the same technical effect will be achieved. Overall, sufficient equalization of gate inductance can be achieved without facing high total inductance.

[0053] Interconnection bridges are, - First conductive layer for gate connection, - A second conductive layer for source connection, and - Layer structure of the insulating layer placed between the first conductive layer and the second conductive layer It is equipped with.

[0054] The interconnection bridge is connected within the control loop of the semiconductor switch; that is, the current flowing through the first conductive layer to the gate terminal also flows through the second conductive layer, at least partially, but in the opposite direction.

[0055] Note that while connection paths for gates and sources are required for the technical effect of the interconnection bridge 57, only the gate path needs to be modified for the compensation structure.

[0056] Figure 12 shows details of the embodiment of Figure 11 relating to the interconnect bridge 57. The interconnect bridge 57 comprises two conductive layers 60 and 61. Layer 60 is used as the gate connection, while layer 61 is used as the source connection. Both layers are separated by an insulating layer, which is not shown in this figure. On both sides of the interconnect bridge 57 are provided legs 62 for the gate connection and legs 63 for the source connection. These legs are connected to the gate terminal or source terminal of the semiconductor switch, respectively, via traces on the substrate on which the semiconductor switch is placed. One or more additional layers may be applied to increase the mechanical stability of the bridge, or adhesive may be added to provide additional support. This may be necessary, for example, for very long interconnect bridges.

[0057] Figure 13 shows a more detailed diagram of the interconnection bridge 57. As can be seen from the figure, the conductive layers 60 and 61 are separated by the insulating layer 64. The closer the conductive layers 60 and 61 are, the better the inductive coupling between them. The better the coupling, the lower the inductance of the gate connection. Therefore, a thin insulating layer is beneficial for the performance of the power semiconductor module. It is beneficial if the thickness of the insulating layer is less than 150 μm, and even less than 80 μm.

[0058] The embodiments shown in Figures 1 to 13 above represent exemplary embodiments of improved configurations of power semiconductor modules. Therefore, they do not constitute a complete list of all embodiments with improved configurations. Actual apparatus and methods may differ from the embodiments shown with respect to the apparatus and devices. [Explanation of Symbols]

[0059] Reference sign 1 Power semiconductor module 2. Group of semiconductor switches 3. Group of semiconductor switches 4. Semiconductor switches 5 Module gate contacts 6 Group Gate Contacts 7 Group Gate Contacts 8. The First Branching Point 9 Compensation structure 10 Gate terminals 11. First substrate 12. First metallization layer 13. Serpentine structure 14 Spiral structure 15 Wired meandering structure 16 Islands 17 Bonding wire 18 Bonding wires 19 Module source contact 20 Second board 21. Second Metallization Layer 22 Source terminals 23 Third board 24. The third metallization layer 25 Bonding wires 26 Bond Wire 27 First contact point 28 Second point of contact 29 Resistor 31 Semiconductor switch group 32 Group of semiconductor switches 33 Semiconductor switch group 34 Semiconductor Switch Group 37. The Second Turning Point 38. The Third Branch 39 Compensation structure 40. "Iriki" Contact Points 41 "Departure" Point of Contact 42 "Departure" Contact Point 43 Gate inductance without compensation structure 44 Gate inductance with compensation structure 51 Group of semiconductor switches 52 Group of semiconductor switches 53 Submodules 54 Group of semiconductor switches 55 Group of semiconductor switches 56 Submodules 57 Interconnection Bridges 60 conductive layer 61. Conductive layer 62 Legs 63 Legs 64 Insulating layer

Claims

1. A power semiconductor module (1), - At least two groups (2, 3; 31, 32, 33, 34) of semiconductor switches (4) connected in parallel, wherein the semiconductor switches (4) in each group are connected in parallel within the group (2, 3; 31, 32, 33, 34), and - Module gate contact (5), - Group gate contacts (6, 7) for each group, - The first branch point (8) connected to the module gate contact (5) and the group gate contacts (6, 7), - A gate path between the module gate contact (5) and the first branch point (8) that is shared by at least two groups (2, 3; 31, 32, 33, 34) of the semiconductor switch, - A compensation structure (9; 39) for increasing the inductance of the connection path in the connection path between the first branch point (8) and the gate terminal (10) of the semiconductor switch (4) of at least one group (3) of the semiconductor switch (4), A power semiconductor module (1) equipped with the following features.

2. The power semiconductor module (1) according to claim 1, characterized in that the compensation structure (9; 13; 14; 15; 39) includes an artificial extension of the gate path.

3. The power semiconductor module (1) according to claim 2, characterized in that the artificial extension exceeds 5%, 10%, or 20%.

4. The aforementioned compensation structure (9; 13; 14; 15; 39) has the following characteristics, namely - Formed within the metallization of a ceramic substrate or PCB, - Formed by wire bonding, or - Formed as a discrete device, A power semiconductor module (1) according to claim 2 or 3, characterized in that it is formed by one or more of the following.

5. The compensation structure (9) is characterized in that it is formed within the metallization layer (12; 24) by one or more of the following features: a serpentine structure (13) or a helical structure (14), as described in any one of claims 1 to 3, for the power semiconductor module (1) according to claim 1 to 3.

6. The power semiconductor module (1) according to any one of claims 1 to 3, characterized in that the compensation structure (15) comprises wires connecting islands (16) formed within the metallization layers (12; 24).

7. The power semiconductor module (1) according to any one of claims 1 to 3, characterized in that at least one group gate contact (6) is configured using the compensation structure (9).

8. The power semiconductor module (1) according to any one of claims 1 to 3, characterized in that the compensation structure (9) is arranged between the first branch point (8) and at least one group gate contact (6, 7).

9. The power semiconductor module (1) according to any one of claims 1 to 3, characterized in that the geometric distance between the first branch point (8) and the group gate contacts (6, 7) differs for at least two groups (2, 3; 31, 32, 33, 34) of semiconductor switches (4), and the compensation structure (9) is implemented only for groups of semiconductor switches (4) where the geometric distance is smaller than the largest geometric distance.

10. The power semiconductor module (1) according to claim 7, characterized in that the same compensation structure (9) is formed for each of several groups of gate contacts (6, 7), except that the compensation effect is selective, i.e., individually attenuated or neutralized for each of the relevant groups, by at least partially excluding the compensation structure (14) from the gate path.

11. The power semiconductor module (1) according to any one of claims 1 to 3, characterized in that the inductance of the compensation structure in the form of a first compensation structure for a first group of semiconductor switches (4) is different from the inductance of the compensation structure in the form of a second compensation structure for a second group of semiconductor switches (4).

12. A power semiconductor module (1) according to any one of claims 1 to 3, characterized by at least one second branch point (37, 38) in the gate path.

13. A power semiconductor module (1) according to any one of claims 1 to 3, characterized in that some semiconductor switches (4) of the group of semiconductor switches are arranged on a substrate (11) having a first metallization layer (12), and the module has a stacked second substrate (20) having a second metallization layer (21) as a source connection layer, and a stacked third substrate (23) having a third metallization layer (24) as a gate connection layer.

14. The power semiconductor module (1) according to any one of claims 1 to 3, characterized in that the semiconductor switch (4) is at least one of a MOSFET, MISFET, JFET, or IGBT based on Si or a wide bandgap material.

15. The power semiconductor module (1) according to any one of claims 1 to 3, characterized in that the group gate contacts (6, 7) are connected directly or via a semiconductor-based resistor (29) having a resistance of less than 3 ohms to the gate terminal (10) of the semiconductor switch (4) belonging to the group.

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