Imaging device

Abstract

To provide an imaging device capable of performing image processing.SOLUTION: An imaging device has additional functions, such as an image recognition function. The imaging device has a function of acquiring imaging data by cells arranged in a matrix and a function of retaining weight data. Some cells of the cells arranged in a matrix acquire the image data and the remaining cells retain the weight data. The imaging device performs calculation using the imaging data and the weight data. For example, the imaging device can calculate the product of the imaging data and the weight data for all pieces of imaging data and sum up the calculated products, that is, perform a product-sum operation. Since image processing can be carried out on the imaging data by the operation result being incorporated into a neural network, such as a convolutional neural network (CNN), the additional functions are available.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] One aspect of the present invention relates to an imaging device and an electronic device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. The technical field of one aspect of the invention disclosed herein relates to a product, a method, or a method of manufacture. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. More specifically, examples of the technical fields of one aspect of the present invention disclosed herein include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, energy storage devices, memory devices, imaging devices, methods for driving them, or methods for manufacturing them.

[0003] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Transistors and semiconductor circuits are examples of semiconductor devices. Furthermore, memory devices, display devices, imaging devices, and electronic devices may contain semiconductor devices. [Background technology]

[0004] A technology for constructing transistors using oxide semiconductor thin films formed on a substrate is attracting attention. For example, Patent Document 1 discloses an imaging device in which an oxide semiconductor transistor with an extremely low off-current is used in the pixel circuit.

[0005] Furthermore, a technology for adding a calculation function to an imaging device is disclosed in Patent Document 2. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2011-119711 [Patent Document 2] Japanese Patent Publication No. 2016-123087 [Overview of the project] [Problems that the invention aims to solve]

[0007] Imaging devices equipped with solid-state image sensors such as CMOS image sensors have made it easy to capture high-quality images thanks to technological advancements. In the next generation, there is a demand to incorporate various additional functions into imaging devices, such as image recognition capabilities, by performing image processing on the captured images.

[0008] Therefore, one aspect of the present invention aims to provide an imaging device capable of image processing. Alternatively, one aspect aims to provide an imaging device with low power consumption. Alternatively, one aspect aims to provide an imaging device that can be driven at high speed. Alternatively, one aspect aims to provide a compact imaging device. Alternatively, one aspect aims to provide a highly reliable imaging device. Alternatively, one aspect aims to provide an imaging device with high light detection sensitivity. Alternatively, one aspect aims to provide a novel imaging device or the like. Alternatively, one aspect aims to provide a driving method for the above-mentioned imaging device or the like. Alternatively, one aspect aims to provide a novel semiconductor device or the like.

[0009] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other problems from the description in the specification, drawings, and claims. [Means for solving the problem]

[0010] One aspect of the present invention is an imaging device comprising a cell array in which a plurality of cells are arranged in a matrix, and a logic circuit, wherein each cell has a photoelectric conversion element, each cell has the function of acquiring imaging data using the photoelectric conversion element, each cell has the function of holding weight data, and the logic circuit has the function of performing calculations using the imaging data acquired by the cell and the weight data held in a cell different from the cell that acquired the imaging data.

[0011] Alternatively, in the above embodiment, the logic circuit may have a function to calculate the product of the imaging data and the weight data.

[0012] Alternatively, one aspect of the present invention is an imaging device comprising a cell array in which a plurality of cells are arranged in a matrix, and a logic circuit, wherein each cell has a photoelectric conversion element, each cell has a function to acquire imaging data using the photoelectric conversion element, each cell has a function to hold weight data, and the logic circuit has a function to perform calculations using the first imaging data, the second imaging data, the first weight data, and the second weight data when, among the plurality of cells, the first cell acquires the first imaging data, the second cell acquires the second imaging data, the third cell holds the first weight data, and the fourth cell holds the second weight data.

[0013] Alternatively, in the above embodiment, the logic circuit may have a function to calculate the sum of the product of the first imaging data and the first weight data, and the product of the second imaging data and the second weight data.

[0014] Alternatively, in the above embodiment, the imaging device has a readout circuit, and the cell has a first transistor, a second transistor, a third transistor, and a fourth transistor, and one electrode of the photoelectric conversion element is electrically connected to one of the source or drain of the first transistor, the other of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor, one of the source or drain of the second transistor is electrically connected to the gate of the third transistor, and one of the source or drain of the third transistor is electrically connected to the source of the fourth transistor The source or drain of the third transistor is electrically connected to one side of the drain, the other side of the source or drain of the third transistor is electrically connected to a logic circuit, the other side of the source or drain of the fourth transistor is electrically connected to a readout circuit, the cell has the function of holding weight data supplied via the source and drain of the second transistor, the cell has the function of outputting imaging data from the other side of the source or drain of the third transistor, or the other side of the source or drain of the fourth transistor, and the cell may also have the function of outputting weight data from the other side of the source or drain of the third transistor.

[0015] Alternatively, in the above embodiment, the cell may have a function to output imaging data as binary data from the source or drain of the third transistor, and the cell may have a function to output weight data as binary data from the source or drain of the third transistor.

[0016] Alternatively, in the above embodiment, the first transistor and the second transistor may have a metal oxide in the channel forming region, and the metal oxide may have In, Zn, and M (where M is Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf).

[0017] Alternatively, in the above embodiment, the device may have a colored layer, and at least one of the first to fourth transistors, the photoelectric conversion element, and the colored layer may have overlapping regions, and the colored layer may function as a microlens.

[0018] Alternatively, in the above embodiment, the logic circuit may have a fifth transistor, and the fifth transistor, at least one of the first to fourth transistors, the photoelectric conversion element, and the colored layer may have overlapping regions.

[0019] Alternatively, in the above embodiment, the imaging device has a readout circuit and an A / D conversion circuit, and the cell has a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor, and one electrode of the photoelectric conversion element is electrically connected to one of the source or drain of the first transistor, the other of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor, one of the source or drain of the second transistor is electrically connected to the gate of the third transistor, one of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor, and one of the source or drain of the fourth transistor is electrically connected to one of the source or drain of the fifth transistor The fourth transistor is electrically connected, with the other of its source or drain electrically connected to a readout circuit, one of its source or drain electrically connected to an A / D conversion circuit, the A / D conversion circuit is electrically connected to a logic circuit, a first potential is supplied to the other of its source or drain of the third transistor, a second potential is supplied to the other of its source or drain of the fifth transistor, the cell has the function of holding weight data supplied via the source and drain of the second transistor, the cell has the function of outputting imaging data from one of its source or drain of the third transistor or the other of its source or drain, and the cell may also have the function of outputting weight data from one of its source or drain of the third transistor.

[0020] Alternatively, in the above embodiment, the first transistor and the second transistor may have a metal oxide in the channel forming region, and the metal oxide may have In, Zn, and M (where M is Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf).

[0021] Alternatively, in the above embodiment, the device may have a colored layer, and at least one of the first to fifth transistors, the photoelectric conversion element, and the colored layer may have overlapping regions, and the colored layer may function as a microlens.

[0022] Alternatively, in the above embodiment, the logic circuit may have a sixth transistor, and the sixth transistor, at least one of the first to fifth transistors, the photoelectric conversion element, and the colored layer may have overlapping regions.

[0023] An electronic device having an imaging device and a display unit according to one aspect of the present invention is also an aspect of the present invention. [Effects of the Invention]

[0024] By using one aspect of the present invention, it is possible to provide an imaging device capable of image processing. Alternatively, it is possible to provide an imaging device with low power consumption. Alternatively, it is possible to provide an imaging device that can be driven at high speed. Alternatively, it is possible to provide a compact imaging device. Alternatively, it is possible to provide a highly reliable imaging device. Alternatively, it is possible to provide an imaging device with high light detection sensitivity. Alternatively, it is possible to provide a novel imaging device, etc. Alternatively, it is possible to provide a driving method for the above-mentioned imaging device, etc. Alternatively, it is possible to provide a novel semiconductor device, etc.

[0025] Furthermore, the effects of one aspect of the present invention are not limited to those listed above. The effects listed above do not preclude the existence of other effects. These other effects are those described below and not mentioned in this section. Those skilled in the art can deduce these effects from the description in the specification, drawings, etc., and can be appropriately extracted from these descriptions. Furthermore, one aspect of the present invention has at least one of the effects listed above and / or other effects. Therefore, one aspect of the present invention may, in some cases, not have the effects listed above. [Brief explanation of the drawing]

[0026] [Figure 1] Figure 1 is a block diagram illustrating an example of the configuration of an imaging device. [Figure 2] Figures 2A and 2B are circuit diagrams illustrating an example of a cell configuration. [Figure 3] Figure 3 is a circuit diagram illustrating an example of the configuration of an arithmetic circuit. [Figure 4] Figures 4A and 4B illustrate an example of the operation. [Figure 5] Figures 5A and 5B illustrate an example of the calculation. [Figure 6] Figure 6 illustrates an example of an operation. [Figure 7] Figure 7 is a circuit diagram illustrating an example of the configuration of an imaging device. [Figure 8] Figure 8 is a timing chart illustrating an example of how to drive the imaging device. [Figure 9] Figure 9 illustrates an example of a method for driving an imaging device. [Figure 10] Figure 10 is a timing chart illustrating an example of how to drive an imaging device. [Figure 11] Figure 11 is a circuit diagram illustrating an example of a method for driving an imaging device. [Figure 12] Figures 12A and 12B are circuit diagrams illustrating an example of a cell configuration. [Figure 13]Figure 13 is a circuit diagram illustrating an example of the configuration of an arithmetic circuit. [Figure 14] Figure 14 is a circuit diagram illustrating an example of the configuration of an imaging device. [Figure 15] Figure 15 is a timing chart illustrating an example of how to drive an imaging device. [Figure 16] Figure 16 is a timing chart illustrating an example of how to drive an imaging device. [Figure 17] Figures 17A and 17B are circuit diagrams illustrating an example of a method for driving an imaging device. [Figure 18] Figures 18A to 18E are perspective views illustrating examples of the configuration of an imaging device. [Figure 19] Figures 19A and 19B are cross-sectional views illustrating an example of the configuration of an imaging device. [Figure 20] Figures 20A to 20C are cross-sectional views illustrating an example of the configuration of an imaging device. [Figure 21] Figures 21A and 21B are cross-sectional views illustrating an example of the configuration of an imaging device. [Figure 22] Figures 22A to 22D are cross-sectional views illustrating an example of the configuration of an imaging device. [Figure 23] Figures 23A to 23C are perspective views illustrating an example of the configuration of an imaging device. [Figure 24] Figures 24A and 24B are cross-sectional views illustrating an example of the configuration of an imaging device. [Figure 25] Figures 25A and 25B are cross-sectional views illustrating an example of the configuration of an imaging device. [Figure 26] Figures 26A and 26B are cross-sectional views illustrating an example of the configuration of an imaging device. [Figure 27] Figures 27A and 27B are cross-sectional views illustrating an example of the configuration of an imaging device. [Figure 28] Figures 28A and 28B are perspective views illustrating an example of the configuration of an imaging device. [Figure 29]Figure 29A illustrates the classification of IGZO crystal structures. Figure 29B illustrates the XRD spectrum of a CAAC-IGZO film. Figure 29C illustrates the micro-electron diffraction pattern of a CAAC-IGZO film. [Figure 30] Figures 30A1 to 30B3 are perspective views of the package and module containing the imaging device. [Figure 31] Figures 31A to 31F are diagrams illustrating electronic equipment. [Figure 32] Figures 32A and 32B are diagrams illustrating an automobile. [Modes for carrying out the invention]

[0027] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the invention. Therefore, the present invention is not to be interpreted as being limited to the descriptions of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated descriptions may be omitted. In addition, hatching of the same elements constituting the figures may be omitted or changed as appropriate between different drawings.

[0028] Furthermore, even if an element is shown as a single element in a circuit diagram, it may be composed of multiple elements as long as there is no functional disadvantage. For example, multiple transistors that act as switches may be connected in series or parallel. Also, a capacitor may be divided and placed in multiple locations.

[0029] Furthermore, a single conductor may have multiple functions, such as wiring, electrodes, and terminals, and in this specification, multiple designations may be used for the same element. Also, even if elements are shown as directly connected in a circuit diagram, they may actually be connected via multiple conductors, and in this specification, such configurations are included in the category of direct connections.

[0030] (Embodiment 1) This embodiment describes an imaging device that is one aspect of the present invention.

[0031] One aspect of the present invention is an imaging device equipped with additional functions such as image recognition. In this imaging device, pixels arranged in a matrix have the function of acquiring imaging data and the function of holding weight data. Of the pixels arranged in a matrix, some pixels acquire imaging data, and the remaining pixels hold weight data. Then, calculations are performed using the imaging data and the weight data. For example, it is possible to calculate the product of the imaging data and the weight data for all the imaging data and then sum the calculated products. In other words, a sum-of-products operation can be performed. By inputting the calculation results into a neural network such as a convolutional neural network (CNN), image processing can be performed on the imaging data, thus enabling the use of additional functions.

[0032] <Example configuration of imaging device_1> Figure 1 is a block diagram illustrating an example configuration of an imaging device 10, which is an imaging device according to one aspect of the present invention. The imaging device 10 has a cell array 11 in which cells 12 are arranged in a matrix of m rows and n columns (where m and n are integers of 1 or more). The imaging device 10 also has a load driver circuit 13, a data generation circuit 14, a readout circuit 16, an arithmetic circuit 17, and a transistor 27. Note that each circuit shown in Figure 1 is not limited to a single circuit configuration, but may be composed of multiple circuits. Alternatively, any multiple of the above circuits may be integrated.

[0033] In this specification, for example, cell 12 in the 1st row and 1st column is described as cell 12[1,1], and cell 12 in the mth row and nth column is described as cell 12[m,n].

[0034] The low driver circuit 13 is electrically connected to the cell 12 via wiring 35. Here, for example, cells 12 in the same row can be electrically connected to the low driver circuit 13 via the same wiring 35. In this specification, for example, the wiring 35 electrically connected to the cell 12 in the first row is described as wiring 35[1], the wiring 35 electrically connected to the cell 12 in the second row is described as wiring 35[2], and the wiring 35 electrically connected to the cell 12 in the mth row is described as wiring 35[m]. Similar descriptions may be used for other wiring, etc.

[0035] The data generation circuit 14 is electrically connected to the cells 12 via wiring 43. Here, for example, cells 12 in the same column can be electrically connected to the data generation circuit 14 via the same wiring 43. In this specification, for example, the wiring 43 electrically connected to the cell 12 in the first column is described as wiring 43[1], the wiring 43 electrically connected to the cell 12 in the second column is described as wiring 43[2], and the wiring 43 electrically connected to the cell 12 in the nth column is described as wiring 43[n]. Similar descriptions may be used for other wirings, etc.

[0036] The reading circuit 16 is electrically connected to the cell 12 via wiring 45. Here, for example, cells 12 in the same row can be electrically connected to the reading circuit 16 via the same wiring 45.

[0037] The arithmetic circuit 17 is electrically connected to the cell 12 via wiring 44. Here, for example, each cell 12 can be electrically connected to a different wiring 44. In this specification, for example, the wiring 44 electrically connected to cell 12[1,1] is described as wiring 44[1,1], and the wiring 44 electrically connected to cell 12[m,n] is described as wiring 44[m,n]. Similar descriptions may be used for other wirings, etc.

[0038] One of the sources or drains of transistor 27 is electrically connected to wiring 45. The other of the sources or drains of transistor 27 is electrically connected to wiring 47. The gate of transistor 27 is electrically connected to wiring 37. Here, for example, a transistor 27 electrically connected to wiring 45[1] is denoted as transistor 27[1], a transistor 27 electrically connected to wiring 45[2] is denoted as transistor 27[2], and a transistor 27 electrically connected to wiring 45[n] is denoted as transistor 27[n].

[0039] Wiring 47 functions as a power line. For example, a low potential can be supplied to wiring 47. Wiring 37 also functions as a signal line that controls the conduction / non-conductivity of transistor 27.

[0040] Cell 12 has a photoelectric conversion element and has the function of acquiring imaging data using this photoelectric conversion element. In other words, cell 12 functions as a pixel. Furthermore, as will be described in detail later, cell 12 has the function of holding the weight data generated by the data generation circuit 14. Therefore, cell 12 functions as a memory.

[0041] In this specification, the term "element" may be replaced with the term "device." For example, "photoelectric element" can be replaced with "photoelectric device."

[0042] The low driver circuit 13 has a function to select cell 12. For example, the low driver circuit 13 has a function to select cell 12 from which to read imaging data. The low driver circuit 13 has a function to select cell 12 by, for example, generating a selection signal and supplying the generated selection signal to cell 12 via wiring 35. Therefore, wiring 35 functions as a signal line.

[0043] The data generation circuit 14 has the function of generating weight data. The generated weight data is supplied to and held by the cell 12 via the wiring 43. Specifically, the weight data is supplied to and held by the cell 12 that has not acquired imaging data. The data generation circuit 14 also has the function of generating reset data, which is data supplied to the cell 12 during the reset operation that the cell 12 performs before the imaging operation, and supplying it to the cell 12 via the wiring 43. Thus, the wiring 43 functions as a data line.

[0044] The readout circuit 16 includes a column driver circuit. The column driver circuit has the function of selecting the cell 12 from which to read the imaging data. The readout circuit 16 may also include a correlated double sampling circuit (CDS circuit) and an analog-to-digital conversion circuit (A / D conversion circuit). Here, the imaging data output from cell 12 to wiring 45 is supplied to the readout circuit 16. Therefore, wiring 45 functions as an output line.

[0045] The arithmetic circuit 17 has the function of performing calculations using the image data and weight data. As mentioned above, image processing can be performed by inputting the calculation results into a neural network such as a CNN. Details of the calculations performed by the arithmetic circuit 17 will be described later. Here, the image data and weight data output from cell 12 to wiring 44 are supplied to the arithmetic circuit 17. Therefore, wiring 44 functions as an output line.

[0046] The imaging device 10 can be driven in either a first or second mode. In the first mode, for example, all cells 12 acquire imaging data and output the acquired imaging data to the readout circuit 16. In the second mode, some cells 12 acquire imaging data, while the remaining cells 12 hold weight data. The imaging data and weight data are then output to the calculation circuit 17.

[0047] Therefore, in the first mode, the imaging data is output to the outside of the imaging device 10 without performing calculations using the weight data generated by the data generation circuit 14. Thus, the first mode is a mode that does not use additional functions. On the other hand, in the second mode, image processing is performed by performing calculations using the imaging data and the weight data. Thus, the second mode is a mode that uses additional functions. In the first mode, for example, all cells 12 are used to acquire imaging data, so additional functions cannot be used, but the resolution of the image represented by the imaging data can be made higher than the resolution of the image represented by the imaging data in the second mode. In the first mode, the calculation circuit 17 can be stopped from driving. Also, in the second mode, the readout circuit 16 can be stopped from driving.

[0048] Figure 2A is a circuit diagram showing an example configuration of cell 12. Cell 12 includes a photoelectric conversion element 21, transistors 22, 23, 24, 25, and 26.

[0049] One electrode of the photoelectric conversion element 21 is electrically connected to either the source or the drain of transistor 22. The other source or drain of transistor 22 is electrically connected to either the source or the drain of transistor 23. One source or drain of transistor 23 is electrically connected to the gate of transistor 24. One source or drain of transistor 24 is electrically connected to either the source or the drain of transistor 25.

[0050] The other electrode of the photoelectric conversion element 21 is electrically connected to the wiring 41. The gate of transistor 22 is electrically connected to the wiring 32. The other source or drain of transistor 23 is electrically connected to the wiring 43. The gate of transistor 23 is electrically connected to the wiring 33. The other source or drain of transistor 24, and one source or drain of transistor 26, are electrically connected to the wiring 44. The other source or drain of transistor 25 is electrically connected to the wiring 45. The gate of transistor 25 is electrically connected to the wiring 35. The other source or drain of transistor 26 is electrically connected to the wiring 46. The gate of transistor 26 is electrically connected to the wiring 36.

[0051] In Figure 2A, one electrode of the photoelectric conversion element 21 is designated as the anode, and the other electrode of the photoelectric conversion element 21 is designated as the cathode. Therefore, in Figure 2A, the anode of the photoelectric conversion element 21 is electrically connected to either the source or the drain of the transistor 22, and the cathode of the photoelectric conversion element 21 is electrically connected to the wiring 41.

[0052] Here, node FD is defined as the electrical connection point between the other source or drain of transistor 22, the other source or drain of transistor 23, and the gate of transistor 24.

[0053] Wires 41 and 46 function as power lines. For example, high potential can be supplied to wires 41 and 46. In addition, signals that control the conduction / non-conductivity of each transistor are supplied to wires 32, 33, and 36. Therefore, wires 32, 33, and 36 function as signal lines.

[0054] The photoelectric conversion element 21 has the function of acquiring imaging data. A photodiode can be used as the photoelectric conversion element 21. If you want to increase the light detection sensitivity at low light levels, it is preferable to use an avalanche photodiode.

[0055] Transistor 22 has the function of controlling the transfer of charge accumulated in the photoelectric conversion element 21 to node FD in accordance with the illuminance of the light irradiated onto the photoelectric conversion element 21. Therefore, transistor 22 functions as a transfer transistor.

[0056] Transistor 23 has the function of controlling the supply of potentials corresponding to the reset data and weight data generated by the data generation circuit 14 to node FD. Therefore, transistor 23 functions as a reset transistor.

[0057] Transistor 24 has the function of making the potential of wiring 44 or wiring 45 correspond to the potential of node FD. As a result, the imaging data acquired by cell 12 is read out via wiring 44 or wiring 45, and the weight data held in cell 12 is read out via wiring 44. Here, the imaging data or weight data held in cell 12 is amplified by transistor 24 and output. Therefore, transistor 24 functions as an amplifying transistor.

[0058] Transistor 25 has the function of controlling the selection of the cell 12 that outputs imaging data to the readout circuit 16. Therefore, transistor 25 functions as a selection transistor.

[0059] Transistor 26 has the function of controlling the potential of wiring 44. When transistor 26 is in a conducting state, the potential of wiring 44 becomes the potential corresponding to the potential of wiring 46. This allows wiring 44 to be precharged. Therefore, transistor 26 has the function of controlling the precharge of wiring 44. Thus, transistor 26 functions as a precharge transistor.

[0060] In this specification, a transistor being in a conducting state, or being in an ON state, means that current flows between the drain and source of the transistor. For example, a transistor can be made to conduct by making the difference between the gate potential and the source potential greater than or equal to the threshold voltage of the transistor. Conversely, a transistor being in a non-conducting state, or being in an OFF state, means that no current flows between the drain and source of the transistor. A transistor can be made to non-conducting by making the difference between the gate potential and the source potential less than the threshold voltage of the transistor.

[0061] Here, it is preferable to use transistors 22 and 23 that have extremely low off-currents. This makes it possible to hold the charge at node FD for an extremely long period of time. As a result, cell 12 can hold imaging data and weight data for a long period of time. Because cell 12 can hold weight data for a long period of time, the frequency of refresh operations can be reduced. Therefore, the power consumption of the imaging device 10 can be reduced. In addition, because cell 12 can hold imaging data for a long period of time, a global shutter method can be applied in which charge accumulation operations are performed simultaneously in all cells 12 without complicating the circuit configuration or driving method. Furthermore, it is possible to perform multiple calculations using the imaging data while the node FD is holding the imaging data. Examples of transistors with extremely low off-currents include transistors that use metal oxides in the channel formation region (hereinafter referred to as OS transistors).

[0062] Furthermore, OS transistors have the characteristic of high voltage resistance. Here, when an avalanche photodiode is used as the photoelectric conversion element 21, a high voltage may be applied, so it is preferable to use a high-voltage transistor for the transistor connected to the photoelectric conversion element 21. Therefore, when an avalanche photodiode is used as the photoelectric conversion element 21, it is preferable to use an OS transistor as the transistor 22.

[0063] In this case, if transistors 22 and 23 are OS transistors, it is preferable that transistors 24 to 26 are also OS transistors. By making transistors 22 to 26 all of the same type, all transistors in cell 12 can be formed in the same process. This allows the imaging device 10 to be manufactured in a simple manner.

[0064] Note that transistors other than OS transistors may be used as transistors 22 to 26. For example, it is preferable to use transistors that use silicon in the channel formation region (hereinafter referred to as Si transistors) as transistors 22 to 26. For example, if transistors that use single-crystal silicon in the channel formation region are used as transistors 22 to 26, the on-current of transistors 22 to 26 will increase. Therefore, the imaging device 10 can be driven at high speed.

[0065] Figure 2B is a circuit diagram showing an example configuration of cell 12, and is a modified version of the configuration shown in Figure 2A. Cell 12 shown in Figure 2B differs from cell 12 shown in Figure 2A in that the cathode of the photoelectric conversion element 21 is electrically connected to either the source or the drain of the transistor 22, and the anode of the photoelectric conversion element 21 is electrically connected to the wiring 41. In cell 12 shown in Figure 2B, the potential of the wiring 41 can be set to a low potential.

[0066] Figure 3 is a circuit diagram showing an example configuration of the arithmetic circuit 17. The arithmetic circuit 17 includes a logic circuit 51 and transistors 52[1,1] to 52[p,q] (where p and q are integers greater than or equal to 1). In the arithmetic circuit 17 shown in Figure 3, the transistors 52 are arranged in a p × q matrix.

[0067] The input terminals of the logic circuit 51 are electrically connected to wiring 44[1,1] to wiring 44[m,n]. The output terminals of the logic circuit 51 are electrically connected to either the source or drain of transistor 52[1,1] to transistor 52[p,q]. Here, the logic circuit 51 can be configured to have, for example, m × n input terminals, each of which is electrically connected to a different wiring 44. The logic circuit 51 can also be configured to have, for example, p × q output terminals, each of which is electrically connected to a different transistor 52.

[0068] Furthermore, for example, the other source or drain of transistors 52 in the same row can be electrically connected to each other. For example, the other source or drain of transistors 52[1,1] to 52[p,1] located in the first row can be electrically connected to each other, and the other source or drain of transistors 52[1,q] to 52[p,q] located in the q row can be electrically connected to each other.

[0069] The gate of transistor 52 is electrically connected to wiring 53. Here, for example, the gates of transistors 52 in the same row can be electrically connected to each other via the same wiring 53. Wiring 53 is supplied with a signal that controls the conduction / non-conductivity of transistor 52. Therefore, wiring 53 functions as a signal line.

[0070] The logic circuit 51 has the function of performing logical operations using the imaging data and weight data output from the cell 12. The logic circuit 51 also has the function of performing logical operations using digital data. The calculation result can be represented, for example, by a p x q matrix, and data representing each component of the matrix is ​​output from the output terminal of the logic circuit 51.

[0071] Transistor 52 has the function of controlling the reading of the calculation result by logic circuit 51. For example, suppose logic circuit 51 outputs a p x q matrix as the calculation result. In this case, if transistor 52[1,1] is in a conducting state, the component in the 1st row and 1st column can be read, and if transistor 52[p,q] is in a conducting state, the component in the p row and q column can be read.

[0072] It is preferable to use Si transistors as the transistors in logic circuit 51 and transistor 52. For example, it is preferable to use transistors in which single-crystal silicon is used in the channel formation region as the transistors in logic circuit 51 and transistor 52. As mentioned above, transistors in which single-crystal silicon is used in the channel formation region have a large on-current. Therefore, if transistors in which single-crystal silicon is used in the channel formation region are used as the transistors in logic circuit 51, logic circuit 51 can perform calculations at high speed. Also, if transistors in which single-crystal silicon is used in the channel formation region are used as transistor 52, the calculation results of logic circuit 51 can be read out at high speed. Note that as Si transistors, transistors in which amorphous silicon, microcrystalline silicon, or polycrystalline silicon is used in the channel formation region may also be used.

[0073] <Example of an operation> Figures 4A, 4B, 5A, and 5B show examples of data held in cell 12 and calculations performed by logic circuit 51. Here, imaging data is represented by "x" and weight data by "w". In addition, numbers are assigned to "x" to distinguish different imaging data, and alphanumeric characters are assigned to "w" to distinguish different weight data.

[0074] In FIGS. 4A, 4B, 5A, and 5B, cells 12[1,1] to 12[6,12] are shown, and the cells 12 in which imaging data is held are hatched. In FIGS. 4A, 4B, 5A, and 5B, it is assumed that out of the four cells 12, imaging data is held in one cell 12 and weight data is held in three cells 12. Specifically, it is assumed that imaging data is held in the cells 12 at odd row and odd column positions, and weight data is held in the other cells 12.

[0075] In FIG. 4A, the imaging data x 11 to the imaging data x 33 and the weight data wa1 to wa9 are shown performing a sum-of-products operation to obtain the convolution data Ca1. Also, the imaging data x 11 to the imaging data x 33 and the weight data wb1 to wb9 are shown performing a sum-of-products operation to obtain the convolution data Cb1. Further, the imaging data x 11 to the imaging data x 33 and the weight data wc1 to wc9 are shown performing a sum-of-products operation to obtain the convolution data Cc1.

[0076] In FIG. 4B, the imaging data x 12 to the imaging data x 34 and the weight data wa1 to wa9 are shown performing a sum-of-products operation to obtain the convolution data Ca2. Also, the imaging data x 12 to the imaging data x 34 and the weight data wb1 to wb9 are shown performing a sum-of-products operation to obtain the convolution data Cb2. Further, the imaging data x 12 to the imaging data x 34 and the weight data wc1 to wc9 are shown performing a sum-of-products operation to obtain the convolution data Cc2.

[0077] As shown in FIG. 4B, for example, when obtaining the convolution data Ca2, the imaging data x12 Then, the product of the weight data wa1 and is calculated. Here, the weight data wa1 is stored not only in cell 12[1,2] but also in cell 12[1,8]. However, cell 12[1,2] has more of the imaging data x 12 The coordinates of cell 12[1,3], where the data is stored, are close. Therefore, using the weight data wa1 stored in cell 12[1,2] when acquiring the convolution data Ca2 is preferable because it reduces the delay time compared to using the weight data wa1 stored in cell 12[1,8]. Similarly, for example, using the weight data wc1 stored in cell 12[2,2] when acquiring the convolution data Cc2 is preferable because it reduces the delay time compared to using the weight data wc1 stored in cell 12[2,8]. The same can be said for other weight data used when acquiring the convolution data Ca2, convolution data Cb2, or convolution data Cc2.

[0078] In Figure 5A, the imaging data x 13 or imaging data x 35 This shows how convolution data Ca3 is obtained by performing a sum-of-products operation between weight data wa1 to weight data wa9. Also, imaging data x 13 or imaging data x 35 This shows how convolution data Cb3 is obtained by performing a sum-of-products operation between weight data wb1 to weight data wb9. Furthermore, imaging data x 13 or imaging data x 35 This shows how the convolution data Cc3 is obtained by performing a sum-of-products operation between the weight data wc1 to wc9.

[0079] In Figure 5B, the imaging data x 14 or imaging data x 36 This shows how convolution data Ca4 is obtained by performing a sum-of-products operation between weight data wa1 to weight data wa9. Also, imaging data x 14 or imaging data x 36This shows how convolution data Cb4 is obtained by performing a sum-of-products operation between weight data wb1 to weight data wb9. Furthermore, imaging data x 14 or imaging data x 36 This shows how the convolution data Cc4 is obtained by performing a sum-of-products operation between the weight data wc1 to wc9.

[0080] As described above, a sum-of-products operation can be performed to obtain convolution data. In the examples shown in Figures 4A, 4B, 5A, and 5B, a convolution operation (sum-of-products operation) with a stride of 1 can be performed using three types of 3x3 filters. For example, by performing the operation shown in Figure 5A after performing the operation shown in Figure 4A, without performing the operation shown in Figure 4B, the stride can be made 2.

[0081] Here, by storing the same weight data in multiple cells 12, it is possible to suppress the separation between the coordinates of the cell 12 that stores the imaging data and the coordinates of the cell 12 that stores the weight coefficients multiplied by the imaging data, as shown in Figure 4B. This suppresses the increase in delay time, allowing the calculations by the logic circuit 51 to be performed at high speed. On the other hand, by reducing the number of cells 12 that store the same weight data, it is possible to increase the types of filters that can be used in convolution operations, for example.

[0082] Figure 6 shows an example of the data held in cells 12 and the operations performed by the logic circuit 51 when the number of cells 12 holding each weight data is half that of the examples shown in Figures 4A, 4B, 5A, and 5B. In the examples shown in Figures 4A, 4B, 5A, and 5B, one type of weight data is held in two cells 12 from cells 12[1,1] to cells 12[6,12]. On the other hand, in the example shown in Figure 6, one type of weight data is held in one cell 12 from cells 12[1,1] to cells 12[6,12]. Therefore, in the example shown in Figure 6, cells 12 can hold weight data Wa1 to Wa9, weight data Wb1 to Wb9, weight data Wc1 to Wc9, weight data Wd1 to Wd9, weight data We1 to We9, and weight data Wf1 to Wf9. In other words, 54 types of weight data can be stored in cell 12. This allows, for example, a convolution operation using 6 types of 3x3 filters to be performed. This enables, for example, imaging data x 11 or imaging data x 33 When performing a convolution operation using this method, as shown in Figure 6, in addition to convolution data Ca1, Cb1, and Cc1, convolution data Cd1, Ce1, and Cf1 can be obtained. Therefore, for example, a large number of image features can be extracted, enabling the imaging device 10 to perform high-precision image processing. Thus, the additional functions of the imaging device 10 can be made high-performance.

[0083] Furthermore, in the examples shown in Figures 4A, 4B, 5A, 5B, and 6, one of the four cells 12 holds the imaging data, and three of the cells 12 hold the weight data. In other words, of the cells 12 that make up the cell array 11, 1 / 4 of the cells 12 hold the imaging data, and 3 / 4 of the cells 12 hold the weight data. Here, increasing the proportion of cells 12 that hold imaging data can increase the resolution of the image represented by the imaging data. On the other hand, increasing the proportion of cells 12 that hold weight data can enable more accurate image processing, and the additional functions of the imaging device 10 can be made more high-performance.

[0084] Furthermore, the logic circuit 51 may have functions to perform operations other than multiply-accumulate operations. For example, it may have a pooling function. By having the logic circuit 51 have a pooling function, the amount of data output to the outside of the imaging device 10 can be reduced.

[0085] As described above, when the imaging device 10 is driven in the second mode, the arithmetic circuit 17, which has the logic circuit 51, performs calculations. Therefore, the calculations shown in Figures 4A, 4B, 5A, 5B, and 6 are performed when the imaging device 10 is driven in the second mode. Note that when the imaging device 10 is driven in the first mode, all cells 12 can hold the imaging data x.

[0086] <An example of how to drive an imaging device_1> The following describes an example of a driving method for the imaging device 10. Specifically, an example of a driving method for cell 12[i,j] (where i is an integer between 1 and m-1, and j is an integer between 1 and n-1), cell 12[i,j+1], cell 12[i+1,j], cell 12[i+1,j+1], transistor 27[j], transistor 27[j+1], transistor 52[h,k] (where h is an integer between 1 and p-1, and k is an integer between 1 and q-1), transistor 52[h,k+1], transistor 52[h+1,k], and transistor 52[h+1,k+1] will be described. Figure 7 is a circuit diagram showing the components of the imaging device 10 that illustrate this example of a driving method. As shown in Figure 7, it is assumed that the potential VSS is supplied to wiring 47 as a low potential. It is also assumed that the high potential is supplied to wiring 41 and wiring 46.

[0087] In the following explanation of the driving method, all transistors are assumed to be n-channel type transistors. However, by appropriately changing the relative potentials, the following explanation of the driving method can be applied even if some or all transistors are p-channel type. Also, as shown in Figure 7, the explanation of the driving method assumes that cell 12 has the configuration shown in Figure 2A. However, by appropriately changing the relative potentials, the following explanation can be applied even if cell 12 has the configuration shown in Figure 2B.

[0088] Figure 8 is a timing chart showing an example of how to drive the imaging device 10 when it is driven in the first mode. As mentioned above, in the first mode, no calculations using weight data are performed.

[0089] In the timing chart shown in Figure 8, high potential is indicated by "H" and low potential by "L". Furthermore, the timing chart in Figure 8 does not take into account internal circuit delays. The same applies to other timing charts.

[0090] During period T01, a high potential is supplied to wires 32[i,j], 32[i+1,j], 32[i,j+1], 32[i+1,j+1], 33[i,j], 33[i+1,j], 33[i,j+1], 33[i+1,j+1], and 36. As a result, transistors 22[i,j], 22[i,j+1], 22[i+1,j], 22[i+1,j+1], 23[i,j], 23[i,j], 23[i+1,j], 23[i+1,j+1], 23[i+1,j+1], 26[i,j], 26[i+1,j], and 26[i+1,j+1] become conductive. Furthermore, a low potential is supplied to wiring 35[i], wiring 35[i+1], wiring 43[j], wiring 43[j+1], wiring 53[h], and wiring 53[h+1]. As a result, transistors 25[i,j], 25[i,j+1], 25[i+1,j], 25[i+1,j+1], 52[h,k], 52[h,k+1], 52[h+1,k], and 52[h+1,k+1] become non-conductive. In addition, a bias potential Vb is supplied to wiring 37. Here, the bias potential is the potential at which, when supplied to the gate of a transistor, the transistor is driven as a current source. For example, when supplied to the gate of a transistor, it is the potential at which the transistor is driven in the saturation region.

[0091] During period T01, the potentials of nodes FD[i,j], FD[i,j+1], FD[i+1,j], and FD[i+1,j+1] become low potentials, which are the same as the potentials of wiring 43[j] and wiring 43[j+1]. As a result, the potentials of nodes FD[i,j], FD[i,j+1], FD[i+1,j], and FD[i+1,j+1] are reset. Therefore, period T01 is the period during which the reset operation is performed. During period T01, the data generation circuit 14 generates reset data, and this reset data is supplied to cell 12 via wiring 43.

[0092] During period T02, the potentials of wires 32[i,j], 32[i+1,j], 32[i,j+1], and 32[i+1,j+1] are set to a low potential, and then the potentials of wires 33[i,j], 33[i+1,j], 33[i,j+1], and 33[i+1,j+1] are set to a low potential. As a result, transistors 22[i,j], 22[i,j+1], 22[i+1,j], and 22[i+1,j+1] become non-conductive, and then transistors 23[i,j], 23[i,j+1], 23[i+1,j], and 23[i+1,j+1] become non-conductive. With this, the reset operation is completed.

[0093] During period T03, the potentials of wiring 32[i,j], wiring 32[i+1,j], wiring 32[i,j+1], and wiring 32[i+1,j+1] are raised to a high potential. As a result, transistors 22[i,j], 22[i,j+1], 22[i+1,j], and 22[i+1,j+1] become conductive, and the potentials of nodes FD[i,j], FD[i,j+1], FD[i+1,j], and FD[i+1,j+1] rise in accordance with the illuminance of the light shining on photoelectric conversion elements 21[i,j], 21[i,j+1], 21[i+1,j], and 21[i+1,j+1], respectively. Therefore, period T03 is the period during which the exposure operation is performed.

[0094] During period T04, the potentials of wiring 32[i,j], wiring 32[i+1,j], wiring 32[i,j+1], and wiring 32[i+1,j+1] are set to a low potential. As a result, transistors 22[i,j], transistors 22[i,j+1], transistors 22[i+1,j], and transistors 22[i+1,j+1] become non-conductive, and the exposure operation ends. As a result, cells 12[i,j], cell 12[i,j+1], cell 12[i+1,j], and cell 12[i+1,j+1] can acquire imaging data.

[0095] During period T05, first, the potential of wiring 35[i] is set to a high potential, making transistors 25[i,j] and 25[i,j+1] conductive. Then, the potential of wiring 35[i] is set to a low potential, making transistors 25[i,j] and 25[i,j+1] non-conductive. By making transistor 25[i,j] conductive, the imaging data acquired by cell 12[i,j] is output to the readout circuit 16 via wiring 45[j], and the imaging data acquired by cell 12[i,j] is read out. Also, by making transistor 25[i,j+1] conductive, the imaging data acquired by cell 12[i,j+1] is output to the readout circuit 16 via wiring 45[j+1], and the imaging data acquired by cell 12[i,j+1] is read out.

[0096] Next, the potential of wiring 35[i+1] is set to a high potential, making transistors 25[i+1,j] and 25[i+1,j+1] conductive. Then, the potential of wiring 35[i+1] is set to a low potential, making transistors 25[i+1,j] and 25[i+1,j+1] non-conductive. By making transistor 25[i+1,j] conductive, the imaging data acquired by cell 12[i+1,j] is output to the readout circuit 16 via wiring 45[j], and the imaging data acquired by cell 12[i+1,j] is read out. Also, by making transistor 25[i+1,j+1] conductive, the imaging data acquired by cell 12[i+1,j+1] is output to the readout circuit 16 via wiring 45[j+1], and the imaging data acquired by cell 12[i+1,j+1] is read out. Therefore, period T05 is the period during which the read operation is performed.

[0097] The above is an example of a driving method for the imaging device 10 in the first mode.

[0098] Next, an example of how to drive the imaging device 10 in the second mode will be described. Specifically, as shown in Figure 9, an example of how to drive the imaging device 10 will be described when cell 12[i,j] acquires imaging data x, and writes weight data w1 to cell 12[i,j+1], weight data w2 to cell 12[i+1,j], and weight data w3 to cell 12[i+1,j+1]. Figure 10 is a timing chart showing an example of how to drive the imaging device 10 when the imaging device 10 is driven in the second mode.

[0099] During period T11, a high potential is first supplied to wiring 37. This causes transistors 27[j] and 27[j+1] to become conductive. Additionally, a low potential is supplied to wirings 32[i,j], 32[i,j+1], 32[i+1,j], 32[i+1,j+1], 33[i,j], 33[i,j+1], 33[i+1,j], 33[i+1,j+1], 35[i], 35[i+1], 36, 53[h], and 53[h+1]. As a result, transistors 22[i,j], 22[i,j+1], 22[i+1,j], 22[i+1,j+1], 23[i,j], 23[i,j+1], 23[i+1,j], 23[i+1,j+1], 25[i,j], 25[i,j+1], 25[i+1,j], 25[i+1,j+1], 26[i,j], 26[i,j], 26[i+1,j], 26[i+1,j+1], 52[h,k], 52[h,k+1], 52[h+1,k], and 52[h+1,k+1] become non-conductive.

[0100] Next, the data generation circuit 14 supplies weight data w1 to wiring 43[j+1]. It also sets the potential of wiring 33[i,j+1] to a high potential, causing transistor 23[i,j+1] to conduct. This causes the potential of node FD[i,j+1] to correspond to the weight data w1, and the weight data w1 is written to cell 12[i,j+1]. Subsequently, the potential of wiring 33[i,j+1] is set to a low potential, causing transistor 23[i,j+1] to deconduct. This maintains the potential of node FD[i,j+1], and thus the weight data w1 is retained in cell 12[i,j+1].

[0101] Next, the data generation circuit 14 supplies weight data w2 to wiring 43[j] and weight data w3 to wiring 43[j+1]. Furthermore, the potentials of wiring 33[i+1,j] and wiring 33[i+1,j+1] are set to high potentials, causing transistors 23[i+1,j] and 23[i+1,j+1] to conduct. As a result, the potential of node FD[i+1,j] becomes the potential corresponding to weight data w2, and weight data w2 is written to cell 12[i+1,j]. Additionally, the potential of node FD[i+1,j+1] becomes the potential corresponding to weight data w3, and weight data w3 is written to cell 12[i+1,j+1]. Subsequently, the potential of wiring 33[i+1,j] and wiring 33[i+1,j+1] are set to a low potential, and transistors 23[i+1,j] and transistors 23[i+1,j+1] are made non-conductive. As a result, the potential of node FD[i+1,j] and node FD[i+1,j+1] are maintained, so weight data w2 is held in cell 12[i+1,j] and weight data w3 is held in cell 12[i+1,j+1].

[0102] Based on the above, period T11 is the period during which weight data is written to cell 12. During period T11, for example, a high potential can be supplied simultaneously to all wirings 33 that are electrically connected to cell 12 to which weight data is written, from wiring 33[i,1] to wiring 33[i,n]. Subsequently, for example, a high potential can be supplied simultaneously to all wirings 33 that are electrically connected to cell 12 to which weight data is written, from wiring 33[i+1,1] to wiring 33[i+1,n].

[0103] During period T12, the potentials of wiring 32[i,j] and wiring 33[i,j] are set to high potential. This causes transistors 22[i,j] and 23[i,j] to conduct. Also, the potential of wiring 43[j] is set to low potential. As a result, the potential of node FD[i,j] becomes low potential. This resets the potential of node FD[i,j]. Therefore, period T12 is the period during which cell 12, which acquires imaging data, performs a reset operation. During period T12, the data generation circuit 14 generates reset data, and this reset data is supplied to cell 12[i,j] via wiring 43[j].

[0104] During period T13, the potential of wiring 32[i,j] is lowered, and then the potential of wiring 33[i,j] is lowered. As a result, transistor 22[i,j] becomes non-conductive, and then transistor 23[i,j] becomes non-conductive. With this, the reset of cell 12[i,j] is completed.

[0105] During period T14, the potential of wiring 32[i,j] is raised. This causes transistor 22[i,j] to conduct, and the potential of node FD[i,j] rises in accordance with the illuminance of the light shining on photoelectric conversion element 21[i,j]. Therefore, period T14 is the period during which exposure operation is performed on cell 12 to acquire imaging data.

[0106] During period T15, the potential of wiring 32[i,j] is set to a low potential. This causes transistor 22[i,j] to become non-conductive, and the exposure operation ends. As a result, cell 12[i,j] can acquire imaging data.

[0107] In Figure 10, weight data is written to cell 12[i,j+1], cell 12[i+1,j], and cell 12[i+1,j+1], and then cell 12[i,j] acquires imaging data. However, one aspect of the present invention is not limited to this. Weight data may be written after the acquisition of imaging data. That is, the operations shown in period T11 may be performed after the operations shown in period T12 to period T15. For example, after writing imaging data to each of cell [i,j], cell 12[i,j+1], cell 12[i+1,j], and cell 12[i+1,j+1], weight data may be written so as to replace the imaging data held in cell 12[i,j+1], cell 12[i+1,j], and cell 12[i+1,j+1] with weight data.

[0108] During period T16, the potential of wiring 36 is set to a high potential, causing transistors 26[i,j], 26[i,j+1], 26[i+1,j], and 26[i+1,j+1] to conduct. As mentioned above, a high potential is supplied to wiring 46. Therefore, wirings 44[i,j], 44[i,j+1], 44[i+1,j], and 44[i+1,j+1] become high potential. As a result, wirings 44[i,j], 44[i,j+1], 44[i+1,j], and 44[i+1,j+1] are precharged. After the pre-charge is complete, the potential of the wiring 36 is set to a low potential, making transistors 26[i,j], 26[i,j+1], 26[i+1,j], and 26[i+1,j+1] non-conductive.

[0109] During period T17, the potentials of wiring 35[i] and wiring 35[i+1] are set to a high potential, causing transistors 25[i,j], 25[i,j+1], 25[i+1,j], and 25[i+1,j+1] to conduct. During period T17, for example, a high potential can be supplied simultaneously to wiring 35[1] to wiring 35[m].

[0110] Here, the potential of node FD[i,j] during period T17 is set to potential VFD[i,j], the potential of node FD[i,j+1] is set to potential VFD[i,j+1], the potential of node FD[i+1,j] is set to potential VFD[i+1,j], and the potential of node FD[i+1,j+1] is set to potential VFD[i+1,j+1]. Furthermore, the threshold voltage of transistor 24[i,j] is set to potential Vth[i,j], the threshold voltage of transistor 24[i,j+1] is set to potential Vth[i,j+1], the threshold voltage of transistor 24[i+1,j] is set to potential Vth[i+1,j+1], and the threshold voltage of transistor 24[i+1,j+1] is set to potential Vth[i+1,j+1]. In addition, as mentioned above, the potential of wiring 47 is set to potential VSS. Furthermore, the potential VFD[i,j] is greater than the potential "Vth[i,j]+VSS", the potential VFD[i,j+1] is less than the potential "Vth[i,j+1]+VSS", the potential VFD[i+1,j] is less than the potential "Vth[i+1,j]+VSS", and the potential VFD[i+1,j+1] is greater than the potential "Vth[i+1,j+1]+VSS".

[0111] Figure 11 is a circuit diagram illustrating the operation of the imaging device 10 during period T17. In Figure 11, transistors that are not conducting are marked with an "x". Current is indicated by arrows.

[0112] As shown in Figure 11, during period T17, transistors 25[i,j], 25[i,j+1], 25[i+1,j], 25[i+1,j+1], 27[j], and 27[j+1] are conducting. Also, transistors 26[i,j], 26[i,j+1], 26[i+1,j], and 26[i+1,j+1] are not conducting.

[0113] During period T16, wires 44[i,j], 44[i,j+1], 44[i+1,j], and 44[i+1,j+1] were precharged to a high potential. Also, as mentioned above, a low potential was supplied to wire 47. Therefore, wire 44 is electrically connected to the drain of transistor 24, and wire 45 is electrically connected to the source of transistor 24 via transistor 25.

[0114] As mentioned above, during period T17, transistors 25 and 27 are in a conducting state. Therefore, the source potential of transistor 24 is potential VSS. Thus, if the gate potential of transistor 24 is greater than or equal to the sum of the threshold voltage of transistor 24 and potential VSS, transistor 24 is in a conducting state. On the other hand, if the gate potential of transistor 24 is less than the sum of the threshold voltage of transistor 24 and potential VSS, transistor 24 is in a non-conducting state. As mentioned above, the gate potential VFD[i,j] of transistor 24[i,j] is greater than the sum of the threshold voltage Vth[i,j] and potential VSS. Also, the gate potential VFD[i+1,j+1] of transistor 24[i+1,j+1] is greater than the sum of the threshold voltage Vth[i+1,j+1] and potential VSS. As a result, transistors 24[i,j] and 24[i+1,j+1] become conductive. This causes wiring 44[i,j] and wiring 47 to become conductive, and the potential of wiring 44[i,j] becomes low. Also, wiring 44[i+1,j+1] and wiring 47 become conductive, and the potential of wiring 44[i+1,j+1] becomes low.

[0115] On the other hand, the gate potential VFD[i,j+1] of transistor 24[i,j+1] is less than the sum of the threshold voltage Vth[i,j+1] and the potential VSS. Also, the gate potential VFD[i+1,j] of transistor 24[i+1,j] is less than the sum of the threshold voltage Vth[i+1,j] and the potential VSS. Therefore, transistors 24[i,j+1] and 24[i+1,j] are in a non-conductive state. As a result, the potentials of wiring 44[i,j+1] and 44[i+1,j] remain at the high potential, which is the precharge potential.

[0116] Therefore, during period T17, the imaging data and weight data held in cell 12 can be output as binary data from wiring 44. This allows the imaging data and weight data held in cell 12 to be read out.

[0117] The imaging data and weight data output by cell 12 to wiring 44 are supplied to logic circuit 51. Logic circuit 51 performs calculations using this imaging data and weight data. For example, sum-of-products operations are performed as shown in Figures 4A, 4B, 5A, and 5B. Since the imaging data and weight data output by cell 12 to wiring 44 are binary data, they can be supplied to logic circuit 51 without A / D conversion.

[0118] During period T18, the potential of wiring 35[i] and wiring 35[i+1] is set to a low potential, and transistors 25[i,j], 25[i,j+1], 25[i+1,j], and 25[i+1,j+1] are made non-conductive. This completes the readout of imaging data x, weight data w1, weight data w2, and weight data w3. During period T17, for example, a low potential can be supplied simultaneously to wiring 35[1] through wiring 35[m].

[0119] During period T19, first, the potential of wiring 53[h] is set to a high potential, making transistors 52[h,k] and 52[h,k+1] conductive. Then, the potential of wiring 53[h] is set to a low potential, making transistors 52[h,k] and 52[h,k+1] non-conductive. After that, the potential of wiring 53[h+1] is set to a high potential, making transistors 52[h+1,k] and 52[h+1,k+1] conductive. Then, the potential of wiring 53[h+1] is set to a low potential, making transistors 52[h+1,k] and 52[h+1,k+1] non-conductive. As a result, the calculation result from logic circuit 51 can be read out. As described above, by inputting the read calculation result into a neural network such as a CNN, image processing can be performed.

[0120] The above is an example of a driving method for the imaging device 10 in the second mode.

[0121] <Example configuration of imaging device_2> Figure 12A is a circuit diagram showing an example configuration of cell 12, and is a modified version of the configuration shown in Figure 2A. Cell 12 shown in Figure 12A differs from cell 12 shown in Figure 2A in that it does not have transistor 26, but does have transistor 28. The following will mainly describe the configuration that differs from cell 12 shown in Figure 2A.

[0122] One source or drain of transistor 24 is electrically connected to one source or drain of transistor 25, one source or drain of transistor 28, and wiring 44. The other source or drain of transistor 24 is electrically connected to wiring 46. The other source or drain of transistor 25 is electrically connected to wiring 45. The other source or drain of transistor 28 is electrically connected to wiring 48. The gate of transistor 28 is electrically connected to wiring 38.

[0123] Wiring 48 functions as a power line. For example, a low potential can be supplied to wiring 48.

[0124] As will be explained in more detail later, a source follower circuit is formed by transistors 24 and 28 by supplying a bias potential to wiring 38. In this case, the input terminal of the source follower circuit is electrically connected to node FD, and the output terminal is electrically connected to wiring 44. Therefore, the imaging data and weight data held in cell 12 can be output to wiring 44 as analog data.

[0125] As transistor 28, a transistor of the same type as transistors 22 to 25 can be used. For example, as transistor 28, an OS transistor or a Si transistor can be used.

[0126] Figure 12B is a circuit diagram showing an example configuration of cell 12, and is a modified version of the configuration shown in Figure 12A. Cell 12 shown in Figure 12B differs from cell 12 shown in Figure 12A in that the cathode of the photoelectric conversion element 21 is electrically connected to either the source or the drain of the transistor 22, and the anode of the photoelectric conversion element 21 is electrically connected to the wiring 41.

[0127] Figure 13 is a circuit diagram showing an example configuration of the arithmetic circuit 17 when cell 12 has the configuration shown in Figure 12A or Figure 12B. The arithmetic circuit 17 shown in Figure 13 differs from the arithmetic circuit 17 shown in Figure 3 in that it has an A / D conversion circuit 54.

[0128] The input terminals of the A / D conversion circuit 54 are electrically connected to the wiring 44, and the output terminals of the A / D conversion circuit 54 are electrically connected to the input terminals of the logic circuit 51. Here, the number of input terminals and output terminals of the A / D conversion circuit 54 can be the same as the number of input terminals of the logic circuit 51. For example, they can be m × n.

[0129] The A / D conversion circuit 54 has the function of converting the analog data output by the cell 12 to the wiring 44 into digital data. As described above, when the imaging device 10 is driven in the second mode, the imaging data or weight data held by the cell 12 is output to the wiring 44. Therefore, by providing the A / D conversion circuit 54 between the wiring 44 and the logic circuit 51, even when the cell 12 outputs the imaging data or weight data as analog data from the wiring 44, the logic circuit 51 can perform calculations using the imaging data and weight data.

[0130] <An example of how to drive an imaging device_2> In the following, an example of a driving method for an imaging device 10, in which cell 12 has the configuration shown in Figure 12A and the arithmetic circuit 17 has the configuration shown in Figure 13, will be explained using Figures 15 to 17. Specifically, an example of a driving method for cells 12[i,j], 12[i,j+1], 12[i+1,j], 12[i+1,j+1], transistor 27[j], transistor 27[j+1], transistor 52[h,k], transistor 52[h,k+1], transistor 52[h+1,k], and transistor 52[h+1,k+1], in the configuration shown in Figure 12A, will be explained. Figure 14 is a circuit diagram showing the components of the imaging device 10 that illustrate an example of a driving method. As shown in Figure 14, it is assumed that the potential VSS is supplied to wiring 47 as a low potential. It is also assumed that the high potential is supplied to wiring 41 and wiring 46. Furthermore, it is assumed that the low potential is supplied to wiring 48.

[0131] In the following explanation of the driving method, all transistors are assumed to be n-channel type transistors. However, by appropriately changing the relative potentials, the following explanation of the driving method can be applied even if some or all transistors are p-channel type. Furthermore, as shown in Figure 14, the explanation of the driving method assumes that cell 12 has the configuration shown in Figure 12A. However, by appropriately changing the relative potentials, the following explanation can be applied even if cell 12 has the configuration shown in Figure 12B.

[0132] Figure 15 is a timing chart showing an example of how to drive the imaging device 10 when it is driven in the first mode. As mentioned above, in the first mode, no calculations using weight data are performed.

[0133] During periods T21 to T25, a low potential is supplied to wiring 38, causing transistors 28[i,j], 28[i,j+1], 28[i+1,j], and 28[i+1,j+1] to be in a non-conductive state. Otherwise, the operation during periods T21 to T25 can be the same as the operation during periods T01 to T05 in the timing chart shown in Figure 8. Note that the bias potential supplied to wiring 37 during periods T21 to T25 is defined as bias potential Vb1.

[0134] Figure 17A is a circuit diagram showing a configuration from Figure 12A, with the transistor that can be kept in a non-conductive state for the entire period from T21 to T25 omitted. In addition to the configuration of cell 12, Figure 17A also shows transistor 27, to which a bias potential Vb1 is supplied to the gate during periods T21 to T25. As mentioned above, transistor 28 is in a non-conductive state during periods T21 to T25. Therefore, transistor 28 is not shown in the circuit diagram of Figure 17A.

[0135] Next, an example of how to drive the imaging device 10 in the second mode will be described. Specifically, as shown in Figure 9, an example of how to drive the imaging device 10 will be described when cell 12[i,j] acquires imaging data x, and writes weight data w1 to cell 12[i,j+1], weight data w2 to cell 12[i+1,j], and weight data w3 to cell 12[i+1,j+1]. Figure 16 is a timing chart showing an example of how to drive the imaging device 10 when the imaging device 10 is driven in the second mode.

[0136] The potentials of wiring 32, wiring 33, wiring 35, wiring 37, wiring 43, wiring 53, and node FD during periods T31 to T35 can be the same as the potentials of wiring 32, wiring 33, wiring 35, wiring 37, wiring 43, wiring 53, and node FD during periods T11 to T15 of the timing chart shown in Figure 10. Furthermore, the potentials of wiring 32, wiring 33, wiring 35, wiring 37, wiring 43, wiring 53, and node FD during period T36 can be the same as the potentials of wiring 32, wiring 33, wiring 35, wiring 37, wiring 43, wiring 53, and node FD during period T19 of the timing chart shown in Figure 10.

[0137] During periods T31 to T36, a bias potential Vb2 is supplied to the wiring 38. Figure 17B is a circuit diagram showing a configuration in which the transistor that can be in a non-conductive state for the entire duration of periods T31 to T36 is omitted from the circuit diagram shown in Figure 12A. As shown in Figure 16, the transistor 25 is in a non-conductive state during periods T31 to T36. Therefore, the transistor 25 is not shown in the circuit diagram shown in Figure 17B.

[0138] As described above, during periods T31 to T36, a bias potential Vb2 is supplied to the gate of transistor 28. In addition, a high potential is supplied to wiring 46 and a low potential is supplied to wiring 48. Thus, transistors 24 and 28 constitute a source follower circuit 29. Here, the input terminal of the source follower circuit 29 is electrically connected to node FD, and the output terminal of the source follower circuit 29 is electrically connected to wiring 44. During periods T31 to T36, analog data of a potential corresponding to the potential of node FD can be continuously output from wiring 44. As a result, imaging data x corresponding to VFD[i,j], which is the potential of node FD[i,j], can be output from wiring 44[i,j+1]. In addition, weight data w1 corresponding to VFD[i,j+1], which is the potential of node FD[i,j+1], can be output from wiring 44[i,j+1]. Furthermore, wiring 44[i+1,j] can output weight data w2 corresponding to VFD[i+1,j], which is the potential of node FD[i+1,j]. In addition, wiring 44[i+1,j+1] can output weight data w3 corresponding to VFD[i+1,j+1], which is the potential of node FD[i+1,j+1].

[0139] The above is an example of a driving method for the imaging device 10, in which cell 12 has the configuration shown in Figure 12A and the arithmetic circuit 17 has the configuration shown in Figure 13.

[0140] As described above, by configuring cell 12 as shown in Figure 12A or Figure 12B, the imaging data and weighting data output by cell 12 from wiring 44 in the second mode can be made into analog data. The analog data output by cell 12 from wiring 44 is then converted into digital data by the A / D conversion circuit 54 and supplied to the logic circuit 51. Thus, the imaging data and weighting data input to the logic circuit 51 can be made into multi-level digital data.

[0141] <Example of imaging device configuration_3> Figures 18A and 18B are perspective views showing examples of the configuration of the imaging device 10. Figure 18A shows an example configuration with a stacked structure of layer 561 and layer 562.

[0142] Layer 561 has a photoelectric conversion element 21. The photoelectric conversion element 21 can be formed by stacking layers 565a, 565b, and 565c, as shown in Figure 18C.

[0143] The photoelectric conversion element 21 shown in Figure 18C is a pn junction type photodiode, for example, with p in layer 565a. + n-type semiconductor in layer 565b, n-type semiconductor in layer 565c + A type semiconductor can be used. Alternatively, n in layer 565a. + P-type semiconductor, p-type semiconductor in layer 565b, p-type semiconductor in layer 565c + A type i semiconductor may be used. Alternatively, a pin-junction photodiode with layer 565b being an i-type semiconductor may be used.

[0144] The above-mentioned pn-junction photodiodes or pin-junction photodiodes can be formed using single-crystal silicon. Furthermore, pin-junction photodiodes can also be formed using thin films of amorphous silicon, microcrystalline silicon, polycrystalline silicon, etc.

[0145] Furthermore, the photoelectric conversion element 21 in layer 561 may be a stack of layers 566a, 566b, 566c, and 566d, as shown in Figure 18D. The photoelectric conversion element 21 shown in Figure 18D is an example of an avalanche photodiode, where layers 566a and 566d correspond to electrodes, and layers 566b and 566c correspond to the photoelectric conversion section.

[0146] Layer 566a is preferably a low-resistance metal layer. For example, aluminum, titanium, tungsten, tantalum, silver, or a lamination thereof can be used.

[0147] It is preferable to use a conductive layer with high light transmittance to visible light for layer 566d. For example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, or graphene can be used. It is also possible to omit layer 566d.

[0148] The photoelectric conversion layers 566b and 566c can be configured as a pn junction type photodiode, for example, with a selenium-based material as the photoelectric conversion layer. It is preferable to use a p-type semiconductor selenium-based material for layer 566b and an n-type semiconductor such as gallium oxide for layer 566c.

[0149] Photoelectric devices using selenium-based materials exhibit high external quantum efficiency for visible light. These photoelectric devices utilize avalanche multiplication to significantly amplify electrons in response to incident light. Furthermore, selenium-based materials have a high light absorption coefficient, offering production advantages such as the ability to fabricate the photoelectric conversion layer as a thin film. Thin films of selenium-based materials can be formed using methods such as vacuum deposition or sputtering.

[0150] Selenium-based materials that can be used include crystalline selenium such as single-crystal selenium and polycrystalline selenium, amorphous selenium, compounds of copper, indium, and selenium (CIS), or compounds of copper, indium, gallium, and selenium (CIGS).

[0151] n-type semiconductors are preferably formed from materials with a wide bandgap and transparency to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or oxides containing a mixture of these materials can be used. These materials also function as hole injection blocking layers, which can reduce dark current.

[0152] Furthermore, the photoelectric conversion element 21 of layer 561 may be a stack of layers 567a, 567b, 567c, 567d, and 567e, as shown in Figure 18E. The photoelectric conversion element 21 shown in Figure 18E is an example of an organic photoconductive film, where layers 567a and 567e correspond to electrodes, and layers 567b, 567c, and 567d correspond to the photoelectric conversion part.

[0153] In the photoelectric conversion section, either layer 567b or layer 567d can be a hole transport layer, and the other can be an electron transport layer. Additionally, layer 567c can be a photoelectric conversion layer.

[0154] For the hole transport layer, for example, molybdenum oxide can be used. For the electron transport layer, for example, fullerenes such as C60 and C70, or their derivatives, can be used.

[0155] As the photoelectric conversion layer, a mixed layer of n-type organic semiconductors and p-type organic semiconductors (bulk heterojunction structure) can be used.

[0156] As shown in Figure 18A, layer 562 can be, for example, a silicon substrate. This silicon substrate has Si transistors, etc. For example, the transistors of cell 12 and the transistors of arithmetic circuit 17 can be provided on layer 562. Also, for example, the transistors of the load driver circuit 13, the transistors of the data generation circuit 14, the transistors of the readout circuit 16, and transistor 27 can be provided on layer 562.

[0157] Furthermore, the imaging device 10 may have a laminated structure of layers 561, 563, and 562, as shown in Figure 18B.

[0158] Layer 563 may have OS transistors. In this case, layer 562 may have Si transistors. For example, the transistors of cell 12 and transistor 27 can be provided in layer 563, and the transistors of the arithmetic circuit 17 can be provided in layer 562. Also, for example, the transistors of the load driver circuit 13, the data generation circuit 14, and the readout circuit 16 can be provided in layer 562.

[0159] As shown in Figure 18B, the cell 12 provided in layer 563 and the arithmetic circuit 17 provided in layer 562 can be arranged so as to have an overlapping area. This reduces the occupied area of ​​the imaging device 10 and makes the imaging device 10 more compact. In the configuration of Figure 18B, layer 562 may be used as a support substrate, and the cell 12 and other circuits may be provided in layers 561 and 563.

[0160] As the semiconductor material used in OS transistors, metal oxides with an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more, can be used. Typical examples include indium-containing oxide semiconductors, such as CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) or CAC-OS (Cloud-Aligned Composite Oxide Semiconductor), which will be described later. CAAC-OS has stable atoms constituting the crystal, making it suitable for transistors where reliability is important. In addition, CAC-OS exhibits high mobility characteristics, making it suitable for transistors that require high-speed operation.

[0161] OS transistors exhibit extremely low off-current characteristics of a few yA / μm (current value per 1 μm channel width) due to the large energy gap of the semiconductor layer. Furthermore, OS transistors have characteristics that differ from Si transistors, such as the absence of impact ionization, avalanche breakdown, and short-channel effects, enabling the formation of highly reliable circuits with high voltage resistance. Additionally, variations in electrical characteristics caused by crystalline non-uniformity, which are problematic in Si transistors, are less likely to occur in OS transistors.

[0162] The semiconductor layer of an OS transistor can be a film represented as an In-M-Zn oxide containing, for example, indium, zinc, and M (a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium).

[0163] When the oxide semiconductor constituting the semiconductor layer is an In-M-Zn oxide, it is preferable that the atomic ratio of the metal elements in the sputtering target used to deposit the In-M-Zn oxide satisfy In≧M≧M and Zn≧M. Preferred atomic ratios of the metal elements in such a sputtering target include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, and In:M:Zn=5:1:8. The atomic ratio of the deposited semiconductor layer includes a variation of plus or minus 40% of the atomic ratio of the metal elements contained in the sputtering target.

[0164] For the semiconductor layer, an oxide semiconductor with a low carrier density is used. For example, the semiconductor layer has a carrier density of 1 × 10⁻¹⁶. 17 / cm 3 The following is preferably 1 × 10 15 / cm 3 More preferably 1 × 10 13 / cm 3 More preferably 1 × 10 11 / cm 3More preferably 1 × 10 10 / cm 3 It is less than 1 × 10 -9 / cm 3 Oxide semiconductors with the carrier densities described above can be used. Such oxide semiconductors are called high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. These oxide semiconductors have a low defect level density and are considered to be stable oxide semiconductors.

[0165] However, this is not limited to these, and any composition appropriate to the semiconductor and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor should be used. Furthermore, in order to obtain the semiconductor characteristics of the transistor, it is preferable to set the carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, or density of the semiconductor layer appropriately.

[0166] In oxide semiconductors that constitute a semiconductor layer, the presence of silicon, one of the Group 14 elements, or carbon increases oxygen vacancies, leading to n-type semiconductor formation. Therefore, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 2 × 10⁻¹⁰. 18 atoms / cm 3 The following is preferably 2 × 10 17 atoms / cm 3 The following applies:

[0167] Furthermore, alkali metals and alkaline earth metals can generate carriers when bonded with oxide semiconductors, which can increase the transistor's off-current. For this reason, the concentration of alkali metals or alkaline earth metals in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) should be set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0168] Furthermore, if nitrogen is present in the oxide semiconductor constituting the semiconductor layer, electrons, which act as carriers, are generated, increasing the carrier density and making it easier to achieve n-type characteristics. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. For this reason, the nitrogen concentration in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 5 × 10⁻¹⁰. 18 atoms / cm 3 The following is preferable:

[0169] Furthermore, if the oxide semiconductor constituting the semiconductor layer contains hydrogen, it can react with oxygen bonded to metal atoms to form water, thus potentially creating oxygen vacancies in the oxide semiconductor. If oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor may exhibit normally-on characteristics. Moreover, a defect containing hydrogen can function as a donor, generating electrons as carriers. Additionally, some of the hydrogen may combine with oxygen bonded to metal atoms to generate electrons as carriers. Therefore, transistors using oxide semiconductors with a high hydrogen content tend to exhibit normally-on characteristics.

[0170] Defects where hydrogen fills an oxygen vacancy can function as donors in oxide semiconductors. However, quantitatively evaluating such defects is difficult. Therefore, in oxide semiconductors, evaluation is sometimes done using carrier concentration rather than donor concentration. Accordingly, in this specification, the carrier concentration, assuming no electric field is applied, may be used as a parameter for oxide semiconductors, rather than the donor concentration. In other words, "carrier concentration" as described in this specification may sometimes be rephrased as "donor concentration."

[0171] Therefore, it is preferable that the hydrogen content in the oxide semiconductor be reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) should be 1 × 10⁻⁶. 20 atoms / cm 3 Less than 1 × 10 19atoms / cm 3 Less than 5x10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 It should be less than [amount]. By using an oxide semiconductor with sufficiently reduced impurities such as hydrogen in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0172] Furthermore, the semiconductor layer may have, for example, a non-single-crystal structure. Non-single-crystal structures include, for example, CAAC-OS having crystals oriented along the c axis, polycrystalline structures, microcrystalline structures, or amorphous structures. Among non-single-crystal structures, the amorphous structure has the highest defect level density, and CAAC-OS has the lowest defect level density.

[0173] An amorphous oxide semiconductor film, for example, has a disordered atomic arrangement and does not contain crystalline components. Alternatively, an amorphous oxide film, for example, has a completely amorphous structure and does not contain crystalline parts.

[0174] Furthermore, the semiconductor layer may be a mixed film having two or more regions from among amorphous, microcrystalline, polycrystalline, CAAC-OS, and single-crystal structures. The mixed film may have a single-layer structure or a stacked structure that includes, for example, two or more of the regions described above.

[0175] Figure 19A is a diagram illustrating an example of a cross-section of the imaging device 10 shown in Figure 18A. Layer 561 has a pn junction photodiode with silicon as the photoelectric conversion layer, which serves as the photoelectric conversion element 21. Layer 562 has Si transistors, and in Figure 19A, transistors 22 and 23 of the transistors in cell 12 are shown as examples.

[0176] In the photoelectric conversion element 21, layer 565a is p + Layer 565b is an n-type region, and layer 565c is an n-type region. +It can be a type region. In addition, a region 536 for connecting the power line and layer 565c is provided in layer 565b. For example, region 536 is p + It can be a type region.

[0177] Figure 20A is a cross-sectional view of the region indicated by the dashed line A1-A2 in Figure 19A, showing a cross-section in the channel width direction of transistor 22 and the like. As shown in Figure 20A, the Si transistor can be a fin type having a channel formation region on the silicon substrate 540. Alternatively, the Si transistor may be a planar type, as shown in Figure 20B, instead of a fin type.

[0178] Alternatively, as shown in Figure 20C, the transistor may have a semiconductor layer 545 made of a silicon thin film. The semiconductor layer 545 can be, for example, single-crystal silicon (SOI: Silicon on Insulator) formed on an insulating layer 546 on a silicon substrate 540.

[0179] Figure 19A shows an example of a configuration in which the electrical connection between the elements of layer 561 and the elements of layer 562 is obtained by bonding technology.

[0180] Layer 561 is provided with an insulating layer 542, a conductive layer 533, and a conductive layer 534. The conductive layer 533 and the conductive layer 534 have regions embedded in the insulating layer 542. The conductive layer 533 is electrically connected to layer 565a. The conductive layer 534 is electrically connected to region 536. In addition, the surfaces of the insulating layer 542, the conductive layer 533, and the conductive layer 534 are flattened so that their heights are the same.

[0181] Layer 562 is provided with an insulating layer 541, a conductive layer 531, and a conductive layer 532. The conductive layer 531 and the conductive layer 532 have regions embedded in the insulating layer 541. The conductive layer 531 is electrically connected to the source or drain of the transistor 22. The conductive layer 532 is electrically connected to the power line. In addition, the surfaces of the insulating layer 541, the conductive layer 531, and the conductive layer 532 are flattened so that their heights are the same.

[0182] Here, it is preferable that conductive layers 531 and 533 have the same main component metal element. Furthermore, it is preferable that conductive layers 532 and 534 have the same main component metal element. In addition, it is preferable that insulating layers 541 and 542 are composed of the same component.

[0183] For example, conductive layers 531, 532, 533, and 534 can be made of Cu, Al, Sn, Zn, W, Ag, Pt, or Au. Due to their ease of bonding, Cu, Al, W, or Au are preferred. In addition, insulating layers 541 and 542 can be made of silicon oxide, silicon oxide nitride, silicon nitride, silicon nitride, titanium nitride, or the like.

[0184] In other words, it is preferable to use the same metal material as described above for both the combination of conductive layer 531 and conductive layer 533, and the combination of conductive layer 532 and conductive layer 534. It is also preferable to use the same insulating material as described above for both insulating layer 541 and insulating layer 542. With this configuration, bonding can be performed with the boundary between layer 561 and layer 562 as the bonding position.

[0185] This bonding process provides electrical connections between the conductive layer 531 and conductive layer 533, and between the conductive layer 532 and conductive layer 534. It also provides a mechanically strong connection between the insulating layer 541 and insulating layer 542.

[0186] For joining metal layers, a surface activation bonding method can be used, in which oxide films and adsorbed impurity layers on the surface are removed by sputtering, and the cleaned and activated surfaces are brought into contact for bonding. Alternatively, a diffusion bonding method can be used, which uses a combination of temperature and pressure to bond the surfaces. In both cases, bonding occurs at the atomic level, resulting in a bond that is excellent not only electrically but also mechanically.

[0187] Furthermore, for joining insulating layers, a hydrophilic joining method can be used, in which highly flat surfaces are obtained by polishing, then hydrophilic treated with oxygen plasma or the like, and the surfaces are brought into contact for temporary joining, followed by dehydration by heat treatment to perform the final joining. Since bonding occurs at the atomic level in the hydrophilic joining method, a mechanically superior bond can be obtained.

[0188] When bonding layer 561 and layer 562, since insulating layers and metal layers are present on each bonding surface, for example, a combination of surface activation bonding and hydrophilic bonding methods can be used for bonding.

[0189] For example, a method can be used in which the surface is cleaned after polishing, an anti-oxidation treatment is applied to the surface of the metal layer, and then a hydrophilic treatment is performed before joining. Alternatively, the surface of the metal layer may be made of a metal that is difficult to oxidize, such as Au, and then a hydrophilic treatment is performed. In addition, joining methods other than those described above may also be used.

[0190] Figure 19B is a cross-sectional view of a pn junction photodiode using a selenium-based material as the photoelectric conversion layer in the photoelectric conversion element 21 shown in Figure 18A. It has layer 566a as one electrode, layers 566b and 566c as the photoelectric conversion layer, and layer 566d as the other electrode.

[0191] In this case, layer 561 can be formed directly on layer 562. Layer 566a is electrically connected to the source or drain of transistor 22. Layer 566d is electrically connected to the power line via conductive layer 537. The connection configuration with the transistor is the same even when an organic photoconductive film is used for the photoelectric conversion element 21.

[0192] Figure 21A is a diagram illustrating an example of a cross-section of the imaging device 10 shown in Figure 18B. Layer 561 has a pn junction photodiode with silicon as the photoelectric conversion layer, which serves as the photoelectric conversion element 21. Layer 562 has Si transistors, and in Figure 21A, transistors 52 and 61 of the transistors in the arithmetic circuit 17 are shown as examples. Here, transistor 61 can be a transistor in the logic circuit 51. Layer 563 has OS transistors, and transistors 22 and 23 included in the cell 12 are shown as examples. Layers 561 and 563 are shown as an example of a configuration in which electrical connection is obtained by bonding them together.

[0193] Figure 22A shows a detailed example of the OS transistor configuration. The OS transistor shown in Figure 22A is a self-aligned type in which an insulating layer is provided on a stack of oxide semiconductor layers and conductive layers, and a source electrode 705 and a drain electrode 706 are formed by providing grooves that reach the semiconductor layer.

[0194] The OS transistor can have a channel formation region, a source region 703, and a drain region 704 formed in an oxide semiconductor layer, as well as a gate electrode 701 and a gate insulating film 702. At least the gate insulating film 702 and the gate electrode 701 are provided in the groove. The groove may also be further provided with an oxide semiconductor layer 707.

[0195] The OS transistor may also have a self-aligned configuration, as shown in Figure 22B, in which the gate electrode 701 is used as a mask to form the source region and drain region in the semiconductor layer.

[0196] Alternatively, as shown in Figure 22C, a non-self-aligned top-gate transistor may be used, having a region where the source electrode 705 or drain electrode 706 and the gate electrode 701 overlap.

[0197] Transistors 22 and 23 have a back gate 535. Figure 22D is a cross-sectional view of the area indicated by the dashed line B1-B2 in Figure 22A, showing a cross-section in the channel width direction of transistor 22 and the like. The back gate 535 may be electrically connected to the front gate of the opposing transistor, as shown in Figure 22D. Although Figure 22D shows the transistor in Figure 22A as an example, the same applies to transistors with other structures. Furthermore, the back gate 535 may be configured to be supplied with a fixed potential different from that of the front gate. Note that transistors 22 and 23 may also have a structure without a back gate 535.

[0198] An insulating layer 543, which has the function of preventing hydrogen diffusion, is provided between the region where the OS transistor is formed and the region where the Si transistor is formed. Hydrogen in the insulating layer provided near the channel formation region of transistors 52 and 61 terminates the silicon dangling bond. On the other hand, hydrogen in the insulating layer provided near the channel formation region of transistors 22 and 23 becomes one of the factors that generate carriers in the oxide semiconductor layer.

[0199] The insulating layer 543 traps hydrogen in one layer, thereby improving the reliability of transistors 52 and 61. Furthermore, the diffusion of hydrogen from one layer to the other is suppressed, which also improves the reliability of transistors 22 and 23.

[0200] For example, the insulating layer 543 can be aluminum oxide, aluminum oxide nitride, gallium oxide, gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, hafnium oxide nitride, yttria-stabilized zirconia (YSZ), etc.

[0201] Figure 21B is a cross-sectional view of the imaging device 10 when a pn junction photodiode with a selenium-based material as the photoelectric conversion layer is used as the photoelectric conversion element 21. The layer 561 on which the photoelectric conversion element 21 is provided can be formed directly on layer 563. Details of layers 561, 562, and 563 can be found in the previous description. The connection configuration with the transistor is the same even when an organic photoconductive film is used as the photoelectric conversion element 21.

[0202] Figure 23A is a perspective view showing an example of the configuration of a colored layer (color filter) and the like in the imaging device 10. An insulating layer 580 is formed on the layer 561 on which the photoelectric conversion element 21 is formed. The insulating layer 580 can be made of a silicon oxide film or the like, which has high light transmittance to visible light. Alternatively, a silicon nitride film may be laminated as a passivation film. Alternatively, a dielectric film such as hafnium oxide may be laminated as an anti-reflective film.

[0203] A light-shielding layer 581 may be formed on the insulating layer 580. The light-shielding layer 581 has the function of preventing the mixing of colors of light passing through the upper colored layer. A metal layer such as aluminum or tungsten can be used for the light-shielding layer 581. Alternatively, a dielectric film having the function of an anti-reflective film may be laminated with the metal layer.

[0204] An insulating layer 582 can be provided as a planarization film on the insulating layer 580 and the light-shielding layer 581. In addition, a colored layer 583 (colored layer 583a, colored layer 583b, and colored layer 583c) is formed. For example, by assigning colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to the colored layers 583a, 583b, and 583c, a color image can be obtained.

[0205] An insulating layer 586 or the like, which is transparent to visible light, can be provided on the colored layer 583.

[0206] Furthermore, as shown in Figure 23B, an optical conversion layer 585 may be used instead of the colored layer 583. This configuration allows for an imaging device that can obtain images in various wavelength ranges.

[0207] For example, by using a filter that blocks light with wavelengths below visible light in the optical conversion layer 585, an infrared imaging device can be created. Furthermore, by using a filter that blocks light with wavelengths below near-infrared light in the optical conversion layer 585, a far-infrared imaging device can be created. Additionally, by using a filter that blocks light with wavelengths above visible light in the optical conversion layer 585, an ultraviolet imaging device can be created.

[0208] Furthermore, by using a scintillator in the optical conversion layer 585, the imaging device 10 can be made into an imaging device that obtains images visualizing the intensity of radiation used in X-ray imaging devices, etc. When radiation such as X-rays that has passed through the subject is incident on the scintillator, it is converted into visible light or ultraviolet light (fluorescence) by the photoluminescence phenomenon. Then, imaging data is obtained by detecting this light with the photoelectric conversion element 21. Alternatively, an imaging device with this configuration may be used in a radiation detector, etc.

[0209] A scintillator contains a substance that, when irradiated with radiation such as X-rays or gamma rays, absorbs the energy and emits visible light or ultraviolet light. Examples of such substances include those dispersed in a resin or ceramic, such as Gd2O2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, LiI, and ZnO.

[0210] Furthermore, in the photoelectric conversion element 21 using selenium-based materials, since radiation such as X-rays can be directly converted into electric charge, a configuration that does not require a scintillator can be adopted.

[0211] Furthermore, as shown in Figure 23C, a microlens array 584 may be provided on the insulating layer 586 such that it has a region overlapping with the colored layer 583. Light passing through each lens of the microlens array 584 passes through the colored layer 583 directly below and irradiates the photoelectric conversion element 21. Alternatively, the microlens array 584 may be provided such that it has a region overlapping with the optical conversion layer 585 shown in Figure 23B.

[0212] <Example of imaging device configuration_4> Figure 24A is a diagram illustrating an example of an imaging device 10, showing a configuration in which layer 564 is provided on the imaging device 10 shown in Figure 19A. Layer 564 is provided on layer 561. Layer 564 has an insulating layer 580, a light-shielding layer 581, an insulating layer 582, an insulating layer 586, and a colored layer 587.

[0213] An insulating layer 580 is formed on layer 561, and a light-shielding layer 581 and an insulating layer 582 are formed on the insulating layer 580. An insulating layer 586 is formed on the insulating layer 582, and a colored layer 587 is formed on the insulating layer 586.

[0214] The colored layer 587 can also function as a microlens. Therefore, there is no need to separately form a microlens in addition to the colored layer 587, and the imaging device 10 can be manufactured using a simple method. Furthermore, when light is shone on the interface of materials with different refractive indices, a portion of the shone light is reflected. For example, when light is shone on the interface between a microlens and a layer such as an insulating layer provided in contact with the bottom of the microlens, a portion of the light is reflected. Therefore, by not separately forming a microlens in addition to the colored layer, it is possible to suppress the attenuation of light shone on the imaging device 10 before it is received by the photoelectric conversion element 21. This makes it possible to increase the light detection sensitivity of the imaging device 10.

[0215] Figures 24B, 25A, and 25B illustrate an example of an imaging device 10. Figure 24B shows an example configuration in which layer 564 is provided to the imaging device 10 shown in Figure 19B, Figure 25A shows an example configuration in which layer 564 is provided to the imaging device 10 shown in Figure 21A, and Figure 25B shows an example configuration in which layer 564 is provided to the imaging device 10 shown in Figure 21B. The configuration of layer 564 in the imaging device 10 shown in Figures 24B, 25A, and 25B can be the same as the configuration of layer 564 in the imaging device 10 shown in Figure 24A.

[0216] Figure 26A is a diagram illustrating an example of the imaging device 10, and is a modified version of the imaging device 10 shown in Figure 24A. The imaging device 10 shown in Figure 26A differs from the imaging device 10 shown in Figure 24A in the configuration of the layer 564. The layer 564 provided in the imaging device 10 shown in Figure 26A has an insulating layer 580, a light-shielding layer 581, a colored layer 587, and an insulating layer 588.

[0217] An insulating layer 580 is formed on layer 561, and a light-shielding layer 581 and a colored layer 587 are formed on the insulating layer 580. As mentioned above, the colored layer 587 can also function as a microlens. Then, an insulating layer 588 is formed on the colored layer 587. The insulating layer 588 can be a planarized film. The insulating layer 588 can be, for example, a film that is transparent to visible light.

[0218] Figures 26B, 27A, and 27B illustrate an example of the imaging device 10, and are modified versions of the imaging device 10 shown in Figures 24B, 25A, and 25B, respectively. The imaging device 10 shown in Figures 26B, 27A, and 27B has the same configuration of layer 564 as layer 564 shown in Figure 26A.

[0219] Figure 28A is a perspective view showing an example configuration of layer 564 as shown in Figures 24A, 24B, 25A, and 25B. Figure 28B is a perspective view showing an example configuration of layer 564 as shown in Figures 26A, 26B, 27A, and 27B. As shown in Figures 28A and 28B, a colored layer 587 (colored layer 587a, colored layer 587b, and colored layer 587c) is formed. For example, a color image can be obtained by assigning colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to colored layers 587a, 587b, and 587c.

[0220] This embodiment can be combined with other embodiments as appropriate.

[0221] (Embodiment 2) This embodiment describes metal oxides (hereinafter also referred to as oxide semiconductors) that can be used in the OS transistor described in the above embodiment.

[0222] <Classification of crystal structures> First, we will explain the classification of crystal structures in oxide semiconductors using Figure 29A. Figure 29A is a diagram illustrating the classification of crystal structures in oxide semiconductors, specifically IGZO (a metal oxide containing In, Ga, and Zn).

[0223] As shown in Figure 29A, oxide semiconductors are broadly classified into "Amorphous," "Crystalline," and "Crystal." "Amorphous" includes completely amorphous materials. "Crystalline" includes CAAC, nc (nanocrystalline), and CAC. Note that single crystal, polycrystal, and completely amorphous materials are excluded from the "Crystalline" classification. "Crystal" includes single crystal and polycrystal materials.

[0224] The structure within the thick frame shown in Figure 29A represents an intermediate state between "Amorphous" and "Crystal," and belongs to a new boundary region (New crystalline phase). In other words, this structure can be described as being completely different from the energetically unstable "Amorphous" and "Crystal" states.

[0225] The crystal structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 29B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or Seemann-Bohlin method. Hereafter, the XRD spectrum obtained by the GIXD measurement shown in Figure 29B will simply be referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 29B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 29B is 500 nm.

[0226] As shown in Figure 29B, the XRD spectrum of the CAAC-IGZO film shows a peak indicating clear crystallinity. Specifically, the XRD spectrum of the CAAC-IGZO film shows a peak indicating c-axis orientation near 2θ=31°. As shown in Figure 29B, the peak near 2θ=31° is asymmetrical with respect to the angle at which the peak intensity was detected.

[0227] Furthermore, the crystal structure of a film or substrate can be evaluated by the diffraction pattern (also called the nano-beam electron diffraction pattern) observed using nano-beam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 29C. Figure 29C shows the diffraction pattern observed by NBED with the electron beam incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 29C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In nano-beam electron diffraction, electron diffraction is performed with a probe diameter of 1 nm.

[0228] As shown in Figure 29C, the diffraction pattern of the CAAC-IGZO film shows multiple spots indicating c-axis orientation.

[0229] <<Oxide semiconductor structure>> Note that when focusing on the crystal structure, oxide semiconductors may be classified differently from those shown in Figure 29A. For example, oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the aforementioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors also include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0230] Here, we will explain the details of the CAAC-OS, nc-OS, and a-like OS mentioned above.

[0231] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystal regions, and the c-axis of the plurality of crystal regions is oriented in a specific direction. Here, the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. Also, a crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, the crystal region is also a region where the lattice arrangements are aligned. Further, CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have strain. Here, strain refers to a portion where the direction of the lattice arrangement changes between a region where the lattice arrangements are aligned and another region where the lattice arrangements are aligned in a region where a plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor in which the c-axis is oriented and there is no clear orientation in the a-b plane direction.

[0232] Each of the plurality of crystal regions is composed of one or more minute crystals (crystals having a maximum diameter of less than 10 nm). When a crystal region is composed of one minute crystal, the maximum diameter of the crystal region is less than 10 nm. Also, when a crystal region is composed of a number of minute crystals, the size of the crystal region may be on the order of several tens of nm.

[0233] Also, in an In-M-Zn oxide (the element M is one or more selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing the element M, zinc (Zn), and oxygen (hereinafter, (M,Zn) layer) are laminated. Here, indium and the element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain the element M. Note that the In layer may also contain Zn. The layered structure is observed as a lattice image, for example, in a high-resolution TEM image.

[0234] When performing a structural analysis on a CAAC-OS film using, for example, an XRD device, in an out-of-plane XRD measurement using a θ / 2θ scan, a peak indicating c-axis orientation is detected at 2θ = 31° or in its vicinity. Note that the position of the peak indicating c-axis orientation (the value of 2θ) may vary depending on the type and composition of the metal elements constituting CAAC-OS.

[0235] Also, for example, in the electron diffraction pattern of a CAAC-OS film, a plurality of bright spots (spots) are observed. Note that one spot and another spot are observed at point-symmetric positions with the spot of the incident electron beam transmitted through the sample (also referred to as the direct spot) as the center of symmetry.

[0236] When observing the crystal region from the above specific direction, the lattice arrangement within the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. Also, in the above distortion, there may be a lattice arrangement such as a pentagon or a heptagon. Note that in CAAC-OS, even in the vicinity of the distortion, a clear grain boundary cannot be confirmed. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is presumably because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal atoms.

[0237] Note that a crystal structure in which a clear grain boundary is confirmed is called a so-called polycrystal. Grain boundaries can become recombination centers and are likely to cause the capture of carriers, resulting in a decrease in the on-current of a transistor and a decrease in the field-effect mobility. Therefore, CAAC-OS in which a clear grain boundary is not confirmed is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of a transistor. Note that for forming CAAC-OS, a configuration having Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are preferable because they can suppress the generation of grain boundaries more than In oxide.

[0238] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. Furthermore, since the crystallinity of oxide semiconductors can decrease due to the inclusion of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are heat-resistant and highly reliable. In addition, CAAC-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using CAAC-OS in OS transistors allows for greater flexibility in the manufacturing process.

[0239] [nc-OS] nc-OS exhibits periodicity in atomic arrangement in minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). In other words, nc-OS contains minute crystals. These minute crystals are also called nanocrystals because their size is, for example, between 1 nm and 10 nm, particularly between 1 nm and 3 nm. Furthermore, nc-OS shows no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Consequently, depending on the analytical method, nc-OS may be indistinguishable from a-like OS or amorphous oxide semiconductors. For example, when structural analysis of an nc-OS film is performed using an XRD instrument, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Also, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of the nanocrystals (e.g., 50 nm or larger), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystal (for example, 1 nm to 30 nm), an electron diffraction pattern may be obtained in which multiple spots are observed within a ring-shaped region centered on a direct spot.

[0240] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. a-like OS has porous or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS. Also, a-like OS has a higher hydrogen concentration in the film compared to nc-OS and CAAC-OS.

[0241] <<Oxide Semiconductor Composition>> Next, we will explain the details of CAC-OS mentioned above. Note that CAC-OS refers to the material composition.

[0242] [CAC-OS] CAC-OS is a material composition in which, for example, the elements constituting the metal oxide are unevenly distributed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide, and the regions containing these metal elements are mixed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size, is also referred to as a mosaic or patchy state.

[0243] Furthermore, CAC-OS is a composite metal oxide having a mosaic-like structure formed by the separation of the material into a first region and a second region, with the first region distributed within the film (hereinafter also referred to as a cloud-like structure). In other words, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0244] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is the region where [In] is greater than the [In] in the composition of the CAC-OS film. The second region is the region where [Ga] is greater than the [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is the region where [In] is greater than the [In] in the second region, and [Ga] is smaller than the [Ga] in the second region. The second region is the region where [Ga] is greater than the [Ga] in the first region, and [In] is smaller than the [In] in the first region.

[0245] Specifically, the first region described above is a region whose main components are indium oxide, indium zinc oxide, etc. The second region described above is a region whose main components are gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region whose main component is In. Similarly, the second region can be rephrased as a region whose main component is Ga.

[0246] Furthermore, a clear boundary may not be observed between the first region and the second region described above.

[0247] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) confirms that it has a structure in which regions mainly composed of In (first region) and regions mainly composed of Ga (second region) are unevenly distributed and mixed.

[0248] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulation due to the second region work complementaryly to give CAC-OS a switching function (on / off function). In other words, CAC-OS has conductive function in part of the material, insulating function in part of the material, and semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I) can be achieved. on This enables high field-effect mobility (μ) and good switching operation.

[0249] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention may include two or more of the following: amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0250] <Transistors containing oxide semiconductors> Next, we will explain the case where the above oxide semiconductor is used in a transistor.

[0251] By using the above-mentioned oxide semiconductor in transistors, it is possible to realize transistors with high field-effect mobility. Furthermore, it is possible to realize highly reliable transistors.

[0252] It is preferable to use an oxide semiconductor with a low carrier concentration for the transistor. For example, the carrier concentration of an oxide semiconductor is 1 × 10⁻⁶. 17 cm -3 The following is preferably 1 × 10 15 cm -3 More preferably 1 × 10 13 cm -3 More preferably 1 × 10 11 cm -3 More preferably 1 × 10 10 cm -3 It is less than 1 × 10 -9 cm-3 The above is the case. When reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be decreased and the density of defect levels may be decreased. In this specification and the like, the fact that the impurity concentration is low and the density of defect levels is low is referred to as highly pure intrinsic or substantially highly pure intrinsic. In some cases, an oxide semiconductor having a low carrier concentration may be referred to as a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor.

[0253] In addition, an oxide semiconductor film that is highly pure intrinsic or substantially highly pure intrinsic may have a low trap level density because the density of defect levels is low.

[0254] In addition, the charge trapped in the trap levels of the oxide semiconductor may take a long time to disappear and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor having a high trap level density may have unstable electrical characteristics.

[0255] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of the impurity include hydrogen, nitrogen, an alkali metal, an alkaline earth metal, iron, nickel, silicon, and the like.

[0256] <Impurity> Here, the influence of each impurity in the oxide semiconductor will be described.

[0257] In an oxide semiconductor, when silicon or carbon, which is one of the Group 14 elements, is contained, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are 2×10 18 atoms / cm 3 or less, preferably 2×1017 atoms / cm 3 shall be as follows.

[0258] In addition, when an alkali metal or an alkaline earth metal is contained in an oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, the concentration of an alkali metal or an alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0259] In addition, in an oxide semiconductor, when nitrogen is contained, electrons as carriers are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Or, in an oxide semiconductor, when nitrogen is contained, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to less than 5×10 19 atoms / cm 3 , preferably less than 5×10 18 atoms / cm 3 or less, more preferably 1×10 18 atoms / cm 3 or less, even more preferably 5×10 17 atoms / cm 3 or less.

[0260] In addition, since hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, oxygen vacancies may be formed. When hydrogen enters these oxygen vacancies, electrons, which are carriers, may be generated. Also, a part of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by SIMS is less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , still more preferably less than 1×10 18 atoms / cm 3 .

[0261] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0262] This embodiment can be appropriately combined with the descriptions of other embodiments.

[0263] (Embodiment 3) In this embodiment, an example of a package containing an image sensor chip and a camera module will be described. The above-described configuration of the imaging device can be used for the image sensor chip.

[0264] FIG. 30A1 is an external perspective view of the upper surface side of a package containing an image sensor chip. The package includes a package substrate 410 for fixing an image sensor chip 450, a cover glass 420, an adhesive 430 for bonding both, and the like. Note that the image sensor chip 450 is shown in FIG. 30A3 described later.

[0265] Figure 30A2 is a perspective view of the bottom surface of the package. The bottom surface of the package is provided with a BGA (Ball Grid Array) with solder balls as bumps 440. Note that it may also have an LGA (Land Grid Array) or a PGA (Pin Grid Array), etc., instead of a BGA.

[0266] Figure 30A3 is a perspective view of the package, with the cover glass 420 and a portion of the adhesive 430 omitted. Electrode pads 460 are formed on the package substrate 410, and the electrode pads 460 and bumps 440 are electrically connected via through-holes. The electrode pads 460 are electrically connected to the image sensor chip 450 by wires 470.

[0267] Figure 30B1 is a perspective view of the top side of a camera module in which an image sensor chip is housed in a lens-integrated package. The camera module includes a package substrate 411 for fixing the image sensor chip 451, a lens cover 421, and a lens 435, etc. An IC chip 490, which has functions such as a drive circuit and a signal conversion circuit for the imaging device, is also provided between the package substrate 411 and the image sensor chip 451, thus having a System in Package (SiP) configuration. The image sensor chip 451 and the IC chip 490 are shown in Figure 30B3, which will be described later.

[0268] Figure 30B2 is a perspective view of the lower side of the camera module. The package substrate 411 has a QFN (Quad flat no-lead package) configuration with mounting lands 441 on the lower and side surfaces. Note that this configuration is just an example, and a QFP (Quad flat package) or the aforementioned BGA may also be provided.

[0269] Figure 30B3 is a perspective view of the module, with the lens cover 421 and part of the lens 435 omitted. Land 441 is electrically connected to electrode pad 461, and electrode pad 461 is electrically connected to image sensor chip 451 or IC chip 490 by wire 471.

[0270] By housing the image sensor chip in the type of package described above, mounting it onto printed circuit boards and other devices becomes easier, allowing the image sensor chip to be incorporated into various semiconductor devices and electronic equipment.

[0271] This embodiment can be combined with other embodiments as appropriate.

[0272] (Embodiment 4) This embodiment describes an example of an electronic device that can use an imaging device according to one aspect of the present invention.

[0273] Electronic devices that can use an imaging device according to one aspect of the present invention include display devices, personal computers, image storage devices or image playback devices equipped with recording media, mobile phones, game consoles including portable ones, portable data terminals, e-book readers, cameras such as video cameras and digital still cameras, goggle-type displays (head-mounted displays), navigation systems, sound playback devices (car audio systems, digital audio players, etc.), photocopiers, facsimile machines, printers, printer-multifunction devices, automated teller machines (ATMs), vending machines, and the like. Specific examples of these electronic devices are shown in Figures 31A to 31F.

[0274] Figure 31A shows an example of a mobile phone 910, which includes a housing 911, a display unit 912, operation buttons 913, an external connection port 914, a speaker 915, a slot 916, a camera 917, an earphone jack 918, etc. The mobile phone 910 can be equipped with a touch sensor on the display unit 912. All operations, such as making a phone call or entering text, can be performed by touching the display unit 912 with a finger or stylus. In addition, various removable storage devices such as memory cards like SD cards, USB memory sticks, and SSDs (Solid State Drives) can be inserted into the slot 916.

[0275] An imaging device according to one aspect of the present invention can be applied to a mobile phone 910. For example, an imaging device according to one aspect of the present invention can be applied to elements for acquiring image data by the mobile phone 910, such as a camera 917. An imaging device according to one aspect of the present invention can perform part of the calculations by a neural network. Therefore, additional functions such as image recognition can be installed in the mobile phone 910. Furthermore, the power consumption of the mobile phone 910 can be reduced compared to when all of the calculations by the neural network are performed by software.

[0276] Figure 31B shows an example of a portable data terminal 920, which includes a housing 921, a display unit 922, a speaker 923, a camera 924, etc. Information can be input and output using the touch panel function of the display unit 922. In addition, characters can be recognized from images acquired by the camera 924, and these characters can be output as sound by the speaker 923.

[0277] An imaging device according to one aspect of the present invention can be applied to a mobile data terminal 920. For example, an imaging device according to one aspect of the present invention can be applied to elements for acquiring image data by the mobile data terminal 920, such as a camera 924. An imaging device according to one aspect of the present invention can perform part of the calculations by a neural network. Therefore, additional functions such as image recognition can be installed in the mobile data terminal 920. Furthermore, the power consumption of the mobile data terminal 920 can be reduced compared to when all of the calculations by the neural network are performed by software.

[0278] Figure 31C shows an example of a surveillance camera 960, which includes a mounting bracket 961, a housing 962, a lens 963, etc. The surveillance camera 960 can be mounted on a wall or ceiling using the mounting bracket 961. Note that "surveillance camera" is a common name and does not limit its use. For example, a device that functions as a surveillance camera is also called a camera or video camera.

[0279] An imaging device according to one aspect of the present invention can be applied to the surveillance camera 960. For example, an imaging device according to one aspect of the present invention can be applied to the elements for acquiring image data by the surveillance camera 960. The imaging device according to one aspect of the present invention can perform part of the calculations by a neural network. Therefore, additional functions such as image recognition can be installed in the surveillance camera 960. Furthermore, the power consumption of the surveillance camera 960 can be reduced compared to when all of the calculations by the neural network are performed by software.

[0280] Figure 31D shows an example of a video camera 940, which includes a first housing 941, a second housing 942, a display unit 943, operation keys 944, a lens 945, a connection unit 946, a speaker 947, a microphone 948, etc. The operation keys 944 and the lens 945 can be provided in the first housing 941, and the display unit 943 can be provided in the second housing 942.

[0281] An imaging device according to one aspect of the present invention can be applied to the video camera 940. For example, an imaging device according to one aspect of the present invention can be applied to the elements for acquiring image data by the video camera 940. The imaging device according to one aspect of the present invention can perform part of the calculations by a neural network. Therefore, additional functions such as image recognition can be equipped to the video camera 940. Furthermore, the power consumption of the video camera 940 can be reduced compared to when all of the calculations by the neural network are performed by software.

[0282] Figure 31E shows an example of a digital camera 950, which includes a housing 951, a shutter button 952, a light-emitting unit 953, a lens 954, etc. An imaging device according to one aspect of the present invention can be applied to the digital camera 950. For example, an imaging device according to one aspect of the present invention can be applied to the elements for acquiring image data by the digital camera 950. An imaging device according to one aspect of the present invention can perform part of the calculations by a neural network. Therefore, additional functions such as image recognition can be equipped to the digital camera 950. Furthermore, the power consumption of the digital camera 950 can be reduced compared to when all of the calculations by the neural network are performed by software.

[0283] Figure 31F shows an example of a wristwatch-type information terminal 930, which includes a housing / wristband 931, a display unit 932, operation buttons 933, an external connection port 934, a camera 935, etc. The display unit 932 is equipped with a touch panel for operating the information terminal 930. The housing / wristband 931 and the display unit 932 are flexible and offer excellent wearability on the body.

[0284] A semiconductor device according to one aspect of the present invention can be applied to the information terminal 930. For example, an imaging device according to one aspect of the present invention can be applied to elements for acquiring image data by the information terminal 930, such as a camera 935. The imaging device according to one aspect of the present invention can perform part of the calculations by a neural network. Therefore, additional functions such as image recognition can be installed in the information terminal 930. Furthermore, the power consumption of the information terminal 930 can be reduced compared to when all of the calculations by the neural network are performed by software.

[0285] Figure 32A shows an external view of an automobile as an example of a mobile device. Figure 32B is a simplified diagram showing data exchange inside the automobile. The automobile 890 has multiple cameras 891, etc. The automobile 890 is also equipped with various sensors (not shown), such as infrared radar, millimeter-wave radar, and laser radar.

[0286] An imaging device according to one aspect of the present invention can be applied to camera 891. This imaging device according to one aspect of the present invention can perform a portion of the calculations performed by a neural network. Therefore, additional functions such as image recognition can be incorporated into camera 891. Furthermore, the power consumption of the automobile 890 can be reduced compared to when all of the calculations performed by the neural network are done by software.

[0287] In the automobile 890, the integrated circuit 893 can be used in the camera 891, etc. The automobile 890 processes multiple images obtained by the camera 891 in multiple imaging directions 892 using the integrated circuit 893, and the multiple images are analyzed together by the host controller 895, etc., via the bus 894, etc. As a result, the automobile 890 can determine the surrounding traffic conditions, such as the presence or absence of guardrails or pedestrians, and perform autonomous driving. It can also be used in systems that perform road guidance, hazard prediction, etc.

[0288] The integrated circuit 893 can perform various processing tasks on the obtained image data, such as increasing image resolution, reducing image noise, face recognition (for security purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (widening dynamic range), image restoration of lensless image sensors, positioning, character recognition, and reduction of reflections.

[0289] In the above description, an automobile is used as an example of a mobile vehicle, but the automobile may be any type of vehicle, such as an automobile with an internal combustion engine, an electric vehicle, or a hydrogen vehicle. Furthermore, the mobile vehicle is not limited to an automobile. For example, examples of mobile vehicles include trains, monorails, ships, and aerial vehicles (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), and a computer according to one aspect of the present invention can be applied to these mobile vehicles to provide them with a system utilizing artificial intelligence.

[0290] This embodiment can be combined with other embodiments as appropriate. [Explanation of Symbols]

[0291] 10: Imaging device, 11: Cell array, 12: Cell, 13: Low driver circuit, 14: Data generation circuit, 16: Circuit, 17: Arithmetic circuit, 21: Photoelectric conversion element, 22: Transistor, 23: Transistor, 24: Transistor, 25: Transistor, 26: Transistor, 27: Transistor, 28: Transistor, 29: Source follower circuit, 32: Wiring, 33: Wiring, 35: Wiring, 36: Wiring, 37: Wiring, 38: Wiring, 41: Wiring, 43: Wiring, 44: Wiring, 45: Wiring, 46: Wiring, 47: Wiring, 48: Wiring, 51: Logic circuit, 52: Transistor, 53: Wiring, 54: A / D conversion circuit, 61: Transistor, 410: Package substrate, 411: Package substrate, 420: Cover glass, 421: Lens cover, 430: Adhesive, 435: Lens, 440: Bump, 441: Land, 450: Image sensor chip, 451: Image sensor chip, 460: Electrode pad, 461: Electrode pad, 470: Wire, 471: Wire, 490: IC chip, 531: Conductive layer, 532: Conductive layer, 533: Conductive layer, 534: Conductive layer, 535: Back gate, 536: Region, 537: Conductive layer, 540: Silicon substrate 541: insulating layer, 542: insulating layer, 543: insulating layer, 545: semiconductor layer, 546: insulating layer, 561: layer, 562: layer, 563: layer, 564: layer, 565a: layer, 565b: layer, 565c: layer, 566a: layer, 566b: layer, 566c: layer, 566d: layer, 567a: layer, 567b: layer, 567c: layer, 567d: layer, 567e: layer, 580: insulating layer, 581: light-shielding layer, 582: insulating layer, 583: colored layer, 583a: colored layer, 583b: colored layer, 583c: colored layer, 584: microlens array, 585: optical conversion layer, 586: insulating layer, 587: colored layer , 587a: Colored layer, 587b: Colored layer, 587c: Colored layer, 588: Insulating layer, 701: Gate electrode, 702: Gate insulating film, 703: Source region, 704: Drain region, 705: Source electrode, 706: Drain electrode, 707: Oxide semiconductor layer, 890: Automobile, 891: Camera, 892: Imaging direction, 893: Integrated circuit, 894: Bus, 895: Host controller, 910: Mobile phone, 911: Housing, 912: Display unit, 913: Operation buttons, 914: External connection port, 915: Speaker, 916: Socket, 917: Camera, 918: Earphone jack,920: Portable data terminal, 921: Housing, 922: Display unit, 923: Speaker, 924: Camera, 930: Information terminal, 931: Housing and wristband, 932: Display unit, 933: Operation buttons, 934: External connection port, 935: Camera, 940: Video camera, 941: Housing, 942: Housing, 943: Display unit, 944: Operation keys, 945: Lens, 946: Connection unit, 947: Speaker, 948: Microphone, 950: Digital camera, 951: Housing, 952: Shutter button, 953: Light emitter, 954: Lens, 960: Surveillance camera, 961: Mounting bracket, 962: Housing, 963: Lens,

Claims

1. A cell array having a plurality of cells, each containing a photoelectric conversion element and first to fourth transistors, a data generation circuit, a logic circuit, a readout circuit, a fifth transistor, and a first wiring that functions as a power line, The aforementioned multiple cells are arranged in a matrix, One electrode of the photoelectric conversion element is electrically connected to either the source or the drain of the first transistor. The source or drain of the first transistor is electrically connected to the source or drain of the second transistor. Either the source or the drain of the second transistor is electrically connected to the gate of the third transistor. The source or drain of the second transistor, the other of which is electrically connected to the data generation circuit, Either the source or drain of the third transistor is electrically connected to either the source or drain of the fourth transistor. The source or drain of the third transistor, the other of which is electrically connected to the logic circuit, The source or drain of the fourth transistor, the other of which is electrically connected to the readout circuit, Either the source or the drain of the fifth transistor is electrically connected to the readout circuit. An imaging device in which the source or drain of the fifth transistor is electrically connected to the first wiring.

2. A cell array having a plurality of cells, each containing a photoelectric conversion element and first to fourth transistors, a data generation circuit, a logic circuit, a readout circuit, a fifth transistor, and a first wiring that functions as a power line, The aforementioned multiple cells are arranged in a matrix, One electrode of the photoelectric conversion element is electrically connected to either the source or the drain of the first transistor. The source or drain of the first transistor is electrically connected to the source or drain of the second transistor. Either the source or the drain of the second transistor is electrically connected to the gate of the third transistor. The source or drain of the second transistor, the other of which is electrically connected to the data generation circuit, Either the source or drain of the third transistor is electrically connected to either the source or drain of the fourth transistor. The source or drain of the third transistor, the other of which is electrically connected to the logic circuit, The source or drain of the fourth transistor, the other of which is electrically connected to the readout circuit, Either the source or the drain of the fifth transistor is electrically connected to the readout circuit. The source or drain of the fifth transistor, the other of which is electrically connected to the first wiring, Each of the first transistor and the second transistor has a metal oxide in the channel forming region. The imaging device comprises the metal oxide In, Zn, and M (where M is Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf).

Images