Search system

Abstract

To provide an AI system for creating a netlist from a document showing a circuit diagram or a circuit configuration.SOLUTION: An AI system SIH includes an input / output interface INTFC, a control unit CTL, and a conversion unit PTN. The input / output interface is electrically connected to the control unit. The conversion unit is electrically connected to the control unit. The input / output interface has a function of transmitting input data generated by user operation, to the control unit. The control unit has a function of transmitting the input data to the conversion unit. The input data is a circuit diagram showing a circuit configuration or a document file containing the circuit configuration. The conversion unit includes a circuit equipped with a neural network. The system converts the input data to a netlist using the neural network in the conversion unit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to an AI system and a method for operating the AI ​​system.

[0002] One aspect of the present invention is not limited to the above-mentioned technical field. The technical field relates to a product, a method, or a method of manufacture. Alternatively, one aspect of the present invention is: Process, machine, manufacture, or composition of matter This relates to the technology of one aspect of the present invention disclosed more specifically herein. The fields include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, energy storage devices, imaging devices, Memory devices, signal processing devices, processors, electronic devices, systems, methods for driving them, and A manufacturing method or inspection method thereof can be given as an example. [Background technology]

[0003] Artificial neural networks (hereinafter referred to as neural networks) are nerves It is an information processing system modeled after a circuit network. It utilizes neural networks. Therefore, it is expected that a computer with higher performance than conventional von Neumann architecture can be realized. In recent years, various studies have been conducted on constructing neural networks on electronic circuits. Yes, they are.

[0004] For example, Patent Document 1 describes a method for converting the charging characteristics of a secondary battery into image data and performing convolutional microscopy. Using a neural network (CNN), the normal characteristics of the secondary battery are determined from the image data. A control system is disclosed that identifies abnormal characteristics. Also, for example, the patent document Submission 2 discloses a system for analyzing literature data using neural networks and other technologies. It is being done. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] International Publication No. 2019 / 021095 [Patent Document 2] Japanese Patent Publication No. 2018-49430 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] When manufacturing electronic devices, semiconductor devices, semiconductor wafers, etc., for example, their specifications The specifications are predetermined, and the circuit diagram is created based on those specifications. However, if the specifications are the same However, depending on the creator of the circuit diagram, the orientation and placement of wiring, circuit elements, etc. may differ. It may be designed in this way. Therefore, even if the specifications and circuit configuration are the same, the appearance of the circuit diagram may differ. Sometimes their eyes look different.

[0007] In other words, even if the specifications and circuit configuration are the same, depending on how the circuit is represented, there are many possibilities. A circuit diagram of the pattern may exist. Therefore, AI (Artificial Intel) Using image recognition processing such as (Igence), for example, in a certain database When performing an image search using a circuit diagram as the input image, the database contains specifications and circuit diagrams. Even if a circuit identical to the circuit diagram exists, its appearance may differ from the input image. Therefore, circuits within the database may not be included in the image search results.

[0008] One aspect of the present invention is an AI system that converts an image or document showing a circuit configuration into a netlist. One of the objectives is to provide a system that allows searching for circuit configurations. Alternatively, one aspect of the present invention provides a system that allows searching for circuit configurations. One of the objectives is to provide an AI system. Alternatively, one aspect of the present invention is to provide a novel AI system. One objective is to provide a system. Alternatively, one aspect of the present invention is a novel AI system. One of the objectives is to provide a method for its operation.

[0009] The problems addressed by one embodiment of the present invention are not limited to those listed above. This does not preclude the existence of other issues. These other issues are described in the following section. This is an issue not mentioned in the specification. Issues not mentioned in this section can be found in the specification or by those skilled in the art. This can be derived from drawings and other descriptions, and can be extracted as appropriate from these descriptions. Furthermore, one aspect of the present invention addresses at least one of the problems listed above and other problems. This invention solves the problems. One aspect of the present invention addresses the problems listed above, as well as other problems. You don't need to solve all of them. [Means for solving the problem]

[0010] (1) One aspect of the present invention comprises a first electronic device, the first electronic device having an input / output interface and The AI ​​system comprises a control unit and a first conversion unit. The input / output interface is The first conversion unit is electrically connected to the control unit. The output interface controls the input data generated by user operations. The control unit has a function to transmit to the first conversion unit, and the control unit has a function to transmit the input data to the first conversion unit. The first conversion unit has a circuit in which a neural network is formed, and the first conversion unit has a neural It has the function of converting input data into a first netlist using a network. The input data is a circuit diagram showing the circuit configuration, or a document file indicating the circuit configuration. .

[0011] (2) Alternatively, in one aspect of the present invention, in the configuration of (1) above, the first electronic device is the first database It may have a first database and a second database. The first database is electrically connected to the control unit. The second database is connected to the control unit. The second netlist is stored, and the second database contains information linked to the second netlist. The attached bibliographic data is stored. The control unit targets the first database and the first database The function to search for the circuit configuration of the netlist, and the function to search for the circuit configuration of the first netlist. If a second netlist is found, the bibliographic data is read from the second database. It has the function of outputting to an input / output interface.

[0012] (3) Alternatively, in one aspect of the present invention, the configuration of (1) above has a second electronic device and a first electronic device The device has an external interface, and the second electronic device has a third database and a fourth data The third database may have a third database that is electrically connected to an external interface. The fourth database is then electrically connected to an external interface, and the third database The second netlist is stored in the second netlist. The bibliographic data linked to the to is stored. The control unit, via an external interface, Then, it communicates with the second electronic device and targets the third database, and the circuit of the first netlist. The function to search for configurations, and in searching for circuit configurations in the first netlist, the third database If a second netlist is found in the database, the bibliographic data will be retrieved from the fourth database. It has the function of outputting to an input / output interface.

[0013] (4) Alternatively, one aspect of the present invention comprises a first electronic device and a second electronic device, wherein the first electronic device is The second electronic device has an input / output interface, a control unit, and an external interface. The device is an AI system having a second conversion unit. The input / output interface is powered to the control unit. The external interface is electrically connected to the control unit and the second converter unit of the second electronic device, and is electrically connected to the control unit and the second converter unit of the second electronic device. They are connected in a specific way. Furthermore, the input / output interface can be operated by the user. It has a function to transmit the generated input data to the control unit, and the control unit processes the input data externally. It has the function of transmitting to the second conversion unit of the second electronic device via the interface. The first part has a circuit in which a neural network is formed, and the second conversion part has a neural network The control unit has the function of converting input data into a first netlist via a network, and the control unit is external It has the ability to obtain the first netlist from the second electronic device via an interface. The input data must be a circuit diagram showing the circuit configuration, or a document file indicating the circuit configuration. It is.

[0014] (5) Alternatively, in one aspect of the present invention, in the configuration of (4) above, the second electronic device is the third database The third database may have an external interface. The fourth database is electrically connected to the external interface. It is stored in the third database, and the fourth database The database stores bibliographic data linked to the second netlist. The control unit via an external interface, it communicates with the second electronic device and accesses the third database. The elephant has a function to search for the circuit configuration of the first netlist, and the circuit configuration of the first netlist In the search, if the second netlist is found in the third database, the bibliographic data It has the function of reading from the fourth database and outputting it to the input / output interface. ru.

[0015] (6) Alternatively, one aspect of the present invention includes an input / output interface, a control unit, and a first conversion unit. This is the operation method of the AI ​​system. The first conversion unit is configured with a neural network. It has a circuit, and the input / output interface is electrically connected to the control unit, and the first conversion The unit is electrically connected to the control unit. The operation method of the AI ​​system is the first to third steps It has a . The first step is that the input data created by the user is input to the control unit. The first step involves a neural network of the first transformer, and the second step involves a neural network of the first transformer. The third step is to convert the input data into a first netlist, and the control unit The process includes a step of outputting to an input / output interface.

[0016] (7) Alternatively, the operation method of (6) described above, which is one aspect of the present invention, comprises the fourth to sixth steps. That is also fine. The AI ​​system has a first database and a second database, and also the Database 1 is electrically connected to the control unit, and Database 2 is electrically connected to the control unit. They are connected. The first database stores the second netlist, and the second data The database stores bibliographic data linked to the second netlist. The first step is to search for the circuit configuration of the first netlist in the first database. The fifth step involves finding the second netlist from the first database in the fourth step. If this occurs, the literature data will be read from the second database, and the input / output interface will be used. The sixth step involves outputting to the second database in the fourth step. If the netlist is not found, the control unit will determine that the first netlist is in the first database The system includes a step of outputting information to the input / output interface indicating that it could not be found. ru.

[0017] In this specification, a semiconductor device is a device that utilizes semiconductor properties. Circuits containing structural elements (transistors, diodes, photodiodes, etc.), and circuits having the same This refers to devices, etc. It also refers to all devices that can function by utilizing semiconductor properties. For example, Integrated circuits, chips containing integrated circuits, and electronic components that house chips in a package are called semiconductors. This is an example of a device. Furthermore, storage devices, display devices, light-emitting devices, lighting devices, and electronic equipment are also examples. It is a semiconductor device in itself, and may have a semiconductor device.

[0018] Furthermore, if it is stated in this specification, etc., that X and Y are connected, then X and When Y is electrically connected, when X and Y are functionally connected, and when X and The case in which Y and are directly connected is disclosed in this specification, etc. Furthermore, the predetermined connection relationships, for example, the connection relationships shown in the diagram or text, are not limited to those shown in the diagram or text. Other connection relationships besides those shown are also disclosed in the diagram or text. X and Y are, Let's assume the object is (for example, a device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.). .

[0019] One example of a case where X and Y are electrically connected is when the electrical connection between X and Y is possible. Elements that perform this function (for example, switches, transistors, capacitive elements, inductors, resistive elements, etc.) One or more (electrodes, display devices, light-emitting devices, loads, etc.) are connected between X and Y. It is possible to do so. Furthermore, the switch has a function that controls on / off. In other words, the switch can be in a conductive state (on state) or a non-conductive state (off state), and current flows. It has a function to control whether or not to release the fluid.

[0020] One example of a functional connection between X and Y is a functional connection between X and Y. Circuits that can perform this function (for example, logic circuits (inverters, NAND gates, NOR gates, etc.), signals) Conversion circuits (digital-to-analog conversion circuits, analog-to-digital conversion circuits, gamma correction circuits, etc.) ), potential level conversion circuit (power supply circuit (boost circuit, buck circuit, etc.), changes the potential level of the signal Level shifter circuits, etc.), voltage sources, current sources, switching circuits, amplification circuits (signal amplitude or Circuits that can increase the amount of current, etc., operational amplifiers, differential amplifiers, source follower circuits, batteries One or more circuits (such as FA circuits, signal generation circuits, memory circuits, control circuits, etc.) are located between X and Y. It is possible to connect them. For example, if another circuit is placed between X and Y... However, if a signal output from X is transmitted to Y, then X and Y are functionally connected. It shall be considered as such.

[0021] Furthermore, if it is explicitly stated that X and Y are electrically connected, then X and Y are electrically connected. When connected electrically (i.e., connected with another element or circuit in between X and Y) (if such a connection exists) and (if X and Y are functionally connected) (When functionally connected with another circuit in between) and when X and Y are directly connected (That is, the case where X and Y are connected without another element or circuit in between) It shall be assumed that they are electrically connected. In other words, when explicitly stating that they are electrically connected, simply, This is equivalent to the case where it is explicitly stated that it is "continued."

[0022] Also, for example, "X and Y and the source (or first terminal, etc.) and drain of the transistor ( (or the second terminal, etc.) are electrically connected to each other, and X is the source of the transistor. (or the first terminal, etc.), the transistor drain (or the second terminal, etc.), and Y in that order. It can be expressed as, "It is electrically connected." Or, "The source of the transistor ( The first terminal (or the first terminal, etc.) is electrically connected to X, and the drain (or second terminal) of the transistor is connected to X. The terminals (or other terminals) are electrically connected to Y, and X is the source of the transistor (or the first terminal, etc.). The transistor's drain (or second terminal, etc.), Y, are electrically connected in this order. It can be expressed as "X is the source (or first terminal) of the transistor." Alternatively, "X is the source (or first terminal) of the transistor." Y is electrically connected to X, via the drain (or second terminal, etc.) and X, The source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal) (etc.), Y is provided in this connection order. By using a similar method of expression to specify the order of connections in the circuit configuration, Connect the source (or first terminal, etc.) and the drain (or second terminal, etc.) of the transistor. By distinguishing between them, the technical scope can be determined. Note that these expressions are just examples. However, it is not limited to these methods of expression. Here, X and Y are objects (e.g., devices, elements, (This refers to circuits, wiring, electrodes, terminals, conductive films, layers, etc.)

[0023] Note that, in circuit diagrams, independent components are shown as being electrically connected to each other. Even if such a combination exists, one component may possess the functions of multiple components. Yes. For example, if part of the wiring also functions as an electrode, one conductive film will function as the wiring, and It possesses the functions of both components of the electrode. Therefore, in this specification Electrically connected means that a single conductive film combines the functions of multiple components. This also falls under that category.

[0024] Furthermore, in this specification, the term "resistive element" refers to a circuit element, wiring, etc., that has a resistance value. Therefore, in this specification, etc., "resistive element" refers to a wiring having a resistance value, source- This includes transistors, diodes, coils, etc., through which current flows between the drains. Therefore, the term "resistive element" is used in contexts such as "resistance," "load," and "region having a resistance value." These terms can be rephrased as follows: Conversely, terms such as "resistance," "load," and "region with resistance" are used. This can be rephrased as terms such as "resistive element." As for the resistance value, for example, The impedance is 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ It can be between Ω and 1Ω. Also, for example, 1Ω or more, 1 × 109 Even if it is less than Ω good.

[0025] Furthermore, in this specification, etc., "capacitive element" means a circuit element having a capacitance value, electrostatic This includes areas of wiring that have capacitance values, parasitic capacitance, and the gate capacitance of transistors. Therefore, in this specification, etc., "capacitive element" refers to a pair of electrodes and an element contained between the electrodes. Dielectrics, as well as circuit elements containing them, parasitic capacitances appearing between wiring and transistors This includes the gate capacitance that appears between the source or drain of the gate and the gate. Furthermore, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" are used in conjunction with terms like "capacitance." It can be rephrased as a word, and conversely, the term "capacitance" can be used as "capacitive element," "parasitic capacitance," It can be rephrased as terms such as "gate capacitance". Also, the "pair of electrodes" in "capacitance" and The term can be rephrased as "a pair of conductors," "a pair of conductive regions," or "a pair of regions." This is possible. The capacitance value should, for example, be between 0.05 fF and 10 pF. This is possible. Alternatively, for example, it may be set to between 1 pF and 10 μF.

[0026] Furthermore, in this specification, a transistor is referred to as gate, source, and drain. It has three terminals. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as source or drain are the input and output terminals of the transistor. The input / output terminals specify the transistor's conductivity type (n-channel type, p-channel type) and the transistor's... Depending on the potential applied to the three terminals of the sta, one becomes the source and the other the drain. Therefore, in this specification, the terms source and drain may be rephrased. be achievable. In addition, in this specification and the like, when explaining the connection relationship of transistors, the notations " one of the source or drain" (or the first electrode, or the first terminal), "the other of the source or drain" (or the second electrode, or the second terminal) are used. Note that depending on the structure of the transistor, in addition to the three terminals described above, there may be a back gate. In this case , in this specification and the like, one of the gate or back gate of the transistor may be referred to as the first gate 》and the other of the gate or back gate of the transistor may be referred to as the second gate <000(0899>. Furthermore, in the same transistor, the terms "gate" and "back gate" may be interchangeable with each other. Also, when the transistor has three or more gates , in this specification and the like, each gate may be referred to as the first gate, the second gate, the third gate, etc. .

[0027] Also, in this specification and the like, a node can be equivalently referred to as a terminal, a wire, an electrode, a conductive layer, a conductor, an impurity region, etc., depending on the circuit configuration, device structure, etc. Also, a terminal, a wiring, etc. can be equivalently referred to as a node.

[0028] Also, in this specification and the like, "voltage" and "potential" can be equivalently replaced as appropriate. " Voltage" is the potential difference from a reference potential. For example, if the reference potential is the ground potential (ground potential), "voltage" can be replaced with "potential". The ground potential does not necessarily mean 0V. Note that potential is relative, and depending on the reference potential, the potential applied to a wiring or the like may be changed.

[0029] Generally, "electric current" refers to the phenomenon of electric charge transfer associated with the movement of a positively charged object (electrical conduction). Although defined, the statement "electrical conduction is occurring in a positively charged body" implies "the opposite is true." This can be rephrased as "electrical conduction of a negatively charged body is occurring." Therefore, this specification, etc. In this context, "electric current" refers to the phenomenon of electric charge movement associated with the movement of carriers (electric current) unless otherwise specified. This refers to gas conduction. Here, carriers are electrons, holes, anions, and cations. Examples include complex ions, and systems through which electric current flows (e.g., semiconductors, metals, electrolytes, vacuum, etc.). The carrier differs depending on the carrier. Also, the "direction of current" in wiring, etc., is determined by the positive carrier. The direction of movement is expressed as a positive current. In other words, the direction in which negative carriers move is This is in the opposite direction to the current and is expressed as a negative current. Therefore, in this specification, If there is no indication of the positive or negative (or direction) of the current, then "current flows from element A to element B." Descriptions such as "current flows" can be rephrased as "current flows from element B to element A." It shall be as follows. Also, descriptions such as "current is input to element A" shall be changed to "current is output from element A." It can be rephrased as "to be," etc.

[0030] Furthermore, in this specification, the ordinal numbers "1st," "2nd," and "3rd" refer to constituent elements. This was added to avoid confusion. Therefore, it does not limit the number of constituent elements. Furthermore, this does not limit the order of the components. For example, one of the embodiments described herein The components referred to as "first" in this invention may be used in other embodiments or claims. It may also be the component referred to in "Section 2". For example, in this specification, etc. In one embodiment, the component referred to as "first" may be used in other embodiments, or in other embodiments. It may be possible to omit certain details within the scope of the permitted claim.

[0031] Furthermore, in this specification, phrases indicating placement such as "above" and "below" refer to the relative positions of the components. In some cases, positional relationships are used for convenience in explaining them by referring to diagrams. The relative positions of the elements change appropriately depending on the direction in which each element is depicted. Therefore, The terminology is not limited to what is explained in the detailed document, etc., and can be appropriately rephrased depending on the situation. For example, However, in the expression "insulator located on the upper surface of the conductor," the orientation of the diagram shown should be rotated 180 degrees. By rephrasing it, it can be described as "an insulator located on the underside of a conductor."

[0032] Furthermore, the terms "up" and "down" refer to situations where the relative positions of the constituent elements are directly above or directly below, and directly connected. It does not limit what is being done. For example, if the expression is "electrode B on insulating layer A", It is not necessary for electrode B to be directly in contact with insulating layer A, and the insulating layer A and electrode B are not in direct contact. This does not exclude those that include other components in between.

[0033] Furthermore, in this specification, terms such as "membrane" and "layer" may be interchanged depending on the context. It is possible to change the term. For example, the term "conductive layer" can be changed to the term "conductive film." It may be possible to change it. Or, for example, change the term "insulating film" to "insulating layer". It may be possible to change the terminology to this. Or, depending on the circumstances, or depending on the situation. Therefore, it is possible to replace terms such as "membrane" and "layer" with other terms without using them. For example, changing the term "conductive layer" or "conductive film" to the term "conductor" It may be possible. Or, for example, the terms "insulating layer" and "insulating film" could be changed to "insulator". It may be possible to change to such terms.

[0034] Also, in this specification and the like, terms such as "electrode", "wiring", "terminal", etc. do not functionally limit these constituent elements. For example, an "electrode" may be used as part of "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where a plurality of "electrodes" and "wirings" are integrally formed. Also, for example, a "terminal" may be used as part of "wiring" or "electrode", and vice versa. Furthermore, the term "terminal" includes cases where a plurality of "electrodes", "wirings", "terminals", etc. are integrally formed. Therefore, for example, an "electrode" can be part of "wiring" or "terminal", and, for example, a "terminal" can be part of "wiring" or "electrode". Also, the terms "electrode", "wiring", "terminal", etc. may be replaced with terms such as "region" in some cases. Also, in this specification and the like, terms such as "wiring", "signal line", "power supply line", etc. may be interchangeable depending on the case or according to the situation. For example, the term "wiring" may be changed to the term "signal line" in some cases. Also, for example z

[0035] the term "wiring" may be changed to terms such as "power supply line" in some cases. Also, vice versa, terms such as "signal line" and "power supply line" may be changed to the term "wiring" in some cases. The term "power supply line" etc. may be changed to the term "signal line" etc. in some cases. Also, vice versa, terms such as "signal line" etc. may be changed to the term "power supply line" in some cases, and vice versa, the terms "signal line", etc. may be changed to the term "power supply line" in some cases. Also, vice versa, the terms "signal line", etc. may be changed to the term "power supply line" in some cases. In some cases, it may be possible to change the terminology to terms such as the "potential" applied to the wiring. Depending on the situation, the term "signal" may be changed to a different term such as "traffic light." In some cases, this is possible. Conversely, terms like "signal" and "electric potential" are also possible. It may be possible to change the terminology.

[0036] In this specification, semiconductor impurities refer to, for example, components other than the main components that constitute the semiconductor layer. For example, elements with a concentration of less than 0.1 atomic percent are considered impurities. For example, when DOS (Density of States) is formed in a semiconductor... In some cases, this can lead to a decrease in carrier mobility or a decrease in crystallinity. If the semiconductor is an oxide semiconductor, impurities that change the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and elements other than the main component. These include transition metals, and in particular, for example, hydrogen (also found in water), lithium, sodium, These include silicon, boron, phosphorus, carbon, and nitrogen. When the semiconductor is a silicon layer, the semiconductor Examples of impurities that alter the properties of the body include, for example, Group 1 elements and Group 2 elements excluding oxygen and hydrogen. These include elements from Group 13 and Group 15.

[0037] In this specification, a switch refers to a conductive state (on state) or a non-conductive state (off state). This refers to a device that has the function of controlling whether or not to allow current to flow when it enters a certain state. Alternatively, it can refer to a switch. A switch is a device that has the function of selecting and switching the path through which electric current flows. One example is... Electrical switches, mechanical switches, etc. can be used. In other words, switches are Any device capable of controlling the current will suffice; it is not limited to any specific device.

[0038] An example of an electrical switch is a transistor (for example, a bipolar transistor). MOS transistors, diodes (for example, PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) die Od, MIS (Metal Insulator Semiconductor) die Odes, diode-connected transistors, etc., or logic circuits combining these. There is. Furthermore, when using a transistor as a switch, the "conductivity state" of the transistor... This refers to a state where the source and drain electrodes of a transistor can be considered to be electrically short-circuited. It refers to a state. Also, the "non-conductive state" of a transistor is when the source electrode and the drive of the transistor are not connected. This refers to a state in which the input electrode can be considered electrically isolated. Note that a transistor is not simply a transistor. When operating as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0039] One example of a mechanical switch is MEMS (Micro-Electro-Mechanical Systems). There are switches that use (STEM) technology. These switches are capable of being moved mechanically. It has electrodes, and operates by controlling the transition between conductivity and non-conductivity through the movement of these electrodes.

[0040] In this specification, "parallel" means that two lines are positioned at an angle of -10° or more and 10° or less. This refers to a state in which it is in a certain condition. Therefore, it also includes cases where the angle is between -5° and 5°. Also, "abbreviated "Parallel" or "approximately parallel" means that two lines are positioned at an angle of -30° or more and 30° or less. It refers to a state in which two lines are aligned at an angle of 80° to 100°. This refers to the state in which something is placed. Therefore, it also includes cases where the angle is between 85° and 95°. Also, "Approximately perpendicular" or "roughly perpendicular" means that two lines are positioned at an angle of 60° to 120°. This refers to a state of being in a certain condition. [Effects of the Invention]

[0041] According to one aspect of the present invention, AI converts an image or document showing a circuit configuration into a netlist. A system can be provided. Alternatively, according to one aspect of the present invention, a circuit configuration can be searched. It is possible to provide a capable AI system. Or, according to one aspect of the present invention, a novel AI A system can be provided. Or, according to one aspect of the present invention, a novel AI system This can provide a method for its operation.

[0042] The effects of one embodiment of the present invention are not limited to those listed above. This does not preclude the existence of other effects. These other effects are described in the following section. This is an effect not mentioned in the specification. Effects not mentioned in this section can be described in the specification or by those skilled in the art. This can be derived from drawings and other descriptions, and can be extracted as appropriate from these descriptions. Furthermore, one aspect of the present invention provides at least one of the effects listed above and other effects. It has the effect of, in some cases, the effects listed above. They may not always be present. [Brief explanation of the drawing]

[0043] [Figure 1] Figure 1 is a block diagram showing an example of the system configuration. [Figure 2] Figure 2 is a block diagram showing an example of the system configuration. [Figure 3] Figure 3 is a flowchart illustrating an example of the system's operation. [Figure 4] Figure 4 is a flowchart illustrating an example of the system's operation. [Figure 5] Figure 5 illustrates the procedure for creating a netlist from a circuit diagram. [Figure 6] Figure 6 illustrates the procedure for creating a netlist from a document file. [Figure 7] Figure 7 is a block diagram illustrating an example of system operation. [Figure 8] Figures 8A and 8B illustrate a hierarchical neural network. [Figure 9] Figure 9 is a block diagram showing an example of the configuration of an arithmetic circuit. [Figure 10] Figure 10 is a circuit diagram showing an example of the circuit configuration of an arithmetic circuit. [Figure 11] Figure 11 is a timing chart showing an example of the operation of the arithmetic circuit. [Figure 12] Figure 12 is a block diagram showing an example of the configuration of an arithmetic circuit. [Figure 13] Figure 13 is a circuit diagram showing an example of the configuration of an arithmetic circuit. [Figure 14] Figure 14 is a circuit diagram showing an example of the configuration of an arithmetic circuit. [Figure 15] Figure 15 is a circuit diagram showing an example of the configuration of an arithmetic circuit. [Figure 16] Figure 16 is a circuit diagram showing an example of an equivalent circuit of the arithmetic circuit in Figure 15. [Figure 17] Figure 17 is a block diagram showing an example of the configuration of an arithmetic circuit. [Figure 18] Figure 18 is a timing chart showing an example of the operation of the arithmetic circuit. [Figure 19] Figure 19 is a schematic cross-sectional diagram illustrating the configuration of a semiconductor device. [Figure 20] Figure 20 is a schematic cross-sectional diagram illustrating the configuration of a semiconductor device. [Figure 21] Figures 21A to 21C are schematic cross-sectional diagrams illustrating the configuration of a semiconductor device. [Figure 22]Figures 22A and 22B are schematic cross-sectional diagrams illustrating an example of transistor configuration. [Figure 23] Figure 23 is a schematic cross-sectional diagram illustrating an example of a semiconductor device configuration. [Figure 24] Figures 24A and 24B are schematic cross-sectional diagrams illustrating an example of transistor configuration. [Figure 25] Figure 25 is a schematic cross-sectional diagram illustrating an example of the configuration of a semiconductor device. [Figure 26] Figure 26A is a top view showing an example of the capacity configuration, while Figures 26B and 26C are cross-sectional perspective views showing an example of the capacity configuration. [Figure 27] Figure 27A is a top view showing an example of the capacity configuration, Figure 27B is a cross-sectional view showing an example of the capacity configuration, and Figure 27C is a cross-sectional perspective view showing an example of the capacity configuration. [Figure 28] Figure 28A illustrates the classification of IGZO crystal structures, Figure 28B illustrates the XRD spectrum of quartz glass, Figure 28C illustrates the XRD spectrum of crystalline IGZO, and Figure 28D illustrates the micro-electron diffraction pattern of crystalline IGZO. [Figure 29] Figure 29A is a circuit diagram showing the configuration of the multiplication circuit included in the prototype semiconductor device, and Figure 29B is an optical microscope image of the prototype semiconductor device. [Figure 30] Figure 30A is a graph showing the source-drain current IDS(VW, VX) of transistor M2 of the multiplier circuit included in the prototype semiconductor device when data corresponding to VW is written to the multiplier circuit and a voltage VX is applied to the wiring VX. Figure 30B is a graph showing the multiplication characteristics of the multiplier circuit included in the prototype semiconductor device calculated from Figure 30A. [Figure 31] Figure 31 is a graph showing the temperature dependence of the multiplication characteristics of the multiplication circuit included in the prototype semiconductor device. [Figure 32] Figures 32A and 32B are graphs showing the time evolution of the multiplication characteristics of the multiplication circuit included in the prototype semiconductor device. [Figure 33]Figure 33A is a graph showing the multiplication characteristics of the multiplication circuit included in the prototype semiconductor device, and Figure 33B is a graph showing the degree of variation in the multiplication characteristics of the multiplication circuit included in the prototype semiconductor device when each potential is written to it. [Figure 34] Figure 34 is a graph showing the degree of element variation in the read current of each of the multiple multiplier circuits included in the prototype semiconductor device. [Figure 35] Figures 35A, 35B, 35C, and 35D are graphs showing the degree of elemental variation in readout current in multiple multiplier circuit configurations, as determined by Monte Carlo analysis. [Figure 36] Figure 36 shows an example of a hierarchical artificial neural network model used to calculate inference accuracy. [Figure 37] Figure 37 is a circuit diagram illustrating an example of a semiconductor device configuration. [Figure 38] Figure 38A is a graph showing the product of the first data and the second data, and Figure 38B is a graph showing the calculated values ​​according to the number of rows in the memory cell array. [Figure 39] Figures 39A and 39B are histograms showing the variation in the product of the first and second data points when considering variations in the characteristics of the transistors. [Figure 40] Figure 40A is a graph showing the degree of agreement output from the output layers of a neural network constructed using a circuit simulator and a neural network constructed using a programming language, respectively. Figure 40B is a graph showing the correlation between the values ​​output from the output layers of a neural network constructed using a circuit simulator and a neural network constructed using a programming language, respectively. [Figure 41] Figure 41 shows an example of the output waveform from the output layer of a neural network constructed using a circuit simulator. [Modes for carrying out the invention]

[0044] In artificial neural networks (hereinafter referred to as neural networks): The synaptic connection strength is determined by providing existing information to the neural network. It can change. In this way, by giving existing information to a neural network, The process of determining the overall strength is sometimes called "learning."

[0045] Furthermore, for a neural network that has undergone "learning" (where connection strengths have been defined), By providing that information, new information can be output based on the bond strength. Thus, in a neural network, based on the given information and connection strength... The process of outputting new information is sometimes called "inference" or "cognition."

[0046] Examples of neural network models include the Hopfield type and the hierarchical type. One example is a multi-layered neural network called a "deep neural network." It is called a "deep neural network" (DNN), and machine learning using deep neural networks is called It is sometimes referred to as "deep learning."

[0047] In this specification, metal oxide refers to metal in a broad sense. It is an oxide. Metal oxides are oxide insulators and oxide conductors (including transparent oxide conductors). ), oxide semiconductor (also called OS) They are classified into the following categories. For example, when a metal oxide is used in the active layer of a transistor, the metal acid These materials are sometimes called oxide semiconductors. In other words, metal oxides have amplification and rectification effects. and constitute a channel formation region of a transistor having at least one switching action. If possible, the metal oxide is used as a metal oxide semiconductor. It can be called an OS conductor, or simply OS. It can also be called an OS FET, or OS When referring to a transistor, it means a transistor having a metal oxide or oxide semiconductor. It can be rephrased as "sta".

[0048] Furthermore, in this specification, metal oxides containing nitrogen are also referred to as metal oxides (metal oxides). They are sometimes collectively referred to as metal oxynitrides (metal oxides). Also, metal oxides containing nitrogen are sometimes called metal oxynitrides (metal oxides). It may also be called tal oxynitride.

[0049] Furthermore, in this specification, the configurations shown in each embodiment (or example) may be used in other embodiments. This can be combined with the configuration shown in (or other embodiments) as appropriate to form one embodiment of the present invention. Furthermore, if multiple configuration examples are shown within a single embodiment, these configuration examples should be considered in relation to each other. It is possible to combine them as needed.

[0050] Furthermore, the content described within one embodiment (or example) (even if only a part of it) This includes other information (even partial information) described in that embodiment (or example), and Contents described in one or more other embodiments (or one or more other embodiments) Apply, combine, or place at least one of the following (even if only a part of it is acceptable): Replacements and other modifications can be made.

[0051] Furthermore, the content described in each embodiment (or example) refers to the respective embodiment (or implementation) For example, the content described using various diagrams, or the content described using the text in the specification. It is the content of that.

[0052] Furthermore, the figures (even if only a part of them) described in one embodiment (or example) are... Another part of the figure, another figure described in the embodiment (or example thereof) (even if only a part of it) (i) In one or more other embodiments (or one or more other examples) By combining at least one of the figures (even a part of it) described above, This allows for the creation of even more diagrams.

[0053] Embodiments (or examples) described herein are explained with reference to the drawings. However, the embodiments (or examples) can be implemented in many different ways, and The form and details may be changed in various ways without deviating from the principle and scope thereof. This will be easily understood by anyone. Therefore, the present invention is the content of the embodiment (or example) It is not to be interpreted as being limited to the above. In these drawings, the same reference numeral is used for identical parts or parts with similar functions across different drawings. It is used in this way, and the repeated explanation may be omitted. Also, in perspective drawings, etc., For clarity, some components may be omitted from the description.

[0054] In this specification, when the same reference numeral is used for multiple elements, it is particularly important to distinguish between them. When necessary, add identifying codes such as "_1", "[n]", or "[m,n]" to the code. It may be noted or written down.

[0055] Furthermore, in the drawings of this specification, the size, thickness of the layers, or the area may be exaggerated for clarity. In some cases, this may be the case. Therefore, it is not necessarily limited to that scale. Note that the drawings are for reference only. It schematically shows an ideal example and is not limited to the shape or value shown in the drawings. For example it can include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0056] Regarding this specification, etc., "In:Ga:Zn = 4:2:3 or in the vicinity thereof" means that when In is 4 with respect to the total number of atoms, Ga is 1 or more and 3 or less (1 ≤ Ga ≤ 3), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, "In:Ga:Zn = 5:1:6 or in the vicinity thereof" means that when In is 5 with respect to the total number of atoms, Ga is greater than 0.1 and 2 or less (0.1 < Ga ≤ 2), and Zn is 5 or more and 7 or less (5 ≤ Zn ≤ 7). Also "In:Ga:Zn = 1:1:1 or in the vicinity thereof" means that when In is 1 with respect to the total number of atoms, Ga is greater than 0.1 and 2 or less (0.1 < Ga ≤ 2), and Zn is greater than 0.1 and 2 or less (0.1 < Zn ≤ 2). Also, "In:Ga:Zn = 5:1:3 or in the vicinity thereof" means that when In is 5 with respect to the total number of atoms, Ga is between 0.5 and 1.5 inclusive (0.5 ≤ Ga ≤ 1.5), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, "In:Ga:Zn = 10:1:3 or in the vicinity thereof" means that when In is 10 with respect to the total number of atoms, Ga is between 0.5 and 1.5 inclusive (0.5 ≤ Ga ≤ 1.5), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, "In:Zn = 2:1 or in the vicinity thereof" means that when In is 1 with respect to the total number of atoms, Zn is greater than 0.25 and less than 0.75 (0.25 < Zn ≤ 0.75). Also, "In:Zn = 5:1 or in the vicinity thereof" means that when In is 1 with respect to the total number of atoms, Zn is greater than 0.25 and , with respect to the total number of atoms, when In is 1, Zn is greater than 0.12 and less than or equal to 0.25 (0 .12 < Zn ≦ 0.25). Also, In:Zn = 10:1 or in the vicinity thereof means that when In is 1 with respect to the total number of atoms, Zn is greater than 0.07 and less than or equal to 0.12 (0.0 7 < Zn ≦ 0.12).

[0057] (Embodiment 1) In this embodiment, a system according to an aspect of the present invention will be described.

[0058] FIG. 1 shows a system (which may be referred to as an electronic device) having a function of converting "circuit drawings" and "circuit configurations described in the scope of claims" etc. in AI using a neural network into a netlist. Further, the system has a function of searching within an existing database using the converted netlist. (which may be referred to as an electronic device). Further, the system has a function of searching within an existing database using the converted netlist.

[0059] A netlist is data having connection information of circuit elements, logic circuits, signal conversion circuits, potential level conversion circuits, voltage sources, current sources, switching circuits, amplifier circuits, etc. included in an electronic circuit. Specifically, a netlist is data in which the connection destinations of terminals of circuit elements, circuits, etc. included in an electronic circuit are described, and is used in circuit simulators, circuit design software, etc. A netlist is data having connection information of circuit elements, logic circuits, signal conversion circuits, potential level conversion circuits, voltage sources, current sources, switching circuits, amplifier circuits, etc. included in an electronic circuit. Specifically, a netlist is data in which the connection destinations of terminals of circuit elements, circuits, etc. included in an electronic circuit are described, and is used in circuit simulators, circuit design software, etc. Specifically, a netlist is data in which the connection destinations of terminals of circuit elements, circuits, etc. included in an electronic circuit are described, and is used in circuit simulators, circuit design software, etc.

[0060] The system SIH shown in FIG. 1 has an electronic device ED. The electronic device ED has an input / output interface INTFC, a control unit CTL, a conversion unit PTN, a database DTB1, a database DTB2, and a storage unit MP.

[0061] ​​​​​The input / output interface INTFC is electrically connected to the control unit CTL. The INTFC power interface is used when a user utilizes the SIH system. It has the function of inputting and outputting information between the server and electronic equipment ED. Input / Output Interface Examples of INTFCs include organic EL (Electro Luminescence). Display devices such as displays and LCDs, keyboards, and pointing devices Examples of hardware include (for example, a mouse). Also, display equipment The device may have an input device such as a touch panel.

[0062] The memory unit MP is electrically connected to the control unit CTL. The memory unit MP is a volatile memory It has devices, non-volatile memory devices, etc.

[0063] Examples of volatile memory devices include DRAM (Dynamic Random Access Memory). Examples include cess memory. Volatile memory devices are, for example, in the process of calculations. It has functions such as temporarily storing data needed during software startup. ru.

[0064] Examples of non-volatile storage devices include HDDs (hard disk drives) and SSDs ( Examples include solid-state drives, optical discs, and magnetic tapes. When using optical discs, magnetic tapes, etc. in detailed documents, etc., reading and writing Devices capable of handling such data, along with optical discs, magnetic tapes, etc., are collectively referred to as non-volatile storage devices. Non-volatile memory devices, for example, can store software executable programs and circuit configurations. It has the function to save drawings, netlists of circuit configurations, and other related information.

[0065] The converter PTN is electrically connected to the control unit CTL. The converter PTN is shown in the circuit diagram. Document files that describe circuits in text (for example, the claims of a patent specification), etc. It has the function of converting to a netlist. The conversion unit PTN is, for example, a neural network It may also be an arithmetic circuit that constitutes the q. Alternatively, a neural network may be constructed in the conversion unit PTN. If this has been done, the neural network has already been trained, and the neural Assume that the weight coefficients between neurons in the network are fixed.

[0066] Database DTB1 is electrically connected to the control unit CTL. B1 has the function of storing document data such as patent specifications, papers, and other materials.

[0067] Database DTB2 is electrically connected to the control unit CTL. Database DT B2 refers to the number of times listed in the bibliographic data stored in database DTB1, for example. It has a function to save the netlist of the road, etc. Furthermore, the netlist contains the net Management numbers, management symbols, etc., for linking the TRist with the circuit configuration of the relevant document data. It may be included.

[0068] Note that databases DTB1 and DTB2 are considered to be a single database. You can combine them like this.

[0069] Furthermore, as mentioned above, databases DTB1 and DTB2 contain bibliographic data and Since netlists and other data are stored, database DTB1 and database DTB2 This may be included in the memory unit MP. In particular, database DTB1, database DT B2 is preferably a non-volatile storage device for the storage unit MP.

[0070] Furthermore, as shown in Figure 2, the electronic device ED may have an external interface INF. The external interface INF communicates with the electronic device WSV located outside the electronic device ED. It has the function of performing the following. Therefore, the external interface INF is connected to the control unit CTL and the electronics It is electrically connected to the WSV device.

[0071] The electronic device WSV can be, for example, an external server. Therefore, external input The interface INF is connected to the electronic device WSV via an internet connection, etc. It is preferable that they be present.

[0072] The electronic WSV includes, for example, database WDTB1 and database WDTB2. It has a conversion unit WPTN and the same as database WDTB1 and database DTB1. In this way, the literature data is stored. Also, the database WDTB2 contains database Similar to DTB2, the net of circuits described in the literature data of database WDTB1 Lists and other data are stored here. The WPTN converter, like the PTN converter, contains circuit diagrams and circuit diagrams. It has the function of converting document files and other text-based representations into netlists.

[0073] At least one of the database WDTB1, database WDTB2, and conversion unit WPTN is It may also function as an external server. Database WDTB1, Database WDTB2 By providing at least one of the conversion units WPTN as an external server, the provided server In some cases, it is possible to increase the scale, memory capacity, and computing power of a database. By having WDTB1 function as an external server, the database WDTB1 is used It may be possible to store more bibliographic data than database DTB1. Also, for example, By making the database WDTB2 function as an external server, the database WDTB Database 2 can store more information, such as netlists, than database DTB2. In some cases, the WPTN transformer performs calculations on a larger scale than the PTN transformer. It may have a circuit.

[0074] <<Example of operation 1>> Here, we will explain an example of operation in the system SIH shown in Figure 1. Figure 3 shows system S A flowchart showing an example of IH operation, wherein the example of system SIH operation is in step S It has steps TI01 to STI03. Also, Figure 3 shows the start of an example operation as “START”. It is written as "END" and the end of the operation example is indicated as "END". Note that in this operation example, the circuit diagram, Alternatively, this describes the process of converting a document file that describes a circuit in text into a netlist. .

[0075] Step STI01 is when the user uses the input / output interface INTFC to control electronics Input a circuit diagram or a document file describing the circuit into the control unit CTL of the ED. It has a function. The means by which the user inputs the circuit diagram is, for example, circuit design software. Using software such as airbrush, circuit simulator, paint software, and CAD software, Examples include methods for creating route maps. Also, methods for users to input information into the document file. For example, you can create document files using word processing software, text editors, etc. These include methods such as: circuit diagrams and document files in progress, and completed circuit diagrams. Document files and the like may be temporarily stored in the storage unit MP. The circuit diagram or document file created in step STI01 is referred to as input data.

[0076] In addition to the data created, the input data in step STI01 is also data You may also apply circuit diagrams, document files, etc., read from the database DTB1.

[0077] Step STI02 uses the input data created in Step STI01 to convert the PTN. It includes a step of converting to a setlist. Specifically, for example, the user inputs and outputs an input / output interface. - Using face INTFC, input data is sent to the control unit CTL, and said input data The control unit CTL sends a signal containing an instruction to convert the input data into a netlist. Upon receiving the signal, the input data is transmitted to the conversion unit PTN. Upon receiving the input data, it converts that input data into a netlist.

[0078] If the input data is a circuit diagram, one way to convert the input data to a netlist is, for example, For example, methods using convolutional neural networks (CNNs) are preferred. If the input data is a document file, the method for converting the input data into a netlist is as follows: Therefore, for example, a method using a recurrent neural network is preferable. Input data A specific example of how to convert this to a netlist will be discussed later.

[0079] The converted netlist may be temporarily stored in the memory unit MP.

[0080] Step STI03 takes the netlist converted in Step STI02 and inputs it to the input / output. The process includes a step of outputting to a display device or the like included in the INTFC interface. For example, the netlist converted in step STI02 is transmitted via the control unit CTL. It is then sent to a display device or other device included in the input / output interface INTFC. Later, by displaying the netlist on the display device, the user can change the input data. You can check the contents of the changed netlist.

[0081] After step STI03 is performed, this operation will terminate.

[0082] <<Example of operation 2>> Next, we will look at an example of operation in the system SIH shown in Figure 1, which is different from the flowchart shown in Figure 3. Let me explain. Figure 4 is a flowchart showing an example of the operation of the System SIH, and The flowchart further adds steps STI04 to STI08 to the example operation shown in Figure 3. This is an example of the added operation. Note that this example of operation uses the converted netlist to modify the circuit. This explains how to perform a search.

[0083] Steps STI01 to STI03, as shown in the flowchart in Figure 4, Please refer to the descriptions of steps STI01 to STI03 in the flowchart in Figure 3. To pour a drink.

[0084] Step STI04 uses the netlist converted in Step STI02 to perform data The process includes a step of searching for a circuit in the database DTB2. Specifically, for example, The CTL is stored in database DTB2. A signal is sent containing instructions to read the netlist linked to the bibliographic data. And, upon receiving the signal, the database DTB2 will then use the netlist The data is read and sent to the control unit CTL, which then converts it in step STI02. We will compare the netlist we obtained with the netlist contained in the database DTB2.

[0085] Note that the netlist linked to the bibliographic data from the DTB2 database is retrieved. This may target all netlists stored in database DTB2, You can also set conditions to narrow down the results to a subset of the netlists stored in the database DTB2. stomach.

[0086] Furthermore, the search performed in step STI04 is performed using the net converted in step STI02. You can extract items that are exact matches from the list, or items that are partially matches (similar items). You may also extract ).

[0087] Furthermore, the converted netlist used for searching may be temporarily stored in the memory unit MP. .

[0088] Furthermore, the circuit search performed in step STI04 may also utilize AI. For example, using AI, the netlist converted in step STI02 and the data The netlist linked to the bibliographic data stored in TabBase DTB2, and each By comparing these descriptions, we can see the types, number, and connection configurations of the circuit elements in each netlist. The search results are displayed by calculating a similarity score that indicates how closely the results match, and then sorting them by the similarity score. You may output this.

[0089] Step STI05 is a search in Step STI04 that is modified in Step STI02. A step to determine whether the replaced netlist was found in the database DTB2. It has. Here, the netlist found in database DTB2 is the step The netlist searched using STI04 may either be an exact match or a partial match. This shall include the following. In this determination, if the netlist searched in step STI04 is If found in the database DTB2, this operation proceeds to step STI06. In this determination, if the netlist searched in step STI04 is in database DTB If it is not found in step 2, this operation proceeds to step STI07.

[0090] Step STI06 is the search performed in step STI04 in database DTB2. The bibliographic data corresponding to the netlist used is read from database DTB1. It has a . Specifically, for example, the control unit CTL has a . The search for step STI04 yielded results, and the net data read from database DTB2 was retrieved. A signal is sent containing instructions to retrieve the bibliographic data corresponding to the list. Upon receiving the signal, DTB1 reads out the document data and controls the control unit C The data is sent to the TL. The control unit CTL receives the document data via the input / output interface INTFC. The document data is then transmitted to a display device or similar device. By displaying this information, users can review the content of the literature data.

[0091] Furthermore, the converted netlist used for the search, and the data read from database DTB1, The collected literature data may be temporarily stored in the memory unit MP.

[0092] After step STI06 is performed, this operation will terminate.

[0093] Step STI07 is a search in Step STI04 that is modified in Step STI02. Outputs the result that the replaced netlist could not be found in the database DTB2. It has a top. Specifically, for example, the control unit CTL has an input / output interface INTF For C, the netlist converted in step STI02 is in database DTB2. The system transmits information that the item could not be found. This information is then displayed on the display device, etc. By displaying it, the user can see that the netlist converted in step STI02 is in the database. You can check the search results, which indicate that the item was not found in DTB2.

[0094] Step STI08 stores the input data in database DTB1, and Step STI The process includes the step of storing the netlist converted in step 02 into the database DTB2. In essence, the user uses the input / output interface INTFC to communicate with the control unit CTL. Then, the command to save the input data and the netlist converted in step STI02. The control unit CTL receives the signal and input data. A signal containing a command to write data to database DTB1, and to database DTB1 The netlist that was sent and converted in step STI02, and the data of the said netlist A signal containing a command to write to database DTB2 is sent to database DTB2. At that time, the input data sent to database DTB1 and the data sent to database DTB2 The converted netlist is temporarily stored in memory MP, and then controlled You may send it via your CTL.

[0095] After step STI08 is performed, this operation will terminate.

[0096] Furthermore, the operation method according to one aspect of the present invention is described in steps STI01 to STI00 above. Not limited to 8. In this specification, etc., the processes shown in the flowchart are classified by function. They are shown as independent steps. However, in actual processing, etc., It is difficult to separate the processes shown in the low chart by function, and multiple steps are involved in one step. There may be cases where a step is involved, or where one step is involved across multiple steps. Therefore, the processes shown in the flowchart are not limited to each step described in the specification. They can be appropriately replaced depending on the situation. Specifically, depending on the situation, they can be replaced depending on the circumstances. Or, if necessary, rearrange the order of the steps, add steps, and delete steps, etc. It is possible. For example, step STI08 can be performed if the user does not want it to. You can remove it from the example and it doesn't need to be done.

[0097] It should be noted that the operation method of one aspect of the present invention is not limited to the operation example described in this embodiment. For example, as described above, the PTN conversion unit of the electronic device ED is used to convert input data into a netlist. Although an example of the conversion operation has been described, the conversion unit PTN is instead the conversion unit of the electronic device WSV. WPTN may also be used. In addition, as mentioned above, the database DTB1 of the electronic device ED, and We have explained an example of how to search for a netlist circuit using the database DTB2, but Database DTB1 and Database DTB2 are instead electronic WSV databases. You may also use WDTB1 and WDTB2 database.

[0098] Furthermore, according to one aspect of the present invention, an electronic device ED and an external electronic device WSV are used to input A service that converts force data to a netlist, and / or uses a netlist. You could offer a business model that charges a fee for services such as route search.

[0099] <<Example 1 of how to convert to a netlist>> Next, in step STI02 of the above example of operation, when the input data is represented as a circuit diagram, This section explains how to convert the circuit diagram into a netlist.

[0100] Figure 5 is a schematic diagram illustrating the process of converting a circuit diagram to a netlist.

[0101] In Figure 5, step PH1 is the input data that is input to the conversion unit PTN in step STI02. An example of an image is shown. The image PIC has a circuit diagram drawn on it, and this circuit diagram is... This shows the route symbols, wiring, and their connection configurations. In some cases, it also refers to the image in Figure 5. As shown in the PIC, the image PIC contains the names of circuit symbols, characters indicating the names of wiring, and other symbols. Any of these may be included. Also, the circuit diagram shown in the image PIC in Figure 5 includes the names of the circuit symbols, The wiring names do not need to include letters, symbols, or other identifiers.

[0102] In step PH2 of Figure 5, the image PIC from step PH1 is input to the conversion unit PTN, and the image PI This shows an example of object region recognition being performed for C. Figure 5, left side of stage PH2. In the PIC image, you can see the circuit symbol and the electrical connection points (such as the black circles in the circuit diagram shown in the PIC image). This corresponds to ). It shows how to recognize and enclose each with a dotted line. Depending on the method, object region recognition may include wiring.

[0103] Examples of object region recognition methods mentioned above include Objectness and CPM. C(Constrained Parametric Min-Cuts), Object Examples include proposals.

[0104] Next, after object region recognition is complete, image recognition is performed on each object region. This is done. This allows the conversion unit PT to determine what kind of circuit element the circuit symbol enclosed by the dotted line represents. It can be recognized by N. For example, in the image PIC on the left side of stage PH2 in Figure 5, By performing image recognition, the conversion unit PTN, for example, converts a circuit symbol enclosed by a thick dashed line into a capacitance element. It recognizes a child, and also recognizes, for example, a circuit symbol enclosed in a thick dashed line as a transistor. The conversion unit PTN recognizes which circuit element a circuit symbol represents, and Names to be used for the circuit symbol in the netlist (e.g., letters, abbreviations, symbols, words, etc.) ) can be attached.

[0105] Similarly, by performing image recognition, the PTN conversion unit's electrical connections enclosed by the dotted line It is possible to recognize parts (such as black circles). This allows the PTN converter to recognize electrical connections. For each part (such as a black circle), a name (e.g., a letter, an abbreviation) is used to describe it in the netlist. Symbols, words, etc. can be added.

[0106] One method of performing image recognition is to use AI to pre-process the conversion unit PTN. First, circuit symbols are trained as training data, and then images are input data to the conversion unit PTN. Given a PIC, based on the learned circuit symbol, the image of the PIC contains One method is to extract circuit symbols.

[0107] Furthermore, one method for performing image recognition is, for example, a convolutional neural network (CN). N) and others can be used. Also, when using a convolutional neural network, In advance, the circuit symbol is used as the filter for the convolutional layer of the convolutional neural network. You can use images of the electrical connections (such as black circles), or parts of those images. Therefore, through calculations using a convolutional neural network, the image PIC contains The similarity between the circuit symbol, electrical connection points (such as black circles), etc., and the filter in question is calculated. It is possible to determine the circuit symbols and electrical connections contained in the image PIC based on the similarity. It can identify elements such as minutes (black dots, etc.).

[0108] Furthermore, the PTN converter recognizes the connection between the electrical connection points (such as black circles) and the circuit symbols. In such cases, it is preferable to repeatedly perform object region recognition and image recognition. Specifically, object region After performing area recognition and image recognition once, the PTN conversion unit recognizes the electrical connection part (such as a black circle). Symbols used to identify electrical connections (such as black dots) and to describe them in the netlist. Next, the first image recognition determines which electrical connection points (such as black circles) are connected. The system determines the direction in which the wiring extends, and in the second recognition of the object region, Expanding the area in the direction of the extension, the wiring and electrical connection parts (black circles, etc.) are grouped together as an object area. The area is recognized as a region. Then, a second image recognition is performed to determine the direction in which the wiring extends. After determining whether it is a real object, the process of recognizing the object region and recognizing the image is repeated in the same way from the third time onward. The PTN converter then connects the wiring to the electrical connection points (such as the black circles) in the same way. Depending on the number of iterations of object region recognition and image recognition, recognition can be performed, ultimately The PTN converter recognizes the electrical connection between the circuit symbol and the electrical connection point (such as the black circle). This is possible. In Figure 5, the left image PIC of stage PH2 shows, as an example, the recognition of the object region. The area of ​​wiring obtained by repeatedly performing recognition and image recognition is represented by a thick dotted line. The enclosed area is illustrated.

[0109] Note that the image PIC in stage PH1 contains characters and symbols indicating the names of circuit symbols and wiring. If included, as shown in the image PIC on the right side of stage PH2 in Figure 5, those names, letters, The symbols and other elements are recognized along with circuit symbols and electrical connections during the object domain recognition stage. This is also acceptable. This allows the names, characters, codes, etc., obtained through the recognition of the object region to be used in the same way. It is possible to associate the recognized object region with circuit symbols and electrical connections. It can also be used to name, write, or code a circuit symbol, or a name associated with an electrical connection point. These can be treated as symbols, characters, etc., to be written in a list.

[0110] In step PH3 of Figure 5, the circuit symbol recognized by the conversion unit PTN in step PH2 of Figure 5 This shows an example of describing the connection configuration between the electrical connection parts (such as the black dots) in a netlist. ru.

[0111] At the left end of the netlist (NTL), the circuit symbol recognized by the image PIC is displayed, along with the name of the circuit element (C). It is listed as SW (e.g., letters, abbreviations, symbols, words, etc.). For example, Tr[1 ], Tr[2] indicates the transistor in the circuit diagram drawn on the image PIC, and C[1] is The image PIC shows the capacitance elements in the circuit diagram, and EL[1] is drawn on the image PIC. This shows the light-emitting element in the circuit diagram.

[0112] Furthermore, the netlist (NTL) contains information indicating the connection configuration of circuit symbols, including the names of the circuit elements. To the right of the designation CSW, across the space SPC, is the designation CN for the electrical connection part (black circle, etc.). P (for example, a letter, abbreviation, symbol, word, etc.) is written. Note that the terminals of the circuit symbol are If there are multiple entries, it is preferable to have a space between the names CNP. The order in which the names CNP of the electrical connection parts (such as black circles) are listed is as follows: The name CSW is determined by the terminals of the circuit symbol. For example, the netlist NTL. Regarding the electrical connections of each terminal of the transistor, either the source or the drain, It is stipulated that the components should be listed in the order of source, or the other of drain. Also, for example, In the NTL netlist, the electrical connections of each terminal of the light-emitting element are defined as input terminals, output terminals, etc. The terminals are to be listed in the order of their positions.

[0113] As described above, by performing object region recognition and image recognition, the input data is used Route maps can be converted into netlists.

[0114] <<Example 2 of how to convert to a netlist>> Next, in step STI02 of the above example, input data is sent to a document file, etc. The method for converting the circuit diagram into a netlist will be explained.

[0115] Figure 6 is a schematic diagram illustrating the process of converting a document file to a netlist.

[0116] In Figure 6, step PH4 is the input data that is input to the conversion unit PTN in step STI02. An example of a document file is shown. The document file DOC is shown in step PH4 of Figure 6. The circuit configuration is provided as information for converting to a netlist using the PTN conversion unit. It is written in text.

[0117] Examples of document files (DOCs) that describe circuit configurations in text include patent specifications. This includes the section describing the circuit described in the patent specification, the claims attached to the patent specification, etc. This is possible. For example, the following table shows an example of the conversion method: The document file DOC contains the following: The text is assumed to be as shown in 1.

[0118] [Table 1]

[0119] The conversion unit PTN, when a document file DOC like the one described above is input as input data, For example, text analysis is performed on a document file (DOC).

[0120] Furthermore, as a method for performing text analysis, for example, using AI on the conversion unit PTN Therefore, document files (for example, papers, published patent gazettes) are used as training data in advance. The netlist should be trained to include the patent claims and their corresponding document files. This is preferable. As a result, when a document file is given as input data to the conversion unit PTN... Then, based on the learned content, convert the document file into a netlist. It is possible.

[0121] Furthermore, as a method for creating the training data mentioned above, for example, one can use software to create one From the netlist, multiple document files (for example, multiple files with the same content but different descriptions) Examples include methods for generating a number of "claims" (or similar terms).

[0122] Furthermore, one method for performing text analysis is, for example, a recurrent neural network (R You can use NN, etc.

[0123] When text analysis is performed on the document file DOC, the conversion unit PTN performs text analysis on the document file Recognize circuit elements, wiring, or electrical connection points from the circuit configuration shown in the file DOC. This is possible. For example, text analysis can be performed on the first paragraph of a document file (DOC). By doing so, the conversion unit PTN has the first circuit configuration shown in the document file DOC. It is recognized that it includes a transistor, a second transistor, a capacitive element, and a light-emitting element. This is possible. Next, for example, paragraphs 2, 3, 5, and 7 By performing text analysis on the text, the conversion unit PTN is shown in the document file DOC. The circuit configuration includes electrical connections between signal lines, scan lines, a first power line, and a second power line. It can be recognized that this is being done. Here, the conversion unit PTN is the name of the circuit element. The term CSW (e.g., letter, abbreviation, code, word, etc.) is, for example, the first transistor. Let the first transistor be Tr[1], the second transistor be Tr[2], the capacitive element be C[1], and the light-emitting element be EL [1] Named as CNP (e.g., letters, abbreviations, symbols, single) and the name of the electrical connection point. For example, the signal line, scan line, first power line, and second power line are each referred to as (words, etc.). By naming them N1, N2, N5, and N6, this stage corresponds to stage P in Figure 6. It is possible to write the H5 netlist (NTL).

[0124] Note that the netlist NTL shown in stage PH5 of Figure 6 corresponds to stage P of Figure 5 described above. The rules described in the netlist NTL illustrated in H3 are the same. Therefore, A space SPC is provided between the name of the circuit element CSW and the name of the electrical connection point CNP. It is being done.

[0125] Continuing from stage PH5, by performing text analysis on the document file DOC... The conversion unit PTN can describe a more detailed netlist NTL. For example, By performing text analysis on the text in paragraphs 4 and 8 of the document file DOC, changes can be made. The PTN converter consists of the source of the first transistor, the gate of the second transistor, and a capacitive element. It can be recognized that one of the pair of electrodes is connected to the same electrical connection point. Here, the conversion unit PTN shall designate the electrical connection point as N3. .

[0126] Furthermore, text analysis will be performed on the text in paragraphs 6 and 9 of the document file DOC. Therefore, the conversion unit PTN connects the source of the second transistor, the input terminal of the light-emitting element, and the capacitance. It is important to recognize that the other electrode of a pair of electrodes in an element is connected to the same electrical connection point. Yes, it is possible. Here, the conversion unit PTN will designate the electrical connection point as N4. ru.

[0127] As described above, text analysis was performed on the document file DOC, and the document file DOC Determine the circuit elements included in the circuit configuration described, and their electrical connections. By extracting the netlist N shown in step PH6 of Figure 6, the conversion unit PTN produces the netlist N You can write a timeline (TL).

[0128] By using the system described in this embodiment, from a circuit diagram or document file It can be converted to a netlist, and the converted netlist can be obtained from the database. You can search for information. The database also includes journals, science and engineering books, papers, conferences, and lectures. If technical documents such as materials from meetings, published patent gazettes, and patent publications are preserved, ( Acts of infringement of intellectual property rights such as copyright, and violations of intellectual property laws are committed. (Assuming there are no users,) the user, by using the system, It is possible to determine whether the created circuit diagram or document file contains new information. Furthermore, by using the system, users can create circuit diagrams or documents. It is possible to determine whether the document file is publicly known information. In other words, the user can determine whether the information is publicly known. By using the system, the system can handle prior art regarding circuit diagrams or document files created by the user. This allows for more efficient investigation of the technique.

[0129] Here, we will specifically explain an example of netlist retrieval using the SIH system shown in Figure 1. I will reveal it.

[0130] For example, as shown in Figure 7, in the system SIH of Figure 1, the database DTB1 The information PKEDD, information PKPD, information HSCD, and information HSPD are stored. The database DTB2 contains netlists PKEDN and PKPN, Consider the case where the netlist HSCN and the netlist HSPN are stored (however Figure 7 shows the input / output interface INTFC, control unit CTL, conversion unit PTN, and storage unit. (MP is omitted.)

[0131] Information PKEDD includes, for example, circuit diagrams, specifications, etc. of known electronic devices, and information PKP D is, for example, the technical content that was handled by someone other than the user (patent specification, especially patent drawings, patent claims). Scope. Information HSCD includes, for example, patent specifications that the user has been involved with. The information HSPD has the claims of the circuit described in the detailed description (regardless of whether an application has been filed), For example, if the user has a patent specification (regardless of whether an application has been filed) in which they have worked, they may have a circuit diagram or similar document. do.

[0132] Furthermore, the netlist PKEDN corresponds to the circuit diagrams and other information contained in the PKEDN. Netlist PKPN contains patent drawings and patent requests included in PKPD. It has a netlist corresponding to the range of requests, and the netlist HSCN is in the information HSCD. The netlist HSPN has a netlist corresponding to the included claims, etc. It has a netlist corresponding to the patent drawings and other information included in the HSPD. Note that Figure 7 shows As a way of expressing the link between netlists and information, netlist PKEDN and information PKED Between D and netlist PKPN and information PKPD, between netlist HSCN and information H A thick solid line is drawn between the SCD and the netlist HSPN and the information HSPD. ru.

[0133] Here, the first search SRC1 is a net corresponding to the circuit diagram of a known electronic device. The list PKEDN contains multiple nets such as the claims of patent applications that the user has been involved with. Let's consider the case where we search using the search range HSCN. In this case, multiple netlists From HSCN, a netlist corresponding to netlist PKEDN was found, and the The filing date of the patent corresponding to the found netlist is earlier than the date the child device became publicly known. If so, it is possible to find out if the electronic device infringes on the user's patents. By performing the first search SRC1, the user's patents are infringed upon known electronic devices. A tactile investigation can be conducted.

[0134] Furthermore, as a second search SRC2, the claims of the patent application filed by the user before it is filed are also searchable. One netlist HSCN corresponds to multiple nets, such as circuit diagrams of known electronic devices. The PKEDN list and multiple netlists that cover technical details and other aspects of the work done by non-users. Let's consider a case where we search using PKPN as the search range. In this case, multiple netlists From PKEDN and multiple netlists PKPN, the netlist corresponding to HSCN If a trilist is found, the netlist HSCN can be considered publicly known. In other words, by performing a second search, SRC2, the novelty of the invention the user was involved in can be assessed. The review can be conducted before the patent application is filed. This allows the user to review the patent application they are involved in. It may be possible to increase its effectiveness.

[0135] Furthermore, as a third search SRC3, one network corresponding to the circuit diagram of a known electronic device The PKEDN is a set of multiple netlists, such as drawings from patent applications that the user has been involved with, and HSPN. Let's consider a case where we search using the search range. In this case, from multiple netlists HSPN... , a netlist matching netlist PKEDN was found, and the electronic device in question is publicly known If the filing date of the patent corresponding to the found netlist was earlier than the date on which this occurred. The electronic device may utilize the content of a patent application filed by the user. This means that by performing the third search SRC3, known electronic devices can be identified. To examine the degree of similarity between the circuit diagram and the circuit diagram of the patent application filed by the user. It is possible.

[0136] In addition, the third search, SRC3, is one that corresponds to the circuit diagram of a known electronic device. The netlist PKEDN is a collection of multiple netlists, such as drawings from patent applications the user has worked on. The explanation described how to search using HSPN as the search range, but the third search SRC3 is for the user One netlist HSPN, including drawings from a patent application that he was involved with, is a known circuit of an electronic device. You may also search using multiple netlists PKEDNs corresponding to the figure as the search scope. In this regard, the circuit diagram of a publicly known electronic device and the circuit diagram of the content of a patent application in which the user was involved, The degree of similarity can be examined.

[0137] Furthermore, the first search SRC1 and the third search SRC3 may be performed simultaneously.

[0138] Furthermore, the first search SRC1, the second search SRC2, and the third search SRC3 are each, AI can be used. For example, by using AI, the netlist to be searched can be calculated. Then, compare the descriptions of the netlists included in the search range and each other's nets The list shows how closely the types, numbers, and connection configurations of the circuit elements match. The system can calculate similarity and output search results starting with those that have the highest similarity.

[0139] As described above, in the system SIH shown in Figure 1, the information stored in the database DTB1 Each of the following is: Report PKEDD, Information PKPD, Information HSCD, and Information HSPD. It is linked to the netlist stored in the database DTB2. Also, the first check Search SRC1, the second search SRC2, and the third search SRC3 each use a separate netlist. You can perform searches without converting the file to a different format (e.g., circuit diagrams, document files, etc.). Therefore, it makes searching easier and speeds up the search process.

[0140] Furthermore, while the above shows a search example using the system SIH in Figure 1, Figure 2 shows the system S The same search examples as above can be performed using induction heating (IH).

[0141] By the way, regarding the neural network of the conversion unit PTN or conversion unit WPTN When performing training, a large amount of data (sometimes called big data) is required. Yes. One way to prepare a large amount of data is, for example, to automatically randomize the netlist. We create a program to generate the circuit, and then use circuit design software, circuit simulators, etc. Using this, image data is created from the netlist. At this time, the netlist is generated. It is preferable to write a program that allows the creation of image data and this process to be performed in a single, continuous sequence. This allows you to prepare a set of netlist and circuit image data as training data. This is possible. Also, as a method for preparing large amounts of data, for example, a netlist can be automatically generated. Create a program that generates randomly, and further, from the automatically generated netlist... Create a program that creates document files. This will involve generating a netlist and creating a document file. It is preferable to write the program so that file creation and other operations can be performed in a single sequence. A set of netlists and document files can be prepared as training data.

[0142] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0143] (Embodiment 2) In this embodiment, a neural network used in a system according to one aspect of the present invention is described. An example of an arithmetic circuit that performs calculations will be described.

[0144] <Hierarchical Neural Network> First, let's explain hierarchical neural networks. A network, for example, consists of one input layer, one or more intermediate layers (hidden layers), and one output layer. It has layers and is composed of a total of 3 or more layers. Figure 8A shows a hierarchical neural network. The neural network 100 is an example of this, and the neural network 100 is the first It has layers up to the Rth layer (where R can be an integer greater than or equal to 4). In particular, The first layer corresponds to the input layer, the Rth layer corresponds to the output layer, and the other layers correspond to the hidden layers. Note that Figure 8A shows the (k-1)th layer and the kth layer (where k is 3 or greater, R-1) as intermediate layers. The following integers are used.) are shown in the diagram, and other intermediate layers are omitted from the diagram. .

[0145] Each layer of the neural network 100 has one or more neurons. In FIG. 8A the first layer has neurons N1 (1) to Np p (1) (where p is an integer greater than or equal to 1 ). The (k - 1)-th layer has neurons N1 (k-1) to Nm m (k-1) (where m is an integer greater than or equal to 1). The k-th layer has neurons N1 ( k) to Nn n (k) (where n is an integer greater than or equal to 1). The R-th layer has neurons N1 (R) to Nq q (R) (where q is an integer greater than or equal to 1).

[0146] In addition, in FIG. 8A, neurons N1 (1) , N p (1) , N1 ( k-1) , N 6] m (k-1) , N1 (k) , N n (k) , N1 (R) , N q (R) are shown. In addition, neurons N i (k-1) of the (k - 1)-th layer (where i is an integer from 1 to m) and neurons N j ( k) of the k-th layer (where j is an integer from 1 to n) are also shown, and other neurons are not shown.

[0147] Next, the transmission of signals from neurons in the previous layer to neurons in the next layer, and each of the neurons This section describes the signals that are input and output in the ron. Note that in this explanation, the k-th layer of the neurons... N j (k) We are focusing on that.

[0148] Figure 8B shows neurons N in layer k. j (k) And, neuron N j (k) The signal input to And, neuron N j (k) This shows the signal output from and .

[0149] Specifically, the (k-1) neuron N1 (k-1) Neuron N m (k-1 ) z1 is the output signal of each of the following: (k-1) ~z m (k-1) However, neuron N j ( k) It is outputting towards neuron N. j (k) is z1 (k-1) ~z m (k-1) z j (k) Generate z j (k) The (k+1)th is used as the output signal. Output is sent to each neuron in the layer (not shown in the diagram).

[0150] The signals that are input from neurons in the previous layer to neurons in the next layer are transmitted between those neurons. The strength of the synaptic connections (hereinafter referred to as the weighting coefficient) determines the transmission of signals. The degree is determined. In the neural network 100, the signal output from the neurons in the previous layer is multiplied by the corresponding weight coefficient and input into the neurons in the next layer. Let i be an integer from 1 to m When the weight coefficient of the synapse between the neuron N i (k-1) in the (k - 1)th layer and the neuron N j (k) in the kth layer is w i (k-1) j (k) neuron N j (k) in the kth layer can be expressed by Equation (D1).

[0151]

Equation

[0152] That is, when signals are transmitted from the neurons N1 (k-1) to N m (k-1) in the (k - 1)th layer to the neuron N in the kth layer, the signals z1 j (k) to z (k-1) m (k-1) (k-1 ) j (k) m (k-1) j (k) j (k) (k-1) j (k) (k-1) m (k-1) j (k) m (k-1) j (k) j (k) (k-1) ​​ z m (k-1) is input. At this time, the neuron N in the k-th layer j (k) The sum u of the signals input to is given by equation (D2). j (k)

[0153]

Equation

[0154] Also, a bias may be added as a bias to the result of the sum of products of the weight coefficients w1 (k-1) j (k) to w m (k-1) j (k) and the signals z1 of the neuron (k-1) to z<000011​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​j (k) ) is an activation function in hierarchical neural networks. Step functions, linear ramp functions, sigmoid functions, etc. can be used. The tempering function may be the same for all neurons, or it may be different for all neurons. Therefore, the activation function of neurons may be the same or different in each layer.

[0159] By the way, the signal output by the neurons in each layer, the weight coefficient w, or the bias b is, It can be an analog value or a digital value. For example, a binary value. You can use that, or you can use a 3-value. You can even use a value with a larger number of bits. For example, For analog values, activation functions can include, for example, a linear ramp function or a sigmoid function. You can use it. In the case of a binary digital value, for example, the output can be -1 or 1, or 0 or A step function where < is 1 can be used. Also, the signals output by neurons in each layer are It is also possible to have three or more values; in this case, the activation function has three or more values, for example, the output may be -1, 0, or Use a step function where the value is 1, or a step function where the value is 0, 1, or 2. That would be fine. Also, for example, as an activation function that outputs 5 values, -2, -1, 0, 1, or A step function with a value of 2 may also be used. The signals output by neurons in each layer, the weights Use a digital value for at least one of the watts or bias b. This allows for reducing circuit size, lowering power consumption, or increasing processing speed. It can be made faster, etc. Also, the signals output by neurons in each layer, the weight coefficient w, Alternatively, by using an analog value for at least one of the bias b, the precision of the calculation can be improved. The degree can be improved.

[0160] The neural network 100 is formed when an input signal is input to the first layer (input layer) So, in each layer from the first layer (input layer) to the last layer (output layer), the input is processed sequentially from the previous layer. Based on the applied signal, use equations (D1), (D2) (or (D3)), and (D4) It generates an output signal and outputs that output signal to the next layer. The last layer (output layer) The output signal corresponds to the result calculated by the neural network 100. .

[0161] <Example of arithmetic circuit configuration 1> Next, in the neural network 100 described above, the sum-of-products operation and the activation function operation are performed. An example of a circuit that performs this task will be described.

[0162] Figure 9 shows an example of the configuration of the arithmetic circuit MAC1. The arithmetic circuit MAC1 shown in Figure 9 is later The sum-of-products operation is performed on the first data held in the memory cell described above and the second data that is input. Furthermore, it is a circuit that performs the activation function calculation using the result of the sum-of-products operation. The first and second data may be, for example, analog data or multi-level data (discrete data). It can be treated as data.

[0163] The arithmetic circuit MAC1 consists of a current source circuit CS, a current mirror circuit CM, and a circuit WDD. Circuit WLD, Circuit CLD, Circuit OFST, Activation function circuit ACTV, Memory cell It has an array CA.

[0164] The memory cell array CA consists of memory cell AM[1], memory cell AM[2], and memory It has cell AMref[1] and memory cell AMref[2]. Memory cell AM[ 1], and memory cell AM[2] have the role of holding the first data, and memory cell AM ref[1] and memory cell AMref[2] are references necessary for performing multiply-accumulate operations. It has a function to retain reference data. Furthermore, the reference data also includes the first data and the second data. Similarly, the data can be analog data or multi-level data (discrete data).

[0165] Note that the memory cell array CA in Figure 9 has two memory cells in the row direction and two in the column direction. Although arranged in a trix pattern, the memory cell array CA has 3 or fewer memory cells in the row direction. The configuration may also consist of three or more elements arranged in a matrix in the upper and column directions. When performing multiplication rather than arithmetic, the memory cell array CA has one memory cell in the row direction and one in the column direction. The configuration may also consist of two or more elements arranged in a matrix.

[0166] Memory cell AM[1], memory cell AM[2], memory cell AMref[1], Memory cell AMref[2] is a combination of transistor Tr11 and transistor T11, respectively. It has r12 and capacity C1.

[0167] Furthermore, it is preferable that transistor Tr11 is an OS transistor. In addition, The channel-forming region of lampistor Tr11 is indium, element M (for example, element M is Aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, Tungsten, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, One selected from neodymium, hafnium, tantalum, tungsten, or magnesium. Examples include one or more species of zinc, and it is an oxide containing at least one of the zinc species. More preferable. Transistor Tr11 has the transistor structure described in particular in Embodiment 3. It is even more preferable that this be the case.

[0168] By using an OS transistor as transistor Tr11, transistor T Because the leakage current of r11 can be suppressed, a highly accurate multiply-accumulate circuit can be realized. In some cases, this may occur. Also, by using an OS transistor as transistor Tr11, Furthermore, when transistor Tr11 is in a non-conductive state, the connection from the holding node to the write word line Leakage current can be made very small. In other words, the potential of the holding node can be refreshed. Because the number of operations can be reduced, the power consumption of the multiply-accumulate circuit can be decreased.

[0169] Furthermore, by using an OS transistor for transistor Tr12, the transistor Since it can be manufactured at the same time as Tr11, the manufacturing process for the multiply-accumulate circuit is shortened. In some cases, this is possible. Also, in the channel formation region of transistor Tr12, oxide It may not contain silicon, but it may also contain silicon. For example, amorphous silicon (water (Sometimes called amorphous silicon), microcrystalline silicon, polycrystalline silicon, single-crystalline silicon Crystalline silicon may also be used.

[0170] Memory cell AM[1], memory cell AM[2], memory cell AMref[1], In each of the memory cell AMref[2] and the first terminal of transistor Tr11 It is electrically connected to the gate of transistor Tr12. The first terminal is electrically connected to the wiring VR. The first terminal of capacitance C1 is connected to the transistor. It is electrically connected to the gate of Tr12.

[0171] In the memory cell AM[1], the second terminal of transistor Tr11 is connected to the wiring WD and electrical The gate of transistor Tr11 is electrically connected to the wiring WL[1]. The second terminal of transistor Tr12 is electrically connected to the wiring BL, and the first terminal of capacitance C1 is connected to the wiring BL. Terminal 2 is electrically connected to wiring CL[1]. Note that in Figure 9, memory cell AM [1] The first terminal of transistor Tr11 and the gate of transistor Tr12 The connection point between the first terminal of capacitance C1 and the other terminal is designated as node NM[1]. In addition, wiring BL The current flowing from the transistor Tr12 to its second terminal is I AM[1] Let's assume that.

[0172] In the memory cell AM[2], the second terminal of transistor Tr11 is connected to the wiring WD and electrical The gate of transistor Tr11 is electrically connected to the wiring WL[2]. The second terminal of transistor Tr12 is electrically connected to the wiring BL, and the first terminal of capacitance C1 is connected to the wiring BL. Terminal 2 is electrically connected to wiring CL[2]. Note that in Figure 9, memory cell AM [2] The first terminal of transistor Tr11 and the gate of transistor Tr12 The connection point between the first terminal of capacitance C1 and the other terminal is designated as node NM[2]. In addition, wiring BL The current flowing from the transistor Tr12 to its second terminal is I AM[2] Let's assume that.

[0173] In memory cell AMref[1], the second terminal of transistor Tr11 is connected to wiring WD Electrically connected to ref, the gate of transistor Tr11 is electrically connected to wiring WL[1]. It is connected to the wiring BLref. The second terminal of transistor Tr12 is electrically connected to the wiring BLref. Furthermore, the second terminal of capacitor C1 is electrically connected to wiring CL[1]. Note that in Figure 9... In memory cell AMref[1], the first terminal of transistor Tr11 and The connection point between the gate of zista Tr12 and the first terminal of capacitor C1 is shown in node NMref[1 ] is stated. In addition, the current flowing from the wiring BLref to the second terminal of transistor Tr12 Flow I AMref[1] Let's assume that.

[0174] In memory cell AMref[2], the second terminal of transistor Tr11 is connected to wiring WD Electrically connected to ref, the gate of transistor Tr11 is electrically connected to wiring WL[2]. It is connected to the wiring BLref. The second terminal of transistor Tr12 is electrically connected to the wiring BLref. Furthermore, the second terminal of capacitor C1 is electrically connected to wiring CL[2]. Note that in Figure 9... In memory cell AMref[2], the first terminal of transistor Tr11 and The connection point between the gate of zista Tr12 and the first terminal of capacitor C1 is shown in node NMref[2 ] is stated. In addition, the current flowing from the wiring BLref to the second terminal of transistor Tr12 Flow I AMref[2] Let's assume that.

[0175] The above-mentioned nodes NM[1], NM[2], NMref[1], and node NMref[2] functions as the holding node for each memory cell.

[0176] Wiring VR is memory cell AM[1], memory cell AM[2], memory cell AMref[ 1], and the first terminal of transistor Tr12 of each of the memory cell AMref[2] - This is wiring for allowing current to flow between the second terminals. Therefore, the VR wiring provides a predetermined potential. It functions as wiring for that purpose. In this embodiment, the potential supplied by the wiring VR is the reference electric current. The potential can be set to a position or a potential lower than the reference potential.

[0177] The current source circuit CS is electrically connected to wiring BL and wiring BLref. The source circuit CS has the function of supplying current to wiring BL and wiring BLref. The amount of current supplied to wiring BL and wiring BLref is different from that of the other. This is also good. In this configuration example, the current flowing from the current source circuit CS to the wiring BL is I C And the current source circuit The current flowing from circuit CS to wiring BLref is I Cref Let's assume that.

[0178] The current mirror circuit CM has wiring IL and wiring ILref. Wiring IL is Electrically connected to wiring BL, in Figure 9, the connection point between wiring IL and wiring BL is node NP. This is illustrated in the diagram. Wiring ILref is electrically connected to wiring BLref, and in Figure 9, The connection point between wiring ILref and wiring BLref is designated as node NPref. The CM circuit supplies current to node NPref according to the potential of node NPref in the wiring BLref. Discharge from ref to wiring ILref, and discharge the same amount of current to node N of wiring BL. It has the function of discharging from P to wiring IL. Note that in Figure 9, it is discharging from node NP to wiring IL. The current output, and the current discharged from node NPref to wiring ILref, are defined as I CM And it says In addition, in the wiring BL, the current mirror circuit CM is connected to the memory cell array CA. The current flowing is I B It is noted that in the wiring BLref, the current mirror circuit CM is connected to the memory. The current flowing through the cell array CA is I Bref It is written as follows.

[0179] Circuit WDD is electrically connected to wiring WD and wiring WDref. D sends data to be stored in each memory cell of the memory cell array CA. It has the function of trusting.

[0180] Circuit WLD is electrically connected to wiring WL[1] and wiring WL[2]. The path WLD writes data to the memory cells of the memory cell array CA. It has the function of selecting the memory cell to which the data will be written.

[0181] Circuit CLD is electrically connected to wiring CL[1] and wiring CL[2]. The path CLD is the second terminal of the capacitance C1 of each memory cell in the memory cell array CA. It has the function of applying an electric potential to it.

[0182] Circuit OFST is electrically connected to wiring BL and wiring OL. This is the amount of current flowing from wiring BL to circuit OFST, and / or from wiring BL to circuit OFST. It has the function of measuring the change in the amount of current flowing. In addition, the OFST circuit is based on the results of the measurement. It has the function of outputting the result to the wiring OL. Circuit OFST outputs the measurement result as is. The configuration may be such that the output is made as current to the wiring OL, or the result of the measurement may be converted to a voltage. The configuration may also involve outputting to wiring OL. Note that in Figure 9, the current flows from wiring BL to circuit OFST. The current is I α It states that.

[0183] For example, the OFST circuit can have the configuration shown in Figure 10. In Figure 10, The OFST circuit consists of transistors Tr21, Tr22, and Tr2 It has 3, capacitance C2, and resistance R1.

[0184] The first terminal of capacitor C2 is electrically connected to wiring BL, and the first terminal of resistor R1 is connected to wiring B It is electrically connected to L. The second terminal of capacitor C2 is connected to the first terminal of transistor Tr21. Electrically connected to the first terminal of transistor Tr21, the gateway of transistor Tr22 It is electrically connected to transistor Tr22. The first terminal of transistor Tr22 is connected to transistor Tr2 The first terminal of 3 is electrically connected to the first terminal of transistor Tr23, and the first terminal of transistor Tr23 is electrically connected to the wiring OL. They are connected. Furthermore, the electrical connection between the first terminal of capacitor C2 and the first terminal of resistor R1 is Let the connection point be node Na, the second terminal of capacitor C2 and the first terminal of transistor Tr21, Let node Nb be the electrical connection point between the gate of transistor Tr22 and the other element.

[0185] The second terminal of resistor R1 is electrically connected to the wiring VrefL. Transistor Tr The second terminal of 21 is electrically connected to the wiring VaL, and the gate of transistor Tr21 is It is electrically connected to wiring RST. The second terminal of transistor Tr22 is connected to wiring VDD. It is electrically connected to L. The second terminal of transistor Tr23 is electrically connected to wiring VSSL. The gate of transistor Tr23 is electrically connected to wiring VbL. .

[0186] Wiring VrefL is a wire that gives potential Vref, and wiring VaL gives potential Va. Wiring VbL is the wiring that gives potential Vb. Wiring VDDL gives potential VD Wiring VSSL is a wire that gives potential D, and wiring VSSL is a wire that gives potential VSS. In particular, here In the example circuit OFST configuration, the potential VDD is set to the high-level potential, and the potential VSS is set to the low-level potential. The position is as follows. Wiring RST switches between the conductive and non-conductive states of transistor Tr21. This is wiring that provides the necessary electrical potential.

[0187] From the OFST circuit shown in Figure 10, transistors Tr22 and Tr23 are... The source follower circuit is formed by the wiring VDDL, VSSL, and VbL. It is being done.

[0188] From the circuit OFST shown in Figure 10, the resistor R1 and the wiring VrefL form node N A is given a potential corresponding to the current flowing from wiring BL and the resistance of resistor R1.

[0189] An example of the operation of the OFST circuit shown in Figure 10 will be explained. The first current from wiring BL ( Later, when the first current (which will be referred to as the first current) flows, the resistor R1 and the wiring VrefL, A potential corresponding to the first current and the resistance of resistor R1 is applied to the circuit Na. Also, at this time, The transistor Tr21 is made conductive, and a potential Va is applied to node Nb. Then, the transistor Set the zista Tr21 to a non-conductive state.

[0190] Next, when the second current (hereinafter referred to as the second current) flows from wiring BL, the first Similar to when current flows, the resistor R1 and the wiring VrefL create a second current at node Na. A potential is given corresponding to the current and the resistance of resistor R1. At this time, node Nb is floating Since it is in a coupling state, the potential of node Na has changed, and due to capacitive coupling, The potential of node Nb also changes. The change in the potential of node Na is ΔV Na And set the capacity coupling coefficient to 1 In this case, the potential at node Nb is Va + ΔV Na This is the threshold for transistor Tr22. Value voltage V th In this case, the potential Va + ΔV from the wiring OL Na -V th This is output. Here, the potential Va is set to the threshold voltage V th By doing so, the potential ΔV from the wiring OL Na Output It is possible.

[0191] Potential ΔV Na This involves the change in current from the first to the second current, the resistance value of resistor R1, and the potential Vr. It is determined by ef and the potential Vref. The resistance value of resistor R1 and the potential Vref can be assumed to be known. Therefore, by using the OFST circuit shown in Figure 10, the potential ΔV Na From, wiring BL The change in the current flowing through it can be determined.

[0192] The activation function circuit ACTV is electrically connected to wiring OL and wiring NIL. The activation function circuit ACTV receives the change in current measured by circuit OFST via wiring OL. The result is input. The activation function circuit ACTV applies a predefined value to this result. This is a circuit that performs operations according to a defined function system. For example, the sigmoid function... Use functions such as numbers, tanh, softmax, ReLU, and threshold functions. These functions can be applied as activation functions in neural networks. .

[0193] <Example of operation of the arithmetic circuit 1> Next, we will explain an example of the operation of the MAC1 arithmetic circuit.

[0194] Figure 11 shows a timing chart of an example of the operation of the arithmetic circuit MAC1. The chart shows wiring WL[1], wiring WL[2], and wiring at times T01 to T09. Line WD, wiring WDref, node NM[1], node NM[2], node NMref[1] This shows the potential fluctuations of node NMref[2], wiring CL[1], and wiring CL[2]. , current I B -I α , and current I Bref This shows the magnitude of the fluctuations. In particular, current I B - I α From wiring BL, memory cell AM[1] of memory cell array CA, memory cell AM [2] shows the total current flowing through it.

[0195] <<From time T01 to time T02>> Between time T01 and time T02, a high-level potential occurred in the wiring WL[1] (Figure 11) Then it is labeled as High.) is applied, and a low level potential (in Figure 11) is applied to the wiring WL[2]. It is labeled as Low.) is applied. In addition, the ground potential (Figure 11) is applied to the wiring WD. Then it is written as GND. ) is more V PR -V W[1] A large potential is applied, wiring W Dref has a potential greater than ground potential. PR A large potential is applied. Furthermore, wiring CL[1] The wiring CL[2] and the wiring each have a reference potential (labeled REFP in Figure 11). It is being applied.

[0196] Note that potential V W[1] This is the potential corresponding to one of the first data points. Also, potential V PR teeth This is the potential corresponding to the reference data.

[0197] At this time, the respective traces of memory cell AM[1] and memory cell AMref[1] Because a high-level potential is applied to the gate of transistor Tr11, the memory cell AM[1] and Each transistor Tr11 of the memory cell AMref[1] is turned ON. Therefore, in the memory cell AM[1], the wiring WD and node NM[1] are electrically connected. Therefore, the potential of node NM[1] is V PR -V W[1] Similarly, memory In cell AMref[1], there is conductivity between the wiring WDref and node NMref[1]. As a result, the potential of node NMref[1] is V PR This is the result.

[0198] Here, the respective transistors of memory cell AM[1] and memory cell AMref[1] Consider the current flowing from the second terminal to the first terminal of the zista Tr12. From the wiring BL to the memory cell The current flowing from the second terminal to the first terminal of transistor Tr12 of AM[1] is I AM[ 1],0 In that case, I AM[1],0 It can be expressed by the following formula.

[0199]

number

[0200] k is the channel length, channel width, mobility, and gate dielectric of transistor Tr12. It is a constant determined by capacitance, etc. Also, V th This is the threshold voltage of transistor Tr12. be.

[0201] From the wiring BLref to the second terminal of transistor Tr12 of memory cell AMref[1] The current flowing through the first terminal is I AMref[1],0 In that case, similarly, I AMre f[1],0It can be expressed by the following formula.

[0202]

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[0203] Note that the transients of memory cell AM[2] and memory cell AMref[2] Because a low-level potential is applied to the gate of Tr11, the memory cell AM[2] and the Each transistor Tr11 of the Morissel AMref[2] is in the off state. Therefore, the potential is not written to node NM[2] and node NMref[2]. .

[0204] <<From time T02 to time T03>> Between time T02 and time T03, a low-level potential is applied to the wiring WL[1]. At this time, each of memory cell AM[1] and memory cell AMref[1] Because a low-level potential is applied to the gate of transistor Tr11, the memory cell AM[1] The transistors Tr11 of the memory cell AMref[1] are turned off. .

[0205] Furthermore, a low-level potential has been applied to the wiring WL[2] since before time T02. Therefore, each of the memory cells AM[2] and AMref[2] Transistor Tr11 has remained in the OFF state since before time T02.

[0206] As mentioned above, memory cell AM[1], memory cell AM[2], memory cell AMref [1] and the transistor Tr11 of the memory cell AMref[2] are in the off state. Therefore, between time T02 and time T03, node NM[1], node The potentials of NM[2], node NMref[1], and node NMref[2] are It is retained.

[0207] In particular, as described in the explanation of the circuit configuration of the arithmetic circuit MAC1, the memory cell AM[1], Morisel AM[2], memory cell AMref[1], and memory cell AMref[2] By applying an OS transistor to each transistor Tr11, the transistor This allows for a reduction in the leakage current flowing between the first and second terminals of Tr11. , node NM[1], node NM[2], node NMref[1], and node NMre Each potential of f[2] can be maintained for a long period of time.

[0208] Between time T02 and time T03, wiring WD and wiring WDref are grounded. A potential is applied. Memory cell AM[1], memory cell AM[2], memory cell AM The transistor Tr11 in ref[1] and the memory cell AMref[2] is Since it is in the off state, applying a potential from wiring WD and wiring WDref will Node NM[1], Node NM[2], Node NMref[1], and Node NMref The potentials held in each of [2] will not be overwritten.

[0209] <<From time T03 to time T04>> Between time T03 and time T04, a low-level potential was applied to the wiring WL[1]. Therefore, a high-level potential is applied to the wiring WL[2]. In addition, the wiring WD has a ground potential. RimoV PR -V W[2]When a large potential is applied, the potential at wiring WDref is higher than the ground potential. P R A large potential is applied. Furthermore, the wiring CL[1] continues from before time T02, A reference potential is applied to both the wiring CL[2] and the other wire.

[0210] Note that potential V W[2] This is the potential corresponding to one of the first data points.

[0211] At this time, the respective traces of memory cell AM[2] and memory cell AMref[2] Because a high-level potential is applied to the gate of the transistor Tr11, the memory cell AM[2] and Each transistor Tr11 of the memory cell AMref[2] is turned ON. Therefore, in the memory cell AM[2], the wiring WD and node NM[2] are electrically connected. Therefore, the potential at node NM[2] is V PR -V W[2] Similarly, memory In cell AMref[2], there is conductivity between the wiring WDref and node NMref[2]. As a result, the potential of node NMref[2] is V PR This is the result.

[0212] Here, the respective transistors of memory cell AM[2] and memory cell AMref[2] Consider the current flowing from the second terminal to the first terminal of the zista Tr12. From the wiring BL to the memory cell The current flowing from the second terminal to the first terminal of transistor Tr12 of AM[2] is I AM[ 2],0 In that case, I AM[2],0 It can be expressed by the following formula.

[0213]

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[0214] From the wiring BLref to the second terminal of transistor Tr12 of memory cell AMref[2] The current flowing through the first terminal is I AMref[2],0 In that case, similarly, I AMre f[2],0 It can be expressed by the following formula.

[0215]

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[0216] <<From time T04 to time T05>> Here, between time T04 and time T05, wiring BL and wiring BLref Let's explain the flow of electric current.

[0217] Wiring BLref is supplied with current from the current source circuit CS. In addition, wiring BLre f comprises a current mirror circuit CM, a memory cell AMref[1], and a memory cell AMr Current is discharged by ef[2]. In wiring BLref, current is supplied from the current source circuit CS. The current supplied is I Cref The current discharged by the current mirror circuit CM is I C M,0 In that case, according to Kirchhoff's laws, the following equation holds true.

[0218]

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[0219] Wiring BL is supplied with current from the current source circuit CS. In addition, wiring BL is supplied with current from the current source circuit CS. Current is discharged by the mirror circuit CM, memory cell AM[1], and memory cell AM[2]. In addition, current flows from wiring BL to circuit OFST. In wiring BL, current The current supplied from the source circuit CS is I C Let I be the current flowing from wiring BL to circuit OFST. α,0 In that case, according to Kirchhoff's laws, the following equation holds true.

[0220]

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[0221] <<From time T05 to time T06>> Between time T05 and time T06, the wiring CL[1] has a potential higher than the reference potential. X[ 1] A high potential is applied. At this time, memory cell AM[1] and memory cell AMre At the second terminal of each capacitance C1 of f[1], the potential V X[1] Because it is applied, The gate potential of zista Tr12 increases.

[0222] Note that potential V x[1] This is the potential corresponding to one of the second data points.

[0223] Furthermore, the increase in the gate potential of transistor Tr12 corresponds to the change in the potential of wiring CL[1]. The potential is obtained by multiplying the capacitance coupling coefficient, which is determined by the configuration of the memory cell. The capacitance coupling coefficient is It is calculated using the capacitance of capacitor C1, the gate capacitance of transistor Tr12, parasitic capacitance, etc. In this example, to avoid the complexity of the explanation, the increase in the potential of wiring CL[1] is also included in the transistor. The increase in the gate potential of Zistor Tr12 is also explained as the same value. This corresponds to memory cell A Assuming that the capacitive coupling coefficients in M[1] and memory cell AMref[1] are 1 It is equivalent to being there.

[0224] Since the capacitive coupling coefficient is set to 1, the memory cell AM[1] and the memory cell AMref [1] The second terminal of each capacitance C1 is given a potential V X[1] When applied, The potentials at node NM[1] and node NMref[1] are V, respectively. X[1] rising .

[0225] Here, the respective transistors of memory cell AM[1] and memory cell AMref[1] Consider the current flowing from the second terminal to the first terminal of the zista Tr12. From the wiring BL to the memory cell The current flowing from the second terminal to the first terminal of transistor Tr12 of AM[1] is I AM[ 1],1 In that case, I AM[1],1 It can be expressed by the following formula.

[0226]

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[0227] In other words, there is a potential V in the wiring CL[1]. X[1] By applying this, the memory from wiring BL The current flowing from the second terminal to the first terminal of transistor Tr12 of the RICEL AM[1] is: I AM[1],1 -I AM[1],0 (In Figure 11, ΔI AM[1] (This is how it is written.) Increase do.

[0228] Similarly, the wiring from BLref to the cell memory AMref[1] of transistor Tr12 The current flowing from terminal 2 to terminal 1 is I AMref[1],1 In that case, I AMre f[1],1 It can be expressed by the following formula.

[0229]

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[0230] In other words, there is a potential V in the wiring CL[1]. X[1] By applying the wire BLref The current flows from the second terminal of transistor Tr12 of memory cell AMref[1] to the first terminal. The current is I AMref[1],1 -I AMref[1],0 (In Figure 11, ΔI AM ref[1] It is written as follows: ) It increases.

[0231] Here, we will explain the current flowing through wiring BL and wiring BLref.

[0232] The wiring BLref has a current source circuit CS, similar to the period from time T04 to time T05. Current I Cref A current mirror circuit C is supplied to the wiring BLref. Current is discharged by M, memory cell AMref[1], and memory cell AMref[2]. In the wiring BLref, the current discharged by the current mirror circuit CM is I CM,1 In that case, according to Kirchhoff's laws, the following equation holds true.

[0233]

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[0234] Wiring BL receives current from the current source circuit CS, similar to the period from time T04 to time T05. Flow I C The following are supplied. At the same time, the wiring BL is supplied with a current mirror circuit CM and a memory cell AM. [1], current is discharged by the memory cell AM[2]. Furthermore, from wiring BL to circuit O Current also flows through FST. In wiring BL, the current flowing from wiring BL to circuit OFST is I α,1 In that case, according to Kirchhoff's laws, the following equation holds true.

[0235]

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[0236] Current flowing from wiring BL to circuit OFST between time T04 and time T05 I α,0 And, between time T05 and time T06, from wiring BL to circuit OFST Current I α,1 The difference between and is ΔI α Let's assume that ΔI α In the arithmetic circuit MAC1 This is called differential current. Differential current ΔI α This is done using equations (E1) to (E10), as follows: It can be expressed as shown in the formula.

[0237]

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[0238] <<From time T06 to time T07>> Between time T06 and time T07, a reference potential is applied to wiring CL[1]. At this time, each of the memory cell AM[1] and memory cell AMref[1] Since a reference potential is applied to the second terminal of capacitance C1, nodes NM[1] and N The potentials at Mref[1] return to the potentials between time T04 and time T05, respectively.

[0239] <<From time T07 to time T08>> Between time T07 and time T08, the wiring CL[1] has a potential higher than the reference potential. X[ 1] A high potential is applied, and the wiring CL[2] has a potential higher than the reference potential VX[2] A high potential is applied. At this time, each of memory cell AM[1] and memory cell AMref[1] Potential V at the second terminal of capacitor C1 X[1] A voltage is applied, and the memory cell AM[2] and memory cell A potential V is applied to the second terminal of each capacitor C1 of AMref[2]. X[2] This is applied. Therefore, memory cell AM[1], memory cell AM[2], memory cell AMref[1], And the gate potential of each transistor Tr12 of the memory cell AMref[2] is higher To rise.

[0240] The potentials of the respective nodes of memory cell AM[1] and memory cell AMref[1] The changes take into account the operation between time T05 and time T06. Memory cell AM[2], Similarly, for memory cells AMref[2], the capacitive coupling of each memory cell Let's explain using the number 1.

[0241] Since the capacitive coupling coefficient is set to 1, the memory cell AM[2] and the memory cell AMref [2] A potential V is applied to the second terminal of each capacitance C1. X[2] When applied, The potentials at node NM[2] and node NMref[2] are V, respectively. X[2] rising .

[0242] Here, the respective transistors of memory cell AM[2] and memory cell AMref[2] Consider the current flowing from the second terminal to the first terminal of the zista Tr12. From the wiring BL to the memory cell The current flowing from the second terminal to the first terminal of transistor Tr12 of AM[1] is I AM[ 2],1 In that case, I AM[2],1 It can be expressed by the following formula.

[0243]

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[0244] In other words, there is a potential V in the wiring CL[2]. X[2] By applying this, the memory from wiring BL The current flowing from the second terminal to the first terminal of transistor Tr12 of the RICEL AM[2] is: I AM[2],1 -I AM[2],0 (In Figure 11, ΔI AM[2] (This is how it is written.) Increase do.

[0245] Similarly, the wiring from BLref to the cell memory AMref[2] of transistor Tr12 The current flowing from terminal 2 to terminal 1 is I AMref[2],1 In that case, I AMre f[2],1 It can be expressed by the following formula.

[0246]

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[0247] In other words, there is a potential V in the wiring CL[2]. X[2] By applying the wire BLref The current flows from the second terminal of transistor Tr12 of memory cell AMref[2] to the first terminal. The current is I AMref[2],1 -I AMref[2],0 (In Figure 11, ΔI AM ref[2] It is written as follows: ) It increases.

[0248] Here, we will explain the current flowing through wiring BL and wiring BLref.

[0249] The wiring BLref has a current source circuit CS, similar to the period from time T04 to time T05. Current I Cref A current mirror circuit C is supplied to the wiring BLref. Current is discharged by M, memory cell AMref[1], and memory cell AMref[2]. In the wiring BLref, the current discharged by the current mirror circuit CM is I CM,2 In that case, according to Kirchhoff's laws, the following equation holds true.

[0250]

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[0251] Wiring BL receives current from the current source circuit CS, similar to the period from time T04 to time T05. Flow I C The following are supplied. At the same time, the wiring BL is supplied with a current mirror circuit CM and a memory cell AM. [1], current is discharged by the memory cell AM[2]. Furthermore, from wiring BL to circuit O Current also flows through FST. In wiring BL, the current flowing from wiring BL to circuit OFST is I α,3 In that case, according to Kirchhoff's laws, the following equation holds true.

[0252]

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[0253] Current flowing from wiring BL to circuit OFST between time T04 and time T05 I α,0 And, between time T07 and time T08, from wiring BL to circuit OFST Current I α,3 The difference between and is the differential current ΔI α is, formulas (E1) to (E8), formula ( Using formulas E12) through (E15), it can be expressed as follows:

[0254]

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[0255] As shown in equations (E11) and (E16), the differential current ΔI input to the OFST circuit α This is the potential V, which is the first data point. W And, multiple second data points, the potential V X The sum of the products of and The value will be corresponding to the difference current ΔI. α By measuring with the OFST circuit, the The sum of the products of data 1 and data 2 can be calculated.

[0256] <<From time T08 to time T09>> Between time T08 and time T09, wiring CL[1] and wiring CL[2] A reference potential is applied. At this time, memory cell AM[1] and memory cell AM[2] The capacities C1 of each of the memory cells AMref[1] and AMref[2] A reference potential is applied to the second terminal of the node NM[1], node NM[2], and the node NM[2]. The potentials of node NMref[1] and node NMref[2] are measured from time T06 to time The potential returns to the level before time T07.

[0257] Between time T05 and time T06, V X[1] Apply, Between time T07 and time T08, wiring CL[1] and wiring CL[2] That V X[1] , V X[2] Although it was applied, it was applied to wiring CL[1] and wiring CL[2]. The potential may be lower than the reference potential REFP. Wiring CL[1], and / or wiring CL [2] When a potential lower than the reference potential REFP is applied, the wiring CL[1] and / or The potential of the memory cell holding node connected to wiring CL[2] is determined by capacitive coupling. This can be made lower. As a result, in the sum-of-products operation, the first data and the negative value of the second data It is possible to multiply two data points by one. For example, between time T07 and time T08 Next, connect the wiring CL[2] to V X[2] not -V X[2] When applied, the difference current Δ I α It can be expressed as follows:

[0258]

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[0259] In this example, the memory cells are arranged in a 2x2 matrix. We have discussed Morisel array CA, but what about memory cell arrays with one row and two or more columns, or three? Similarly, multiply-accumulate operations can be performed on memory cell arrays with more than one row and three or more columns. In this case, the sum-of-accumulate circuit uses one of the multiple columns as reference data (potential V). PR ) hold By using this type of memory cell, the number of multiply-accumulate operations can be performed simultaneously for the number of remaining columns among multiple columns. This can be achieved by increasing the number of columns in the memory cell array, enabling faster multiply-accumulate operations. We can provide a semiconductor device that enables processing. Furthermore, by increasing the number of lines, In sum-of-products operations, the number of terms being added can be increased. The difference when the number of rows is increased. Minute current ΔI α This can be expressed by the following formula:

[0260]

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[0261] When the sum-of-accumulate circuit described in this embodiment is applied as the hidden layer described above, the weight coefficient w s[k]s[k-1] (k) This is stored as the first data in each memory cell AM of the same column. , output signal z from the s[k-1] neuron in the (k-1) layer s[k-1] (k-1) By using the potential applied from the wiring CL of each row (second data), the differential current ΔI α From the first The sum of the products of data 1 and data 2 can be calculated. In addition, the value of this sum of products can be used to... By determining the value of the activation function, the value of the activation function can be used as the signal for the s[k] n of the k-th layer. The output signal z of the euron s[k] (k) It can be done this way.

[0262] Furthermore, when the sum-of-accumulate circuit described in this embodiment is applied as the output layer described above, Mi coefficient w s[L]s[L-1] (L) Using this as the first data, in each memory cell AM of the same column Stored, the output signal z from the s[L-1] neuron in the (L-1) layer. s[L-1] (L -1) By using the potential applied from the wiring CL of each row (second data), the differential current ΔI α From this, the sum of the products of the first data and the second data can be calculated. In addition, the value of this sum of products By using this to determine the value of the activation function, the value of the activation function is used as the signal for the s of the L layer. [L] Neuron output signal z s[L] (L) It can be done this way.

[0263] In this embodiment, the input layer is a buffer circuit that outputs the input signal to the second layer. It may function as intended.

[0264] By the way, in the arithmetic circuit described in this embodiment, the number of rows of memory cell AM is the number of New in the previous layer. This corresponds to the number of neurons. In other words, the number of rows in the memory cell AM corresponds to the number of neurons input to one neuron in the next layer. This corresponds to the number of output signals from the neurons in the preceding layer. And the number of columns of memory cell AM is This corresponds to the number of neurons in the next layer. In other words, the number of rows of memory cells (AM) corresponds to the number of neurons in the next layer. This corresponds to the number of output signals produced by each neuron in the previous and next layers. The number of rows and columns in the memory cell array of the arithmetic circuit is determined by the number of cells, so we want to configure it accordingly. The number of rows and columns of the memory cell array are determined and designed according to the neural network. That's all you need to do.

[0265] Furthermore, the arithmetic circuit described in this embodiment may be modified depending on the situation. For example Alternatively, the arithmetic circuit MAC1 shown in Figure 9 may be changed to the arithmetic circuit MAC1 shown in Figure 12. The arithmetic circuit MAC1 in Figure 12 is different from the arithmetic circuit MAC1 in Figure 9 in terms of the memory cell array C In the column containing memory cells AM[1] and AM[1] of A, add memory cell AMB. It has been modified to include additional components.

[0266] The memory cell AMB is powered by wiring WD, wiring BL, wiring WLB, and wiring CLB. They are connected precisely. Also, wiring WLB is electrically connected to circuit WLD, and wiring CLB It is electrically connected to the CLD circuit.

[0267] In the memory cell AMB, the first terminal of transistor Tr11 and transistor Tr1 The connection point between gate 2 and the first terminal of capacitor C1 is designated as node NMB.

[0268] The wiring WLB is used when writing data to the memory cell AMB, from the circuit WLD to the memory cell. It functions as a wire that supplies a selection signal to the AMB. The CLB wire also functions as a memory wire. This wiring functions to apply a constant potential to the second terminal of capacitance C1 of cell AMB. The constant potential is preferably the ground potential or a low-level potential.

[0269] An example of the operation of the arithmetic circuit MAC1 in Figure 12 is, for example, the timing chart in Figure 11. Between time T01 and time T05, the transistor Tr of the memory cell AMB To turn 12 off, the node NMB is connected to ground potential, low level potential, or wiring VR. The applied potential is maintained. Then, in the timing chart of Figure 11, from time T05 Up to time T09, the source-drain of transistor Tr12 of memory cell AMB Any current I in between BIAS To allow the current to flow, the potential V is set to node NMB. BIAS It holds. At this time, I BIAS It can be expressed by the following formula.

[0270]

number

[0271] In this case, equations (E16) and (E18) can be rewritten as follows:

[0272]

number

[0273]

number

[0274] Equations (E20) and (E21) apply an arbitrary bias to the result of the sum-of-products operation. This corresponds to the calculation. In other words, by using the calculation circuit MAC1 in Figure 12, equation (D3 The operation ) can be performed. BIAS This is not the potential of node NMB, but the potential of wiring C. It is also determined by the potential supplied by LB, for example, in the timing chart in Figure 11. Between time T01 and time T05, transistor Tr12 of memory cell AMB To turn it off, apply ground potential to the wiring CLB, from time T05 to time T09. In between, the potential of the wiring CLB is changed from ground potential to an arbitrary potential, and the memory cell AMB Any current I between the source and drain of transistor Tr12 BIAS Even if you make it flow good.

[0275] Furthermore, for example, the arithmetic circuit MAC1 shown in Figure 9 is equivalent to the arithmetic circuit MAC1A shown in Figure 13. It may be changed. The arithmetic circuit MAC1A in Figure 13 is the current in the arithmetic circuit MAC1 in Figure 9. The source circuit CS and the current mirror circuit CM are combined into a circuit CMS, and the circuit OFST and activation are also connected. It has a circuit OFAC which combines the function circuit ACTV, and a memory cell array CA.

[0276] Circuit CMS, as an example, consists of a current mirror circuit CM, a current source circuit CS1, and a current source It has a circuit CS2 and a switch SW3.

[0277] A current mirror circuit CM is, as an example, made up of transistor Tr31 and transistor Tr It has 32 and, as an example, the current source circuit CS1 has transistor Tr33 and It has a capacitor C6 and a switch SW1. Furthermore, the current source circuit CS2 is, as an example, It has a transistor Tr34, a capacitor C7, and a switch SW2.

[0278] Circuit OFAC, for example, includes a switch SW4 and a resistor RE.

[0279] Furthermore, transistors Tr31 through Tr33 are as shown in Figure 13. Therefore, it is preferable to use a p-channel type transistor. Also, transistor Tr34 is As shown in Figure 13, it is preferable to use an n-channel transistor. Each of the transistors Tr31 through Tr34 can, for example, use a Si transistor. It is possible.

[0280] Furthermore, transistors Tr31 through Tr34 are O unless otherwise specified. The state includes cases where it operates in the saturation region. That is, each of the above The gate voltage, source voltage, and drain voltage of this transistor operate in the saturation region. This includes cases where the voltage is properly biased within the specified range.

[0281] Note that each of switches SW1 to SW4 is, for example, an electrical switch. Mechanical switches can be used, in particular switches SW1 to SW4. When using an electrical switch for each of these, the electrical switch is an OS switch. Transistors, such as Si transistors, can be used.

[0282] Regarding the memory cell array CA, the memory cell array CA of the arithmetic circuit MAC1 in Figure 9 Refer to the description. Note that in Figure 13, circuits CLD, WDD, and WLD are shown. Each of the commas has been omitted.

[0283] In the current mirror circuit CM, the first terminal of transistor Tr31 is connected to the wiring VHE. Electrically connected, the second terminal of transistor Tr31 is connected to the gate of transistor Tr31. And it is electrically connected to the wiring BLref. The first terminal of transistor Tr32 is Electrically connected to line VHE, the second terminal of transistor Tr32 is connected to the first terminal of switch SW3. Terminal 1 is electrically connected to the first terminal of switch SW4 of circuit OFAC.

[0284] In the current source circuit CS1, the first terminal of transistor Tr33 is electrically connected to the wiring VHE. The second terminal of transistor Tr33 is connected to the first terminal of switch SW1, and the switch The second terminal of SW3 is electrically connected to the wiring BL, and the gate of transistor Tr33 The switch SW1 is electrically connected to the second terminal and the first terminal of the capacitor C6. The second terminal of capacitor C6 is electrically connected to wiring VHE.

[0285] In the current source circuit CS2, the first terminal of transistor Tr34 is electrically connected to the wiring VLE. The second terminal of transistor Tr34 is connected to the first terminal of switch SW2, and the switch The first terminal of switch SW3 and the first terminal of switch SW4 of circuit OFAC are electrically connected. The gate of transistor Tr34 is connected to the second terminal of switch SW2 and the first terminal of capacitor C7. The child is electrically connected to the second terminal of capacitor C7. The second terminal of capacitor C7 is electrically connected to the wiring VLE. It is being done.

[0286] In circuit OFAC, the second terminal of switch SW4 is electrically connected to the first terminal of resistor RE. The second terminal of resistor RE is connected and electrically connected to the wiring VcL.

[0287] Wiring VHE functions as wiring that supplies a constant voltage. This constant voltage can be, for example, High-level potentials can be achieved. Furthermore, the VLE wiring can be configured to supply a constant voltage. It functions in this way. The constant voltage can be, for example, a low-level potential or ground potential. It can be done. Also, the wiring VcL functions as wiring that supplies a constant voltage. As for the constant voltage For example, these can be high-level potential, low-level potential, ground potential, etc.

[0288] The current mirror circuit CM generates a current corresponding to the potential of the second terminal of transistor Tr31. Wiring VHE supplies power to the second terminal of transistor Tr31, and also from wiring VHE to the transistor It has the function of supplying power to the second terminal of transistor Tr32. The source-drain junction of 1 and the source-drain junction of transistor Tr32, respectively It is preferable that the currents flowing through them are equal.

[0289] The resistor RE included in circuit OFAC is connected to the first terminal of resistor RE via switch SW4. It has the function of converting the input current into voltage. In other words, the OFAC circuit, for example, converts current It functions as a voltage conversion circuit.

[0290] Next, we will explain a specific example of the operation of the MAC1A arithmetic circuit.

[0291] First, memory cells AM[1] and AM[ Each holding node in [2] contains V PR -V W[1] , V PR -V W[2] is retained It is assumed that the memory cells included in the memory cell array CA are AMref[ 1], and each holding node of the memory cell AMref[2] contains V PR is held It is assumed that the wiring CL[1] and wiring CL[2] each have a potential R Assume that EFP is entered.

[0292] At this time, memory cell AM[1], memory cell AM[2], memory cell AMref[1 The current flowing through each transistor Tr12 of the memory cell AMref[2] is given by the formula (E1), equation (E3), equation (E2), and equation (E4) are obtained.

[0293] Next, as shown in Figure 14, switch SW1 and switch SW2 are turned ON. Set the device to the "on" state, and turn off both switch SW3 and switch SW4.

[0294] Here, if the current flowing through wiring BL is I3, then current I3 is the memory cell AM[1] , flow between the source and drain of each transistor Tr12 of the memory cell AM[2] Since this is the sum of the currents, from equations (E1) and (E3), I3 = I AM[1],0 +I AM[2],0 It can be done this way.

[0295] Furthermore, in the current source circuit CS1, since switch SW1 is in the ON state, Transistor Tr33 has a diode connection configuration. Therefore, transistor Tr3 The gate of transistor 3 becomes potential corresponding to the current I3, and the source-drain of transistor Tr33. A current I3 flows between them.

[0296] And at this time, in the current source circuit CS1, switch SW1 is turned off. Therefore, the potential corresponding to the gate current I3 of transistor Tr33 is maintained by capacitor C6. This is done. As a result, the current source circuit CS1 outputs the amount of current to wiring BL to I3. It can be fixed in place.

[0297] On the other hand, when the current flowing through wiring BLref is I4, the current I4 is equal to the current of memory cell AMR Source of transistor Tr12 in ef[1] and memory cell AMref[2] - Since this is the sum of the currents flowing between the drains, from equations (E2) and (E4), I4 = I A Mref[1],0 +I AMref[2],0 It can be done this way.

[0298] As a result, in the current mirror circuit CM, the source-drain of transistor Tr31 A current I4 flows between the input and the input. Therefore, between the source and drain of transistor Tr32... A current I4 flows through it.

[0299] The current I4 flowing between the source and drain of transistor Tr32 is supplied to the current source circuit CS2. It flows. Since switch SW2 is in the ON state, transistor Tr34 is diode The configuration is a double-connected configuration. Therefore, the gate of transistor Tr34 responds to the current I4. As the potential changes, a current I4 flows between the source and drain of transistor Tr34.

[0300] Here, in the current source circuit CS2, by setting switch SW2 to the OFF state, The potential corresponding to the gate current I4 of the zista Tr34 is maintained by the capacitor C7. Therefore, the current source circuit CS2 fixes the amount of current output to the wiring VLE to I4. It is possible.

[0301] Next, when the operation of the arithmetic circuit MAC1A changes from Figure 14 to Figure 15, the wiring CL[1] The potential is V X[1] The potential changes to +REFP, and the potential of wiring CL[2] is V X[2] +RE Assume that it has changed to FP.

[0302] At this time, memory cell AM[1], memory cell AM[2], memory cell AMref[1 The current flowing through each transistor Tr12 of the memory cell AMref[2] is given by the formula Equations (E7), (E12), (E8), and (E13) were obtained.

[0303] Also, as shown in Figure 15, switch SW3 and switch SW4 are both turned ON. To make something appear in a certain state.

[0304] Here, if the current flowing through wiring BL is I1, then the current I1 is the memory cell AM[1] , flow between the source and drain of each transistor Tr12 of the memory cell AM[2] Since this is the sum of the currents, from equations (E7) and (E12), I1 = I AM[1],1 + I AM[2],1 It can be done this way.

[0305] Furthermore, when the current flowing through the wiring BLref is denoted as I2, the current I2 is equal to the memory cell AMr Source of transistor Tr12 in ef[1] and memory cell AMref[2] - Since this is the sum of the currents flowing between the drains, from equations (E8) and (E13), I2 = I AMref[1],1 +I AMref[2],1 It can be done this way.

[0306] As a result, in the current mirror circuit CM, the source-drain of transistor Tr31 A current I2 flows between the input and the input. Therefore, between the source and drain of transistor Tr32... A current I2 flows through it.

[0307] Here, since switch SW4 of circuit OFAC is in the ON state, circuit OFAC and Current flows between circuit CMS. Current flows between the first and second terminals of switch SW4. When I5 is denoted as I5, then I5 = I1 - I2 - I3 + I4 = 2k(V W[1] V X[1] +V W [2] V X[2] The sum of products can be calculated in the same way as in equation (E16).

[0308] Furthermore, the equivalent circuit of the arithmetic circuit MAC1A in Figure 15 is the circuit shown in Figure 16. This is possible. The current source CI1 shown in Figure 16 is connected to the memory cell AM[1] and memory cell A shown in Figure 15. M[2] corresponds to the current source CI2 shown in Figure 16, which corresponds to the current source circuit CS1, and is shown in Figure 16. The current source CI3 shown corresponds to the current source circuit CS2, and the current source CI4 shown in Figure 16 is a current source. This corresponds to the Tomilla circuit CM2.

[0309] Note that the memory cell array CA of the arithmetic circuit MAC1A in Figure 13 is a 2x2 matrix. We have dealt with memory cell arrays having memory cells arranged in a row, and For memory cell arrays with two or more rows, or memory cell arrays with three or more rows and three or more columns Similarly, sum-of-products operations can be performed. In this case, the sum-of-products circuit is one of multiple columns. The reference data (potential V PR By making it a memory cell that holds ) the remaining of the multiple columns The number of multiply-accumulate operations can be performed simultaneously for each column. Furthermore, by increasing the number of rows... Therefore, in the sum-of-products operation, the number of terms to be added can be increased, so in this case, current I 5 is similar to equation (E18) in that I5 = 2kΣV W[i] V X[i]It can be expressed as follows.

[0310] Here, in circuit OFAC, the current I5 is converted to a voltage by resistor RE. Figure 1 Although not shown in Figure 3, the OFAC circuit operates according to the voltage, with a predetermined activity By creating a circuit that performs calculations according to the characterization function, similar to the MAC1 calculation circuit in Figure 9, It can perform calculations on hierarchical neural networks.

[0311] <Example of arithmetic circuit configuration 2> Next, in the neural network 100 described above, the circuit configuration of the arithmetic circuit MAC1 is as follows: This section describes an example of a circuit that performs sum-of-accumulate operations and activation function operations, but with different characteristics.

[0312] Figure 17 shows an example of the configuration of the arithmetic circuit MAC2. The arithmetic circuit MAC2 shown in Figure 17 is The sum-of-products operation is performed on the first data corresponding to the voltage held in each cell and the second data that was input. This is a circuit that performs an operation and then uses the result of the sum-of-products operation to perform an activation function operation. Data, and secondary data, are examples of analog data or multi-valued data (discrete data) (This can be considered as data.)

[0313] The MAC2 arithmetic circuit consists of circuits WCS, XCS, WSD, and SWS1. Circuit SWS2, cell array CA2, and conversion circuit ITRZ[1] or conversion circuit ITRZ[ It has m] and

[0314] The cell array CA2 consists of cells IM[1,1] to IM[m,n] (where m is 1). The above integers, where n is an integer greater than or equal to 1.) and cell IMref[1] to cell IM It has ref[m] and, cells IM[1,1] to IM[m,n] are the first data It has the function of maintaining a potential corresponding to the amount of current, and cells IMref[1] to I Mref[m] corresponds to the second data required to perform the sum-of-products operation with the held potential. It has the function of supplying voltage to signal lines XCL[1] to XCL[m].

[0315] Note that the cell array CA2 in Figure 17 has n+1 cells in the row direction and m cells in the column direction, and Although arranged in a cubic shape, the cell array CA2 has 2 or more cells in the row direction and 1 in the column direction. The configuration may consist of more than one element arranged in a matrix.

[0316] Cells IM[1,1] through IM[m,n] consist of transistor F1 and transistor F It has 2 and capacity C5, and cells IMref[1] to IMref[m] are each It has transistor F1m, transistor F2m, and capacitance C5m.

[0317] Note that transistors F1 and F1m are in the ON state unless otherwise specified. In this case, it is assumed that the operation ultimately takes place in the linear domain. That is, each of the above The gate voltage, source voltage, and drain voltage of this transistor operate in the linear region. This includes cases where the voltage is appropriately biased within the range. However, one aspect of the present invention The term is not limited to this. For example, transistors F1 and F1m are ON state In this state, it may operate in the saturation region, and it may also operate in the linear region or in the saturation region. It is acceptable to have a mix of cases where this is the case and cases where it is not.

[0318] Also, unless otherwise specified, transistors F2 and F2m are subthreads. When operating in the low-pressure region (i.e., transistor F2 or transistor F2m) This includes the case where the gate-source voltage is lower than the threshold voltage. The gate voltage, source voltage, and drain voltage of each of the transistors mentioned above are: This includes cases where the voltage is properly biased to operate in the subthreshold region. Therefore, transistors F2 and F2m are source-drain. This includes cases where an off-current flows between them.

[0319] Furthermore, transistor F1 and / or transistor F1m are connected to transistor Tr11. Similarly, it is preferable that it be an OS transistor. In addition, transistor F1, and / or The channel formation region of transistor F1m is composed of indium, element M (for example, element M is...). For example, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, Titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium Selected from neodymium, hafnium, tantalum, tungsten, or magnesium, etc. Examples include one or more types, and the oxide must contain at least one zinc. More preferable. Transistor Tr1 and / or transistor F1m are particularly in the embodiment It is even more preferable that the transistor structure is as described in section 3.

[0320] OS transistors are used as transistor F1 and / or transistor F1m. This suppresses the leakage current of transistor F1 and / or transistor F1m. Because this is possible, it is sometimes possible to realize a multiply-accumulate circuit with high calculation accuracy. Also, transient By using an OS transistor as transistor F1 and / or transistor F1m, , when transistor F1 and / or transistor F1m are in a non-conductive state, holding node The leakage current from the writing word line can be made very small. In other words, the holding note This reduces the refresh operation of the potential of the circuit, thus reducing the power consumption of the sum-of-accumulate circuit. This can be reduced.

[0321] Furthermore, for transistor F2 and / or transistor F2m, OS transistors By using this, it is possible to operate in a wide current range in the subthreshold region. Therefore, current consumption can be reduced. Also, transistor F2, and / or transistor By using an OS transistor for the Zistor F2m, the same properties as transistor Tr11 can be achieved. Because it can be manufactured at any time, the manufacturing process for multiply-accumulate circuits can be shortened in some cases. Yes. Also, transistor F2 and / or transistor F2m are in the channel formation region. A transistor containing silicon may also be used. For example, amorphous silicon can be used as the silicon. (Sometimes called hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, Single-crystal silicon and similar materials can be used.

[0322] In each of cells IM[1,1] through IM[m,n], the transistor F1 The first terminal is electrically connected to the gate of transistor F2. The first terminal is electrically connected to wiring VE. The first terminal of capacitance C5 is connected to the transistor. It is electrically connected to the F2 gate.

[0323] Incidentally, one aspect of the present invention does not depend on the connection configuration of the transistor's back gate. (Figure) In diagram 17, back gates are shown for transistors F1 and F2. This shows a configuration that includes the back gate. Figure 17 shows the connection structure of the back gate. Although not shown in the diagram, the electrical connection destination of the back gate was determined during the design phase. It can be determined. For example, in a transistor with a back gate, the transistor To increase the on-current of the zistor, the gate and back gate may be electrically connected. In other words, for example, the gate and back gate of transistor M2 may be electrically connected. Also, for example, in a transistor having a back gate, the structure of the transistor To vary the voltage value, or to reduce the off-current of the transistor, By providing wiring that is electrically connected to an external circuit, etc., the external circuit etc. will transmit A potential may be applied to the back gate of the transistor. Note that this is related to transistor F1 m, transistor F2m, transistors F3[1] to F3[n] described later , transistors F4[1] to F4[n], and furthermore, not only Figure 17 but also the specification Transistors mentioned elsewhere, or transistors illustrated in other drawings. The same applies to this matter.

[0324] Furthermore, the semiconductor device according to one aspect of the present invention has a structure of transistors included in the semiconductor device. It does not depend on. For example, transistors F1 and F2 shown in Figure 17 are shown in Figure As shown in 17, a configuration without a back gate, that is, a single-gate structure It may also be a transistor. Furthermore, some transistors have a back gate configuration. Furthermore, some other transistors may have a configuration without a back gate. Regarding this, transistor F1m, transistor F2m, and transistor F (described later) 3[1] to transistor F3[n], transistor F4[1] to transistor F4[ Furthermore, in addition to the circuit diagram shown in Figure 17, the transistors described in other parts of the specification are also described elsewhere. The same applies to the transistors shown in the diagrams or other drawings.

[0325] Wiring VE is for cell IM[1,1], cell IM[m,1], cell IM[1,n], and Current is passed between the first and second terminals of each transistor F2 of IM[m,n]. The wiring is for cell IMref[1] and cell IMref[m] respectively. It functions as wiring to allow current to flow between the first and second terminals of transistor F2. For example, wiring VE functions as wiring that supplies a constant voltage. This constant voltage is: For example, this could be a low-level potential or ground potential.

[0326] In cell IM[1,1], the second terminal of transistor F1 is connected to wiring WCL[1]. The gate of transistor F1 is electrically connected to the wiring WSL[1]. The second terminal of transistor F2 is electrically connected to wiring WCL[1] and capacitance C5. The second terminal is electrically connected to wiring XCL[1]. Note that in Figure 17, cell I At M[1,1], the first terminal of transistor F1 and the gate of transistor F2, The connection point between the first terminal of capacitor C5 and the node NN[1,1] is defined as node NN[1,1].

[0327] In cell IM[m,1], the second terminal of transistor F1 is connected to wiring WCL[1]. The gate of transistor F1 is electrically connected to the wiring WSL[m]. The second terminal of transistor F2 is electrically connected to wiring WCL[1] and capacitance C5. The second terminal is electrically connected to the wiring XCL[m]. Note that in Figure 17, cell I At M[m,1], the first terminal of transistor F1 and the gate of transistor F2, The connection point between the first terminal of capacitor C5 and the other terminal is defined as node NN[m,1].

[0328] In cell IM[1,n], the second terminal of transistor F1 is connected to the wiring WCL[n]. The gate of transistor F1 is electrically connected to the wiring WSL[1]. The second terminal of transistor F2 is electrically connected to the wiring WCL[n] and capacitance C5. The second terminal is electrically connected to wiring XCL[1]. Note that in Figure 17, cell I In M[1,n], the first terminal of transistor F1 and the gate of transistor F2, The connection point between the first terminal of capacitor C5 and the node NN[1,n] is defined as node NN[1,n].

[0329] In cell IM[m,n], the second terminal of transistor F1 is connected to the wiring WCL[n]. The gate of transistor F1 is electrically connected to the wiring WSL[m]. The second terminal of transistor F2 is electrically connected to the wiring WCL[n] and capacitance C5. The second terminal is electrically connected to the wiring XCL[m]. Note that in Figure 17, cell I In M[m,n], the first terminal of transistor F1 and the gate of transistor F2, The connection point between the first terminal of capacitor C5 and the other terminal is defined as node NN[m,n].

[0330] In cell IMref[1], the second terminal of transistor F1m is connected to wiring XCL[1] The gate of transistor F1m is electrically connected to wiring WSL[1]. The second terminal of transistor F2m is electrically connected to wiring XCL[1], The second terminal of capacitor C5 is electrically connected to wiring XCL[1]. Note that in Figure 17... In cell IMref[1], the first terminal of transistor F1m and transistor F2 The connection point between the gate of m and the first terminal of capacitor C5 is defined as node NNref[1]. .

[0331] In cell IMref[m], the second terminal of transistor F1m is connected to wiring XCL[m]. The gate of transistor F1m is electrically connected to wiring WSL[m]. The second terminal of transistor F2m is electrically connected to the wiring XCL[m]. The second terminal of capacitor C5 is electrically connected to wiring XCL[m]. Note that in Figure 17... In cell IMref[m], the first terminal of transistor F1m and transistor F2 The connection point between the gate of m and the first terminal of capacitor C5 is defined as node NNref[m]. .

[0332] The above node NN[1,1], node NN[m,1], node NN[1,n], no Node NN[m,n], node NNref[1], and node NMref[m] are, respectively It functions as a holding node for the cell.

[0333] Circuit SWS1 has transistors F3[1] to F3[n]. The first terminal of transistor F3[1] is electrically connected to wiring WCL[1], and the transistor The second terminal of F3[1] is electrically connected to the circuit WCS, and the gate of transistor F3[1] The wire is electrically connected to wiring SWL1. The first terminal of transistor F3[m] is The wiring WCL[m] is electrically connected, and the second terminal of transistor F3[m] is connected to circuit W Electrically connected to CS, the gate of transistor F3[m] is electrically connected to wiring SWL1. It is connected.

[0334] Transistors F3[1] through F3[n] are similar to transistor Tr11. It is preferable that the transistor is an OS transistor. In addition, transistor F1, and / or The channel-forming region of lampistor F1m is composed of indium, element M (for example, element M is...). Aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium Iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, One of the following elements: odymium, hafnium, tantalum, tungsten, or magnesium. Examples include, or multiple types. ), and it is more important that it is an oxide containing at least one zinc. This is preferable. Transistors F3[1] to F3[n] are particularly in Embodiment 3. It is even more preferable that the transistor structure is as described.

[0335] Circuit SWS1 is connected to circuit WCS and each of the wirings WCL[1] through WCL[n]. It functions as a circuit that switches between a conductive state and a non-conductive state.

[0336] Circuit SWS2 has transistors F4[1] to F4[n]. The first terminal of transistor F4[1] is electrically connected to wiring WCL[1], and the transistor The second terminal of F4[1] is electrically connected to the conversion circuit ITRZ[1], and transistor F The gate of transistor 4[1] is electrically connected to wiring SWL2. Transistor F4[m] The first terminal is electrically connected to the wiring WCL[m], and the second terminal of transistor F4[m] The child is electrically connected to the conversion circuit ITRZ[1], and the gate of transistor F4[m] is It is electrically connected to wiring SWL2.

[0337] Transistors F4[1] through F4[n] are similar to transistor Tr11. It is preferable that the transistor is an OS transistor. In addition, transistor F1, and / or The channel-forming region of lampistor F1m is composed of indium, element M (for example, element M is...). Aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium Iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, One of the following elements: odymium, hafnium, tantalum, tungsten, or magnesium. Examples include, or multiple types. ), and it is more important that it is an oxide containing at least one zinc. Preferably, transistors F4[1] to F4[n] are particularly in embodiment 3. It is even more preferable that the transistor structure is as described.

[0338] Circuit SWS2 is connected between wiring WCL[1] and circuit ITRZ[1], and wiring WCL[n The circuit is used to switch between the conductive and non-conductive states between [ ] and the circuit ITRZ[n]. To be able to.

[0339] The WCS circuit sends data to be stored in each cell of the cell array CA2. It has the function of trusting.

[0340] Circuit XCS is electrically connected to wiring XCL[1] through wiring XCL[m]. The path XCS is a cell IMref[1] to cell IMref[m] of the cell array CA2. For each of these, there is a function to supply current according to the reference data, or current according to the second data. It has.

[0341] Circuit WSD is electrically connected to wiring WSL[1] through wiring WSL[m]. When writing the first data to a cell in the cell array CA2, the WSD route uses the WSL route. 1) By sending a predetermined signal to the wiring WSL[m], the data writing destination and It has the function of selecting a memory cell.

[0342] Furthermore, circuit WSD is electrically connected to wiring SWL1 and wiring SWL2. Circuit WSD transmits a predetermined signal to wiring SWL1, thereby connecting with circuit WCS and cell. The function of making the connection between the wire CA2 and the wire SWL2 conductive or non-conductive, and the function of sending a predetermined signal to the wiring SWL2. By transmitting, the conversion circuit ITRZ[1] or conversion circuit ITRZ[m] and cell array It has the function of making the connection between CA2 and the other device conductive or non-conductive.

[0343] Each of the conversion circuits ITRZ[1] through ITRZ[m] has an input terminal and an output terminal. It has terminals. Each of the conversion circuits ITRZ[1] to ITRZ[m] is, It has the function of converting the current input to the input terminal into a voltage and outputting it from the output terminal. Each of the conversion circuits ITRZ[1] to ITRZ[m] is, as an example, a circuit OFST can be applied. Also, the conversion circuit ITRZ[1] or the conversion circuit ITRZ Each of [m] may have an activation function circuit ACTV, and using the converted voltage Alternatively, the activation function may be calculated and the result of the calculation may be output to the output terminal.

[0344] <Example of operation of the arithmetic circuit 2> Next, we will explain an example of the operation of the MAC2 arithmetic circuit.

[0345] Figure 18 shows a timing chart of an example of the operation of the MAC2 arithmetic circuit. Timing in Figure 18 The chart shows the wiring switches between time T11 and time T23, and in the vicinity of those times. L1, wiring SWL2, wiring WSL[i] (i is an integer between 1 and m-1), wiring WSL[i+1], wiring XCL[i], wiring XCL[i+1], node NN[i,j], The power of node NNref[i], node NN[i+1,j], and node NNref[i+1] This shows the fluctuation in position. Furthermore, the timing chart in Figure 18 shows that cell IM[i,j] The amount of current I flowing between the first and second terminals of the transistor F2 included. F2 [i,j] And between the first and second terminals of transistor F2m contained in cell IMref[i] Current flowing I F2m [i] and transistor F contained in cell IM[i+1,j] The amount of current I flowing between the first and second terminals of device 2. F2 [i+1,j] and cell IMref[i The amount of current I flowing between the first and second terminals of transistor F2m included in [+1] F2 m The variations of [i+1] and each of them are also shown.

[0346] In this example, the potential of wiring VE is set to the ground potential GND. Also, time T11 Prior to that, each of the following is contained in cell IM[i,j] and cell IM[i+1,j] The transistor F1, cell IMref[i], and cell IMref[i+1] are included in Turn on transistor F1m, node NN[i,j], node NNref[i] The potentials of node NN[i+1,j] and node NNref[i+1] are measured by the grounding current. Assume that the position is set to GND.

[0347] Also, as an initial setting, the contents of cell IM[1,1] to cell IM[m,n] Each transistor F1 is contained in cell IMref[1] or cell IMref[m] Turn on transistor F1m, and node NN[1,1] to node NN[m, n], the potential of node NNref[1] to node NNref[m] is set to the ground potential GND. ru.

[0348] <<From time T11 to time T12>> Between time T11 and time T12, a high-level potential occurred at wiring SWL1 (as shown in Figure 18). This is labeled as High.) A low-level potential (L in Figure 18) is applied to the wiring SWL2. It is written as ow.) is applied. As a result, transistor F3[1] or to A high-level potential is applied to each gate of transistor F3[n], and transistor F Each of transistors 3[1] through F3[n] turns on, and transistor F4[ A low-level potential is applied to the gates of each of transistors F4[n], Each of the transistors F4[1] through F4[n] is turned off.

[0349] Also, between time T11 and time T12, wiring WSL[i], wiring WSL[i+ A low-level potential is applied to [1]. This results in the i-th row of cell array CA2. The gate of transistor F1 contained in IM[i,1] or cell IM[i,n], and The gate of transistor F1m, which is included in IMref[i], and a low-level potential are marked. As a result, transistors F1 and F1m are turned off. , cell IM[i+1,1] to cell IM[i+1,n] in the i+1th row of cell array CA2 The gate of transistor F1 contained in and the cell IMref[i+1] The gate of transistor F1m and a low-level potential are applied to each transistor F1 and transistor F1m are turned off.

[0350] Also, between time T11 and time T12, wiring XCL[i], wiring XCL[i+ [1] has the ground potential (GND) applied to it.

[0351] Also, between time T11 and time T12, wiring WCL[j], wiring XCL[i] Therefore, no current flows through wiring XCL[i+1]. F2 [i,j], I F2m [ i]I F2 [i+1,j], I F2m [i+1] is 0.

[0352] <<From time T12 to time T13>> Between time T12 and time T13, a high-level potential was applied to the wiring WSL[i]. This is done. As a result, cell IM[i,1] to cell IM[i The gate of transistor F1 contained in [n] and the cell IMref[i] The gate of transistor F1m and a high-level potential are applied to each transistor. Transistor F1 and transistor F1m are turned ON. Also, from time T12 to time T13 Between these, wiring WSL[1] to wiring WSL[m], excluding wiring WSL[i], have low-level wiring. A bell potential is applied, and cells IM[1,1] to cells other than row i of cell array CA2 are used. The transistor F1 contained in IM[m,n] and cells IMref[1] other than row i Transistor F1m contained in cell IMref[m] is in the off state. It shall be assumed that...

[0353] Furthermore, a low-level potential is applied to the wiring XCL[1] through wiring XCL[m].

[0354] <<From time T13 to time T14>> Between time T13 and time T14, from circuit WCS, transistor F3[j A current of I0[i,j] flows through the cell array CA2 via ]. At this time, The first transistor F1 contained in cell IM[i,j] of row i of cell array CA2 The terminal and the wiring WCL[j] are in a conductive state, and the i-th row of cell array CA2 The fourth of transistor F1 contained in cells IM[1,j] to IM[m,j] other than the first cell IM[1,j]. Since there is no conductivity between terminal 1 and wiring WCL[j], from wiring WCL[j] A current of I0[i,j] flows through cell IM[i,j].

[0355] By the way, when transistor F1 contained in cell IM[i,j] turns ON... Therefore, transistor F2 contained in cell IM[i,j] has a diode connection configuration. Therefore, when current flows from wiring WCL[j] to cell IM[i,j], The potentials of the gate of transistor F2 and the second terminal of transistor F2 are approximately equal. The potential is determined by the amount of current flowing from wiring WCL[j] to cell IM[i,j] and the transistor. This is determined by the potential of the first terminal of Zistor F2 (in this case, GND), etc. In this example of operation, , a current of amount I0[i,j] flows from wiring WCL[j] to cell IM[i,j]. Therefore, the potential of the gate (node ​​NN[i,j]) of transistor F2 is V g [i,j Let's assume that the gate-source voltage in transistor F2 is V g [i,j]-GND, and the current I0 is present between the first and second terminals of transistor F2. A current of [i,j] flows.

[0356] Here, the threshold voltage of transistor F2 is V th When this happens, transistor F2 is The current I0[i,j] when operating in the threshold region can be described by the following equation. ru.

[0357]

number

[0358] Note I a is V g ga V th The drain current when [i,j], where K is the temperature. This is a correction factor determined by the device structure, etc.

[0359] Also, between time T13 and time T14, from circuit XCS, wiring XCL[i I as the current quantity in ] ref0 At this time, the current flows in cell IMref[i] The first terminal of transistor F1m and the wiring XCL[i] are in a conductive state. Therefore, the current I is supplied from the wiring XCL[i] to cell IMref[i]. ref0 An electric current flows.

[0360] Similar to cell IM[i,j], transistor F1 is included in cell IMref[i]. When m is turned on, the transient contained in cell IMref[i,j] F2m will have a diode connection configuration. Therefore, the wiring from XCL[i] to cell IMre When current flows through f[i], the gate of transistor F2m and the terminal of transistor F2m The potentials of the two terminals and the cell are approximately equal. This potential is measured from the wiring XCL[i] to the cell. The amount of current flowing through IMref[i] and the potential of the first terminal of transistor F2m (here, GN) Determined by D), etc. In this example, wiring XCL[i] to cell IMref[i ] current I ref0 As the current flows, the gate (node) of transistor F2 NNref[i]) is V gm [i] is assumed to be the case, and the wiring XCL[i] at this time The potential is also V gm Let [i]. In other words, in transistor F2m, the gate-source interval Voltage is V gm [i]-GND, and between the first and second terminals of transistor F2m, Current amount I ref0 An electric current flows.

[0361] Here, the threshold voltage of transistor F2m is V thm When [i] is used, the transition Current I when F2m operates in the subthreshold region ref0 As follows It can be described. Note that the correction coefficient K is the transistor F2 contained in cell IM[i,j] This is considered identical to the device structure and size (channel length, channel width) of a transistor. ) are assumed to be the same. Also, due to manufacturing variations, the correction coefficient K of each transistor will vary. However, the variability is suppressed to such an extent that the discussion described later holds true with sufficient accuracy for practical purposes. do.

[0362]

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[0363] Here, the first data point, the weight coefficient w[i,j], is defined as follows.

[0364]

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[0365] Therefore, equation (F1) can be rewritten as follows:

[0366]

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[0367] <<From time T14 to time T15>> Between time T14 and time T15, a low-level potential was applied to the wiring WSL[i]. This is done. As a result, cell IM[i,1] to cell IM[i The gate of transistor F1 contained in [n] and the cell IMref[i] The gate of transistor F1m and a low-level potential are applied to each transistor. Transistor F1 and transistor F1m are turned off.

[0368] When transistor F1 contained in cell IM[i,j] is turned off, Capacitor C5 controls the potential of the gate (node ​​NN[i,j]) of transistor F2 and the wiring XC The potential difference between L[i] and V is the potential difference between L[i] and V. g [i,j]-V gm [i] is retained. Also, the cell The transistor F1 included in IMref[i] is turned off, which affects the capacitance. C5m is connected to the potential of the gate (node ​​NNref[i]) of transistor F2m and the wiring X The difference between the potential of CL[i] and the other potential, which is 0, is maintained. The potential maintained by capacitance C5m is, In the operation from time T13 to time T14, the same applies to transistors F1m and F2m. Depending on the characteristics of each transistor, the potential (denoted as Δ here) will be non-zero. There are also cases where this is the case. However, the potential of node NNref[i] is the potential of wiring XCL[i] plus Δ. By considering that the potential is as described, the following argument holds true.

[0369] <<From time T15 to time T16>> Between time T15 and time T16, GND is applied to wiring XCL[i]. Therefore, each of the cells IM[i,1] through IM[i,n] in row i contains Capacitive coupling by the present C5 allows nodes NN[i,1] to NN[i,n] to The potential changes, and capacitive coupling occurs due to the capacitance C5 contained in cell IMref[i]. The potential of NNref[i] changes.

[0370] The change in potential between nodes NN[i,1] and NN[i,n] is determined by the wiring XCL[i]. The change in potential is determined by each cell IM[i,1] contained in the cell array CA2. The potential is obtained by multiplying by the capacitive coupling coefficient determined by the configuration of cell IM[i,n]. The coefficient is calculated based on the capacitance of capacitor C5, the gate capacitance of transistor F2, parasitic capacitance, etc. In each of cells IM[i,1] through IM[i,n], the capacity C5 is used. When the capacitive coupling coefficient is p, the potential at node NN[i,j] of cell IM[i,j] is given by: From the potential at the time between time T14 and time T15, p(V) gm [i]-GND) It decreases.

[0371] Similarly, a change in the potential of wiring XCL[i] can affect the contents of cell IMref[i]. The capacitive coupling by the contained capacitance C5m also changes the potential of node NNref[i]. When the capacity coupling coefficient due to capacity C5m is set to p, similar to capacity C5, then cell IMref The potential of node NNref[i] in [i] is at a point in time between T14 and T15. From the potential at which, p(V) gm [i]-GND) decreases

[0372] This causes the potential of node NN[i,j] of cell IM[i,j] to decrease, Rangista F2 is turned off, and similarly, the node NNref[ of cell IMref[i] As the potential of [i] decreases, transistor F2m also turns off. Therefore, at time T1 Between 5 and time T16, I F2 [i,j], I F2m Each of [i] is 0 This is the result.

[0373] <<From time T16 to time T17>> Between time T16 and time T17, a high-level potential occurred in the wiring WSL[i+1]. This is applied. As a result, the cell IM[i+1,1] in the i+1th row of the cell array CA2 The gate of transistor F1 contained in cell IM[i+1,n] and cell IMref[ When a high-level potential is applied to the gate of transistor F1m included in [i+1], Transistors F1 and F1m are both turned ON. Also, time T1 Between 6 and time T17, wiring WSL[1] to wiring WSL[i+1] A low-level potential is applied to the wiring WSL[m], and the i+1th row and beyond of the cell array CA2 Transistor F1 contained in the outer cell IM[1,1] or cell IM[m,n], and i Transitions contained in cells IMref[1] or IMref[m] other than row +1 Assume that the F1m is in the off state.

[0374] Furthermore, a low-level potential is applied to the wiring XCL[1] through wiring XCL[m].

[0375] <<From time T17 to time T18>> Between time T17 and time T18, from circuit WCS, transistor F3[j A current of I0[i+1,j] flows through the cell array CA2 via ]. The transient contained in cell IM[i+1,j] in the i+1 row of cell array CA2 The first terminal of terminal F1 and the wiring WCL[j] are in a conductive state, and cell array C The tra containing in cells IM[1,j] through IM[m,j] other than row i+1 of A2 Since there is no conductivity between the first terminal of inverter F1 and the wiring WCL[j], the wiring A current of I0[i+1,j] flows from WCL[j] to cell IM[i+1,j].

[0376] By the way, transistor F1 contained in cell IM[i+1,j] turns ON. As a result, transistor F2 contained in cell IM[i+1,j] becomes a diode junction This is the subsequent configuration. Therefore, current flows from the wiring WCL[j] to the cell IM[i+1,j]. At that time, the gate of transistor F2 and the second terminal of transistor F2, and the respective electrical components The potentials become approximately equal. This potential flows from wiring WCL[j] to cell IM[i+1,j]. It is determined by the amount of current flowing and the potential of the first terminal of transistor F2 (in this case, GND), etc. In this example, the current I0[i+1 As a current of ,j] flows, the gate (node ​​NN[i+1, The potential of j) is V g Let it be [i+1,j]. In other words, transistor F2 And the gate-source voltage is V g [i+1,j] becomes GND, and transistor F2 A current of I0[i+1,j] flows between the first and second terminals.

[0377] Here, the threshold voltage of transistor F2 is V th When [i+1,j], The current I0[i+1,j] when the zistor F2 operates in the subthreshold region is as follows: It can be written as shown in the formula. Note that the correction coefficient is the transient contained in cell IM[i,j] The transistor F2 is set to the same K as transistor F2m, which is included in cell IMref[i]. ru.

[0378]

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[0379] Also, between time T17 and time T18, from circuit XCS, wiring XCL[i I as the current to [+1] ref0 The current flows. At this time, cell IMref[i+1] The first terminal of transistor F1m included in the circuit is in a conductive state with the wiring XCL[i+1]. Therefore, the current I will flow from wiring XCL[i+1] to cell IMref[i+1]. ref0 of An electric current flows.

[0380] Similar to cell IM[i+1,j], the transients contained in cell IMref[i+1] When the F1m is turned on, the contents of cell IMref[i+1,j] The transistor F2m will be configured in a diode connection. Therefore, the wiring XCL[i+1] When current flows from cell IMref[i+1], the gate of transistor F2m and The potentials of the second terminal of transistor F2m and the respective terminals are approximately equal. The amount of current flowing from XCL[i+1] to cell IMref[i+1] and the transistor F2m This is determined by the potential of the first terminal (GND in this case), etc. In this example of operation, the wiring is XCL Current I from [i+1] to cell IMref[i+1] ref0 As the current flows The gate of transistor F2 (node ​​NNref[i+1]) is V gm [i+1] It is assumed that the potential of the wiring XCL[i+1] at this time is also V gm Let [i+1] be the value. In other words, in transistor F2m, the gate-source voltage is V gm [i+1]-GN D is obtained, and the current I is distributed between the first and second terminals of transistor F2m. ref0 The current It flows.

[0381] Here, the threshold voltage of transistor F2m is V thm When we have [i+1,j], Current I when transistor F2m operates in the subthreshold region ref0 The following formula It can be written as follows. Note that the correction coefficient K is the tra contained in cell IM[i+1,j] It is identical to the 'Njista F2'.

[0382]

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[0383] Here, we define the first data point, the weight coefficient w[i+1,j], as follows.

[0384]

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[0385] Therefore, equation (F5) can be rewritten as the following equation:

[0386]

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[0387] <<From time T18 to time T19>> Between time T18 and time T19, a low-level potential occurred in the wiring WSL[i+1]. This is applied. As a result, cell IM[i+1,1] in the i-th row of cell array CA2 to cell The gate of transistor F1 contained in IM[i+1,n] and cell IMref[i+ The gate of transistor F1m included in [1] is subjected to a low-level potential, and Transistors F1 and F1m are turned off.

[0388] When transistor F1 contained in cell IM[i+1,j] turns off... And, the capacitance C5 is at the potential of the gate (node ​​NN[i+1,j]) of transistor F2, The potential difference between the wiring XCL[i+1] and is V. g [i+1,j]-V gm [i+1] is preserved It is held. Also, transistor F1 contained in cell IMref[i+1] is in the off state. By becoming this way, the capacitor C5m is connected to the gate of transistor F2m (node ​​NNref The difference between the potential of [i+1]) and the potential of wiring XCL[i+1], which is 0, is maintained. Oh, the potential held by C5m is the same as the operation from time T18 to time T19 of transistor F The potential is not zero depending on the transistor characteristics of 1m or transistor F2m (here, Let Δ. ) This can also be the case. However, the potential of node NNref[i] is the wiring XCL By considering that the potential becomes the potential of [i] plus Δ, the following argument holds.

[0389] <<From time T19 to time T20>> Between time T19 and time T20, GND was applied to wiring XCL[i+1]. Therefore, the cells IM[i+1,1] through IM[i+1,n] in row i+1 are... Capacitance coupling by the capacity C5 contained in each node NN[i,1] to node The potential of NN[i+1,n] changes, and the capacitance C5 contained in cell IMref[i+1] The potential of node NNref[i+1] changes due to capacitive coupling.

[0390] The change in potential between nodes NN[i+1,1] and NN[i+1,n] is determined by the wiring XC. The change in potential of L[i+1] is determined by each cell IM[ included in the cell array CA2. The electric charge multiplied by the capacitive coupling coefficient determined by the configuration of i+1,1 to cell IM[i+1,n] The capacitive coupling coefficient is calculated by the capacitance of capacitor C5, the gate capacitance of transistor F2, and the parasitic capacitance. It is calculated based on the quantity, etc. Specifically, that of cells IM[i+1,1] through IM[i+1,n]. In each case, the capacity coupling coefficient due to capacity C5 is set from cell IM[i,1] to cell IM[i, Similar to the capacity coupling coefficient due to the capacity C5 in each of n, when p is used, cell IM The potential of node NN[i+1,j] at [i+1,j] is from time T18 to time T19. From the potential at the time interval, p(V) gm[i+1]-GND) decreases.

[0391] Similarly, a change in the potential of wiring XCL[i+1] causes cell IMref[i+ Due to the capacitive coupling by the capacitive C5m contained in [1], node NNref[i+1] The potential also changes. When the capacitive coupling coefficient due to capacitance C5m is denoted as p, similar to capacitance C5, The potential of node NNref[i+1] of IMref[i+1] is obtained from time T18 to time T From the potential at the time point up to 19, p(V) gm [i+1]-GND) decreases.

[0392] This causes the potential of node NN[i+1,j] in cell IM[i+1,j] to decrease. Therefore, transistor F2 is turned off, and similarly, the node of cell IMref[i+1] As the potential of NNref[i] decreases, transistor F2m also turns off. Therefore, between time T19 and time T20, I F2 [i+1,j], I F2m [i Each of the values ​​in [+1] becomes 0.

[0393] <<From time T20 to time T21>> Between time T20 and time T21, a low-level potential is applied to wiring SWL1. This allows each of transistors F3[1] through F3[n] to function correctly. When a low-level potential is applied to the gate, transistor F3[1] to transistor F3[n Each of the ] will be turned off.

[0394] <<From time T21 to time T22>> Between time T21 and time T22, a high-level potential is applied to the wiring SWL2. This allows each of transistors F4[1] through F4[n] to function correctly. When a high-level potential is applied to the gate, transistor F4[1] to transistor F4[n Each of the ] will be turned off.

[0395] <<From time T22 to time T23>> Between time T22 and time T23, power was supplied from circuit XCS to wiring XCL[i]. As flow rate, I ref0 x[i]I is x[i] times the original. ref0 A current flows. In the example, x corresponds to the value of the neuron's signal, which is the second data. At this time, the wiring... The potential of XCL[i] ranges from 0 to V gm Let it change to [i] + ΔV[i].

[0396] A change in the potential of wiring XCL[i] causes cell I in row i of cell array CA2 to change. Capacity coupling by the capacity C5 contained in each of cells M[i,1] through IM[i,n] Therefore, the potentials of nodes NN[i,1] through NN[i,n] also change. The potential of node NN[i,j] of cell IM[i,j] is V g [i,j]+pΔV[i] This is the result.

[0397] Similarly, a change in the potential of wiring XCL[i] can affect the contents of cell IMref[i]. The capacitive coupling by the contained capacitance C5m also changes the potential of node NNref[i]. Therefore, the potential of node NNref[i] of cell IMref[i] is V gm [i] +pΔV[i]

[0398] As a result, between time T22 and time T23, the first of transistor F2 The current I1[i,j] flows between terminal 1 and terminal 2 of transistor F2m. Current I flowing between the particles ref1 [i,j] can be written as follows:

[0399]

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[0400]

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[0401] From equations (F9) and (F10), x[i] can be expressed by the following equation.

[0402]

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[0403] Therefore, equation (F9) can be rewritten as the following equation.

[0404]

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[0405] In other words, the first terminal to the second terminal of transistor F2 contained in cell IM[i,j] The current flowing through it is determined by the weight coefficient w[i,j], which is the first data, and the neuron, which is the second data. It is proportional to the product of the signal value x[i] and .

[0406] Also, between time T22 and time T23, from circuit XCS, wiring XCL[i I as the current to [+1] ref0 x[i+1]I is x[i+1] times the original. ref0 Current The signal flows. In this example, x corresponds to the value of the neuron's signal, which is the second data. At this time, the potential of the wiring XCL[i+1] is from 0 to V. gm [i+1]+ΔV[i+1 It shall change to ].

[0407] A change in the potential of wiring XCL[i+1] affects the i+1 row of cell array CA2. Capacity C contained in each of cells IM[i+1,1] through IM[i+1,n] Capacitive coupling by 5 enables node NN[i+1,1] to node NN[i+1,n] The potential also changes. Therefore, the potential of node NN[i+1,j] of cell IM[i+1,j] V g The result is [i+1,j]+pΔV[i+1].

[0408] Similarly, a change in the potential of wiring XCL[i+1] causes cell IMref[i+ Due to the capacitive coupling by the capacitive C5m contained in [1], node NNref[i+1] The potential also changes. Therefore, the node NNref[i+1] of cell IMref[i+1] The electric potential is V gm The result is [i+1] + pΔV[i+1].

[0409] As a result, between time T22 and time T23, the first of transistor F2 The current I1[i+1,j] flows between terminal 1 and terminal 2 of transistor F2m. Current I flowing between the two terminals ref1 [i+1,j] can be written as follows:

[0410]

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[0411]

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[0412] From equations (F13) and (F14), x[i+1] can be expressed by the following equation.

[0413]

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[0414] Therefore, equation (F13) can be rewritten as the following equation.

[0415]

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[0416] In other words, the first terminal and second terminal of transistor F2 contained in cell IM[i+1,j] The current flowing between the children is determined by the weight coefficient w[i+1,j], which is the first data, and the second data. It is proportional to the product of the neuron's signal value x[i+1] and .

[0417] Here, from the conversion circuit ITRZ[j], transistor F4[j] and wiring WCL[j] Consider the sum of the currents flowing through cells IM[i,j] and IM[i+1,j] via this process. The sum of the currents is I S If we set it to [j], then I S [j] is from equations (F12) and (F16) It can be expressed by the following formula.

[0418]

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[0419] Therefore, the current output from the conversion circuit ITRZ[j] is the weighted first data. The numbers w[i,j] and w[i+1,j], and the second data, the value of the neuron's signal x[i The current is proportional to the sum of the products of ] and x[i+1].

[0420] In the example above, the flow to cell IM[i,j] and cell IM[i+1,j] is as follows: We have dealt with the sum of currents, but consider multiple cells, such as cell IM[1,j] to cell IM[m The sum of the currents flowing through each of [j] may also be considered. In this case, equation (F17) This can be rewritten as the following equation:

[0421]

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[0422] Therefore, in the case of a calculation circuit MAC2 having a cell array CA2 with 3 or more rows and 2 or more columns However, as mentioned above, it is possible to perform a sum-of-products operation. In this case, the sum-of-products circuit consists of multiple columns One of these rows is defined as the current quantity I ref0 , and xI ref0 By making it a cell that holds, It is possible to perform multiply-accumulate operations simultaneously for the number of remaining columns among multiple columns. In other words, We propose a semiconductor device that enables high-speed multiply-accumulate operations by increasing the number of columns in the Moriscell array. It can be provided.

[0423] When the sum-of-accumulate circuit described in this embodiment is applied as the hidden layer described above, the weight coefficient w s[k]s[k-1] (k) Using this as the first data, the current amount corresponding to the first data is in the same column. The data is sequentially stored in each cell IM, and the output from the s[k-1] neuron in the (k-1)th layer is then generated. signal z s[k-1] (k-1) Using this as the second data, the circuit XC generates a current corresponding to the second data. By flowing current from S through the wiring XCL of each row, the current I output from circuit ITRZ is generated. S from The sum of the products of the first data and the second data can be calculated. In addition, using the value of this sum of products... By determining the value of the activation function, the value of the activation function can be used as the signal for the s[k] of the k-th layer. Neuron output signal z s[k] (k) It can be done this way.

[0424] Furthermore, when the sum-of-accumulate circuit described in this embodiment is applied as the output layer described above, Mi coefficient w s[L]s[L-1] (L) Using this as the first data, the amount of current corresponding to the first data is calculated. The information is sequentially stored in each cell IM of the same column, and then from the s[L-1] neuron of the (L-1) layer... Output signal z s[L-1] (L-1) Using this as the second data, the current corresponding to the second data is rotated. By flowing current from path XCS to wiring XCL in each row, the current I output from circuit ITRZ is generated. S From this, the sum of the products of the first data and the second data can be calculated. In addition, the value of this sum of products By using this method to determine the value of the activation function, the value of the activation function is used as the signal for the Lth layer. Output signal z of the s[L] neuron s[L] (L) It can be done this way.

[0425] In this embodiment, the input layer is a buffer circuit that outputs the input signal to the second layer. It may function as intended.

[0426] Furthermore, in this embodiment, the trajectory included in the arithmetic circuit MAC1 and arithmetic circuit MAC2 We have explained the case where the transistor is an OS transistor or a Si transistor, but One aspect of the invention is not limited to this, but is included in the arithmetic circuit MAC1 and the arithmetic circuit MAC2. Examples of transistors include transistors with semiconductors such as Ge as the active layer, and ZnS Compound semiconductors such as e, CdS, GaAs, InP, GaN, and SiGe are used as the active layer. Transistors, transistors with carbon nanotubes as the active layer, and transistors with organic semiconductors as the active layer Transistors and the like can be used.

[0427] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0428] (Embodiment 3) In this embodiment, the configuration example of the arithmetic circuit described in the above embodiment, and the arithmetic circuit Examples of applicable transistor configurations are described below.

[0429] <Example of semiconductor device configuration> The semiconductor device shown in Figure 19 includes transistor 300, transistor 500, and a capacitive element. It has 600 and . Figure 21A is a cross-sectional view of transistor 500 in the channel length direction. Figure 21B is a cross-sectional view of transistor 500 in the channel width direction, and Figure 21C is a cross-sectional view of transistor 500. This is a cross-sectional view of the ZISTA 300 in the channel width direction.

[0430] Transistor 500 is a transistor (OS) having a metal oxide in the channel formation region. Transistor 500 has a small off-current, so it is used in semiconductor devices. For example, transistor Tr1 of the memory cell array CA included in the arithmetic circuit MAC1, etc. By using it in applications such as 1, it is possible to retain written data for a long period of time. In other words, the refresh operation is infrequent, or does not require a refresh operation. Therefore, the power consumption of semiconductor devices can be reduced.

[0431] The semiconductor device described in this embodiment includes a transistor 300, as shown in Figure 19. It has transistor 500 and capacitive element 600. Transistor 500 is a component of transistor 300. The capacitive element 600 is located above the transistors 300 and 500. It is provided in the above embodiment. The capacity of the memory cell array CA included in 1, etc., is C1, the capacity of the circuit OFST is C2, etc. It is possible.

[0432] The transistor 300 is mounted on the substrate 311 and consists of a conductor 316, an insulator 315, and the substrate A semiconductor region 313 consisting of part of 311, a low-level region that functions as a source region or drain region. It has a resistive region 314a and a low-resistance region 314b. Note that the transistor 300 is an example For example, the memory cell array CA included in the arithmetic circuit MAC1 described in the above embodiment. This can be applied to transistors such as Tr12.

[0433] Furthermore, the substrate 311 can be a semiconductor substrate (for example, a single crystal substrate or a silicon substrate). It is preferable to do so.

[0434] As shown in Figure 21C, transistor 300 is located on the top surface and channel of semiconductor region 313. The sides in the width direction are covered by the conductor 316 via the insulator 315. In this way, By making the ZISTA 300 a Fin type, the effective channel width is increased. The ON characteristics of the transistor 300 can be improved. Also, the contribution of the electric field of the gate electrode. This allows for an increase in the off-peak characteristics of transistor 300. .

[0435] Note that transistor 300 can be either a p-channel or n-channel type. .

[0436] The region in which the channel of the semiconductor region 313 is formed, the region near it, the source region, or In the low-resistance region 314a and low-resistance region 314b, which are rain regions, silicon It is preferable that it contains semiconductors such as semiconductor systems, and it is preferable that it contains single-crystal silicon. These are Ge (germanium), SiGe (silicon germanium), and GaAs (gallium hydrogen). It may be formed from a material containing (aluminum arsenide), GaAlAs (gallium aluminum arsenide), etc. By applying stress to the crystal lattice and changing the lattice spacing, silicon with controlled effective mass is used. Alternatively, by using GaAs and GaAlAs, transistor 30 0 is HEMT (High Electron Mobility Transistor) ) is also acceptable.

[0437] Low-resistance regions 314a and 314b are semiconductor regions applied to semiconductor region 313. In addition to the main material, elements that impart n-type conductivity, such as arsenic and phosphorus, or p-type conductivity, such as boron. It contains elements that impart conductivity.

[0438] The conductor 316, which functions as a gate electrode, imparts n-type conductivity to arsenic, phosphorus, etc. Semiconductor materials such as silicon containing elements, or elements that impart p-type conductivity, such as boron. Conductive materials such as cellulose, metallic materials, alloy materials, or metal oxide materials can be used.

[0439] Furthermore, since the work function is determined by the material of the conductor, the material of the conductor must be selected accordingly. This allows you to adjust the threshold voltage of the transistor. Specifically, by using nitride in the conductor... It is preferable to use materials such as tan or tantalum nitride. Furthermore, both conductivity and embedding properties are desirable. To achieve this, metal materials such as tungsten and aluminum are used as laminates in the conductive material. This is preferable, and using tungsten is particularly preferable in terms of heat resistance.

[0440] Note that the transistor 300 shown in Figure 19 is just one example, and its structure is not limited to that example. Appropriate transistors should be used depending on the configuration and driving method. For example, a semiconductor device can use an OS transistor. When using a unipolar circuit consisting only of transistors, the configuration of transistor 300 is as shown in Figure 20. The configuration should be the same as that of transistor 500, which uses an oxide semiconductor. Details about the Transistor 500 will be described later.

[0441] The transistor 300 is covered by insulators 320, 322, 324, and The bodies 326 are arranged in a series of stacked units.

[0442] As insulators 320, 322, 324, and 326, for example, oxidative Silicon, silicon oxide nitride, silicon nitride, silicon nitride, aluminum oxide, acid Aluminum nitride, aluminum nitride oxide, aluminum nitride, etc., can be used.

[0443] In this specification, silicon oxidnitride refers to a material whose composition contains more oxygen than nitrogen. It refers to materials with a high content of nitrogen, and silicon nitride, in terms of its composition, contains more nitrogen than oxygen. This indicates a material with a high concentration of [amount]. Furthermore, in this specification, aluminum oxide nitride is defined as [component]. It refers to a material in which the oxygen content is higher than the nitrogen content, and aluminum nitride oxide is a combination of these materials. This refers to materials with a higher nitrogen content than oxygen content.

[0444] The insulator 322 provides a step created by the transistor 300 and the like located below it. It may also function as a planarizing film that flattens the surface. For example, the upper surface of the insulator 322 is To improve flatness, the surface is flattened using a planarization treatment such as chemical mechanical polishing (CMP). It's fine if you do that.

[0445] Furthermore, the insulator 324 receives the transistor from the substrate 311 or the transistor 300, etc. A barrier film is used in the region where the TA500 is provided to prevent the diffusion of hydrogen and impurities. It is preferable that they be present.

[0446] As an example of a film that has barrier properties against hydrogen, for example, silica nitride formed by CVD A semiconductor can be used. Here, a semiconductor having an oxide semiconductor such as transistor 500 can be used. The diffusion of hydrogen into the semiconductor element may degrade the characteristics of that semiconductor element. So, a film that suppresses hydrogen diffusion is placed between transistor 500 and transistor 300. It is preferable to use it. Specifically, a membrane that suppresses hydrogen diffusion is one in which the amount of hydrogen desorption is small. It will be called a membrane.

[0447] The amount of hydrogen desorption can be analyzed, for example, using a thermodynamic desorption gas analysis (TDS) method. Yes, it is possible. For example, the amount of hydrogen desorption from insulator 324 can be determined by TDS analysis when the film surface temperature is In the range of 50°C to 500°C, the amount of desorption converted to hydrogen atoms is the area of ​​the insulator 324. Converted to a single win, 10 x 10 15 atoms / cm 2 The following is preferably 5 × 10 15 a toms / cm 2 The following is acceptable.

[0448] Furthermore, it is preferable that the dielectric constant of the insulator 326 is lower than that of the insulator 324. For example, The relative permittivity of the edge material 326 is preferably less than 4, and more preferably less than 3. Also, for example, an insulator... The relative permittivity of 326 is preferably 0.7 times or less, and preferably 0.6 times or less, than the relative permittivity of the insulator 324. This is more preferable. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between the wiring is reduced. It can be reduced.

[0449] Furthermore, insulators 320, 322, 324, and 326 contain capacitive elements 6 A conductor 328 and a conductor 330, etc., which are connected to transistor 500, are embedded. Furthermore, conductors 328 and 330 have the function of a plug or wiring. Furthermore, a conductor that functions as a plug or wiring may combine multiple structures into a single unit. The symbol may be assigned. Also, in this specification, etc., wiring and plastics that connect to the wiring The and may be a single unit. That is, when a part of the conductor functions as wiring, and In some cases, a portion of the conductive material may function as a plug.

[0450] The materials for each plug and wiring (conductor 328, conductor 330, etc.) are metal materials, composite materials, etc. Conductive materials such as gold, metal nitride, or metal oxide are used in a single layer or in a laminated form. It is possible to have both heat resistance and conductivity with high melting point materials such as tungsten and molybdenum. It is preferable to use a material, and it is preferable to use tungsten. Alternatively, aluminum. It is preferable to form it with a low-resistance conductive material such as copper. This can reduce wiring resistance.

[0451] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, as shown in Figure 19 Insulators 350, 352, and 354 are arranged in a sequential stack. Furthermore, a conductor 356 is formed on insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring to connect to the transistor 300. The conductor 356 is provided using the same material as the conductors 328 and 330. It is possible.

[0452] Furthermore, for example, insulator 350 has a barrier property against hydrogen, similar to insulator 324. It is preferable to use an insulator. Furthermore, the conductor 356 has barrier properties against hydrogen. It is preferable to include a conductor. In particular, it is preferable to include an insulator 350 that has barrier properties against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. With this configuration, The transistor 300 and the transistor 500 can be separated by a barrier layer. This can suppress the diffusion of hydrogen from transistor 300 to transistor 500.

[0453] For example, tantalum nitride can be used as a conductor that has barrier properties against hydrogen. It would be good to do so. Also, by laminating tantalum nitride and highly conductive tungsten, the wiring can be made It is possible to suppress the diffusion of hydrogen from transistor 300 while maintaining conductivity. In this case, the tantalum nitride layer having barrier properties against hydrogen has barrier properties against hydrogen It is preferable that the structure is in contact with an insulator 350 having the following properties.

[0454] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, as shown in Figure 19 Insulators 360, 362, and 364 are arranged in a sequential stack. Furthermore, a conductor 366 is formed on insulators 360, 362, and 364. Conductor 366 has the function of a plug or wiring. It can be provided using the same material as body 328 and conductor 330.

[0455] Furthermore, for example, insulator 360 has a barrier property against hydrogen, similar to insulator 324. It is preferable to use an insulator. Furthermore, the conductor 366 has barrier properties against hydrogen. It is preferable to include a conductor. In particular, an insulator 360 having barrier properties against hydrogen is preferable. A conductor having a barrier property against hydrogen is formed in the opening. With this configuration, The transistor 300 and the transistor 500 can be separated by a barrier layer. This can suppress the diffusion of hydrogen from transistor 300 to transistor 500.

[0456] A wiring layer may be provided on the insulator 364 and the conductor 366. For example, as shown in Figure 19 Insulators 370, 372, and 374 are arranged in a sequential stack. Furthermore, a conductor 376 is formed on insulators 370, 372, and 374. The conductor 376 functions as a plug or wiring. It can be provided using the same material as body 328 and conductor 330.

[0457] Furthermore, for example, insulator 370, like insulator 324, has barrier properties against hydrogen. It is preferable to use an insulator. Furthermore, the conductor 376 has barrier properties against hydrogen. It is preferable to include a conductor. In particular, an insulator 370 having barrier properties against hydrogen is preferable. A conductor having a barrier property against hydrogen is formed in the opening. With this configuration, The transistor 300 and the transistor 500 can be separated by a barrier layer. This can suppress the diffusion of hydrogen from transistor 300 to transistor 500.

[0458] A wiring layer may be provided on the insulator 374 and the conductor 376. For example, as shown in Figure 19... Insulators 380, 382, ​​and 384 are arranged in a sequential stack. Furthermore, a conductor 386 is formed on insulators 380, 382, ​​and 384. Conductor 386 functions as a plug or wiring. It can be provided using the same material as body 328 and conductor 330.

[0459] For example, insulator 380, like insulator 324, has barrier properties against hydrogen. It is preferable to use an insulator. Furthermore, the conductor 386 has barrier properties against hydrogen. It is preferable to include a conductor. In particular, an insulator 380 having barrier properties against hydrogen is preferable. A conductor having a barrier property against hydrogen is formed in the opening. With this configuration, The transistor 300 and the transistor 500 can be separated by a barrier layer. This can suppress the diffusion of hydrogen from transistor 300 to transistor 500.

[0460] In the above, a wiring layer containing a conductor 356, a wiring layer containing a conductor 366, and a conductor 376 A wiring layer including and a wiring layer including the conductor 386 have been described, but this embodiment is not applicable. The semiconductor device is not limited to this. A wiring layer similar to a wiring layer containing conductor 356 The number of layers may be three or less, or the wiring layers similar to the wiring layer containing the conductor 356 may be made five or more layers. That's good too.

[0461] Insulator 384 has insulators 510, 512, 514, and 516. They are arranged in a stack in order. Insulator 510, insulator 512, insulator 514, and insulation It is preferable that one of the components 516 is a material that has barrier properties against oxygen and hydrogen. .

[0462] For example, the insulator 510 and the insulator 514 are, for example, a substrate 311 or a transistor Hydrogen and impurities spread from the area where transistor 300 is installed to the area where transistor 500 is installed. It is preferable to use a film that has barrier properties to prevent dispersion. Therefore, insulator 324 Similar materials can be used.

[0463] As an example of a film with hydrogen barrier properties, silicon nitride formed by CVD is used. It is possible to have a semiconductor device having an oxide semiconductor such as transistor 500. Furthermore, hydrogen diffusion can degrade the properties of the semiconductor device. Therefore, A film that suppresses hydrogen diffusion is used between the transistor 500 and the transistor 300. This is preferable. Specifically, a membrane that suppresses hydrogen diffusion is a membrane that has a low rate of hydrogen desorption. ru.

[0464] Furthermore, as films having barrier properties against hydrogen, for example, insulator 510 and insulator 5 14 uses metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide. It is preferable.

[0465] In particular, aluminum oxide is a source of oxygen and hydrogen, which can cause variations in the electrical properties of transistors. It has a high barrier effect that prevents both water and other impurities from passing through the film. Aluminum oxide is susceptible to hydrogen, moisture, and other impurities during and after the transistor manufacturing process. This prevents contamination of the transistor 500 with pure material. This can suppress the release of oxygen from the oxides that make up the transistor 5. It is suitable for use as a protective film for 00.

[0466] Furthermore, for example, the same material as the insulator 320 is used for insulators 512 and 516. It is possible to do so by applying materials with relatively low dielectric constants to these insulators. This can reduce parasitic capacitance between wirings. For example, insulator 512 and insulator For 516, silicon oxide films or silicon oxide nitride films can be used.

[0467] Furthermore, insulators 510, 512, 514, and 516 contain a conductive material 5 18, and a conductor (for example, conductor 503) that constitutes the transistor 500 is embedded. The conductor 518 is connected to the capacitive element 600 or the transistor 300. It functions as a plug or wiring. Conductor 518 is connected to conductor 328 and conductor 3 It can be provided using the same materials as in 30.

[0468] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is oxygen, hydrogen, And preferably it is a conductor that has barrier properties against water. With this configuration, The ZISTA 300 and Transistor 500 have barrier properties against oxygen, hydrogen, and water. The layers can be separated, and hydrogen can be diffused from transistor 300 to transistor 500. It can be suppressed.

[0469] A transistor 500 is provided above the insulator 516.

[0470] As shown in Figures 21A and 21B, the transistor 500 is insulator 514 and insulator 5 A conductor 503 is arranged to be embedded in 16, and the insulator 516 and the conductor 503 An insulator 520 placed on top, an insulator 522 placed on top of the insulator 520, and an insulator An insulator 524 placed on top of 522, and an oxide 530a placed on top of the insulator 524. And, oxide 530b is placed on oxide 530a, and on oxide 530b, separated from each other Conductors 542a and 542b are arranged in such a manner, and conductors 542a and 542b An insulator positioned on top, superimposed between the conductor 542a and the conductor 542b, with an opening formed therein. 580, oxide 530c arranged on the bottom and sides of the opening, and the forming surface of oxide 530c The insulator 550 is arranged on the surface of the insulator 550, and the conductor 560 is arranged on the surface of the insulator 550. do.

[0471] Furthermore, as shown in Figures 21A and 21B, oxide 530a, oxide 530b, conductor 5 The insulator 544 is placed between 42a and the conductor 542b and the insulator 580. It is preferable. Also, as shown in Figures 21A and 21B, the conductor 560 is within the insulator 550. A conductor 560a is provided on the side, and is provided so as to be embedded inside the conductor 560a. It is preferable to have a conductive material 560b. Also, as shown in Figures 21A and 21B The insulator 580, the conductor 560, and the insulator 550 are arranged on top of each other. It is preferable.

[0472] In the following, oxides 530a, 530b, and 530c are summarized. It is sometimes referred to as oxide 530.

[0473] Furthermore, in transistor 500, in the region where the channel is formed and in its vicinity, acid The following describes a configuration in which three layers of oxide 530a, oxide 530b, and oxide 530c are laminated. However, the present invention is not limited to this. For example, a single oxide 530b Layer, two-layer structure of oxide 530b and oxide 530a, two layers of oxide 530b and oxide 530c A layered structure or a stacked structure of four or more layers may be provided. Also, transistor 500 Although the conductor 560 is shown as a two-layer laminated structure, one aspect of the present invention is not limited thereto. It is not the case that it is fixed. For example, the conductor 560 may have a single-layer structure or a multi-layer structure of three or more layers. A layered structure is also acceptable. Furthermore, the transistor 500 shown in Figures 19 and 21A is just one example. It is not limited to that structure; an appropriate transistor can be used depending on the circuit configuration and driving method. stomach.

[0474] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductor 542a and The conductor 542b functions as either a source electrode or a drain electrode, respectively. Furthermore, the conductor 560 is sandwiched between the opening of the insulator 580 and the conductors 542a and 542b. It is formed to be embedded in the region. Conductor 560, Conductor 542a and Conductor 5 The placement of 42b is self-aligned with the opening of the insulator 580. In the inverter 500, the gate electrode is positioned between the source electrode and the drain electrode in a self-aligned manner. It can be positioned in this way. Therefore, the conductor 560 can be positioned with a margin. Since it can be formed without any issues, the occupied area of ​​transistor 500 can be reduced. This makes it possible to miniaturize and highly integrate semiconductor devices.

[0475] Furthermore, the conductor 560 is self-aligned in the region between conductor 542a and conductor 542b. As a result, the conductor 560 has a region that overlaps with the conductor 542a or the conductor 542b. It does not have. As a result, between the conductor 560 and the conductors 542a and 542b The parasitic capacitance can be reduced. Therefore, the switching speed of transistor 500 This improves the degree of performance and allows for high frequency characteristics.

[0476] The conductor 560 may function as the first gate (also called the top gate) electrode. Furthermore, the conductor 503 functions as a second gate (also called a bottom gate) electrode. There are cases where this is the case. In that case, the potential applied to conductor 503 is the same as the potential applied to conductor 560. By changing them independently and without linking them, the threshold voltage of transistor 500 is controlled. This can be done. In particular, by applying a negative potential to the conductor 503, the transistor 5 It becomes possible to increase the threshold voltage of 00 to greater than 0V and reduce the off-current. However, Therefore, applying a negative potential to conductor 503 is better than not applying a negative potential to conductor 560 The drain current can be reduced when the applied potential is 0V.

[0477] The conductor 503 is arranged so as to overlap with the oxide 530 and the conductor 560. Therefore, when a potential is applied to the conductor 560 and the conductor 503, the conductor 560 generates The electric field and the electric field generated from the conductor 503 connect, and channels are formed in the oxide 530. It can cover the gel-forming region. In this specification, the first gate electrode and the second gate The electric field of the electrode electrically surrounds the channel formation region, creating a transistor structure. This is called a surrounded channel (S-channel) structure.

[0478] Furthermore, the conductor 503 has the same configuration as the conductor 518, and the insulators 514 and 5 A conductor 503a is formed in contact with the inner wall of the 16 openings, and a conductor 503b is formed further inside. This has been done. In addition, in transistor 500, conductors 503a and 503b are combined. While a layered configuration is shown, the present invention is not limited to this. For example, Alternatively, the conductor 503 may be provided as a single layer or as a laminated structure of three or more layers.

[0479] Here, the conductor 503a diffuses impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. It is preferable to use a conductive material that has the function of suppressing (the above-mentioned impurities are less likely to permeate) It is difficult. Or, it inhibits the diffusion of oxygen (for example, at least one such as an oxygen atom or oxygen molecule). It is preferable to use a conductive material that has a functional property (i.e., one that is impermeable to the above-mentioned oxygen). In this specification, the function of suppressing the diffusion of impurities or oxygen means the above impurities or the above The function is to suppress the diffusion of one or all of the oxygen molecules.

[0480] For example, the conductor 503a has the function of suppressing the diffusion of oxygen, This can suppress the oxidation of b, which reduces its conductivity.

[0481] Furthermore, if the conductor 503 also functions as wiring, the conductor 503b may be tungsten or copper. Alternatively, it is preferable to use a highly conductive material, mainly composed of aluminum. In that case, the conductor 503a does not necessarily have to be provided. As illustrated, a laminated structure is also possible, for example, titanium or titanium nitride and the above conductive material. It may also be used as a laminate with other materials.

[0482] Insulators 520, 522, and 524 function as a second gate insulating film. It has.

[0483] Here, the insulator 524 in contact with the oxide 530 is more abundant than the oxygen that satisfies the stoichiometric composition. It is preferable to use an insulator containing a certain amount of oxygen. In other words, the insulator 524 contains an excess oxygen region. It is preferable that a region is formed. Such an insulator containing excess oxygen is converted to oxide 530. By providing them in contact, oxygen deficiencies in the oxide 530 are reduced, and the signal strength of the transistor 500 is improved. It can improve reliability.

[0484] As an insulator having an excess oxygen region, specifically, an acid in which some of the oxygen is removed by heating. It is preferable to use an oxide material. Oxides that desorb oxygen upon heating include TDS(Th In urinary desorption spectroscopy analysis, oxygen atoms were found to The amount of oxygen removed after conversion is 1.0 × 10⁻⁶ 18 atoms / cm 3 Preferably 1.0 ×10 19 atoms / cm 3 More preferably 2.0 × 10 19 ate / c m 3 The above, or 3.0 × 10 20 atoms / cm 3 The above describes the oxide film. The surface temperature of the film during the above TDS analysis is between 100°C and 700°C, or 100°C. A temperature range of ℃ to 400℃ is preferred.

[0485] Furthermore, the insulator having the above excess oxygen region and oxide 530 are brought into contact and heat treated, One or more of the following processes may be performed: Kuroh wave processing or RF processing. By doing so, water or hydrogen can be removed from oxide 530. For example, oxide At 530, a reaction occurs in which the VoH bond is broken, or in other words, "V O H→V O + The reaction H occurs, which can lead to dehydrogenation. Some of the hydrogen produced at this time is It combines with oxygen to form H2O and is removed from oxide 530 or the insulator near oxide 530. This may occur. Also, some of the hydrogen diffuses into conductors 542a and 542b. They may be captured (also known as gettering).

[0486] Furthermore, the above microwave processing is performed using, for example, an apparatus having a power supply that generates high-density plasma. Alternatively, it is preferable to use a device that has a power supply that applies RF to the substrate side. For example, acid By using a gas containing elements and employing a high-density plasma, high-density oxygen radicals are generated. This can be achieved by applying RF to the substrate side, generating high-density plasma. Efficiently introduce oxygen radicals into oxide 530 or an insulator near oxide 530. This can be done. Furthermore, the above microwave treatment is performed at a pressure of 133 Pa or higher, preferably 200 Pa. The Pa should be Pa or higher, more preferably 400 Pa or higher. For example, oxygen and argon are used as gases introduced into the apparatus, with an oxygen flow rate ratio (O2 The process should be carried out with (O2+Ar) content of 50% or less, preferably between 10% and 30%.

[0487] Furthermore, during the manufacturing process of transistor 500, the surface of oxide 530 is exposed. Therefore, heat treatment is preferable. This heat treatment is, for example, 100°C to 450°C. More preferably, the heating should be carried out at a temperature of 350°C to 400°C. The heat treatment is performed using nitrogen gas. Alternatively, an inert gas atmosphere, or an oxidizing gas at 10 ppm or more, 1% or more, The procedure should be carried out in an atmosphere containing 10% or more of the substance. For example, heat treatment is preferably carried out in an oxygen atmosphere. This supplies oxygen to oxide 530, thus eliminating oxygen deficiency (V O ) can be reduced. Furthermore, the heat treatment may be carried out under reduced pressure. Alternatively, the heat treatment may be carried out under nitrogen gas or After heat treatment in an active gas atmosphere, an oxidizing gas is added at 10 pJ to replenish the desorbed oxygen. The procedure may be carried out in an atmosphere containing 1% or more of the substance, or 10% or more of the substance. Alternatively, an oxidizing gas may be used. After heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more, then continuously The heat treatment may be carried out in a nitrogen gas or inert gas atmosphere.

[0488] Furthermore, by performing an oxygenation treatment on oxide 530, the oxygen deficiencies in oxide 530 are supplied. It is repaired by the oxygen that is used, in other words, "V O This promotes the reaction "+O → null". Furthermore, the oxygen supplied reacts with the hydrogen remaining in oxide 530. This allows the hydrogen to be removed as H2O (dehydrated). This eliminates oxidation. The hydrogen remaining in substance 530 recombines with the oxygen vacancy and V O Suppresses the formation of H It is possible.

[0489] Furthermore, if the insulator 524 has an excess oxygen region, the insulator 522 will have oxygen (for example, It has the function of suppressing the diffusion of oxygen atoms, oxygen molecules, etc. (making it difficult for the above-mentioned oxygen to permeate). This is preferable.

[0490] The insulator 522 has the function of suppressing the diffusion of oxygen and impurities, so the oxide 530 The oxygen present does not diffuse towards the insulator 520, which is preferable. Also, the conductor 503 This suppresses the reaction between the insulator 524 and the oxygen present in the oxide 530.

[0491] The insulator 522 is, for example, aluminum oxide, hafnium oxide, aluminum and haf Oxides containing nium (hafnium aluminate), tantalum oxide, zirconium oxide, Lead zirconate tane (PZT), strontium titanate (SrTiO3), or (Ba Insulators containing so-called high-k materials such as Sr)TiO3(BST) are used in single layers or multi-layered insulators. It is preferable to use it in layers. As transistors become smaller and more integrated, gate insulation Thinning the film can sometimes lead to problems such as leakage current. By using a high-k material as the insulator, the physical film thickness is maintained while the transistor movement This allows for a reduction in the gate potential during operation.

[0492] In particular, it has the function of suppressing the diffusion of impurities and oxygen (the above oxygen is less permeable). Using an insulator containing an oxide of either aluminum or hafnium, or both, which are insulating materials. It would be good to have one. As an insulator containing an oxide of aluminum, hafnium, or both, acid Aluminum oxide, hafnium oxide, aluminum and hafnium oxide (hafnium It is preferable to use materials such as aluminum oxide. When formed, the insulator 522 prevents the release of oxygen from the oxide 530 and the transistor 500 It functions as a layer that suppresses the incorporation of impurities such as hydrogen from the peripheral area into the oxide 530.

[0493] Alternatively, these insulators may contain, for example, aluminum oxide, bismuth oxide, or germanium oxide. M, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, acid Zirconium oxide may be added. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxide nitride, or silicon nitride may be laminated onto the edge body.

[0494] Furthermore, it is preferable that the insulator 520 is thermally stable. For example, silicon oxide and Silicon oxide nitride is suitable because it is thermally stable. Also, high-k material By combining an insulator with silicon oxide or silicon oxide-nitride, thermal stability can be achieved. This makes it possible to obtain an insulator 520 with a multilayer structure and a high relative permittivity.

[0495] Note that in the transistor 500 shown in Figures 21A and 21B, the second is a three-layer stacked structure. Insulators 520, 522, and 524 are shown as gate insulating films. However, the second gate insulating film may have a single layer, two layers, or a stacked structure of four or more layers. In that case, it is not limited to a laminated structure made of the same material, but can also be a laminated structure made of different materials. stomach.

[0496] Transistor 500 is an oxide semiconductor in oxide 530 including a channel formation region. It is preferable to use a functional metal oxide. For example, as oxide 530, In-M- Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryllium) Rium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, ra Tantum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium It is preferable to use one or more metal oxides selected from the above. In particular, oxide 53 In-M-Zn oxides that can be applied as 0 are CAAC-OS(C-Axis Alig ned Crystalline Oxide Semiconductor), CAC -OS(Cloud-Aligned Composite Oxide Semico It is preferable that the oxide 530 is an inductor. Also, as oxide 530, In-Ga oxide In-Zn oxide, In oxide, etc., may also be used.

[0497] Furthermore, it is preferable to use a metal oxide with a low carrier concentration for transistor 500. i. When lowering the carrier concentration of metal oxides, the impurity concentration in the metal oxides should be reduced. The defect level density should be lowered. In this specification, the impurity concentration is low and the defect level density is low. A low level density is referred to as high-purity intrinsic or substantially high-purity intrinsic. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, and nickel. Examples include silicone, etc.

[0498] In particular, the hydrogen contained in metal oxides reacts with the oxygen bonded to the metal atoms to form water. In some cases, oxygen vacancies may form in metal oxides. Also, water can form oxygen vacancies in oxide 530. When an element is present, the oxygen deficiency and hydrogen combine to form V O It may form H. O H is Donna It functions as a metal, and electrons, which are carriers, can be generated. Also, some of the hydrogen is metallic. It can combine with oxygen atoms to generate electrons, which are carriers. Therefore, water Transistors using metal oxides that contain many elements exhibit normally-on characteristics. Furthermore, hydrogen in metal oxides is easily moved by stresses such as heat and electric fields. If metal oxides contain a large amount of hydrogen, the reliability of transistors may deteriorate. In one embodiment of the invention, V in oxide 530 O To reduce H as much as possible, and to produce high-purity intrinsic It is preferable to make it substantially high-purity intrinsic. Thus, V O Metals with sufficiently reduced H To obtain an oxide, impurities such as water and hydrogen must be removed from the metal oxide (dehydration, dehydration). This is sometimes referred to as chemical treatment.) This involves supplying oxygen to the metal oxide to compensate for oxygen deficiencies. This (sometimes referred to as oxygenation treatment) is important. V O Sufficient impurities such as H By using metal oxides with reduced levels in the channel formation region of transistors, stable electricity can be produced. It is possible to impart specific properties.

[0499] Defects where hydrogen is present in an oxygen vacancy can function as donors for metal oxides. However, Therefore, it is difficult to quantitatively evaluate the defect. In metal oxides, - In some cases, evaluation is based on carrier concentration rather than concentration. Therefore, in this specification, etc., metal The parameter for the oxide is not the donor concentration, but rather the value assuming a state where no electric field is applied. Carrier concentration may be used. In other words, the "carrier concentration" described in this specification, etc., is "d It can sometimes be rephrased as "ener concentration."

[0500] Therefore, when using metal oxides in oxide 530, the amount of hydrogen in the metal oxide should be kept as low as possible. It is preferable that the amount is reduced. Specifically, in metal oxides, secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) The hydrogen concentration obtained is 1 × 10⁻⁶ 20 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5x10 18 atoms / cm 3 Less than, further Preferably 1 × 10 18 atoms / cm 3 Less than. Sufficiently reduced impurities such as hydrogen. By using the metal oxide in the channel formation region of the transistor, stable electrical characteristics are achieved. It can be granted.

[0501] Furthermore, when using a metal oxide for oxide 530, the band gap of the metal oxide is A semiconductor that is highly intrinsic (also called type I) or substantially intrinsic, and has a channel The carrier concentration of the metal oxide in the formation region is 1 × 10⁻⁶ 18 cm -3 It is preferable that it be less than , 1 x 10 17 cm -3 It is more preferable that it be less than 1 × 10 16 cm -3 less than It is even more preferable that there be a 1 × 10 13 cm -3 It is even more preferable that it be less than 1 ×10 12 cm -3 It is even more preferable that it be less than. Furthermore, the metallic acid in the channel-forming region There are no specific limitations on the lower limit of the carrier concentration of the compound, but for example, 1 × 10 -9 cm -3 It can be done this way.

[0502] Furthermore, when a metal oxide is used for oxide 530, conductors 542a and 542b are When oxide 530 comes into contact with the conductor 542a and conductor 54 It may diffuse into 2b, causing oxidation of conductors 542a and 542b. Conductor 542 As a and conductor 542b oxidize, the conductivity of conductor 542a and conductor 542b There is a high probability that it will decrease. Furthermore, the oxygen in oxide 530 is conductor 542a and conductor 542 The diffusion to b is due to conductors 542a and 542b absorbing oxygen in the oxide 530. This can be rephrased as "to do."

[0503] Furthermore, oxygen in oxide 530 diffuses into conductors 542a and 542b, Between the conductor 542a and the oxide 530b, and between the conductor 542b and the oxide 530b A different layer may be formed between the conductors 542a and 542b. Since it also contains a large amount of oxygen, it is presumed that this different layer has insulating properties. At this time, conductor 54 The three-layer structure of 2a or conductor 542b, the heterogeneous layer, and oxide 530b is a metal-insulator. -It can be considered a three-layer structure made of semiconductors, MIS (Metal-Insulator A diode that primarily uses an r-semiconductor (MIS) structure. It is sometimes called a joint structure.

[0504] The above-mentioned heterogeneous layer is formed between the conductor 542a and conductor 542b and the oxide 530b. It is not limited to this, for example, the different layers are conductor 542a and conductor 542b and oxide 5 When formed between 30c, or between conductor 542a and conductor 542b and oxide 530b In the case where a conductor 542a and conductor 542b are formed between the conductor and the oxide 530c, be.

[0505] In oxide 530, the metal oxide that functions as a channel-forming region is the band gap It is preferable to use one with a voltage of 2 eV or higher, preferably 2.5 eV or higher. By using metal oxides with a large bandgap, the off-current of the transistor can be reduced. It is possible.

[0506] Oxide 530 has oxide 530a beneath oxide 530b, so oxide 530a The diffusion of impurities from structures formed below to oxide 530b can be suppressed. Yes, it is possible. Also, by having oxide 530c on oxide 530b, oxide 530c is more Furthermore, the diffusion of impurities from the structure formed above to the oxide 530b can be suppressed. ru.

[0507] Furthermore, oxide 530 has a layered structure of multiple oxide layers with different atomic ratios of each metal atom. It is preferable to do so. Specifically, in the metal oxide used in oxide 530a, the constituent elements The atomic ratio of element M in the elementary oxide is the ratio of constituent elements in the metal oxide used in oxide 530b. It is preferable that it is greater than the atomic ratio of element M. Also, the metal oxide used in oxide 530a In the material, the atomic ratio of element M to In is the same as that of the metal oxide used in oxide 530b. It is preferable that the atomic ratio of element M to In is greater than that of In. Also, oxide 530b In the metal oxide used, the atomic ratio of In to element M is used in oxide 530a. It is preferable that the atomic ratio of In to element M in the metal oxide is greater than that of In. Oxide 530c is a metal oxide that can be used in oxide 530a or oxide 530b. The object can be used.

[0508] Specifically, for oxide 530a, the atomic ratio of In, Ga, and Zn is In:Ga:Z You can use metal oxides with n=1:3:4 or 1:1:0.5. Also, oxide 53 Assuming 0b, the atomic ratio of In, Ga, and Zn is In:Ga:Zn = 4:2:3, or 1 A 1:1 ratio of metal oxides should be used. Also, as oxide 530c, In, Ga, and Zn can be used. The atomic ratio of In:Ga:Zn is 1:3:4, and the atomic ratio of Ga to Zn is Ga:Zn You can use metal oxides with a ratio of 2:1 or Ga:Zn=2:5. Also, oxide 530 A specific example of a layered structure for c is when the atomic ratio of In, Ga, and Zn is In:Ga A layered structure of Zn=4:2:3 and In:Ga:Zn=1:3:4, and Ga and Zn The atomic ratio is Ga:Zn=2:1, and the atomic ratio of In, Ga, and Zn is In:Ga:Zn= The layered structure is 4:2:3, the atomic ratio of Ga to Zn is Ga:Zn=2:5, and In and Ga The atomic ratio of Zn is In:Ga:Zn=4:2:3 in the layered structure, and gallium oxide and In Examples include a layered structure with an atomic ratio of Ga and Zn of In:Ga:Zn=4:2:3. ru.

[0509] Furthermore, for example, the atomic ratio of In to element M in the metal oxide used in oxide 530a The numerical ratio is greater than the atomic ratio of In to element M in the metal oxide used in oxide 530b. In the small case, the oxide 530b is defined as having an atomic ratio of In, Ga, and Zn of In:Ga:Zn =5:1:6 or its vicinity, In:Ga:Zn=5:1:3 or its vicinity, In:G InGa-Zn oxide with a composition such as a:Zn=10:1:3 or nearby is used. It is possible.

[0510] In addition to the above, other compositions include, for example, oxide 530b, In:Zn=2: One of the following compositions: composition 1, composition In:Zn=5:1, composition In:Zn=10:1 Metal oxides having a composition in the vicinity of one can be used.

[0511] These oxides 530a, 530b, and 530c are given the above atomic ratio relationship. It is preferable to satisfy and combine these conditions. For example, oxide 530a and oxide 530c metal oxides having a composition of In:Ga:Zn=1:3:4 or a composition close to it, acid Iridium 530b is composed of a composition of 4.1 from In:Ga:Zn=4:2:3 and a composition near that. It is preferable to use a metal oxide having the above composition. The above composition is the oxide formed on the substrate. This indicates the atomic ratio within the material, or the atomic ratio in the sputtering target. Also, oxide 530 By increasing the ratio of In in the composition of b, the on-current or field effect of the transistor can be increased. It is suitable because it can increase mobility and other factors.

[0512] Furthermore, the energy at the lower end of the conduction band of oxide 530a and oxide 530c is It is preferable that the energy of b is higher than the energy of the lower end of the conduction band. In other words, oxide The electron affinity of oxide 530a and oxide 530c is smaller than the electron affinity of oxide 530b. This is preferable.

[0513] Here, at the joint of oxide 530a, oxide 530b, and oxide 530c, The energy levels at the lower end of the guide band change smoothly. In other words, oxide 530a, oxide The energy levels at the lower end of the conduction band at the junction of 530b and oxide 530c are continuous. It can also be said that it changes or becomes a continuous bond. In order to do this, oxide 530 At the interface between a and oxide 530b, and at the interface between oxide 530b and oxide 530c, the shape It is desirable to lower the defect level density of the resulting mixed layer.

[0514] Specifically, oxide 530a and oxide 530b, and oxide 530b and oxide 530c, By having a common element other than oxygen (as the main component), a mixed layer with a low defect level density is formed. It can be done. For example, if oxide 530b is In-Ga-Zn oxide, 530a and oxide 530c are In-Ga-Zn oxide, Ga-Zn oxide, and oxide Using gallium or similar materials would be a good idea.

[0515] In this case, the main carrier pathway is oxide 530b. Oxide 530a, oxide 5 By configuring 30c as described above, the interface between oxide 530a and oxide 530b, and oxidation The defect level density at the interface between material 530b and oxide 530c can be reduced. Therefore, the influence of interfacial scattering on carrier conduction is reduced, and transistor 500 has high On-current can be obtained.

[0516] On the oxide 530b, there is a conductor 542a that functions as a source electrode and a drain electrode. , and a conductor 542b are provided. The conductors 542a and 542b are, Aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tar ngsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium Choose from beryllium, indium, ruthenium, iridium, strontium, and lanthanum. The identified metal element, or an alloy containing the above-mentioned metal element, or a combination of the above-mentioned metal elements It is preferable to use a blended alloy, such as tantalum nitride, titanium nitride, or tungsten. Titanium nitrides containing titanium and aluminum, tantalum nitrides containing tantalum and aluminum, oxides Thenium, ruthenium nitride, oxides containing strontium and ruthenium, lanthanum and nickel It is preferable to use oxides containing Kel. Also, tantalum nitride, titanium nitride, titan Nitrides containing aluminum, nitrides containing tantalum and aluminum, ruthenium oxide , ruthenium nitride, oxides containing strontium and ruthenium, lanthanum and nickel Oxides are conductive materials that are resistant to oxidation, or materials that maintain their conductivity even when absorbing oxygen. Therefore, it is preferable. Furthermore, metal nitride films such as tantalum nitride are suitable for hydrogen or oxygen. It is preferable because it has barrier properties.

[0517] Furthermore, in Figures 21A and 21B, the conductors 542a and 542b are configured as a single-layer structure. As shown, a laminated structure of two or more layers is also possible. For example, a tantalum nitride film and tungsten It is good to laminate the films. Alternatively, a titanium film and an aluminum film may be laminated. Also, tang A two-layer structure with an aluminum film laminated on a stainless steel film, copper-magnesium-aluminum alloy. Two-layer structure with a copper film laminated on a film, two-layer structure with a copper film laminated on a titanium film, tungsten film A two-layer structure with a copper film laminated on top may also be used.

[0518] Furthermore, a titanium film or titanium nitride film, and aluminum layered on top of the titanium film or titanium nitride film. A three-layer structure consisting of a laminated titanium film or copper film, with a titanium film or titanium nitride film formed on top of it. A molybdenum film or molybdenum nitride film, and on the molybdenum film or molybdenum nitride film An aluminum film or copper film is laminated on top of it, and then a molybdenum film or molybdenum nitride film is placed on top of that. There are three-layer structures that form a film. Furthermore, there are permeable films containing indium oxide, tin oxide, or zinc oxide. A brightly conductive material may be used.

[0519] Furthermore, as shown in Figure 21A, the oxide 530 has conductor 542a (conductor 542b) and Regions 543a and 543b are formed at and near the interface as low-resistance regions. In some cases, region 543a functions as either the source region or the drain region. Furthermore, region 543b functions as either the source region or the drain region. Also, region 54 A channel-forming region is formed in the area sandwiched between region 3a and region 543b.

[0520] By providing the conductor 542a (conductor 542b) in contact with the oxide 530, The oxygen concentration in region 543a (region 543b) may decrease. Also, region 543a ( In region 543b), the metal contained in conductor 542a (conductor 542b) and oxide 530 A metal compound layer containing the component may be formed. In such cases, region 543a (region The carrier concentration in region 543b) increases, and region 543a (region 543b) becomes a low-resistance region. Yes.

[0521] The insulator 544 is provided so as to cover the conductors 542a and 542b, and the conductor The oxidation of 542a and conductor 542b is suppressed. At this time, the insulator 544 is oxide 5 It may be provided to cover the side of 30 and to be in contact with the insulator 524.

[0522] Insulator 544 includes hafnium, aluminum, gallium, yttrium, and zirconium. Umium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum Alternatively, a metal oxide containing one or more metals selected from magnesium, etc., can be used. This is possible. Furthermore, silicon nitride or silicon nitride can also be used as the insulator 544. It is possible to be there.

[0523] In particular, as the insulator 544, an oxide of either aluminum or hafnium, or both. The insulators include aluminum oxide, hafnium oxide, aluminum, and hafnium. It is preferable to use an oxide containing (hafnium aluminate), etc. In particular, hafnium Mualuminate has higher heat resistance than hafnium oxide film. Therefore, heat in subsequent processes In processing, it is preferable because it is less likely to crystallize. Note that conductor 542a and conductor 542 If b is an oxidation-resistant material, or if its conductivity does not significantly decrease even when it absorbs oxygen, then The 544 element is not a mandatory component. It can be designed appropriately depending on the desired transistor characteristics. stomach.

[0524] The presence of the insulator 544 allows water and other impurities such as hydrogen contained in the insulator 580 to be acidic. The diffusion of oxide 530c to oxide 530b via insulator 550 is suppressed. Yes, it is possible. Furthermore, the excess oxygen in the insulator 580 suppresses the oxidation of the conductor 560. It is possible.

[0525] The insulator 550 functions as the first gate insulating film. The insulator 550 is made of oxide 530 It is preferable to place it in contact with the inside (top surface and side surface) of c. The insulator 550 is as described above. Similar to insulator 524, an insulator that contains an excess of oxygen and releases oxygen upon heating It is preferable to use this method to form the product.

[0526] Specifically, silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon oxide containing excess oxygen silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, carbon, and Silicon oxide with added nitrogen and silicon oxide with voids can be used. Silicon oxide and silicon oxide-nitride are preferred because they are stable to heat.

[0527] An insulator that releases oxygen upon heating is designated as insulator 550, and the oxide 530c is placed on its upper surface. By being installed in contact with each other, the oxide 530b is transmitted from the insulator 550 through the oxide 530c. This allows for effective oxygen supply to the channel formation region. Also, similar to insulator 524. Preferably, the concentration of impurities such as water or hydrogen in the insulator 550 is reduced. The thickness of the edge body 550 is preferably between 1 nm and 20 nm.

[0528] Furthermore, in order to efficiently supply excess oxygen from the insulator 550 to the oxide 530, A metal oxide may be provided between the edge 550 and the conductor 560. The metal oxide is an insulating material. It is preferable to suppress oxygen diffusion from body 550 to conductor 560. By providing a metal oxide, the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. This means that the decrease in the amount of excess oxygen supplied to oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to excess oxygen can be suppressed. For the insulator 544, any material suitable for use in the insulator 544 may be used.

[0529] Furthermore, the insulator 550 may have a multilayer structure, similar to the second gate insulating film. As DISTRAs become smaller and more highly integrated, the gate insulating film becomes thinner, leading to leakage current and other issues. Because problems may occur, the insulator that functions as the gate insulating film is made of high-k material. By creating a laminated structure of a material and a thermally stable material, the physical film thickness is maintained while preventing traction. This allows for a reduction in gate potential during inverter operation. Furthermore, it offers thermal stability and a high dielectric constant. It can be made into a layered structure.

[0530] The conductor 560, which functions as the first gate electrode, has a two-layer structure in Figures 21A and 21B. As shown, it may be a single-layer structure or a laminated structure of three or more layers.

[0531] Conductor 560a contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules. Conductive material (such as N2O, NO, NO2, etc.) has the function of suppressing the diffusion of impurities such as copper atoms. It is preferable to use a material that contains oxygen (for example, oxygen atoms, oxygen molecules, etc.). It is preferable to use a conductive material that has the function of suppressing the diffusion of (1). Conductor 56 Because 0a has the function of suppressing oxygen diffusion, the oxygen contained in the insulator 550 This can suppress the oxidation of the conductor 560b and the resulting decrease in conductivity. Oxygen diffusion Examples of conductive materials that have the function of suppressing this include tantalum, tantalum nitride, and ruthenium. It is preferable to use um or ruthenium oxide. Also, as the conductor 560a, An oxide semiconductor applicable to oxide 530 can be used. In that case, conductor 560 By depositing b using the sputtering method, the electrical resistance of the conductor 560a is reduced, thus improving conductivity. It can be incorporated into the body. This is called an OC (Oxide Conductor) electrode. It is possible.

[0532] Furthermore, the conductive material 560b is a conductive material whose main components are tungsten, copper, or aluminum. It is preferable to use the material. Also, since the conductor 560b also functions as wiring, It is preferable to use a highly conductive material. For example, tungsten, copper, or aluminum. A conductive material mainly composed of um can be used. In addition, the conductor 560b has a laminated structure. This may also be done, for example, as a laminated structure of titanium or titanium nitride and the above-mentioned conductive material. stomach.

[0533] The insulator 580 is provided on the conductors 542a and 542b via the insulator 544. It is possible. The insulator 580 preferably has an excess oxygen region. For example, insulator 58 As 0, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, fluorine silicon oxide with added carbon, silicon oxide with added carbon, and silicon oxide with added nitrogen. It is preferable that the material contains silicon, porous silicon oxide, or resin. In particular, acid Silicon oxide and silicon oxide-nitride are preferred because they are thermally stable. In particular, silicon oxide Silicon oxide having voids can easily form excess oxygen regions in subsequent processes. This is preferable because it allows for this.

[0534] The insulator 580 preferably has an excess oxygen region. Oxygen is released upon heating. By placing the insulator 580 in contact with the oxide 530c, the oxygen in the insulator 580 is oxidized. It can be efficiently supplied to the oxide 530 through material 530c. It is preferable that the concentration of impurities such as water or hydrogen in 80 is reduced.

[0535] The opening in the insulator 580 is formed superimposed on the region between the conductor 542a and the conductor 542b. This allows the conductor 560 to pass through the opening of the insulator 580, and the conductor 542a and the conductor. It is formed in a way that it is embedded in the region sandwiched between 542b.

[0536] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but the conductor 5 It is necessary to prevent the conductivity of 60 from decreasing. To that end, the film thickness of conductor 560 is increased. As a result, the conductor 560 can have a shape with a high aspect ratio. In this embodiment, In order to embed the body 560 into the opening of the insulator 580, the conductor 560 is aspect ratio Even when forming a shape with a high ratio, it is possible to form the conductive material 560 without causing it to collapse during the process. Cut.

[0537] The insulator 574 is located on the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 550. It is preferable that it be provided in contact with the insulator 574. This allows for the creation of excess oxygen regions in the insulator 550 and the insulator 580. Oxygen can be supplied to the oxide 530 from the excess oxygen region.

[0538] For example, as insulator 574, hafnium, aluminum, gallium, yttrium, Zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium Metal oxides containing one or more metals selected from elements such as cilium can be used. .

[0539] In particular, aluminum oxide has high barrier properties and is suitable for thin films of 0.5 nm to 3.0 nm. However, the diffusion of hydrogen and nitrogen can be suppressed. Therefore, the sputtering method The aluminum oxide film formed using this method serves as both an oxygen source and a barrier against impurities such as hydrogen. It can also function as a membrane.

[0540] Furthermore, it is preferable to provide an insulator 581 that functions as an interlayer film on top of the insulator 574. i. Insulator 581, like insulator 524, has an impurity concentration of water or hydrogen in the film. It is preferable that it be reduced.

[0541] Furthermore, openings formed in insulators 581, 574, 580, and 544 Conductors 540a and 540b are placed in the opening. 0b is provided opposite the conductor 560. Conductors 540a and 540b are, The configuration is the same as that of conductors 546 and 548, which will be described later.

[0542] An insulator 582 is provided on the insulator 581. The insulator 582 is designed to absorb oxygen and hydrogen. In contrast, it is preferable to use a barrier material. Therefore, the insulator 582 is an insulating material. The same material as the edge 514 can be used. For example, aluminum oxide can be used for the insulator 582. It is preferable to use metal oxides such as nium, hafnium oxide, and tantalum oxide.

[0543] In particular, aluminum oxide is a source of oxygen and hydrogen, which can cause variations in the electrical properties of transistors. It has a high barrier effect that prevents both water and other impurities from passing through the film. Aluminum oxide is susceptible to hydrogen, moisture, and other impurities during and after the transistor manufacturing process. This prevents contamination of the transistor 500 with pure material. This can suppress the release of oxygen from the oxides that make up the transistor 5. It is suitable for use as a protective film for 00.

[0544] Furthermore, an insulator 586 is provided on the insulator 582. The insulator 586 is an insulator Similar materials to 320 can be used. In addition, these insulators have a relatively low dielectric constant. By applying a suitable material, parasitic capacitance between wires can be reduced. For example, As the edge element 586, silicon oxide film or silicon oxide nitride film can be used.

[0545] Also, insulator 520, insulator 522, insulator 524, insulator 544, insulator 580, The edge 574, insulator 581, insulator 582, and insulator 586 contain a conductor 546, and Conductors such as 548 are embedded within.

[0546] Conductors 546 and 548 are connected to the capacitive element 600, the transistor 500, or the transistor. It functions as a plug or wiring to connect to the inverter 300. Conductor 546, and The conductor 548 can be provided using the same material as the conductors 328 and 330. Cut.

[0547] Furthermore, after the transistor 500 is formed, an opening is formed to surround the transistor 500. An insulator with high barrier properties against hydrogen or water may be formed to cover the opening. By encasing the transistor 500 in the aforementioned highly barrier-type insulator, moisture from the outside is prevented... And it can prevent hydrogen from entering. Or, multiple transistors 500 They may be encapsulated together in an insulator with high barrier properties against hydrogen or water. When forming an opening to surround the transistor 500, for example, an insulator 514 or an insulator An opening is formed that reaches 522, and the above-mentioned bar is made to contact the insulator 514 or the insulator 522. By forming a highly reflective insulator, it can also serve as part of the manufacturing process for transistor 500. Therefore, it is suitable. Furthermore, an insulator with high barrier properties against hydrogen or water is, for example, The same material as insulator 522 can be used.

[0548] Next, a capacitive element 600 is provided above the transistor 500. 600 has a conductor 610, a conductor 620, and an insulator 630.

[0549] Furthermore, a conductor 612 may be provided on the conductor 546 and the conductor 548. Conductor 6 12 functions as a plug or wire for connecting to transistor 500. Conductor 610 functions as an electrode for the capacitive element 600. Note that the conductor 612 and the conductive Body 610 can be formed simultaneously.

[0550] Conductors 612 and 610 contain molybdenum, titanium, tantalum, and tungsten. A metal film containing elements selected from aluminum, copper, chromium, neodymium, and scandium. or metal nitride films containing the above-mentioned elements (tantalum nitride film, titanium nitride film, molybdenum nitride film) Butene film, tungsten nitride film, etc. can be used. Alternatively, indium tin oxide, Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium Apply conductive materials such as zinc oxide and indium tin oxide with added silicon dioxide. It is also possible.

[0551] In Figure 19, the conductors 612 and 610 are shown as having a single-layer structure, but the configuration is not limited to this. It is not limited to a single layer, and a laminated structure of two or more layers is also acceptable. For example, a conductor with barrier properties and a highly conductive material. A conductor with barrier properties between it and the conductor, and a conductor with high conductivity that has high adhesion to the conductor. A conductive material may be formed.

[0552] The conductor 620 is provided so as to overlap with the conductor 610 via the insulator 630. The conductor 620 uses a conductive material such as a metal material, an alloy material, or a metal oxide material. This is possible. High-melting-point materials such as tungsten and molybdenum that offer both heat resistance and conductivity. It is preferable to use a conductive material, and it is particularly preferable to use tungsten. When forming it simultaneously with other structures, low-resistance metallic materials such as Cu (copper) or Al (aluminium) are used. You can use (Mu), etc.

[0553] An insulator 650 is provided on the conductor 620 and the insulator 630. 0 can be provided using the same material as insulator 320. Also, insulator 650 is It may also function as a flattening film that covers the uneven surface below it.

[0554] By using this structure, semiconductor devices using transistors having oxide semiconductors This suppresses fluctuations in electrical characteristics and improves reliability. Alternatively, oxidation In semiconductor devices using transistors with physical semiconductors, miniaturization or high integration is achieved. It is possible.

[0555] Next, we will explain another example of an OS transistor configuration, as shown in Figures 19 and 20. Figures 22A and 22B are modified versions of transistor 500 shown in Figures 21A and 21B. Figure 22A is a cross-sectional view of transistor 500 in the channel length direction, and Figure 22B is a cross-sectional view of transistor 500 in the channel length direction. This is a cross-sectional view of the lunger 500 in the channel width direction. Note that the structure shown in Figures 22A and 22B The component is a transistor 300, and other transistors in the semiconductor device according to one aspect of the present invention. This can also be applied.

[0556] The transistor 500 in the configuration shown in Figures 22A and 22B consists of insulator 402 and insulator 40 The presence of 4 differs from the transistor 500 with the configuration shown in Figures 21A and 21B. An insulator 552 is provided in contact with the side surface of the conductor 540a, and in contact with the side surface of the conductor 540b The insulator 552 is provided in the transistor 500 with the configuration shown in Figures 21A and 21B. They are different. Furthermore, the absence of the insulator 520 is a difference from the configuration shown in Figures 21A and 21B. It is different from the Zista 500.

[0557] The transistor 500 in the configuration shown in Figures 22A and 22B has an insulator 40 on top of the insulator 512. 2 is provided. In addition, an insulator 404 is provided on the insulator 574 and on the insulator 402. It is being done.

[0558] In the transistor 500 with the configuration shown in Figures 22A and 22B, insulator 514, insulator 51 6. Insulators 522, 524, 544, 580, and 574 are provided. It is attached, and the insulator 404 covers them. In other words, the insulator 404 is , the top surface of insulator 574, the side surface of insulator 574, the side surface of insulator 580, the side surface of insulator 544 , side of insulator 524, side of insulator 522, side of insulator 516, side of insulator 514 , and they come into contact with the upper surface of the insulator 402. As a result, the oxide 530 etc. comes into contact with the insulator 404 It is isolated from the outside by the insulator 402.

[0559] Insulators 402 and 404 contain hydrogen (for example, hydrogen atoms, hydrogen molecules, etc.) It is preferable that the insulator 402 and have a high function of suppressing the diffusion of water molecules. As the insulator 404, a material with high hydrogen barrier properties is silicon nitride or silicon nitride oxide. It is preferable to use a condenser. This suppresses the diffusion of hydrogen and other elements into oxide 530. Therefore, it is possible to suppress the decline in the characteristics of transistor 500. Therefore, the reliability of a semiconductor device according to one embodiment of the present invention can be improved.

[0560] Insulator 552 is insulator 581, insulator 404, insulator 574, insulator 580, and insulator It is provided in contact with the edge 544. The insulator 552 has the function of suppressing the diffusion of hydrogen or water molecules. It is preferable to have the following. For example, as the insulator 552, a material with high hydrogen barrier properties is Insulators such as silicon nitride, aluminum oxide, or silicon nitride oxide can be used. Preferred. In particular, since silicon nitride is a material with high hydrogen barrier properties, it is used as an insulator 552. It is preferable to use it in this way. By using a material with high hydrogen barrier properties as the insulator 552, Impurities such as water or hydrogen pass from the insulator 580, etc., through the conductors 540a and 540b. This suppresses diffusion into the oxide 530. Also, it is contained in the insulator 580. This makes it possible to suppress the absorption of oxygen by the conductors 540a and 540b. As described above, the reliability of a semiconductor device according to one aspect of the present invention can be improved.

[0561] Figure 23 shows the configuration of transistors 500 and 300 as shown in Figures 22A and 22B. This is a cross-sectional view showing an example of the configuration of a semiconductor device when it is made as is. On the side surface of the conductor 546 An insulator 552 is provided.

[0562] Furthermore, the transistor 500 shown in Figures 22A and 22B may be a transistor depending on the situation. The configuration may be changed. For example, transistor 500 in Figures 22A and 22B is an example of a change. This can be expressed as the transistor shown in Figure 24. Figure 24A shows the transistor's casing. Figure 24B is a cross-sectional view in the direction of the channel length, and Figure 24B is a cross-sectional view in the direction of the transistor's channel width. The transistors shown in Figures 24A and 24B have oxide 530c, oxide 530c1 and oxide It differs from the transistors shown in Figures 22A and 22B in that it has a two-layer structure of material 530c2.

[0563] Oxide 530c1 is on the top surface of insulator 524, the side surface of oxide 530a, and oxide 530b. The top surface and sides, the sides of the conductors 542a and 542b, the sides of the insulator 544, and the insulation The oxide 530c2 is in contact with the side surface of the edge 580. The oxide 530c2 is in contact with the insulator 550.

[0564] For example, In-Zn oxide can be used as oxide 530c1. When the oxide 530c has a single-layer structure, the substance 530c2 is used for the oxide 530c. Materials similar to those that can be used can be used. For example, as oxide 530c2, n:Ga:Zn=1:3:4 [atomic ratio], Ga:Zn=2:1 [atomic ratio], or G A metal oxide with an atomic ratio of a:Zn = 2:5 can be used.

[0565] By making oxide 530c a two-layer structure of oxide 530c1 and oxide 530c2, This allows for a higher on-current of the transistor compared to a single-layer structure of oxide 530c. Therefore, transistors can be applied, for example, as power MOS transistors. This is possible. Note that the oxide 530c present in the transistor with the configuration shown in Figures 21A and 21B Furthermore, it can be made into a two-layer structure of oxide 530c1 and oxide 530c2.

[0566] The transistor configuration shown in Figures 24A and 24B is, for example, the same as the transistor shown in Figures 19 and 20. It can be applied to transistor 300. Also, for example, transistor 300 is as described above. As described above, the memory cell array C included in the arithmetic circuit MAC1 etc. described in the above embodiment This can be applied to transistor Tr12 of A, etc. (See Figures 24A and 24B) The transistors are transistors 300, 500, and are part of a semiconductor device according to one aspect of the present invention. It can also be applied to other transistors.

[0567] Figure 25 shows that transistor 500 has the same transistor configuration as shown in Figure 21A, and the transistor Example of semiconductor device configuration when the TA300 has the transistor configuration shown in Figure 24A. This is a cross-sectional view showing the same configuration as in Figure 23, where an insulator 552 is provided on the side surface of the conductor 546. The configuration is as shown in Figure 25, a semiconductor device according to one aspect of the present invention is a transistor Both transistor 300 and transistor 500 are OS transistors, while transistor 300 Each of the transistors 500 can be configured differently.

[0568] Next, we will describe the capacitive elements that can be applied to the semiconductor devices shown in Figures 19 and 20.

[0569] Figures 26A to 26C show one of the capacitive elements 600 that can be applied to the semiconductor device shown in Figure 19. As an example, the capacitive element 600A is shown. Figure 26A is a top view of the capacitive element 600A. Yes, Figure 26B is a perspective view showing a cross-section of the capacitive element 600A along the dashed line L3-L4. Yes, Figure 26C is a perspective view showing a cross-section of the capacitive element 600A along the dashed line W3-L4. be.

[0570] Conductor 610 functions as one of a pair of electrodes of capacitive element 600A, and conductor 620 is It functions as the other electrode of the pair of electrodes of the capacitive element 600A. In addition, the insulator 630 is a pair It functions as a dielectric material sandwiched between electrodes.

[0571] Examples of insulator 630 include silicon oxide, silicon oxide nitride, and silicon oxide nitride. Silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, nitrile Aluminum oxide, hafnium oxide, hafnium oxide nitride, hafnium oxide nitride, hafnium nitride Materials such as nium and zirconium oxide can be used, and they can be provided in layers or as a single layer.

[0572] Furthermore, for example, the insulator 630 may contain materials with high dielectric strength, such as silicon oxide nitride. A laminated structure with a high-dielectric constant (high-k) material may be used. With this configuration, a capacitive element 600A can ensure sufficient capacitance by having an insulator with a high dielectric constant (high-k). By having an insulator with high dielectric strength, the dielectric strength is improved, and the electrostatic discharge of the 600A capacitive element is increased. It can suppress destruction.

[0573] Furthermore, as an insulator of high-dielectric constant (high-k) materials (materials with a high relative permittivity), Having gallium, hafnium oxide, zirconium oxide, aluminum and hafnium Oxides, aluminum and hafnium-containing oxides and nitrides, silicon and hafnium Oxides having silicon and hafnium, or silicon and ha Examples include nitrides containing humium.

[0574] Alternatively, the insulator 630 may be, for example, aluminum oxide, hafnium oxide, or tantalum oxide. Zirconium oxide, lead zirconate titanate (PZT), strontium titanate (Sr Insulation containing high-k materials such as TiO3 or (Ba,Sr)TiO3(BST). The material may be used in a single layer or in a laminated form. For example, when the insulator 630 is laminated, zir oxide A three-layer laminate formed in sequence of conium, aluminum oxide, and zirconium oxide, Zirconium oxide, aluminum oxide, zirconium oxide, aluminum oxide, A four-layer laminate formed in sequence can be used. Compounds containing um and zirconium may also be used. Miniaturization of semiconductor devices, and As integration progresses, the thinning of the dielectrics used in gate insulators and capacitive elements will lead to... Problems such as leakage current in transistors and capacitive elements may occur. Gate insulator, and By using a high-k material as an insulator that functions as a dielectric in a capacitive element, While maintaining film thickness, the gate potential during transistor operation is reduced, and the capacitance of the capacitive element is reduced. It will become possible to secure it.

[0575] The capacitive element 600 is located below the conductor 610, between the conductor 546 and the conductor 548. They are electrically connected. Conductors 546 and 548 are connected to another circuit element. It functions as a plug or wiring. Also, in Figures 26A to 26C, the conductor 546 and Conductor 548 and conductor 540 are collectively referred to as conductor 540.

[0576] Furthermore, in Figures 26A to 26C, in order to clearly show the figures, conductor 546 and conductor 5 The insulator 586 in which 48 is embedded, and the insulating covering the conductor 620 and the insulator 630 The term "edge body 650" is omitted.

[0577] Note that the capacitive element 600 shown in Figures 19, 20, 26A to 26C is of the planar type. However, the shape of the capacitive element is not limited thereto. For example, the capacitive element 600 is shown in Figures 27A to A cylindrical capacitive element 600B, as shown in Figure 27C, may also be used.

[0578] Figure 27A is a top view of the capacitive element 600B, and Figure 27B shows the dashed line of the capacitive element 600B. Figure 27C shows a cross-sectional view of L3-L4, and Figure 27C shows the dashed line W3-L4 of the capacitive element 600B. This is a perspective view showing a cross-section.

[0579] In Figure 27B, the capacitive element 600B is an insulator 58 in which the conductor 540 is embedded. 6 includes an insulator 631 on top of 6, an insulator 651 having an opening, and functions as one of a pair of electrodes. It has a conductor 610 and a conductor 620 that functions as the other of a pair of electrodes.

[0580] Furthermore, in Figure 27C, to make the diagram clearer, insulator 586, insulator 650, and insulation Body 651 and are omitted.

[0581] For example, the same material as that used for insulator 586 can be used for insulator 631.

[0582] Furthermore, the insulator 631 is embedded with a conductor 611 so as to be electrically connected to the conductor 540. It is embedded. Conductor 611 is made of the same material as, for example, conductor 330 and conductor 518. It can be used.

[0583] For example, the same material as that used for insulator 586 can be used for insulator 651.

[0584] Furthermore, as mentioned above, the insulator 651 has an opening, and this opening is superimposed on the conductor 611. They are doing it.

[0585] The conductor 610 is formed at the bottom and side of the opening. 10 is superimposed on the conductor 611 and is electrically connected to the conductor 611.

[0586] Furthermore, the method for forming the conductor 610 is to create openings in the insulator 651 by etching or the like. The opening is formed, and then a conductive film 610 is deposited by sputtering, ALD, or the like. After that, CMP (Chemical Mechanical Polishing) According to the law, etc., a conductor 610 is deposited on the opening, and a film is deposited on the insulator 651. The conductive material 610 should be removed.

[0587] The insulator 630 is located on the insulator 651 and on the forming surface of the conductor 610. The insulator 630 functions as a dielectric sandwiched between a pair of electrodes in the capacitive element.

[0588] The conductor 620 is formed on the insulator 630 such that it fills the opening in the insulator 651. Yes, they are.

[0589] The insulator 650 is formed to cover the insulator 630 and the conductor 620.

[0590] The cylindrical capacitive element 600B shown in Figures 27A to 27C is a planar capacitive element The capacitance value can be increased to 600A. Therefore, for example, in the above implementation... As explained in the form, by applying the 600B capacitive element as capacitance C1, capacitance C2, etc. This allows the voltage between the terminals of the capacitance to be maintained for a long period of time.

[0591] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0592] (Embodiment 4) In this embodiment, it can be used in the OS transistor described in the above embodiment. CAC-OS (Cloud-Aligned Composite) is a metal oxide. Oxide Semiconductor), and CAAC-OS(c-axis Al Structure of igned Crystalline Oxide Semiconductor Let me explain about the formation.

[0593] <Composition of metal oxides> CAC-OS or CAC-metal oxide refers to materials that have a conductive function in some parts. In addition, a portion of the material has insulating properties, while the material as a whole has semiconductor properties. Furthermore, CAC-OS or CAC-metal oxide is used in the active layer of the transistor. When used, the conductive function is the function of allowing electrons (or holes) that act as carriers to flow, and is an insulating material. The function of a material is to prevent the flow of electrons, which act as carriers. This is the function of both conductivity and insulation. By making the two functions work complementaryly, it enables a switching function (On / Off). This function can be imparted to CAC-OS or CAC-metal oxide. In CAC-OS or CAC-metal oxide, the respective functions are separated. By doing so, the functions of both can be maximized.

[0594] Furthermore, CAC-OS or CAC-metal oxide has conductive and insulating properties. It has regions. The conductive region has the conductive function described above, and the insulating region has the insulating function described above. It has the function of [this]. Furthermore, within the material, the conductive region and the insulating region are at the nanoparticle level. In some cases, they are separated by a rib. Also, conductive regions and insulating regions are located within the material. They may be unevenly distributed. Furthermore, the conductive regions appear blurred around the edges and connected in a cloud-like pattern. There are cases where this occurs.

[0595] Furthermore, in CAC-OS or CAC-metal oxide, the conductive region and the insulating region The marginal region is defined as being between 0.5 nm and 10 nm, preferably between 0.5 nm and 3 nm. These particles may be dispersed in the material at the following sizes.

[0596] Furthermore, CAC-OS or CAC-metal oxide have different band gaps. It is composed of the following components. For example, CAC-OS or CAC-metal oxid e consists of a component with a wide gap due to the insulating region and a narrow gap due to the conductive region. - It consists of a component having a gap. In this configuration, when the carrier is flowed, In components with a narrow gap, mainly carriers flow. Also, the narrow gap The components possessed act complementaryly with components having a wide gap, and have a narrow gap. Carriers also flow to components with a wide gap in conjunction with the components. Therefore, the above CA C-OS or CAC-metal oxide is used in the channel formation region of the transistor. In this case, the transistor has a high current driving force in the ON state, that is, a large ON current, and High field-effect mobility can be obtained.

[0597] In other words, CAC-OS or CAC-metal oxide is a matrix composite material. (matrix composite), or metal matrix composite (metal m It can also be called an atrix composite.

[0598] <Structure of metal oxides> Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include CAAC-OS and polycrystalline oxide semiconductors. , nc-OS(nanocrystalline oxide semiconductor or), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like) Examples include oxide semiconductors and amorphous oxide semiconductors.

[0599] Furthermore, when focusing on the crystal structure, oxide semiconductors may be classified differently from those mentioned above. Here, we will explain the classification of crystal structures in oxide semiconductors using Figure 28A. To proceed. Figure 28A shows an oxide semiconductor, typically IGZO (containing In, Ga, and Zn). This is a diagram illustrating the classification of the crystal structures of metal oxides.

[0600] As shown in Figure 28A, IGZO can be broadly divided into Amorphous and, They are classified into Crystalline and Crystal. Amorphous includes completely amorphous molecules. Furthermore, within Crystalline, there is CAAC (c-axis aligned). crystalline), nc (nanocrystalline), and CAC (C This includes loud-Aligned Composite. The classification of INE includes single crystal, polycrystal, and c Completely amorphous elements are excluded. Also, within Crystal, This includes single crystals and polycrystals.

[0601] The structures within the thick frame shown in Figure 28A are Amorphous and Crystal. It is an intermediate state between al (crystal) and a new boundary region (New crystallin This structure belongs to the e phase. This structure is Amorphous and Cryst It lies in the boundary region between al and Amor. In other words, this structure is energetically unstable. To put it another way, it's a structure that is completely different from phous (amorphous) or crystal (crystalline). It is possible.

[0602] The crystal structure of the film or substrate can be determined by X-ray diffraction (XRD). It can be evaluated using an ion image. Here, quartz glass and Crystal XRD of IGZO (also called crystalline IGZO) having a crystal structure classified as ine The vectors are shown in Figures 28B and 28C. Figure 28B shows quartz glass, and Figure 28C shows crystalline glass. This is the XRD spectrum of IGZO. Note that the composition of crystalline IGZO shown in Figure 28C is I The ratio of n:Ga:Zn is approximately 4:2:3 [atomic ratio]. Also, the crystalline IG shown in Figure 28C The thickness of ZO is 500 nm.

[0603] As shown by the arrow in Figure 28B, the shape of the peak in the XRD spectrum of quartz glass is approximately It is symmetrical. On the other hand, as shown by the arrow in Figure 28C, crystalline IGZO is XRD spectrometer The peak of the XRD spectrum is asymmetrical. This clearly indicates the presence of crystals. In other words, the shape of the peaks in the XRD spectrum is A shape cannot be called amorphous unless it is symmetrical. Note that Figure 28C shows 2θ =31°, or clearly indicate the crystal phase (IGZO crystal phase) in its vicinity. The reason why the peaks in the XRD spectrum are asymmetrical is due to the crystal phase. It is presumed to be caused by (microcrystals).

[0604] Specifically, in the XRD spectrum of crystalline IGZO shown in Figure 28C, 2θ=3 It has a peak at 4° or nearby. Also, the microcrystals have a peak at 2θ=31° or nearby. It has a peak. When evaluating an oxide semiconductor film from an X-ray diffraction pattern, as shown in Figure 28C. In this case, the spectral width at angles lower than the peak at 2θ = 34° or nearby becomes wider. This is because the oxide semiconductor film contains microcrystals with a peak at or near 2θ = 31°. This suggests that it exists.

[0605] Furthermore, the crystalline structure of the film is determined by nano-beam electron diffraction (NBED). Diffraction patterns observed by tron ​​diffraction (micro-electron diffraction) It can be evaluated using the pattern (also called a pattern). IGZ film deposited at room temperature. The diffraction pattern of the O film is shown in Figure 28D. Note that the IGZO film shown in Figure 28D is In:Ga Using an oxide target with an atomic ratio of Zn=1:1:1, the sputtering method is applied to Therefore, a film is formed. In addition, in the ultra-micro electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm. It was carried out.

[0606] As shown in Figure 28D, the diffraction pattern of the IGZO film deposited at room temperature shows a halo, rather than A spot-like pattern is observed. Therefore, the IGZO film deposited at room temperature is in a crystalline state. It is neither an amorphous state nor a non-amorphous state; it is an intermediate state, and it cannot be concluded that it is an amorphous state. It is presumed that it will not be possible.

[0607] CAAC-OS has c-axis orientation and multiple nanocrystals are linked in the ab-plane direction. It has a crystalline structure that is linked and distorted. Note that distortion refers to the linkage between multiple nanocrystals. Within a region, between a region with a aligned grid arrangement and another region with a aligned grid arrangement, the grid arrangement This refers to the point where the orientation has changed.

[0608] Nanocrystals are based on a hexagonal shape, but they are not necessarily regular hexagons; they can also be non-regular hexagonal. Furthermore, the distortion may have a grid arrangement such as pentagons and heptagons. Furthermore, in CAAC-OS, even near strain, clear grain boundaries (grain bounds) are present. It is not possible to confirm the grain boundaries (also known as dally). In other words, due to the distortion of the lattice arrangement, the grain boundaries It can be seen that the formation is suppressed. This is because CAAC-OS is in the ab plane direction The arrangement of oxygen atoms is not dense, and the bond distance between atoms changes due to the substitution of metal elements. This is thought to be because distortion can be tolerated by processes such as transformation.

[0609] Furthermore, crystal structures in which clear grain boundaries can be observed are known as multi-grain structures. It is called a polycrystal. The grain boundaries become recombination centers and carriers. This can lead to a decrease in the transistor's on-current or a decrease in its field-effect mobility. The possibility is high. Therefore, CAAC-OS, in which no clear grain boundaries can be confirmed, is a transistor. It is one of the crystalline oxides having a crystal structure suitable for semiconductor layers. (Note: CAAC-OS) A configuration having Zn is preferred for the structure. For example, In-Zn oxide and In- Ga-Zn oxide is preferred because it can suppress the generation of grain boun...

Claims

1. Image data containing the circuit configuration is input as input data. A search system that searches for data that matches or is similar to the aforementioned input data, The input data is converted into a first netlist using a neural network. The first netlist is compared with multiple netlists stored in the first database. A search system that, when a second netlist matching or similar to the first netlist is found, reads and outputs image data corresponding to the second netlist from a second database.

2. The input data is a document file containing the circuit configuration. A search system that searches for data that matches or is similar to the aforementioned input data, The input data is converted into a first netlist using a neural network. The first netlist is compared with multiple netlists stored in the first database. A search system that, when a second netlist matching or similar to the first netlist is found, reads and outputs the document file corresponding to the second netlist from a second database.

3. In claim 1, Create multiple netlists randomly, A search system that trains a neural network using multiple image data created based on the aforementioned multiple netlists.

4. In claim 2, Create multiple netlists randomly, A search system that trains the neural network using multiple document files created based on the aforementioned multiple netlists.

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