Semiconductor equipment

Abstract

To provide a highly reliable semiconductor device which prevents yield deterioration caused by ESD damage.SOLUTION: A semiconductor device has: a gate electrode layer; a gate insulation layer on the gate electrode layer; an oxide insulation layer on the gate insulation layer; an oxide semiconductor layer which contacts a surface of the oxide insulation layer and overlaps the gate electrode layer; and a source electrode layer and a drain electrode layer which are electrically connected with the oxide semiconductor layer. The gate insulation layer is composed to include a nitrogen-containing silicon film; and the oxide insulation layer contains one or a plurality of metal elements selected from constituent elements of the oxide semiconductor layer; and a film thickness of the gate insulation layer is thicker than that of the oxide insulation layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The inventions disclosed herein relate to semiconductor devices and methods for manufacturing semiconductor devices.

[0002] In this specification, a semiconductor device refers to a device that can function by utilizing semiconductor properties. This refers to all types of semiconductor devices, including electro-optical devices, light-emitting display devices, semiconductor circuits, and electronic equipment. be. [Background technology]

[0003] A technology for constructing transistors using semiconductor thin films formed on a substrate having an insulating surface. It is attracting attention. The transistor is used in integrated circuits (ICs) and image display devices (also simply as display devices). It is widely applied to electronic devices such as those shown. Semiconductors applicable to transistors Silicon-based semiconductor materials are widely known as thin film materials, but other materials include oxide semiconductors. Conductors are attracting attention.

[0004] For example, using zinc oxide or an In-Ga-Zn based oxide semiconductor as the oxide semiconductor. Techniques for fabricating transistors have been disclosed (see Patent Documents 1 and 2). [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2007-123861 [Patent Document 2] Japanese Patent Publication No. 2007-96055 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] When mass-producing a semiconductor device using an oxide semiconductor (hereinafter abbreviated as mass production), considering development costs and development speed, it is desirable to use a transistor configuration, process conditions, or production equipment using silicon-based semiconductor materials such as amorphous silicon or polycrystalline silicon, which are mass production technologies that have been put into practical use.

[0007] However, the carrier generation mechanism of oxide semiconductors is significantly different from that of silicon-based semiconductor materials, and the physical properties of oxide semiconductors greatly affect the characteristics or reliability of transistors.

[0008] In particular, the gate insulating layer used for silicon-based semiconductor materials does not have a configuration that sufficiently satisfies the interface characteristics with the oxide semiconductor. Therefore, the development of a gate insulating layer suitable for semiconductor devices using oxide semiconductors is desired.

[0009] Also, semiconductor devices composed of transistors using silicon-based semiconductor materials such as amorphous silicon or polycrystalline silicon can support glass substrates of the 8th generation (horizontal 2160 mm × vertical 2460 mm) or higher, and thus have the advantages of high productivity and low cost. On the other hand, when using a glass substrate, due to its high insulation and large area, the problem of destruction by electrostatic discharge (ESD: Electro-Static Discharge) becomes particularly prominent. This is a problem that should naturally be considered when using oxide semiconductor materials.

[0010] Based on the technical background as described above, one aspect of the present invention is that there are few changes in the transistor configuration, process conditions, or production equipment from mass production technologies that have been put into practical use, and the semiconductor device is stable One of the objectives is to provide highly reliable semiconductor devices by imparting specific electrical characteristics.

[0011] Furthermore, one aspect of the present invention relates to a semiconductor device that can prevent a decrease in yield due to electrostatic discharge. One of the objectives is to provide [this]. [Means for solving the problem]

[0012] One aspect of the disclosed invention is a gate electrode layer and an oxide semiconductor layer, from the gate electrode layer side , a silicon film containing nitrogen, and one or more metals selected from the constituent elements of the oxide semiconductor layer. This semiconductor device has a multilayer structure including an oxide insulating layer containing an element.

[0013] Because silicon films containing nitrogen have a higher dielectric constant compared to silicon oxide films, they achieve equivalent electrostatic capacitance. The required film thickness to obtain the desired quantity increases. Therefore, a silicon film containing nitrogen is used for gate insulation. By forming an edge layer, the gate insulating layer can be physically made thicker, thus increasing the dielectric strength. This can suppress the decrease in voltage and, preferably, improve the dielectric strength. This can suppress electrostatic discharge breakdown in semiconductor devices that include an insulating layer.

[0014] The thickness of the silicon film containing nitrogen is preferably 325 nm to 550 nm. It is more preferable that the wavelength be between 355 nm and 550 nm. Also, a silicon film containing nitrogen. A silicon nitride film can preferably be used as such.

[0015] Nitrogen-containing silicon films are silicon-based semiconductor materials such as amorphous silicon and polycrystalline silicon. Since it is also used as a gate insulating layer for materials, process conditions or production equipment can be repurposed. It is possible. Therefore, by applying a silicon film containing nitrogen to the gate insulating layer, the oxide semiconductor can be used. This makes it possible to mass-produce transistors using conductors at a low cost.

[0016] In addition, one or more elements selected from the constituent elements of the oxide semiconductor layer are placed in contact with the oxide semiconductor layer. By providing an oxide insulating layer of the metal element, the interface between the oxide insulating layer and the oxide semiconductor layer This helps maintain good condition and prevent interface degradation. In particular, it is effective between oxide insulating layers and oxide semiconductor layers. By suppressing carrier trapping at the interface with the body layer, photodegradation of the transistor (e.g., photodegradation) can be reduced. This reduces bias degradation and allows for the creation of highly reliable transistors.

[0017] In other words, according to one aspect of the present invention, mass production technology for silicon-based semiconductor materials that has been put into practical use. While partially utilizing this, a silicon film containing nitrogen and elements selected from the constituent elements of the oxide semiconductor layer are used. A laminated structure comprising an oxide insulating layer containing one or more metal elements and an oxide semiconductor layer. By achieving this, it produces novel effects different from those of semiconductor devices using silicon-based semiconductor materials. A semiconductor device can be provided. Specifically, for example, it can have the following configuration. ru.

[0018] One aspect of the present invention is a gate electrode layer, a gate insulating layer on the gate electrode layer, and on the gate insulating layer An oxide insulating layer, and an oxide semiconductor layer in contact with the oxide insulating layer and superimposed on the gate electrode layer, It has an oxide semiconductor layer and a source electrode layer and a drain electrode layer that are electrically connected to the gate The insulating layer is composed of a silicon film containing nitrogen, and the oxide insulating layer is composed of an oxide semiconductor layer It comprises one or more metallic elements selected from the constituent elements, and the thickness of the gate insulating layer is oxide insulating. This is a semiconductor device that is thicker than the marginal layer.

[0019] In the above semiconductor device, the edges of the oxide semiconductor layer and the oxide insulating layer coincide. This is preferable. In this specification, "identical" includes approximate identical. For example, The edges of layer A and layer B of the layered structure etched using the same mask coincide. It will be considered as such.

[0020] A layer selected from the constituent elements of the oxide semiconductor layer is provided in contact with the lower layer of the oxide semiconductor layer. Alternatively, in addition to a laminated structure of an oxide insulating layer containing multiple metal elements and a silicon film containing nitrogen, The laminated structure may be provided in contact with the upper layer of the oxide semiconductor layer. , providing stable electrical characteristics to the semiconductor device, and / or reducing electrostatic discharge of the semiconductor device. This makes it possible to prevent it.

[0021] In other words, another aspect of the present invention comprises a gate electrode layer and a gate insulating layer on the gate electrode layer, A first oxide insulating layer on the gate insulating layer, and a gate electrode layer in contact with the first oxide insulating layer. A superimposed oxide semiconductor layer, a source electrode layer electrically connected to the oxide semiconductor layer, and a drain The electrode layer, the source electrode layer and the drain electrode layer are covered, and a portion of the oxide semiconductor layer is in contact with it. It has two oxide insulating layers, a protective insulating layer on the second oxide insulating layer, and a gate insulating layer and The protective insulating layer comprises a silicon film containing nitrogen, and consists of a first oxide insulating layer and a second The oxide insulating layer comprises one or more metallic elements selected from the constituent elements of the oxide semiconductor layer. The thickness of the gate insulating layer is thicker than the thickness of the first oxide insulating layer, and the thickness of the protective insulating layer is This semiconductor device has a thickness greater than that of the second oxide insulating layer.

[0022] Furthermore, in the above semiconductor device, the edges of the oxide semiconductor layer and the first oxide insulating layer are It is preferable that this be done.

[0023] Furthermore, in any one of the above semiconductor devices, the thickness of the gate insulating layer is 325 nm or greater. It is preferable that the wavelength is 550 nm or less. Furthermore, a silicon nitride film is suitable as the gate insulating layer. It is preferable to use it.

[0024] Furthermore, the oxide insulating layer in contact with the oxide semiconductor layer contains an excess of oxygen compared to its stoichiometric composition. It is preferable to include a region (hereinafter referred to as the oxygen-rich region). Oxide insulating layer in contact with the oxide semiconductor layer The inclusion of an oxygen-rich region in the layer makes it possible to supply oxygen to the oxide semiconductor layer. For oxide semiconductors, oxygen vacancies act as donors, generating electron carriers within the oxide semiconductor. To achieve this, oxygen is supplied to the oxide semiconductor layer to fill oxygen deficiencies, thereby enabling reliable operation. It can be made into a transistor. [Effects of the Invention]

[0025] A semiconductor device provided according to one aspect of the present invention is a modification of a commercially available mass production technology. A reliable semiconductor device with stable electrical characteristics, manufactured using a minimal manufacturing method. It is placed there.

[0026] Furthermore, according to one aspect of the present invention, a semiconductor can prevent a decrease in yield due to electrostatic discharge. We can provide a body device. [Brief explanation of the drawing]

[0027] [Figure 1] A plan view and a cross-sectional view showing one embodiment of a semiconductor device. [Figure 2] A plan view and a cross-sectional view showing one embodiment of a semiconductor device. [Figure 3] A diagram illustrating an example of the manufacturing process for a semiconductor device. [Figure 4] A diagram illustrating one form of semiconductor device. [Figure 5] A diagram illustrating one form of semiconductor device. [Figure 6] A diagram illustrating one form of semiconductor device. [Figure 7] A diagram illustrating one form of semiconductor device. [Figure 8] A diagram showing electronic equipment. [Figure 9] A diagram showing electronic equipment. [Figure 10] A plan view and a cross-sectional view showing one embodiment of a semiconductor device. [Figure 11] A plan view and a cross-sectional view showing one embodiment of a semiconductor device. [Figure 12] Results of ESR measurement. [Figure 13] TDS measurement results. [Figure 14] Energy band diagram of a multilayer structure included in a transistor according to one embodiment of the present invention. [Modes for carrying out the invention]

[0028] The embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is... The form and details can be changed in various ways, not limited to the description below, as anyone skilled in the art would understand. It is easily understood. Therefore, the present invention shall be interpreted as being limited to the contents of the embodiments described below. It is not something that can be done.

[0029] In the configuration of the present invention described below, the same part or a part having a similar function is The same reference numerals are used consistently across different drawings, and explanations of their repetition are omitted. When referring to a part that has the function of the same, the hatch pattern is the same, and in cases where no special designation is given, There is a match.

[0030] In each figure described herein, the size of each component, the thickness of the film, or the area is clearly indicated. It may be exaggerated for illustrative purposes. Therefore, it is not necessarily limited to that scale.

[0031] In this specification, the ordinal numbers used as "1st," "2nd," etc., are for convenience only. This does not indicate the order of processes or the order of lamination. Furthermore, this specification does not specify the invention. This does not indicate a specific name as a matter of fact.

[0032] (Embodiment 1) In this embodiment, one form of a semiconductor device and a method for manufacturing a semiconductor device are shown in Figures 1, 2, and 3. This will be explained using Figures 10 and 11. In this embodiment, as an example of a semiconductor device, acid This shows a bottom-gate type transistor with a synthetic semiconductor layer.

[0033] <Example of semiconductor device configuration 1> Figures 1(A) to 1(C) show examples of the configuration of transistor 300. Figure 1(A) shows the transistor This is a plan view of the Zista 300, and Figure 1(B) shows the cross section along the dashed line X1-Y1 in Figure 1(A). This is a top view, and Figure 1(C) is a cross-sectional view along the dashed line V1-W1 in Figure 1(A).

[0034] The transistor 300 has a gate electrode layer 402 provided on a substrate 400 having an insulating surface. The gate insulating layer 404 on the gate electrode layer 402, and the oxide insulating layer on the gate insulating layer 404. Layer 406 and an oxide semiconductor that is in contact with the oxide insulating layer 406 and superimposed on the gate electrode layer 402 Layer 408, and source electrode layer 410a and drain that are electrically connected to oxide semiconductor layer 408. It includes an electrode layer 410b.

[0035] In transistor 300, the gate insulating layer 404 comprises a silicon film containing nitrogen. This is achieved. A silicon film containing nitrogen has a higher dielectric constant compared to a silicon oxide film, and is equivalent in performance. Because a large film thickness is required to obtain capacitance, the gate insulating layer is physically made thicker. Yes, it is possible. Therefore, the decrease in dielectric strength of transistor 300 is suppressed, and furthermore, the dielectric strength is improved. This can suppress electrostatic discharge damage to semiconductor devices.

[0036] The thickness of the gate insulating layer 404 shall be at least thicker than that of the oxide insulating layer 406. Furthermore, it is preferable that the wavelength be between 325nm and 550nm, and between 355nm and 550nm. It is more preferable to keep it below m.

[0037] Examples of silicon films containing nitrogen include silicon nitride films, silicon nitride oxide films, and silicon oxide films. A silicon nitride film is one example, but the higher the nitrogen content, the higher the dielectric constant, so nitrides It is preferable to apply a silicon oxide film. Also, the energy gap of silicon oxide is 8 eV. In contrast, silicon nitride has a small energy gap of 5.5 eV, and accordingly Because it also has low resistivity, using a silicon nitride film provides higher ESD resistance. This makes it possible. Furthermore, when silicon nitride films are deposited by CVD, silicon nitride oxide Greenhouse gas is applied when depositing silicon films containing oxygen and nitrogen, such as silicon films, by CVD. It is not necessary to use N2O gas, which is a sulfate. A film, in terms of its composition, refers to a film in which the oxygen content is higher than the nitrogen content, such as a silicon nitride film. This refers to a membrane whose composition contains more nitrogen than oxygen.

[0038] In transistor 300, the oxide insulating layer 406 is composed of the same elements as the oxide semiconductor layer 408. It is composed of one or more metal elements selected from such materials. By forming an insulating layer 406, the interface with the oxide semiconductor layer 408 can be stabilized. This makes it possible to suppress the trapping of charge at the interface. Therefore, transistor This prevents degradation, especially photodegradation, resulting in a highly reliable transistor.

[0039] Specifically, as the oxide insulating layer 406, for example, a gallium oxide film (GaO x Also written as (Note that x is not necessarily a natural number and may include non-natural numbers), gallium oxide zinc film (Ga2Zn x O y (Also written as x=1~5), Ga2O3 (Gd2O3) film, gallium content Insulating In-Ga-Zn oxide films, etc., which have a high concentration of indium and a low indium content. It is preferable to provide one.

[0040] If the constituent elements of the oxide insulating layer 406 and the oxide semiconductor layer 408 are the same, and the compositions of the two are different, It may be done as follows: For example, as oxide semiconductor layer 408, an In-Ga-Zn based oxide semiconductor layer When using this, the ratio of indium (In) to gallium (Ga) determines the energy g Because the top can be controlled, the atomic ratio of the oxide semiconductor layer 408 is set to In:Ga: Assuming Zn=1:1:1 or In:Ga:Zn=3:1:2, the oxide insulating layer 406 The atomic ratio should be In:Ga:Zn = 1:3:2. Note that the oxide insulating layer 406 and The oxide semiconductor layer 408 can be formed by sputtering, Including indium in the target material can reduce the generation of particles during film formation. Therefore, the indium-containing oxide insulating layer 406 and the indium-containing oxide semiconductor It is preferable to have a layer 408.

[0041] In addition, in the transistor 300 shown in Figure 1, when processing the oxide semiconductor layer 408 into an island shape... This shows an example in which the oxide insulating layer 406 is also processed into an island shape by etching. The edges of the oxide semiconductor layer 408 and the oxide insulating layer 406 coincide.

[0042] The structure of the oxide semiconductor layer will be described below.

[0043] Oxide semiconductor layers are broadly classified into single-crystal oxide semiconductor layers and non-single-crystal oxide semiconductor layers. Single-crystal oxide semiconductor layers include amorphous oxide semiconductor layers, microcrystalline oxide semiconductor layers, and polycrystalline oxide layers. physical semiconductor layer, CAAC-OS (C Axis Aligned Crystalline This refers to oxide semiconductor films, etc.

[0044] Amorphous oxide semiconductor layers have an irregular atomic arrangement within the film and do not contain crystalline components. It is a crystalline semiconductor layer. Even in minute regions, it does not have crystalline parts, and the entire film has a completely amorphous structure. Oxide semiconductor layers are a typical example.

[0045] The microcrystalline oxide semiconductor layer is, for example, a microcrystal (nanocrystal) with a size of 1 nm to less than 10 nm. It is also called. ) contains. Therefore, the microcrystalline oxide semiconductor layer is more fundamental than the amorphous oxide semiconductor layer. The arrangement of the microcrystalline oxide semiconductor layer is highly regular. Therefore, the microcrystalline oxide semiconductor layer is more regular than the amorphous oxide semiconductor layer. It also has the characteristic of having a low defect level density.

[0046] CAAC-OS film is one of the oxide semiconductor layers having multiple crystalline regions, and most of the bonds The crystal portion is small enough to fit within a cube with sides less than 100 nm. Therefore, CAAC-O The crystalline portion contained in the S film is within a cube with sides less than 10 nm, less than 5 nm, or less than 3 nm. This also includes cases where the size fits within the given space. CAAC-OS films have fewer defects than microcrystalline oxide semiconductor layers. It is characterized by a low void density. A detailed explanation of the CAAC-OS membrane follows. .

[0047] CAAC-OS film is scanned using a transmission electron microscope (TEM). When observed with a microscope, clear boundaries between crystalline regions, i.e., bonds, can be seen. The grain boundaries (also called crystal grain boundaries) cannot be identified. Therefore, CA AC-OS films are less susceptible to the decrease in electron mobility caused by grain boundaries.

[0048] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). ) This confirms that metal atoms are arranged in layers in the crystalline region. Each layer has irregularities on the surface (also called the surface to be formed) or the upper surface that forms the CAAC-OS film. The shape reflects this, and the elements are arranged parallel to the surface or top surface of the CAAC-OS film.

[0049] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. This refers to the state in which something is positioned. Therefore, it also includes cases where the angle is between -5° and 5°. "Straight" refers to a state in which two straight lines are positioned at an angle of 80° to 100°. This includes cases where the angle is between 85° and 95°.

[0050] On the other hand, the CAAC-OS film was observed by TEM from a direction roughly perpendicular to the sample surface (planar TEM). (M observation) In the crystalline region, metal atoms are arranged in a triangular or hexagonal shape. This can be confirmed. However, no regularity is observed in the arrangement of metal atoms between different crystalline regions. stomach.

[0051] Cross-sectional TEM observation and planar TEM observation revealed that the crystalline portion of the CAAC-OS film exhibits orientation. You can tell they are there.

[0052] X-ray diffraction (XRD) was applied to the CAAC-OS film. When structural analysis is performed using this method, for example, a CAAC-OS film having InGaZnO4 crystals is found. In the out-of-plane analysis, the diffraction angle (2θ) shows a peak near 31°. This peak may appear. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is generally aligned with the surface to be formed or the upper surface. It can be confirmed that it is facing in a nearly vertical direction.

[0053] On the other hand, in-pl X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis. In analysis using the ANE method, a peak may appear when 2θ is around 56°. This peak is It is attributed to the (110) plane of the InGaZnO4 crystal. Single crystal oxidation of InGaZnO4 For a solid semiconductor layer, fix 2θ to around 56°, and use the normal vector of the sample surface as the axis (φ axis). When the analysis (φ scan) is performed while rotating the sample, the crystal plane equivalent to the (110) plane is found. Six attributed peaks are observed. In contrast, in the case of the CAAC-OS film, 2θ is set to 5 Even when fixed at approximately 6° and scanned using the φ scan function, no clear peak appears.

[0054] From the above, it can be concluded that in CAAC-OS films, the orientation of the a-axis and b-axis is inconsistent between different crystalline regions. It is a rule, but it has c-axis orientation and the c-axis is parallel to the normal vector of the surface to be formed or the upper surface. It can be seen that it is facing in a certain direction. Therefore, it is arranged in layers as confirmed by the aforementioned cross-sectional TEM observation. Each layer of arranged metal atoms is a plane parallel to the ab-plane of the crystal.

[0055] The crystalline portion is formed when the CAAC-OS film is deposited, or when crystallization treatment such as heat treatment is performed. It is formed when this occurs. As mentioned above, the c-axis of the crystal is the surface on which the CAAC-OS film is formed or It is oriented in a direction parallel to the normal vector of the upper surface. Therefore, for example, the shape of the CAAC-OS film When the shape is altered by etching or other means, the c-axis of the crystal becomes the surface on which the CAAC-OS film is formed. Alternatively, it may not be parallel to the normal vector of the top surface.

[0056] Furthermore, the degree of crystallinity in the CAAC-OS film does not need to be uniform. For example, the CAAC-OS film When the crystalline portion is formed by crystal growth from near the upper surface of the CAAC-OS film, the upper surface The nearby region may have a higher degree of crystallinity than the region near the surface being formed. Also, CAA When impurities are added to a C-OS film, the degree of crystallinity in the region where the impurities are added changes, and some areas Regions with different degrees of crystallinity may also be formed.

[0057] Furthermore, the out-of-plane method for CAAC-OS films containing InGaZnO4 crystals. Analysis revealed that in addition to a peak near 2θ = 31°, a peak also appeared near 2θ = 36°. In some cases, this may occur. Peaks near 36° 2θ indicate c-axis orientation in a portion of the CAAC-OS film. This indicates that it contains crystals that do not have [the specified characteristic]. The CAAC-OS film has 2θ near 31°. It is preferable that a peak is observed, and that no peak is observed near 36° for 2θ.

[0058] Furthermore, in this specification, if a crystal is trigonal or rhombohedral, it will be represented as a hexagonal crystal system. .

[0059] Transistors using CAAC-OS film exhibit changes in electrical properties due to irradiation with visible light and ultraviolet light. Its value is small. Therefore, this transistor is highly reliable.

[0060] The oxide semiconductor layer 408 may be, for example, an amorphous oxide semiconductor layer or a microcrystalline oxide semiconductor layer. The film may have any of the CAAC-OS film structures, or it may be a mixture of these structures. i. Alternatively, the laminated film may have two or more of these structures.

[0061] Note that the oxide insulating layer 406 may have lower crystallinity compared to the oxide semiconductor layer 408. The oxide insulating layer 406 may have, for example, amorphous portions or nanocrystalline portions.

[0062] The transistor 300 has a source electrode layer 410a and a drain electrode layer 410. an oxide insulating layer 412 that covers b and is in contact with the oxide semiconductor layer 408, and / or an oxide insulating layer A protective insulating layer 414 may be included on layer 412.

[0063] As for the oxide insulating layer 412, similar to the oxide insulating layer 406, the structure of the oxide semiconductor layer 408 It is preferable to apply a layer composed of one or more metallic elements selected from the constituent elements. It is possible to use such materials to create a boundary between the oxide insulating layer 412 and the oxide semiconductor layer 408. The surface can be stabilized. The oxide insulating layer 412 is back-chipped with the oxide semiconductor layer 408. Because it is an insulating layer in contact with the channel side, it suppresses charge trapping at the interface between the two layers. This can suppress the development of parasitic channels.

[0064] Furthermore, the oxide semiconductor layer 408 is sandwiched between two other elements, which are selected from the constituent elements of the oxide semiconductor layer. By providing an oxide insulating layer containing one or more selected metal elements, the oxide semiconductor can be prevented from entering from the outside. The intrusion of impurities that may affect the body layer (such as nitrogen or metallic elements) through diffusion. It can act as a blocker. Therefore, sandwiching an oxide semiconductor layer, or an oxide semiconductor layer By providing the oxide insulating layer so as to surround the surrounding oxide semiconductor layer, the composition of the surrounding oxide semiconductor layer and By maintaining a constant purity, it is possible to realize semiconductor devices with stable electrical characteristics.

[0065] The protective insulating layer 414 may be a silicon oxide film, a gallium oxide film, an aluminum oxide film, or a nitrogen oxide film. Silicon oxide film, silicon oxide nitride film, aluminum oxide nitride film, or silicon nitride oxide film A membrane or the like can be used.

[0066] <Example of semiconductor device configuration 2> Figures 2(A) to 2(C) show examples of the configuration of transistor 310. Figure 2(A) shows the transistor This is a plan view of the Zista 310, and Figure 2(B) shows the cross section along the dashed line X2-Y2 in Figure 2(A). This is a top view, and Figure 2(C) is a cross-sectional view along the dashed line V2-W2 in Figure 2(A).

[0067] The transistor 310 shown in Figure 2, like the transistor 300 in Figure 1, has an insulating surface. A gate electrode layer 402 provided on the substrate 400, and gate insulating on the gate electrode layer 402 Layer 404, oxide insulating layer 406 on gate insulating layer 404, and contact on oxide insulating layer 406 Furthermore, an oxide semiconductor layer 408 superimposed on the gate electrode layer 402, and an oxide semiconductor layer 408 and an electric field It includes a source electrode layer 410a and a drain electrode layer 410b that are connected by gas. - Covers the electrode layer 410a and the drain electrode layer 410b, and is in contact with the oxide semiconductor layer 408. The oxide insulating layer 412 and the protective insulating layer 414 on the oxide insulating layer 412 are connected to the transistor 3 It may also be composed of 10 elements.

[0068] The transistor 310 has a gate insulating layer 404 and an oxide semiconductor layer 408, It differs from transistor 300. That is, in transistor 310, the gate insulating layer 404 is A gate insulating layer 404a in contact with the gate electrode layer 402, and an oxide insulating layer between the gate insulating layer 404a and the oxide insulating layer It is composed of a gate insulating layer 404b provided between the edge layer 406 and the gate insulating layer 404b. In the lampistor 310, the oxide semiconductor layer 408 is in contact with the oxide insulating layer 406. It includes a semiconductor layer 408a and an oxide semiconductor layer 408b in contact with the oxide insulating layer 412. This is how it is constructed. In transistor 310, the gate insulating layer 404 and the oxide semiconductor The configuration other than layer 408 is the same as that of transistor 300, and regarding transistor 300... The explanation can be taken into consideration.

[0069] In transistor 310, gate insulating layer 404a and gate insulating layer 404b are nitrided Contains a silicon film.

[0070] The gate insulating layer 404a has a thicker film than the gate insulating layer 404b, reducing defects within the film. It shall include a silicon nitride film. For example, the thickness of the gate insulating layer 404a is 300 The wavelength should be between 400 nm and 400 nm. Furthermore, electron spin resonance (ESR) spectroscopy is used. In Spin Resonance, the signal that appears at the Nc center (g value of 2.003) The spin density corresponding to the number is preferably 1 × 10⁻⁶. 17 spins / cm3 The following are more preferred Or 5 x 10 16 spins / cm 3 The following silicon nitride film is applied. Next, a silicon nitride film with reduced defects in the film is provided with a thick film thickness (e.g., 300 nm or more). By doing so, the dielectric strength of the gate insulating layer 404a can be set to, for example, 300V or higher. It is Noh.

[0071] Furthermore, since the gate insulating layer 404b is in contact with the oxide semiconductor layer 408, the hydrogen content is low. It includes a reduced silicon nitride film, and its hydrogen concentration is at least that of the gate insulating layer 40 The concentration should be lower than that of 4a. For example, by plasma CVD, the gate insulating layer 404a and When forming the gate insulating layer 404b, the hydrogen concentration in the supply gas is reduced. This allows the hydrogen concentration in the gate insulating layer 404b to be lower than that in the gate insulating layer 404a. Yes, it is possible. Specifically, the gate insulating layer 404a and gate insulating layer 404b are made of silica nitride. When forming a film, ammonia is used as the supply gas for forming the gate insulating layer 404a. The gate insulating layer 404b can be formed by reducing the flow rate or by not using ammonia.

[0072] Furthermore, the thickness of the gate insulating layer 404b shall be between 25 nm and 150 nm. By providing a silicon nitride film with a reduced hydrogen content as 404b, the oxide insulating layer Reduces the inclusion of hydrogen or hydrogen compounds (e.g., water) into 406 and the oxide semiconductor layer 408. It is possible. Hydrogen is a carrier generation factor in oxide semiconductors, and in transistors Because it causes the threshold voltage to fluctuate (shift) in the negative direction, reducing the hydrogen concentration... By providing a silicon nitride film as the gate insulating layer 404b, the electrical characteristics of the transistor are improved. It can stabilize properties. Also, a silicon nitride film with reduced hydrogen concentration can be gate-insulated. By providing it as the edge layer 404b, the hydrogen or hydrogenated compound contained in the gate insulating layer 404a A barrier that prevents the diffusion of impurities such as substances into the oxide insulating layer 406 and the oxide semiconductor layer 408. It also has a membrane-like effect.

[0073] In this embodiment, both gate insulating layer 404a and gate insulating layer 404b are nitrogen It is a silicon dioxide film, and depending on the material and deposition conditions, the interface between each gate insulating layer may be unclear. This can also happen. Therefore, in Figure 2, the gate insulating layer 404a and the gate insulating layer 404 The interface of b is schematically shown with a dotted line. This is also the case in all subsequent drawings.

[0074] The oxide semiconductor layer 408a and oxide semiconductor layer 408b contained in the oxide semiconductor layer 408 are It is preferable to have the same constituent elements but different compositions for both. Oxide semiconductor layer 408a And an oxide semiconductor layer containing indium and gallium is formed as oxide semiconductor layer 408b. In this case, the oxide semiconductor layer 408a on the side closer to the gate electrode layer 402 (channel side) It is preferable to set the content of zinc and gallium so that In > Ga. Also, the farther away from the gate electrode layer 402 The indium and gallium content of the oxide semiconductor layer 408b on the back channel side is I It is best to set n ≤ Ga.

[0075] In oxide semiconductors, the s orbitals of heavy metals are primarily responsible for carrier conduction, and indium Increasing the content tends to increase the overlap of the s orbitals, therefore, In> Oxides with a Ga composition exhibit higher mobility compared to oxides with an In ≤ Ga composition. Furthermore, compared to In, Ga has a higher energy for oxygen vacancy formation, making it less likely for oxygen vacancies to occur. Therefore, oxides with a composition of In ≤ Ga are more stable than oxides with a composition of In > Ga. It possesses certain characteristics.

[0076] An oxide semiconductor with a composition of In > Ga is applied to the channel side, and In ≤ Ga is applied to the back channel side. By applying an oxide semiconductor with a Ga composition, the mobility and reliability of the transistor can be improved. Further improvements become possible. For example, the atomic ratio of the oxide semiconductor layer 408a can be changed to In:G Let a:Zn=3:1:2, and set the atomic ratio of the oxide semiconductor layer 408b to In:Ga:Zn=1 :1:1 is also acceptable.

[0077] Furthermore, the constituent elements of the oxide insulating layer 406 in contact with the oxide semiconductor layer 408a are the oxide semiconductor layer By making it identical to 408a but changing its composition, insulating properties are imparted to the oxide insulating layer 406. This is preferable because it allows for greater stabilization of the interface between the two. Oxide semiconductor layer 408b The oxide insulating layer 412 in contact with the surface is similar.

[0078] Furthermore, oxide semiconductor layers 408a and 408b are made of oxide semiconductors with different crystalline properties. The material may be applied. That is, single-crystal oxide semiconductors, polycrystalline oxide semiconductors, nanocrystalline acids A configuration that appropriately combines a crystalline semiconductor, amorphous oxide semiconductor, or CAAC-OS. This is also acceptable. However, amorphous oxide semiconductors tend to absorb impurities such as hydrogen, and oxygen deficiency... Because losses are likely to occur, it is prone to becoming n-type. Therefore, the oxide semiconductor layer 408a on the channel side It is preferable to use a crystalline oxide semiconductor such as CAAC-OS.

[0079] Furthermore, if an amorphous oxide semiconductor is used for the oxide semiconductor layer 408b on the back channel side, Oxygen deficiency due to etching process during the formation of the - electrode layer 410a and drain electrode layer 410b Damage occurs, and it is prone to becoming n-type. Therefore, the oxide semiconductor layer 408b has crystalline oxide It is preferable to use a material semiconductor.

[0080] Figure 14 shows the gate insulating layer GI and oxide insulating layer OI in the transistor of this embodiment. 1. Oxide semiconductor layers OS1, OS2, oxide insulating layer OI2, and protective insulating layer Passi This is a schematic diagram of the energy bands in a stacked structure. Figure 14 shows the gate insulation. The ideal scenario is that all layers—the oxide insulating layer, the oxide semiconductor layer, and the protective insulating layer—are intrinsic. Assuming the following situation, the gate insulating layer GI and the protective insulating layer Passi are silicon nitride films ( A band gap Eg of 5 eV is used for oxide insulating layer OI1 and oxide insulating layer OI2. In:Ga:Zn=1:3:2 In-Ga-Zn oxide insulating layer (bandgap) With an Eg of 3.6eV, the oxide semiconductor layer OS1 is defined as In:Ga:Zn=3:1:2. A certain In-Ga-Zn oxide semiconductor layer (band gap Eg is 2.8 eV) is made of oxide The semiconductor layer OS2 is an In-Ga-Zn oxide with an In:Ga:Zn ratio of 1:1:1. This shows the case using a semiconductor layer (bandgap Eg of 3.2 eV).

[0081] In Figure 14, the oxide insulating layer OI1, oxide insulating layer OI2, and oxide semiconductor layer OS are shown. The relative permittivity of both layer 1 and the oxide semiconductor layer OS2 was assumed to be 15. Furthermore, the oxide insulating layer OI The mobility of 1 and the oxide insulating layer OI2 was measured at 4 cm. 2Set it as / Vs, and set the mobility of the oxide semiconductor layer OS1 to 25 cm 2 / Vs, and set the mobility of the oxide semiconductor layer OS2 to 10 cm 2 / Vs and performed the calculation. Also, set the film thickness of the gate insulating layer GI to 325 nm, set the film thickness of the oxide insulating layer OI1 to 3 0 nm, set the film thickness of the oxide semiconductor layer OS1 to 10 nm, and set the film thickness of the oxide semiconductor layer OS2 to 10 nm, set the film thickness of the oxide insulating layer OI2 to 30 nm, and set the film thickness of the protective insulating layer Passi to 300 nm and performed the calculation.

[0082] As shown in FIG. 14, on the gate electrode side (channel side) of the oxide semiconductor layer OS1, an energy barrier exists at the interface between the oxide semiconductor layer OS1 and the oxide insulating layer OI1. Similarly, on the back channel side (opposite side to the gate electrode) of the oxide semiconductor layer OS2, an energy barrier also exists at the interface between the oxide semiconductor layer OS2 and the oxide insulating layer OI2. Due to the existence of such an energy barrier at the interface between the oxide semiconductor layer and the oxide insulating layer, the movement of carriers is hindered at that interface. Therefore, the carriers move in the oxide semiconductor layer without moving from the oxide semiconductor layer to the oxide insulating layer. That is, by forming a stacked structure such that the oxide semiconductor layer is sandwiched between materials with a gradually increasing band gap compared to the oxide semiconductor, the carriers move in the oxide semiconductor layer OS1 and the oxide semiconductor layer OS2.

[0083] <Method for manufacturing a semiconductor device> Hereinafter, an example of the method for manufacturing the transistor 310 will be shown using FIG. 3.

[0084] First, a gate electrode layer 402 is formed on a substrate 400 having an insulating surface.

[0085] ​​​​​​​​There are no major restrictions on the type of substrate that can be used for the substrate 400 having an insulating surface, however It is necessary that it has sufficient heat resistance to withstand subsequent heat treatment. For example, barium chloride Glass substrates such as borosilicate glass and aluminoborosilicate glass, ceramic substrates, and quartz substrates. Sapphire substrates can be used, as well as single crystals such as silicon and silicon carbide. Semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI groups A board or the like can be applied, and a substrate 400 is formed by providing semiconductor elements on such a substrate. It may be used in this way.

[0086] The gate electrode layer 402 is made of molybdenum, titanium, tantalum, tungsten, aluminum, Metal materials such as copper, chromium, neodymium, scandium, or alloy materials mainly composed of these materials It can be formed using [this method]. In addition, impurity elements such as phosphorus can be used as the gate electrode layer 402. Semiconductor films such as punctured polycrystalline silicon films, nickel silicides, etc. A film may be used. The gate electrode layer 402 may be a single layer or a stacked structure. Good. The gate electrode layer 402 may also have a tapered shape, for example, with a taper angle of 30° or more and 70°. It should be less than or equal to °. Here, the taper angle is defined as the side surface of a layer having a tapered shape and the layer of the said layer. This refers to the angle between the base and the surface.

[0087] Furthermore, the material of the gate electrode layer 402 includes indium tin oxide and tungsten oxide. Indium oxide, indium zinc oxide containing tungsten oxide, and titanium oxide containing Indium oxide, indium tin oxide containing titanium oxide, indium oxide zinc oxide, acid Conductive materials such as indium tin oxide with added silicon dioxide can also be used.

[0088] Alternatively, as the material for the gate electrode layer 402, an In-Ga-Zn oxide containing nitrogen, nitrogen In-Sn oxides containing nitrogen, In-Ga oxides containing nitrogen, In-Zn oxides containing nitrogen Indium nitride (Sn oxides containing nitrogen, In oxides containing nitrogen, and metallic nitrides) (For example, zinc nitride, tantalum nitride, tungsten nitride, etc.) may be used. These materials are Because these materials have a work function of 5 eV or more, the gate electrode layer 402 is formed using these materials. This allows the transistor's threshold voltage to be made positive, and the normally-off switch A chapping transistor can be realized.

[0089] Next, the gate insulating layer 404a and gate insulating layer 40 cover the gate electrode layer 402. A gate insulating layer 404 including 4b is formed (see Figure 3(A)). In this case, a silicon film containing nitrogen can be applied. In this embodiment, silicon nitride A gate insulating layer 404a made of a film and a gate insulating layer 404b made of a silicon nitride film are laminated together. This forms the gate insulating layer 404. The gate insulating layer 404 is designed to prevent in-plane variations and particle contamination. Furthermore, from the viewpoint of reducing the film deposition cycle time, it is effective to perform film deposition using the CVD method. Furthermore, the CVD method is also effective for film deposition on large-area substrates.

[0090] In this embodiment, the gate insulating layer 404a and the gate insulating layer 4 are formed by plasma CVD. O4b is formed continuously. First, the supply gas is silane (SiH4), nitrogen (N2) and A A silicon nitride film, which forms the gate insulating layer 404a, is formed as a mixed gas of humonia (NH3). After forming a membrane, the supply gas is switched to a mixed gas of silane (SiH4) and nitrogen (N2). Then, a silicon nitride film, which will become the gate insulating layer 404b, is formed.

[0091] The supply gases for the plasma CVD method are silane (SiH4), nitrogen (N2), and ammonia (NH4). 3) The silicon nitride film deposited as a mixed gas is supplied with silane (SiH4) and nitrogen It reduces defects in the film compared to silicon nitride films deposited with a mixed gas of element (N2). Yes, it is possible. Therefore, the gate insulating layer 404a is at least more in the film than the gate insulating layer 404b. A film with reduced defects, for example, Nc centers in electron spin resonance (ESR) spectroscopy. The spin density corresponding to the signal appearing at (g value of 2.003) is preferably 1 × 10⁻⁶. 17 s pins / cm 3 , comfortable 5×10 16 spins / cm 3 The following can be done: It can be done. Also, silicon nitride films formed by adding ammonia to the mixed gas can be supplied with a silicon nitride film. Because it can create a film with better covering properties than when using a mixture of gases of ranic acid and nitrogen, As a gate insulating layer in contact with the electrode layer 402, a silicon nitride film using the above-mentioned mixed gas is used. It is effective to provide it. Also, the gate insulating layer 404a with reduced defects in the film has a film thickness of 30 By providing it in a range of 0 nm to 400 nm, the dielectric strength of the gate insulating layer 404 can be increased to 300 V or less. It can be considered above.

[0092] On the other hand, the gate insulating layer 404b, which is formed without ammonia in the material gas, is gate insulating A film with a lower hydrogen content can be formed compared to the edge layer 404a. A layer with a wavelength of 25 nm to 150 nm is provided between the oxide insulating layer 406 and the gate electrode layer 402. By doing so, the gate insulating layer 404b is transferred to the oxide insulating layer 406 and the oxide semiconductor layer 408. This can reduce the inclusion of hydrogen. In addition, the gate insulating layer 404b is the gate insulating layer 4 The hydrogen or hydrogen compound contained in 04a is present in the oxide insulating layer 406 and the oxide semiconductor layer 408 It also functions as a barrier film that prevents contamination.

[0093] As the gate insulating layer 404, a thick gate insulating layer 404a with reduced defects in the film and hydrogen By laminating with a gate insulating layer 404b with reduced concentration, good dielectric strength is achieved, To suppress the diffusion of impurities such as hydrogen into the oxide insulating layer 406 and the oxide semiconductor layer 408. This is possible. Therefore, electrostatic discharge breakdown of the transistor including the gate insulating layer 404 is suppressed, and This makes it possible to stabilize the electrical characteristics.

[0094] Next, an oxide insulating layer and an oxide semiconductor layer are formed on the gate insulating layer 404b, and etching The oxide insulating layer 406, the oxide semiconductor layer 408a and the acid are processed into island shapes by a grafting process. An oxide semiconductor layer 408 containing an oxide semiconductor layer 408b is formed (see Figure 3(B)). Since this etching process can be performed using the same photomask, oxide insulation Layer 406 and the oxide semiconductor layer 408 have the same pattern shape when viewed from a plane, and the edges The parts match.

[0095] The oxide insulating layer 406 may be one or more elements selected from the constituent elements of the oxide semiconductor layer 408. An oxide insulating layer containing several metal elements is provided. For example, a gallium oxide film, zinc gallium oxide. The film, gallium gadolinium oxide film, has a high gallium content, and also has a high indium content. It is preferable to use an insulating film such as an In-Ga-Zn oxide film with low insulating properties.

[0096] The oxide semiconductor layer 408 may have an amorphous or crystalline structure. When the oxide semiconductor layer has an amorphous structure, heat treatment is applied in a later manufacturing step. A crystalline oxide semiconductor layer 408 may also be used. The heat treatment temperature is 250°C to 700°C, preferably 400°C or higher, more preferably The temperature should be 500°C or higher, more preferably 550°C or higher. This heat treatment is performed during the manufacturing process. It can also be combined with other heat treatments.

[0097] The method for depositing the oxide insulating layer 406 and the oxide semiconductor layer 408 is sputtering, MBE. Molecular Beam Epitaxy, CVD, pulsed laser deposition Appropriate use of methods such as ALD (Atomic Layer Deposition) is recommended. can.

[0098] When forming the oxide insulating layer 406 and the oxide semiconductor layer 408, the film contains as much as possible. It is preferable to reduce the hydrogen concentration. To reduce the hydrogen concentration, for example, sputtering When performing film deposition using the sputtering method, the atmosphere supplied to the deposition chamber of the sputtering apparatus As a substitute, it is a high-purity noble gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed. Typically, argon, oxygen, and mixed gases of noble gases and oxygen are used as appropriate.

[0099] Furthermore, while removing residual moisture in the deposition chamber, sputter gas from which hydrogen and moisture have been removed is introduced. By performing the film formation in this manner, the hydrogen concentration of the formed oxide insulating layer and oxide semiconductor layer is reduced. This is possible. To remove residual moisture in the deposition chamber, an adsorption-type vacuum pump, for example, is used. It is preferable to use cryopumps, ion pumps, and titanium sublimation pumps. Alternatively, a turbomolecular pump with a cold trap may be added. The pump can, for example, contain hydrogen atoms such as hydrogen molecules, water (H2O), or other compounds (more preferably). Because of their high exhaust capacity (including compounds containing carbon atoms), a cryopump is used to exhaust the wastewater. The concentration of impurities in the film deposited in the membrane chamber can be reduced.

[0100] Furthermore, it is preferable to continuously deposit the oxide insulating layer and the oxide semiconductor layer without exposing them to the atmosphere. It is possible to continuously deposit oxide insulating layers and oxide semiconductor layers without opening to the atmosphere, Adhesion of hydrogen or hydrogen compounds to the surface of the oxide insulating layer or the laminated oxide semiconductor layer (e.g.) For example, it can prevent the formation of adsorbed water, thus suppressing the inclusion of impurities. .

[0101] Furthermore, when depositing an oxide insulating layer or an oxide semiconductor layer by sputtering, the following are used for film deposition. The relative density (filling rate) of the metal oxide target is preferably 90% or more and 100% or less. The density should be between 95% and 99.9%. A metal oxide target with a high relative density will be used. This allows for the formation of a denser film.

[0102] Furthermore, forming the oxide semiconductor layer while the substrate 400 is held at a high temperature is also possible. This is effective in reducing the concentration of impurities that may be present in the substrate layer. The temperature at which the substrate 400 is heated and The temperature should be between 150°C and 450°C, preferably the substrate temperature should be between 200°C and 3 The temperature should be kept below 50°C. Also, by heating the substrate at a high temperature during film formation, crystalline oxide semi-crystalline oxides can form. A conductive layer can be formed.

[0103] When a CAAC-OS film is applied as the oxide semiconductor layer 408, the CAAC-OS film is obtained. One method is to set the film deposition temperature to 200°C or higher and 450°C or lower to form an oxide semiconductor layer. One method involves forming a thin film and orienting it along the c-axis roughly perpendicular to the surface. Alternatively, a thin oxide semiconductor layer can be formed. After forming a film with a certain thickness, heat treatment is performed at 200°C to 700°C, and the c-axis is roughly perpendicular to the surface. Orientation may be applied. Alternatively, a thin film can be deposited as the first layer, followed by a heating process at 200°C to 700°C. The following heat treatment may be performed to deposit a second layer, which may then be oriented along the c-axis approximately perpendicular to the surface.

[0104] The oxide semiconductor used in the oxide semiconductor layer 408 is at least indium (In). It contains. In particular, it is preferable that it contains indium and zinc (Zn). Furthermore, the oxide semiconductor As stabilizers to reduce variations in the electrical characteristics of the transistors used, It is preferable to have gallium (Ga) in addition to the above. Also, tin as a stabilizer ( One of the following: Sn (Sn), hafnium (Hf), aluminum (Al), or zirconium (Zr) It is preferable to have one or more types.

[0105] Also, other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce, praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Lu It may contain one or more types of tecium (Lu).

[0106] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and the oxide of binary metals. In-Zn oxides, In-Mg oxides, In-Ga oxides, and ternary metals are materials. Oxides include In-Ga-Zn oxides, In-Al-Zn oxides, and In-Sn-Zn oxides. In-Hf-Zn oxides, In-La-Zn oxides, In-Ce-Zn oxides Oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm-Zn acids In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides Materials, In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er-Zn oxides In-Tm-Zn oxides, In-Yb-Zn oxides, In-Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides and In-Hf-Ga-Zn oxides are oxides of quaternary metals. Oxides, In-Al-Ga-Zn oxides, In-Sn-Al-Zn oxides, In-S n-Hf-Zn oxides and In-Hf-Al-Zn oxides can be used.

[0107] For example, an In-Ga-Zn oxide is an oxide whose main components are In, Ga, and Zn. This means that the ratio of In, Ga, and Zn is not important. Also, other than In, Ga, and Zn... It may contain metallic elements.

[0108] In addition, as an oxide semiconductor, InMO3(ZnO) m (m > 0, and m is not an integer) Materials represented by may also be used. Note that M is selected from Ga, Fe, Mn, and Co. It represents one or more metallic elements. Also, as an oxide semiconductor, In2SnO 5(ZnO) n Materials expressed as (n>0 and n is an integer) may also be used.

[0109] For example, In:Ga:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3), In:Ga:Z n=2:2:1 (=2 / 5:2 / 5:1 / 5), or In:Ga:Zn=3:1:2 In-Ga-Zn oxides and their compositions with an atomic ratio of (=1 / 2:1 / 6:1 / 3) The oxide can be used. Alternatively, In:Sn:Zn=1:1:1 (=1 / 3: 1 / 3:1 / 3), In:Sn:Zn=2:1:3 (=1 / 3:1 / 6:1 / 2) or In-Sn has an atomic ratio of In:Sn:Zn = 2:1:5 (= 1 / 4:1 / 8:5 / 8). -Zn-based oxides or oxides with a similar composition are preferable.

[0110] However, transistors using indium-containing oxide semiconductors are not limited to these, and are not limited to these. Depending on the required electrical characteristics (field effect mobility, threshold, variability, etc.), an appropriate composition is selected. You can use that. Also, in order to obtain the required electrical characteristics, the carrier concentration and impurity concentration The degree, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc., should be appropriate. It is preferable.

[0111] For example, high power can be achieved relatively easily in transistors using In-Sn-Zn oxide semiconductors. Field effect mobility can be obtained. However, traction using In-Ga-Zn oxide semiconductors Even in transistors, the field-effect mobility can be increased by lowering the bulk defect density. Cut.

[0112] For example, if the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of an oxide with c=1 is such that the atomic ratio is In:Ga:Zn=A:B:C(A+B+C The composition of the oxide in the vicinity of (aA) = 1) means that a, b, and c are in the vicinity of (aA) 2 +(bB) 2 + (cC) 2 ≤r 2 This means satisfying the following condition. For example, r can be set to 0.05. The same applies to other oxides.

[0113] Furthermore, the oxide insulating layer 406 and / or oxide semiconductor layer 408 are affected by the amount of peroxide contained in the film. This involves performing a heat treatment to remove excess hydrogen (including water and hydroxyl groups) (dehydration or dehydrogenation). This is preferable. The heat treatment temperature should be between 300°C and 700°C, or below the strain point of the substrate. The heat treatment can be carried out under reduced pressure or in a nitrogen atmosphere. This heat treatment will result in n It is possible to remove hydrogen, an impurity that imparts conductivity to the material.

[0114] Furthermore, the heat treatment for dehydration or dehydrogenation is performed on the oxide insulating layer and / or oxide semiconductor layer. This can be done at any point in the transistor fabrication process after film deposition. The heat treatment for dehydration or dehydrogenation may be performed multiple times and may be combined with other heat treatments. .

[0115] Furthermore, if the oxide insulating layer contains an oxygen-rich region, heat treatment for dehydration or dehydrogenation is performed. If this is done before processing the oxide insulating layer and oxide semiconductor layer into island shapes, the oxide insulating layer contains This is preferable because it prevents oxygen from being released during heat treatment.

[0116] In heat treatment, nitrogen, or noble gases such as helium, neon, or argon are used, along with water, hydrogen, etc. It is preferable that the following are not included. Alternatively, nitrogen, helium, or neon introduced into the heat treatment apparatus. , the purity of noble gases such as argon is preferably 6N (99.9999%) or higher, more preferably 7N (99. 99999%) or higher (i.e., the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower). This is preferable.

[0117] Also, after heating the oxide semiconductor layer 408 by heat treatment, while maintaining the heating temperature or gradually cooling from that heating temperature, high-purity oxygen gas, high-purity dinitrogen monoxide gas, or ultra-dry air (the moisture content measured using a dew point meter of the CRDS (cavity ring-down laser spectroscopy) method is 20 ppm (dew point conversion of -55 °C) or lower, preferably 1 ppm or lower, more preferably 10 ppb or lower) may be introduced into the same furnace. It is preferable that water, hydrogen, etc. are not contained in the oxygen gas or dinitrogen monoxide gas. Or, the purity of the oxygen gas or dinitrogen monoxide gas introduced into the heat treatment apparatus is preferably 6N or higher, more preferably 7N or higher (i.e., the impurity concentration in the oxygen gas or dinitrogen monoxide gas is 1 ppm or lower, preferably 0.1 ppm or lower). By the action of the oxygen gas or dinitrogen monoxide gas, the main component material of the oxide semiconductor that has decreased simultaneously due to the impurity elimination step by dehydration or dehydrogenation treatment, that is, oxygen, is supplied, whereby the oxide semiconductor layer can be made highly pure and i-type (intrinsic).

[0118] Also, there is a possibility that oxygen, which is the main component material constituting the oxide semiconductor, may be simultaneously desorbed and decreased by dehydration or dehydrogenation treatment. Therefore, oxygen (including at least any one of oxygen radicals, oxygen atoms, and oxygen ions) may be introduced into the oxide semiconductor layer that has undergone dehydration or dehydrogenation treatment to supply oxygen into the film.

[0119] Oxygen is introduced into an oxide semiconductor layer that has undergone dehydration or dehydrogenation treatment to supply oxygen to the film. By doing so, the oxide semiconductor layer can be made highly pure and i-type (intrinsic). Transistors with purified and i-type (intrinsic) oxide semiconductors exhibit suppressed variations in electrical properties. It is controlled and electrically stable.

[0120] When introducing oxygen into the oxide semiconductor layer 408, it may be introduced directly into the oxide semiconductor layer 408. It may also be introduced into the oxide semiconductor layer 408 by passing through the insulating layer that is formed later. Even if not present, the method of introducing oxygen radicals, oxygen atoms, or oxygen ions is as follows: Ion implantation, ion doping, plasma immersion ion implantation, plasma treatment Methods such as the following can be used. Furthermore, oxygen-containing gases can be used for the oxygen introduction treatment. Yes. Gases containing oxygen include oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, and carbon dioxide. Carbon and other materials can be used. In addition, in the oxygen introduction treatment, noble gases can be added to the oxygen-containing gas. It may be included.

[0121] For example, when implanting oxygen ions into an oxide semiconductor layer 408 using the ion implantation method, the dose amount to 1 × 10 13 ions / cm 2 The above 5 x 10 16 ions / cm 2 The following is correct.

[0122] Alternatively, the oxide insulating layer 406 in contact with the oxide semiconductor layer is a layer that includes an oxygen-rich region, By performing heat treatment while the oxide insulating layer 406 and the oxide semiconductor layer 408 are in contact, The excess oxygen contained in the oxide insulating layer 406 is diffused into the oxide semiconductor layer 408, Oxygen may be supplied to the conductive layer 408. This heat treatment is part of the transistor manufacturing process. It can also be used in conjunction with the heat treatment process.

[0123] To create an oxygen-rich region in the oxide insulating layer 406, for example, the oxide insulating layer is subjected to an oxygen atmosphere. A layer can be formed. Alternatively, oxygen can be introduced into the oxide insulating layer after film formation to form the oxide insulating layer 40 A region with excess oxygen may be formed in 6.

[0124] The supply of oxygen to the oxide insulating layer 406 or the oxide semiconductor layer 408 is performed on the oxide insulating layer or oxidation The timing is not particularly limited after the deposition of the semiconductor layer. Also, the introduction of oxygen is You can do it multiple times.

[0125] Next, a conductive film is formed on the oxide semiconductor layer 408, and this is processed to form a source electrode layer 410. Form a and drain electrode layer 410b (see Figure 3(C)).

[0126] For example, Al, Cr, and Cu can be used as the source electrode layer 410a and the drain electrode layer 410b. A metal film containing an element selected from Ta, Ti, Mo, and W, or a metal film containing the above-mentioned elements as components. By using metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. This can be done. Also, Ti, M can be placed on either the underside or upperside of a metal film such as Al or Cu, or on both sides. High melting point metal films such as o, W, or their metal nitride films (titanium nitride film, molybdenum nitride film) A configuration in which films (tungsten nitride films) are stacked may also be used. Furthermore, the source electrode layer 410a The drain electrode layer 410b may also be formed of a conductive metal oxide. Examples of oxides include indium oxide (In2O3), tin oxide (SnO2), and zinc oxide (ZnO2). ) Indium tin oxide (In2O3-SnO2), indium zinc oxide (In 2O3-ZnO), or a material obtained by adding silicon oxide to these metal oxide materials can be used. It is possible.

[0127] Also, as the source electrode layer 410a and the drain electrode layer 410b, an In-Ga- Zn-O film containing nitrogen, an In-Sn-O film containing nitrogen, an In-Ga-O film containing nitrogen, an I n-Zn-O film containing nitrogen, a Sn-O film containing nitrogen, an In-O film containing nitrogen, etc., a metal nitride film can be used. Since these films contain the same constituent elements as the oxide semiconductor layer 408, the interface with the oxide semiconductor layer 408 can be stabilized. For example, as the source electrode layer 410a and the drain electrode layer 410b, a laminated structure of an In-Ga-Zn-O film containing nitrogen and a tungsten film can be applied from the side in contact with the oxide semiconductor layer 408. and the drain electrode layer 410b, a laminated structure of an In-Ga-Zn-O film containing nitrogen and a tungsten film can be applied from the side in contact with the oxide semiconductor layer 408. and the drain electrode layer 410b, a laminated structure of an In-Ga-Zn-O film containing nitrogen and a tungsten film can be applied from the side in contact with the oxide semiconductor layer 408.

[0128] Next, an oxide insulating layer 412 is formed so as to cover the source electrode layer 410a, the drain electrode layer 410b, and the exposed oxide semiconductor layer 4 08. The oxide insulating layer 412 can be formed by the same material and the same manufacturing method as the oxide insulating layer 406. The oxide insulating layer 412 can be formed by the same material and the same manufacturing method as the oxide insulating layer 406.

[0129] Thereafter, a protective insulating layer 414 is formed on the oxide insulating layer 412 (see Fig. 3(D)).

[0130] The protective insulating layer 414 can be formed by plasma CVD method or sputtering method, and a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, an oxynitride silicon film, an oxynitride aluminum film, or a silicon oxynitride film, etc., can be used. The protective insulating layer 414 can be formed by plasma CVD method or sputtering method, and a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, an oxynitride silicon film, an oxynitride aluminum film, or a silicon oxynitride film, etc., can be used. However, the protective insulating layer 414 is a silicon film containing nitrogen, more preferably a silicon nitride film By including a layer containing this, static damping on the semiconductor device during or after the manufacturing process is achieved. This is preferable because it makes it possible to further reduce electrical breakdown.

[0131] As described above, the transistor 310 of this embodiment can be formed.

[0132] <Example of semiconductor device configuration 3> Figures 10(A) to 10(C) show examples of the configuration of transistor 320. Figure 10(A) is Figure 10(B) is a plan view of transistor 320, and the dashed line X3-Y3 in Figure 10(A) This is a cross-sectional view, and Figure 10(C) is a cross-section along the dashed line V3-W3 in Figure 10(A). This is a diagram.

[0133] The transistor 320 shown in Figure 10, like the transistor 300 in Figure 1, has an insulating surface. A gate electrode layer 402 is provided on the substrate 400, and a gate insulating layer on the gate electrode layer 402. Edge layer 404, oxide insulating layer 406 on gate insulating layer 404, and on oxide insulating layer 406 An oxide semiconductor layer 408 that is in contact with and superimposed on the gate electrode layer 402, and the oxide semiconductor layer 408 It includes an electrically connected source electrode layer 410a and a drain electrode layer 410b. It covers the source electrode layer 410a and the drain electrode layer 410b and is in contact with the oxide semiconductor layer 408. A transistor consists of an oxide insulating layer 412 and a protective insulating layer 414 on the oxide insulating layer 412. It may also be used as a component of 320.

[0134] The structure of transistor 320 consists of a gate insulating layer 404 and an oxide semiconductor layer 408. It differs from transistor 300. That is, in transistor 320, the gate insulating layer 404 is The gate insulating layer 404c in contact with the gate electrode layer 402, and the gate on the gate insulating layer 404c The insulating layer 404a and the gate insulating layer 404a and the oxide insulating layer 406 are provided together. It is composed of an insulating layer 404b and a transistor 320. The conductive layer 408, like the transistor 310, is in contact with the oxide insulating layer 406. It comprises a body layer 408a and an oxide semiconductor layer 408b in contact with the oxide insulating layer 412. It will be done.

[0135] In addition, in transistor 320, other than the gate insulating layer 404 and the oxide semiconductor layer 408, The configuration is the same as that of transistor 300, so please refer to the explanation for transistor 300. It is possible.

[0136] Furthermore, the structure of the oxide semiconductor layer 408 included in transistor 320 is the same as that of transistor 31 It is the same as 0, and the explanation for transistor 310 can be considered. However, In the lampistor 320, the oxide semiconductor layer 408b is in the oxide insulating layer 412 and The film thickness of the contact region is the same as the film thickness of the region in contact with the source electrode layer 410a and the drain electrode layer 410b. This example illustrates a case where the thickness is smaller than the film thickness. The region with the small film thickness is the source electrode layer 410a. Furthermore, when processing the conductive film that will become the drain electrode layer 410b, a portion of it is etched. Alternatively, an oxide semiconductor layer is formed after the source electrode layer 410a and drain electrode layer 410b are formed. It is formed by etching the exposed area of ​​408b. The region below functions as the channel formation region of transistor 320. By reducing the film thickness of the layer formation region, the source electrode layer 410a and the drain electrode layer 410 The resistance of the region in contact with b can be reduced compared to the channel formation region. Therefore, - The contact resistance between the electrode layer 410a and the drain electrode layer 410b can be reduced. It becomes Noh.

[0137] The gate insulating layer 404 included in transistor 320 is in contact with the gate electrode layer 402. A gate insulating layer 404c, a gate insulating layer 404a in contact with the gate insulating layer 404c, and an oxide It is composed of an insulating layer 406 and a gate insulating layer 404b in contact with the insulating layer 406.

[0138] In this embodiment, gate insulating layer 404c, gate insulating layer 404a and gate insulating layer 40 A silicon nitride film is used as 4b, and each gate insulating layer is continuously processed by plasma CVD. Formation. First, the supply gas is a mixture of silane (SiH4) and nitrogen (N2) as the gas. After forming a silicon nitride film which will become the insulating layer 404c, the supply gas is silane (SiH4), Switch to a mixed gas of nitrogen (N2) and ammonia (NH3) and apply it to the gate insulating layer 404a. A silicon nitride film is formed, and then the supply gas is silane (SiH4) and nitrogen (N2 The mixture gas is switched to a silicon nitride film that will become the gate insulating layer 404b.

[0139] Gate insulating layer 404 formed by supplying a mixed gas of silane (SiH4) and nitrogen (N2) c is a mixture of at least silane (SiH4), nitrogen (N2), and ammonia (NH3). The ammonia in the film formation atmosphere and within the film is greater than that of the gate insulating layer 404a formed by supplying the ammonia. A can be reduced. Ammonia is a metal due to the action of the lone pair of electrons on the nitrogen atom. It acts as a ligand in the complex. Therefore, for example, when copper is used as the gate electrode layer 402, If a gate insulating layer with a high monia content is provided in contact with the gate electrode layer, the following formula is obtained: The reaction shown in 1) may cause copper to diffuse into the gate insulating layer.

[0140]

number

[0141] In the transistor 320 shown in Figure 10, at least the ammonia is greater than the gate insulating layer 404a. A gate insulating layer 404c with a low content of A is provided in a manner that it is in contact with the gate electrode layer 402. Therefore, the material of the gate electrode layer 402 (for example, copper) diffuses into the gate insulating layer 404. This can be suppressed. That is, the gate insulating layer 404c constitutes the gate electrode layer 402. It can function as a barrier film against metal materials. A gate insulating layer 404c is provided. This can further improve the reliability of the transistor.

[0142] Furthermore, in the gate insulating layer 404 included in transistor 320, The configuration of a and the gate insulating layer 404b can be the same as that of transistor 310. By including a gate insulating layer having the above configuration, electrostatic discharge damage to the transistor is prevented, and This can impart stable electrical characteristics to transistors, resulting in highly reliable semiconductor devices. This becomes possible.

[0143] The thickness of the gate insulating layer 404c is 30 nm to 100 nm, preferably 30 nm or more. The wavelength shall be 50 nm or less. In addition, as mentioned above, a gate shall be provided as a measure against electrostatic discharge damage to the transistor. The thickness of the insulating layer 404a is preferably 300 nm or more and 400 nm or less, and oxidation Gate insulating layer 404 functions as a barrier film to prevent hydrogen diffusion into the semiconductor layer 408. The thickness of b is preferably 25 nm or more and 150 nm or less. However, the gate insulating layer 4 04 film thickness (gate insulating layer 404c, gate insulating layer 404a and gate insulating layer 404b) The thickness of each gate insulating layer is such that the total thickness is between 355 nm and 550 nm. It is preferable to adjust as needed.

[0144] <Example of semiconductor device configuration 4> Figures 11(A) to 11(C) show examples of the configuration of transistor 330. Figure 11(A) is Figure 11(B) is a plan view of transistor 330, and the dashed line X4-Y4 in Figure 11(A) This is a cross-sectional view, and Figure 11(C) is a cross-section along the dashed line V4-W4 in Figure 11(A). This is a diagram.

[0145] The transistor 330 shown in Figure 11 is a gate provided on a substrate 400 having an insulating surface. Electrode layer 402, gate insulating layer 404 on gate electrode layer 402, and on gate insulating layer 404 The oxide insulating layer 406 and the gate electrode layer 402 which are in contact with the oxide insulating layer 406 Oxide semiconductor layer 408 and source electrode layer 410 electrically connected to oxide semiconductor layer 408 a and drain electrode layer 410b, and source electrode layer 410a and drain electrode layer 410b Covering and in contact with the oxide semiconductor layer 408, an oxide insulating layer 412 and a retaining layer on the oxide insulating layer 412 Includes a protective insulating layer 414.

[0146] In transistor 330, the protective insulating layer 414 is in contact with the oxide insulating layer 412. It has a laminated structure of an edge layer 414a and a protective insulating layer 414b on the protective insulating layer 414a, A silicon nitride film can be applied to each of them.

[0147] The protective insulating layer 414a has the same configuration as the gate insulating layer 404b of the transistor 310. This can be achieved. By providing a protective insulating layer 414a, the oxide insulating layer 412 and acid Because the incorporation of hydrogen or hydrogen compounds into the hydrogenated semiconductor layer 408 can be suppressed, This allows for greater stability of the electrical properties of the zista.

[0148] The protective insulating layer 414b has the same configuration as the gate insulating layer 404a of transistor 310. This can be achieved by providing a protective insulating layer 414b, which can be used during the manufacturing process or after formation. This makes it possible to further reduce electrostatic discharge (ESD) to semiconductor devices.

[0149] Furthermore, the other components of transistor 330 are configured in the same way as those of transistor 310. This allows us to refer to the explanation of transistor 310.

[0150] Note that the transistors shown in Figures 1, 2, 10, and 11 each have slightly different configurations. However, the present invention is not particularly limited, and various combinations are possible.

[0151] The transistor shown in this embodiment has a thick silicon film containing nitrogen as the gate insulating layer. For example, it contains at a wavelength of 325 nm to 550 nm, and the gate insulating layer and the oxide semiconductor The layer comprises one or more metallic elements selected from the constituent elements of the oxide semiconductor layer. It is composed of an oxide insulating layer. The silicon film containing nitrogen is used in practical quantities. It is possible to form a film by applying industrial technology, and the silicon film containing nitrogen can be formed as a thick film. By doing so, the gate insulating layer is physically thickened, suppressing the decrease in the transistor's dielectric breakdown voltage. Furthermore, by improving the dielectric strength, electrostatic discharge damage to semiconductor devices can be suppressed. By including an oxide insulating layer, the interface with the oxide semiconductor layer can be stabilized, and the interface This can suppress the trapping of charge on the surface. Therefore, transistor degradation can be reduced. This prevents defects and allows for the creation of highly reliable transistors.

[0152] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0153] (Embodiment 2) A semiconductor device (also known as a display device) having a display function using the transistor shown in Embodiment 1. It is possible to manufacture (the said). Also, part or all of a drive circuit including a transistor The pixel section can be integrally formed on the same substrate, allowing for the creation of a system-on-panel configuration.

[0154] In Figure 4(A), the pixel portion 4002 provided on the substrate 4001 is surrounded by A material 4005 is provided and sealed by a substrate 4006. In Figure 4(A) This is in a region different from the region surrounded by the sealing material 4005 on the substrate 4001, I A single-crystal semiconductor film or a polycrystalline semiconductor film formed on a C chip or a separately prepared substrate. A scan line drive circuit 4004 and a signal line drive circuit 4003 are implemented. Various signals are supplied to the pixel unit 4002 through the path 4003 and the scan line driving circuit 4004, and The potential is FPC (Flexible printed circuit) 4018a, 4 It is supplied from 018b.

[0155] In Figures 4(B) and 4(C), the pixel portion 4002 provided on the substrate 4001 and the running A sealing material 4005 is provided so as to surround the probe drive circuit 4004. A substrate 4006 is provided on top of the element 4002 and the scan line driving circuit 4004. The pixel section 4002 and the scanning line driving circuit 4004 are connected by a substrate 4001 and a sealing material 4005 and a base The display element is sealed together with plate 4006. In Figures 4(B) and (C) This is in a region different from the region surrounded by the sealing material 4005 on the substrate 4001, I A single-crystal semiconductor film or a polycrystalline semiconductor film formed on a C chip or a separately prepared substrate. The signal line drive circuit 4003 is implemented. In Figures 4(B) and 4(C), the signal Various signals are supplied to the pixel unit 4002 through the line drive circuit 4003 and the scan line drive circuit 4004. The signals and potentials are supplied from the FPC4018.

[0156] Furthermore, in Figures 4(B) and 4(C), the signal line drive circuit 4003 is formed separately on the substrate. An example implemented in the 4001 is shown, but the configuration is not limited to this. Alternatively, they may be formed and implemented separately, or only a part of the signal line drive circuit or a part of the scan line drive circuit may be used. It may be formed and implemented separately.

[0157] Furthermore, the method of connecting the separately formed drive circuit is not particularly limited, and COG(Ch ip On Glass) method, wire bonding method, or TAB (Tape A Methods such as utmost bonding can be used. Figure 4(A) shows C This is an example of implementing the signal line drive circuit 4003 and the scan line drive circuit 4004 using the OG method. Figure 4(B) shows an example of implementing the signal line drive circuit 4003 using the COG method, and Figure 4(C) shows an example of implementing the signal line drive circuit 4003 using the COG method. This is an example of implementing the signal line drive circuit 4003 using the TAB method.

[0158] A display device is a panel in which the display elements are sealed, and a controller on the panel Includes a module on which ICs, etc., including ra are mounted. That is, in this specification A display device refers to an image display device, a display device, or a light source (including lighting devices). Furthermore, this applies not only to panels where the display elements are sealed, but also to connectors, such as FP. A module with either C or TCP attached, with a printed circuit board located beyond the TCP port. A module or display element on which an IC (integrated circuit) is directly mounted using the COG method. All chures shall also be included in the display device.

[0159] Furthermore, the pixel section and scanning line driving circuit provided on the substrate have multiple transistors. The transistor shown in Embodiment 1 can be applied.

[0160] Display elements provided in a display device include liquid crystal elements (also called liquid crystal display elements) and light-emitting elements ( A light-emitting element (also called a light-emitting display element) can be used. The light-emitting element's brightness is determined by current or voltage. This category includes elements whose properties are controlled, specifically inorganic EL (Electroluminescent Luminous Light). This includes (minescence), organic EL, etc. Also, electronic ink display devices (electronic paper) Display media where the contrast changes due to electrical effects, such as (P) displays, can also be applied. .

[0161] One form of semiconductor device will be explained using Figures 4 to 6. Figure 6 is M of Figure 4(B). - This corresponds to a cross-sectional view in N.

[0162] As shown in Figures 4 and 6, the semiconductor device has connection terminal electrodes 4015 and terminal electrodes 4016. It has, and the connecting terminal electrodes 4015 and 4016 are FPC4018, 4018b It is electrically connected to the terminals it possesses via an anisotropic conductive layer 4019.

[0163] The connecting terminal electrode 4015 is formed from the same conductive layer as the first electrode layer 4034, and the terminal electrode 4 016 is the same conductive material as the source electrode layer and drain electrode layer of transistors 4010 and 4011. It is formed by an electrochemical layer.

[0164] Furthermore, the pixel section 4002 and the scanning line driving circuit 4004 provided on the substrate 4001 are connected by a transistor It has multiple transistors, and in Figure 6, the transistor 4010 included in the pixel section 4002 and This illustrates the transistor 4011 included in the scan line drive circuit 4004. Figure 6(A ) In this case, an oxide insulating layer 4030 and a protective insulating layer are placed on transistors 4010 and 4011. 4032 is provided, and in Figure 6(B), an insulating layer 40 that functions as a planar insulating layer is also provided. 21 is provided.

[0165] For transistors 4010 and 4011, the transistors shown in Embodiment 1 are used. This is possible. In this embodiment, the transistor 300 is similar to the one shown in Embodiment 1. An example of applying transistors with a structure is shown. Transistors 4010 and 4011 are... This is a transistor with a Tomgate structure.

[0166] Transistors 4010 and 4011 are oxide insulating layers that are in contact with the oxide semiconductor layer. Layer 4020b and oxide insulating layer 4030 are selected from the constituent elements of the oxide semiconductor layer. An oxide insulating layer containing one or more metal elements is applied, and the gate insulating layer 4020a and The device has a thick silicon film containing nitrogen (for example, a film thickness of 325 nm to 550 nm). These are transistors. Therefore, transistors 4010 and 4011 have suppressed electrical characteristic fluctuations. It is controlled, and electrostatic discharge is suppressed.

[0167] Furthermore, it overlaps with the channel formation region of the oxide semiconductor layer of transistor 4011 for the drive circuit. A conductive layer may be provided at the same location. The conductive layer may overlap with the channel formation region of the oxide semiconductor layer. By positioning it in such a location, the change in the threshold voltage of transistor 4011 can be further reduced. It can be reduced. Also, the conductive layer has the same potential as the gate electrode layer of transistor 4011. They can be the same or different, and they can also function as a second gate electrode layer. Furthermore, the potential of the conductive layer may be in a floating state.

[0168] Furthermore, the conductive layer shields against external electric fields, that is, external electric fields do not penetrate the internal (including transistors). It also has a function to prevent it from affecting the circuit (particularly an electrostatic shielding function against static electricity). Due to the shielding function of the conductive layer, the electrical properties of the transistor are affected by external electric fields such as static electricity. This prevents the characteristics from fluctuating.

[0169] The transistor 4010 provided in the pixel section 4002 is electrically connected to the display element, and the display The panel is constructed using various display elements, as long as they can perform a display. You can use it.

[0170] Figure 6(A) shows an example of a liquid crystal display device using liquid crystal elements as display elements. The liquid crystal element 4013 comprises a first electrode layer 4034, a second electrode layer 4031, and a liquid crystal layer Includes 4008. Furthermore, insulating layer 4 functions as an alignment layer, sandwiching the liquid crystal layer 4008. Layers 038 and 4033 are provided. The second electrode layer 4031 is provided on the substrate 4006 side. The first electrode layer 4034 and the second electrode layer 4031 are stacked via a liquid crystal layer 4008. It is complete.

[0171] Furthermore, spacer 4035 is a columnar spacer obtained by selectively etching the insulating layer. It is provided to control the film thickness (cell gap) of the liquid crystal layer 4008. Spherical spacers may also be used.

[0172] When using liquid crystal elements as display elements, thermotropic liquid crystals, ferroelectric liquid crystals, and anti-ferroelectric liquid crystals are used. Electrolytic liquid crystals can be used. These liquid crystal materials can be low-molecular-weight compounds or high-molecular-weight compounds. However, this is also acceptable. These liquid crystal materials (liquid crystal compositions) can, depending on the conditions, form a cholesteric phase and a smeck. It exhibits phases such as the tic phase, cubic phase, chiral nematic phase, and isotropic phase.

[0173] Furthermore, a liquid crystal composition that exhibits a blue phase without using an alignment film may be used for the liquid crystal layer 4008. In this case, the liquid crystal layer 4008, the first electrode layer 4034, and the second electrode layer 4031 are The structure is in contact with each other. The blue phase is one of the liquid crystal phases, and the cholesteric liquid crystal is heated up. This is a phase that appears just before the transition from the cholesteric phase to the isotropic phase. The blue phase is a liquid crystal. Furthermore, it can be expressed using a liquid crystal composition mixed with a chiral agent. To broaden the temperature range in which the phase manifests, polymerizable monomers are added to the liquid crystal composition that manifests the blue phase. Furthermore, a polymerization initiator and other substances may be added to stabilize the polymer and form a liquid crystal layer. Yes, it is possible. Liquid crystal compositions that exhibit the blue phase have a short response speed and are optically isotropic, so No alignment processing is required, and it has low viewing angle dependence. Also, since an alignment layer is not required, it is not a Rabin Since rubbing is also unnecessary, it prevents electrostatic discharge damage caused by rubbing. This makes it possible to reduce defects and damage to liquid crystal displays during the manufacturing process. This will make it possible to improve the productivity of the display device.

[0174] Furthermore, the resistivity of the liquid crystal material is 1 × 10⁻⁶ 9 The value is Ω·cm or greater, preferably 1 × 10⁻⁶. 11 It is Ω·cm or greater, and more preferably 1 × 10⁻⁶ 12 It is greater than Ω·cm. Furthermore, this specification... The resistivity values ​​in this document shall be those measured at 20°C.

[0175] The size of the retention capacitance provided in a liquid crystal display device depends on the regeneration of the transistors arranged in the pixel area. The system is set to hold the charge for a predetermined period of time, taking into account the current and other factors. The size should be set considering the transistor's off-current, etc. The oxidation disclosed herein By using a transistor with a material semiconductor layer, the liquid crystal capacitance at each pixel is It is sufficient to provide a holding capacity having a size of 1 / 3 or less, preferably 1 / 5 or less of the capacity. ru.

[0176] The transistor using the oxide semiconductor layer disclosed herein has an off-state current value ( The off-current value can be controlled to be low. Therefore, the holding time of electrical signals such as image signals can be controlled. It can be made longer, and the write interval can also be set to be longer. Therefore, the frequency of refresh operations Because it can reduce power consumption, it has the effect of suppressing power consumption.

[0177] Furthermore, transistors using oxide semiconductor layers disclosed herein have a relatively high field effect. Because mobility is obtained, high-speed driving is possible. For example, such transistors can be used in liquid crystals. When used in a display device, the switching transistors in the pixel section and the driving circuit section are used Driver transistors can be formed on the same substrate. Also, in the pixel area By using such transistors, high-quality images can be provided.

[0178] LCD displays include TN (Twisted Nematic) mode and IPS (In-Place Printed Display). lane-Switching) mode, FFS (Fringe Field Switching) mode ching) mode, ASM(Axially Symmetric aligned) Micro-cell mode, OCB (Optical Compensated B) irefringence) mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq. You can use modes such as UID Crystal.

[0179] Furthermore, normally black type liquid crystal display devices, such as those employing vertical alignment (VA) mode, It may also be used as a transmissive liquid crystal display device. Several vertical orientation modes are possible, For example, MVA (Multi-Domain Vertical Alignment) Mode, PVA (Patterned Vertical Alignment) mode Features such as ASV (Advanced Super View) mode can be used. Furthermore, it can also be applied to VA-type liquid crystal display devices. VA-type liquid crystal display devices are... This is a type of method for controlling the arrangement of liquid crystal molecules in a liquid crystal display panel. VA-type liquid crystal display devices are... This method involves the liquid crystal molecules oriented perpendicular to the panel surface when no voltage is applied. Furthermore, a pixel is divided into several subpixel regions, each in a different direction. This is called multi-domainization or multi-domain design, which is a method of knocking down molecules. A method can be used.

[0180] Furthermore, in a display device, the black matrix (light-shielding layer), polarizing member, phase difference member, and reflector are used. Optical components (optical substrates) such as protective members are provided as appropriate. For example, polarizing substrates and phase difference substrates Circularly polarized light from a plate may be used. Also, backlights, sidelights, etc., may be used as light sources. It's okay to be there.

[0181] Furthermore, the display method used in the pixel area may be a progressive or interlaced method. It is possible. Also, when displaying in color, the color elements controlled by pixels are RGB (R is It is not limited to the three colors (red, green, and blue). For example, RGBW (where W represents white). Alternatively, some models use RGB with one or more additional colors such as yellow, cyan, or magenta. The size of the display area for each dot of the color element may differ. However, the disclosed invention This applies not only to color display devices, but also to monochrome display devices. It is also possible.

[0182] Furthermore, as a display element included in the display device, an electroluminescent light-emitting element is used. It can be applied to light-emitting devices that utilize electroluminescence. They are distinguished by whether they are organic or inorganic compounds, and generally the former are organic E The latter is called an L element, and the latter an inorganic EL element.

[0183] Organic EL elements emit electrons and holes from a pair of electrodes when a voltage is applied to the light-emitting element. Each of these is injected into a layer containing a luminescent organic compound, and an electric current flows through it. Then, these... The recombination of electrons and holes causes the luminescent organic compound to form an excited state. And when that excited state returns to the ground state, it emits light. From this mechanism, Such a light-emitting element is called a current-excited light-emitting element. In this embodiment, the light-emitting element is An example using an electroluminescent element is shown.

[0184] Inorganic electroluminescent (EL) elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements based on their element configuration. They are classified as such. Dispersive inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The luminescence mechanism utilizes donor and acceptor levels, and the donor-acceptor level is the key to this process. This is a receptor recombination type light emission. Thin-film inorganic EL elements sandwich the light-emitting layer between dielectric layers. Furthermore, it has a structure where it is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. This is a localized light emission. Here, we will explain using an organic EL element as the light-emitting element. ru.

[0185] A light-emitting element only needs to have at least one of its pair of electrodes that is translucent in order to extract light. Then, a transistor and a light-emitting element are formed on the substrate, and light is extracted from the side opposite to the substrate. This includes top-side emission, bottom-side emission which extracts light from the substrate side, and emission from both the substrate side and the opposite side of the substrate. There are light-emitting elements with a double-sided emission structure that extract light from both sides, and any light-emitting element with an emission structure is applicable. It is possible.

[0186] Figures 5(A)(B) and 6(B) show examples of light-emitting devices that use light-emitting elements as display elements. .

[0187] Figure 5(A) is a plan view of the light-emitting device, and the dashed lines S1-T1 and S2-T2 in Figure 5(A) The cross-section cut at S3-T3 corresponds to Figure 5(B). Note that the plan view in Figure 5(A) is shown below. In this example, the electroluminescent layer 542 and the second electrode layer 543 are omitted and not shown in the diagram.

[0188] The light-emitting device shown in Figure 5 consists of a transistor 510, a capacitive element 520, and a wiring layer on a substrate 500. It has an intersection 530, and the transistor 510 is electrically connected to the light-emitting element 540. Figure 5 shows a bottom-export type light source that passes through the substrate 500 to extract light from the light-emitting element 540. It is a light-emitting device with a specific structure.

[0189] The transistor shown in Embodiment 1 can be used as the transistor 510. In this embodiment, the transistor 300 has a structure similar to that of the transistor 300 shown in Embodiment 1. An example of applying a transistor is shown. Transistor 510 is a bottom-gate transistor. He is a star.

[0190] Transistor 510 consists of gate electrode layers 511a, 511b, gate insulating layer 502, and oxide insulating layer. Edge layer 512, oxide semiconductor layer 514, and a conductive layer functioning as a source electrode layer or drain electrode layer Includes electrode layers 513a and 513b.

[0191] The transistor 510 is an insulating layer, an oxide insulating layer 51, which is in contact with the oxide semiconductor layer 514. 2. Includes one or more metallic elements selected from the constituent elements of the oxide semiconductor layer 514. An oxide insulating layer is applied, and a gate insulating layer 502 is made with a thick film (for example, film thickness 32 It contains a silicon film containing nitrogen (5 nm to 550 nm). This suppresses the trapping of charge at the interface between the oxide semiconductor layer 514 and the oxide insulating layer 512. This allows for improved electrical characteristics of transistor 510. It can prevent electrostatic discharge (ESD) failure. Therefore, it can produce highly reliable semiconductor devices with a high yield. It will be possible to provide this. Furthermore, as an insulating layer 524 in contact with the oxide semiconductor layer 514 It is preferable to apply an oxide insulating layer having the same structure as the oxide insulating layer 512. Furthermore, the insulating layer 525 in contact with the insulating layer 524 has the same configuration as the gate insulating layer 502. It is preferable to apply an insulating layer.

[0192] The capacitive element 520 consists of conductive layers 521a, 521b, a gate insulating layer 502, and an oxide insulating layer 52 2. Includes an oxide semiconductor layer 526, a conductive layer 523, conductive layers 521a, 521b and conductive layer 5 23 sandwiches the gate insulating layer 502, the oxide insulating layer 522, and the oxide semiconductor layer 526. By forming it, it creates a volume.

[0193] The wiring layer intersection 530 is the intersection of the gate electrode layers 511a and 511b and the conductive layer 533. There is a gate insulating layer 502 between the gate electrode layers 511a and 511b and the conductive layer 533. They intersect via this.

[0194] In this embodiment, the gate electrode layer 511a and the conductive layer 521a have a film thickness of 30 nm. Using a titanium film, the gate electrode layer 511b and the conductive layer 521b are made of copper with a thickness of 200 nm. Thin films are used. Therefore, the gate electrode layer has a layered structure of a titanium film and a copper thin film.

[0195] For the oxide semiconductor layers 514 and 526, an In-Ga-Zn-O film with a thickness of 25 nm is used. .

[0196] An interlayer insulating layer 504 is placed on the transistor 510, the capacitive element 520, and the wiring layer intersection 530. A color fill is formed on the interlayer insulating layer 504 in the region that overlaps with the light-emitting element 540. A flat layer 505 is provided. A flat surface is provided on the interlayer insulating layer 504 and the color filter layer 505. An insulating layer 506 that functions as a chemical insulating layer is provided.

[0197] A first electrode layer 541, an electroluminescent layer 542, and a second electrode layer 543 are stacked on the insulating layer 506 in that order. A light-emitting element 540 is provided, which includes a layered stacked structure. The light-emitting element 540 and a transistor 510 refers to the opening formed in the insulating layer 506 and the interlayer insulating layer 504 that reach the conductive layer 513a. At the mouth, the first electrode layer 541 and the conductive layer 513a are electrically connected by contact. Furthermore, a partition wall 507 is provided to cover a portion of the first electrode layer 541 and the opening. It is being done.

[0198] The insulating layer 506 has a photosensitive acrylic film with a thickness of 1500 nm, and the partition wall 507 has a thickness of 1500 A photosensitive polyimide film with a thickness of nm can be used.

[0199] For the color filter layer 505, for example, a translucent resin with a chromatic color can be used. As the translucent resin for coloring, photosensitive and non-photosensitive organic resins can be used, but Using a non-stick organic resin layer reduces the number of resist masks, thus simplifying the process. And it is preferable.

[0200] Chromatic colors are colors other than achromatic colors such as black, gray, and white, and the color filter layer is a colored chromatic color. It is made of a material that transmits only colored light. Colors used include red, green, and blue. It is possible to use cyan, magenta, yellow, etc. Transmitting only chromatic light means that the transmitted light in the color filter layer is limited to that chromatic color. This means that it has a peak at the wavelength of light. The color filter layer contains coloring material It is best to appropriately control the optimal film thickness by considering the relationship between the concentration and light transmittance. For example, The thickness of the filter layer 505 should be between 1500 nm and 2000 nm.

[0201] In the light-emitting device shown in Figure 6(B), the light-emitting element 4513 is provided in the pixel section 4002. It is electrically connected to transistor 4010. The configuration of the light-emitting element 4513 is as follows: The structure is a laminated structure of electrode layer 4034, electroluminescent layer 4511, and second electrode layer 4031, as shown. The configuration is not limited to this. The light emission is adjusted according to the direction of the light extracted from the light-emitting element 4513. The configuration of element 4513 can be changed as needed.

[0202] Partition walls 4510 and 507 are formed using organic or inorganic insulating materials. Particularly photosensitive. Using a resin material, an opening is formed on the first electrode layers 4034, 541, and the opening It is preferable to form the side walls into inclined surfaces with a continuous curvature.

[0203] Even if the electroluminescent layers 4511 and 542 consist of a single layer, multiple layers are stacked together. It doesn't matter whether it's composed of seaweed or something else.

[0204] To prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting elements 4513 and 540, the second A protective film may be formed on the electrode layers 4031, 543 and the partition walls 4510, 507. The film can be formed from silicon nitride film, silicon nitride oxide film, DLC film, etc. .

[0205] Furthermore, to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting elements 4513 and 540, Alternatively, a layer containing an organic compound covering the light-emitting elements 4513 and 540 may be formed by vapor deposition.

[0206] Furthermore, the space sealed by substrate 4001, substrate 4006, and sealing material 4005 contains A filler material 4514 is provided and sealed. In this way, it is airtight so that it is not exposed to the outside air. High-performance protective films with minimal degassing (laminated films, UV-curing resin films, etc.) It is preferable to package (seal) the product with a cover material.

[0207] In addition to inert gases such as nitrogen and argon, filler material 4514 may also be ultraviolet curing resin or Thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic resin, and poly Imide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (e A ethylene vinyl acetate copolymer can be used. For example, nitrogen can be used as a filler. Just be there.

[0208] Furthermore, if necessary, a polarizing plate or circular polarizing plate (including elliptical polarizing plate) may be placed on the emission surface of the light-emitting element. You may also appropriately incorporate optical films such as phase difference plates (λ / 4 plate, λ / 2 plate) and color filters. Furthermore, an anti-reflective coating may be provided on the polarizing plate or circular polarizing plate. For example, by the surface irregularities An anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0209] Furthermore, it is also possible to provide electronic paper that drives electronic ink as a display device. Electronic paper is also called an electrophoretic display device (electrophoretic display), and it is a paper-like material. It offers the same readability, lower power consumption compared to other display devices, and a thin and light form factor. It has the advantage of being such.

[0210] Electrophoresis display devices can take various forms, but one is a first particle with a positive charge and Multiple microcapsules, each containing a second particle having a negative charge, are dispersed in a solvent. This is a method where an electric field is applied to the microcapsules, and the particles inside the microcapsules are removed. This method involves moving the particles in opposite directions and displaying only the color of the particles that have gathered on one side. Furthermore, the first or second particle contains dye and does not move in the absence of an electric field. Furthermore, the color of the first particle and the color of the second particle are different (including colorless).

[0211] The above microcapsules dispersed in a solvent are called electronic ink. Color display is also possible by using a color filter or particles containing dyes.

[0212] In Figures 4 to 6, substrates 4001, 500, and 4006 are glass substrates. In addition to plates, flexible substrates can also be used, such as translucent plastic substrates. Boards and other similar materials can be used. As for plastics, FRP (Fiberglass- Reinforced Plastics) sheet, PVF (polyvinyl fluoride) sheet A film, polyester film, or acrylic resin film can be used. If light-sensitive materials are not required, use a metal substrate (metal film) such as aluminum or stainless steel. It is acceptable. For example, aluminum foil sandwiched between PVF film or polyester film. It is also possible to use sheets with a slab-like structure.

[0213] Furthermore, insulating layers 4021 and 506, which function as planar insulating layers, are made of acrylic resin, polyimi Heat-resistant organic materials such as benzocyclobutene resins, polyamides, and epoxy resins. In addition to the above organic materials, siloxane resins and PSG (Linguan) can be used. By using low-dielectric materials (low-k materials) such as lath and BPSG (limboron glass) This can be achieved. Furthermore, by stacking multiple insulating layers formed from these materials, an insulating layer 4 021 and 506 may be formed.

[0214] The method for forming the insulating layers 4021 and 506 is not particularly limited and depends on the material, such as sputtering. Spin coating, dip coating, spray coating, droplet ejection (inkjet method), spray Lean printing, offset printing, etc., can be used.

[0215] The first electrode layers 4034, 541 and the second electrode layers 4031, 543 contain tungsten oxide. Contains indium oxide, indium zinc oxide containing tungsten oxide, and titanium oxide. Indium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter (Indicated as ITO.) Indium zinc oxide, silicon oxide-added indium tin oxide. A transparent conductive material such as graphene can be used.

[0216] Furthermore, the first electrode layers 4034, 541 and the second electrode layers 4031, 543 are made of tungsten. W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium ( V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel Ni (Ni), Titanium (Ti), Platinum (Pt), Aluminum (Al), Copper (Cu), Silver ( Using one or more metals such as Ag, or their alloys, or their metal nitrides It can be formed.

[0217] In this embodiment, the light-emitting device shown in Figure 5 is a bottom-extrusion type, so the first electrode layer 541 The first electrode layer 541 is translucent, and the second electrode layer 543 is reflective. Therefore, the metal film When using this, the film thickness should be thin enough to maintain light transmission, and the second electrode layer 543 should have light transmission When using an electrolytic layer, it is advisable to laminate a conductive layer that has reflective properties.

[0218] Furthermore, the first electrode layers 4034, 541 and the second electrode layers 4031, 543 are made of highly conductive material. It can be formed using a conductive composition containing molecules (also called conductive polymers). As the electrochemical polymer, so-called π-electron conjugated conductive polymers can be used. , polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its A derivative, or a copolymer consisting of two or more of aniline, pyrrole, and thiophene. Examples include its derivatives.

[0219] Furthermore, a protection circuit for protecting the drive circuit may be provided. The protection circuit is configured using nonlinear elements. It is preferable to do so.

[0220] As described above, by applying the transistor shown in Embodiment 1, various functions can be obtained. We can provide semiconductor devices.

[0221] The configurations and methods shown in this embodiment may be combined with the configurations and methods shown in other embodiments as appropriate. They can be used together.

[0222] (Embodiment 3) An image sensor device that reads information about an object using the transistor shown in Embodiment 1. A semiconductor device with the necessary capabilities can be fabricated.

[0223] Figure 7(A) shows an example of a semiconductor device having an image sensor function. This is the equivalent circuit of the photosensor, and Figure 7(B) is a cross-sectional view showing a part of the photosensor.

[0224] Photodiode 602 has one electrode connected to the photodiode reset signal line 658, and the other electrode connected to the photodiode reset signal line 658. One electrode is electrically connected to the gate of transistor 640. Transistor 640 In this case, either the source or the drain is connected to the photosensor reference signal line 672, and the source or drain The other end is electrically connected to either the source or the drain of transistor 656. The transistor 656 has its gate connected to the gate signal line 659, and the other of its source or drain connected to the gate signal line 659. It is electrically connected to the sensor output signal line 671.

[0225] Furthermore, in the circuit diagrams in this specification, transistors using oxide semiconductor layers are clearly defined. To make it clear, the symbol for a transistor using an oxide semiconductor layer is written as "OS". In Figure 7(A), transistors 640 and 656 are in Embodiment 1. The transistor shown is applicable and uses an oxide semiconductor layer. In terms of form, it is a transistor having a structure similar to the transistor 300 shown in Embodiment 1. An example of its application is shown. Transistor 640 is a bottom-gate transistor.

[0226] Figure 7(B) shows the photodiode 602 and transistor 640 in the photosensor. This is a cross-sectional view showing a substrate 601 (element substrate) having an insulating surface, which functions as a sensor. A photodiode 602 and a transistor 640 are provided. A substrate 613 is provided on top of transistor 640 using an adhesive layer 608. .

[0227] On transistor 640 are insulating layer 631, insulating layer 632, interlayer insulating layer 633, interlayer insulating layer 634 is provided. The photodiode 602 is formed on the interlayer insulating layer 633. The electrode layer 641b, and the first semiconductor film 606a and the second semiconductor film are sequentially stacked on the electrode layer 641b. Body film 606b and third semiconductor film 606c are provided on the interlayer insulating layer 634, and the first to Electrode layer 642 is electrically connected to electrode layer 641b via a third semiconductor film, and electrode layer 64 It has an electrode layer 641a provided in the same layer as 1b and electrically connected to electrode layer 642, Yes, they are.

[0228] The electrode layer 641b is electrically connected to the conductive layer 643 formed on the interlayer insulating layer 634, and the electrode Layer 642 is electrically connected to the conductive layer 645 via electrode layer 641a. Conductive layer 645 It is electrically connected to the gate electrode layer of transistor 640, and photodiode 60 Point 2 is electrically connected to transistor 640.

[0229] Here, the first semiconductor film 606a is a semiconductor film having a p-type conductivity, and the second semiconductor film 606b is a high-resistance semiconductor film (i-type semiconductor film), and the third semiconductor film 606c is an n-type This example illustrates a pin-type photodiode in which conductive semiconductor films are stacked.

[0230] The first semiconductor film 606a is a p-type semiconductor film, and contains an amorphous impurity element that confers p-type properties. It can be formed by a silicon film. The formation of the first semiconductor film 606a requires a group 13 silicon Using a semiconductor material gas containing impurity elements (e.g., boron (B)) in the plasma CVD method It is formed from this. Silane (SiH4) can be used as the semiconductor material gas. Alternatively, S i2H6, SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. may also be used. Furthermore, after forming an amorphous silicon film free of impurity elements, diffusion or ion implantation is performed. Impurity elements may be introduced into the amorphous silicon film using methods such as ion implantation. It is best to introduce impurity elements first, and then perform heating or other methods to diffuse them. In this case, methods for forming amorphous silicon films include LPCVD, vapor phase growth, Alternatively, sputtering or the like may be used. The thickness of the first semiconductor film 606a should be 10 nm or more. It is preferable to form it so that the size is 0 nm or less.

[0231] The second semiconductor film 606b is an i-type semiconductor film (intrinsic semiconductor film) and is amorphous silicon. It is formed by a film. For the formation of the second semiconductor film 606b, a semiconductor material gas is used to form an amorphous film. A fast silicon film is formed by plasma CVD. Silane is used as the semiconductor material gas. (SiH4) can be used. Alternatively, Si2H6, SiH2Cl2, SiHCl3, S iCl4, SiF4, etc. may be used. The formation of the second semiconductor film 606b is performed by LPCVD. This can be carried out by vapor phase growth, sputtering, etc. The thickness of the second semiconductor film 606b is 2 It is preferable to form the surface to be between 00 nm and 1000 nm.

[0232] The third semiconductor film 606c is an n-type semiconductor film containing an impurity element that confers n-type properties. It is formed by a fast silicon film. The formation of the third semiconductor film 606c involves impurity elements from Group 15. A semiconductor material gas containing an element (e.g., phosphorus (P)) is used to form a material by plasma CVD. For the semiconductor material gas, silane (SiH4) can be used. Alternatively, Si2H6, SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. may also be used. Furthermore, impurities may be present. After forming an amorphous silicon film that does not contain elements, using diffusion or ion implantation methods Impurity elements may be introduced into the amorphous silicon film by ion implantation or the like. It is advisable to diffuse impurity elements by heating or performing other methods after introducing the elements. In this case, Methods for forming morphous silicon films include LPCVD, vapor phase growth, or spasticity. Taring or similar methods can be used. The thickness of the third semiconductor film 606c should be between 20 nm and 200 nm. It is preferable to form it so that it is at the bottom.

[0233] Furthermore, the first semiconductor film 606a, the second semiconductor film 606b, and the third semiconductor film 606c are A It may also be formed using a polycrystalline semiconductor instead of a morphous semiconductor, or a microcrystalline (semi-aluminum) semiconductor. Rufus (Semi-Amorphous Semiconductor: SAS) It may be formed using a conductor.

[0234] Furthermore, because the mobility of holes generated by the photoelectric effect is smaller than that of electrons, the pin-type Photodiodes exhibit better characteristics when the p-type semiconductor film side is the light-receiving surface. Here, p From the surface of the substrate 601 on which the in-type photodiode is formed, the photodiode 602 This example shows how to convert light received by a device into an electrical signal. It also shows the opposite conductivity to the semiconductor film side that acts as the light-receiving surface. Since light from the semiconductor film side with a specific pattern becomes ambient light, the electrode layer uses a conductive layer with light-shielding properties. It would be good to have one. Also, the n-type semiconductor film side can be used as the light-receiving surface.

[0235] Transistor 640 has an oxide insulating layer 621 which is an insulating layer in contact with the oxide semiconductor layer 623. As such, an acid containing one or more metal elements selected from the constituent elements of the oxide semiconductor layer 623. It includes an oxide insulating layer. Therefore, charge is present at the interface between the oxide semiconductor layer 623 and the oxide insulating layer 621. This suppresses the trapping of the transistor 640 and stabilizes its electrical characteristics. It can be done. Also, the transistor 640 has a gate insulating layer 620 with a thick film (for example, (Thickness 325nm to 550nm) Contains a silicon film containing nitrogen. Therefore, Transis This makes it possible to prevent electrostatic discharge damage to transistor 640. This allows us to provide highly reliable semiconductor devices with a high yield.

[0236] The insulating layer 631, insulating layer 632, interlayer insulating layer 633, and interlayer insulating layer 634 are made of an insulating material. Using the material, depending on the material, sputtering, plasma CVD, spin coating, Dip coating, spray coating, droplet ejection (inkjet method), screen printing, offset It can be formed using methods such as T-printing.

[0237] Furthermore, the insulating layer 631 that is in contact with the oxide semiconductor layer 623 is the structure of the oxide semiconductor layer 623. It is preferable to apply an oxide insulating layer containing one or more metallic elements selected from the constituent elements. Furthermore, a silicon film containing nitrogen is provided as the insulating layer 632 that is in contact with the insulating layer 631. It is preferable to do so.

[0238] The interlayer insulating layers 633 and 634 function as flattening insulating layers to reduce surface irregularities. A suitable insulating layer is preferred. Examples of interlayer insulating layers 633 and 634 include polyimide and acrylic. Heat-resistant organic resins such as resins, benzocyclobutene resins, polyamides, and epoxy resins. Insulating materials can be used. In addition to the above organic insulating materials, low dielectric constant materials (low- k-materials), siloxane resins, PSG (phosphorus glass), BPSG (phosphorus boron glass), etc. A single layer or a laminate can be used.

[0239] By detecting the light 622 incident on the photodiode 602, information about the object being detected is obtained. It can be read. Note that when reading information about the detected object, a light source such as a backlight is used. It can be used.

[0240] The configurations and methods shown in this embodiment may be combined with the configurations and methods shown in other embodiments as appropriate. They can be used together.

[0241] (Embodiment 4) The semiconductor devices disclosed herein are applicable to a variety of electronic devices (including amusement machines). This is possible. As an electronic device, it is a television device (also known as a television or television receiver). (e.g., computer monitors, digital cameras, digital video cameras, digital) Photo frames, mobile phones, portable game consoles, personal digital assistants, sound playback devices, amusement machines Examples include (pachinko machines, slot machines, etc.) and game cabinets. Specific examples of these electronic devices include An example is shown in Figure 8.

[0242] Figure 8(A) shows table 9000 having a display unit. Table 9000 is a housing The body 9001 incorporates a display unit 9003, which displays images. This is possible. Note that the configuration shown is one in which the housing 9001 is supported by four legs 9002. It also has a power cord 9005 for power supply attached to the casing 9001.

[0243] The semiconductor device shown in any of the above embodiments can be used in the display unit 9003. This can provide high reliability to electronic devices.

[0244] The display unit 9003 has a touch input function, and the display unit 9003 of table 9000 By touching the displayed button 9004 with your finger, you can operate the screen or input information. This enables communication with or control of other home appliances, and the screen It may also be used as a control device to control other home appliances through operation. For example, in one embodiment... Using the semiconductor device having the image sensor function shown in 3, the display unit 9003 can be touched. It can be equipped with an input function.

[0245] Furthermore, a hinge provided on the housing 9001 allows the screen of the display unit 9003 to be lowered relative to the floor. It can stand upright and can also be used as a television set. In a small room, Installing a large-screen television set reduces the available space, but it can be placed on a table. If the display unit is built-in, the space in the room can be used more effectively.

[0246] Figure 8(B) shows the television equipment 9100. The television equipment 9100 is, The housing 9101 incorporates a display unit 9103, and the display unit 9103 displays video. It is possible to do so. In this example, the housing 9101 is supported by the stand 9105. It shows success.

[0247] The television unit 9100 is operated using the control switches on the housing 9101 and a separate remote control. This can be done using the control unit 9110. The control keys provided by the remote control unit 9110 9109 allows you to control the channel and volume, and the information is displayed on the display unit 9103. The video can be controlled. Furthermore, the remote control unit 9110 can be controlled by the remote control unit. A display unit 9107 may be provided to display the information output from 9110.

[0248] The television system 9100 shown in Figure 8(B) includes a receiver, modem, and other components. The vision device 9100 can receive general television broadcasts using its receiver, and further By connecting to a wired or wireless communication network via a modem, one-way communication is possible. Information from sender to receiver or bidirectional (between sender and receiver, or between receivers, etc.) It is also possible to communicate with others.

[0249] The semiconductor device shown in any of the above embodiments is used for the display units 9103 and 9107. This makes it possible to provide high reliability to television equipment and remote control devices. Cut.

[0250] Figure 8(C) shows a computer, consisting of the main unit 9201, the casing 9202, the display unit 9203, and the keys. Includes board 9204, external connection port 9205, pointing device 9206, etc.

[0251] The semiconductor device shown in any of the above embodiments can be used in the display unit 9203. This allows for greater reliability in computers.

[0252] Figures 9(A) and 9(B) show a foldable tablet device. Figure 9(A) is open In this state, the tablet terminal consists of a housing 9630, a display unit 9631a, and a display unit 963 1b, Display mode switch 9034, Power switch 9035, Power saving mode off It includes a replacement switch 9036, a fastener 9033, and an operating switch 9038.

[0253] The semiconductor device shown in any of the above embodiments has a display unit 9631a and a display unit 9631b. This makes it possible to use this technology and create a highly reliable tablet device.

[0254] The display unit 9631a can be partially designated as a touch panel area 9632a, and the display will be Data can be entered by touching the operation key 9638. Note that the display unit 963 In 1a, as an example, one half of the area has a display-only function, and the other half of the area The diagram shows a configuration that includes touch panel functionality, but is not limited to this configuration. Display unit 963 The entire area of ​​1a may also be configured to have touch panel functionality. For example, the display unit 96 The entire surface of 31a is used as a touch panel with keyboard buttons, and the display unit 9631b is displayed. It can be used as a screen.

[0255] Furthermore, in the display unit 9631b, similar to the display unit 9631a, a part of the display unit 9631b This can be designated as the touch panel area 9632b. Also, the touch panel keyboard... By touching the location where the display switch button 9639 is displayed with your finger or stylus, Keyboard buttons can be displayed on the display unit 9631b.

[0256] Furthermore, touch panel area 9632a and touch panel area 9632b can be touched simultaneously. You can also input text.

[0257] Additionally, the display mode switch 9034 switches the display orientation, such as portrait or landscape. You can switch between black and white and color displays. Power saving mode switch. The 9036 uses a built-in light sensor in the tablet device to detect ambient light during use. The display brightness can be optimized according to the amount of light. The tablet device uses a light sensor. In addition, it incorporates other detection devices such as gyroscopes, accelerometers, and other sensors that detect tilt. It's okay to store it.

[0258] Furthermore, Figure 9(A) shows an example where the display area of ​​display unit 9631b and display unit 9631a are the same. However, this is not particularly limited, and one size may be different from the other, as indicated. The quality can also differ. For example, one display panel can display a higher resolution image than the other. You may do so.

[0259] Figure 9(B) shows the closed state, and the tablet terminal consists of a housing 9630 and a solar cell 963 3. It has a charge / discharge control circuit 9634. Note that in Figure 9(B), the charge / discharge control circuit 9634 As an example, a configuration having a battery 9635 and a DC-DC converter 9636 is shown. It is.

[0260] Since the tablet device is foldable, the casing 9630 can be closed when not in use. Therefore, the display units 9631a and 9631b can be protected, thus providing durability. We can provide tablet devices that are highly durable and reliable from the perspective of long-term use.

[0261] In addition, the tablet devices shown in Figures 9(A) and 9(B) can also display various information. Functions to display still images, videos, text images, etc., calendar, date or time, etc. A touch input device that displays information on a display unit and allows users to perform touch input operations or edit the information displayed on the display unit. It has the ability to control processing through various software (programs), etc. can.

[0262] The solar cell 9633 mounted on the surface of the tablet device powers the touch panel. It can be supplied to the display unit or the video signal processing unit, etc. Note that the solar cell 9633 is housed in a casing. It can be provided on one or both sides of the body 9630, and efficiently charges the battery 9635. It is possible to do so. Furthermore, if a lithium-ion battery is used for the 9635 battery, It has advantages such as enabling standardization.

[0263] Furthermore, the configuration and operation of the charge / discharge control circuit 9634 shown in Figure 9(B) are shown in Figure 9(C). A block diagram will be shown and explained. Figure 9(C) shows the solar cell 9633, battery 9635, DC-DC converter 9636, converter 9637, switches SW1 to SW3, display unit This refers to 9631, battery 9635, DCDC converter 9636, and The converter 9637 and switches SW1 to SW3 are connected to the charge / discharge control circuit 963 shown in Figure 9(B). This corresponds to section 4.

[0264] First, let's explain an example of operation when electricity is generated by the solar cell 9633 using ambient light. The electricity generated by the solar panel is converted to a DCD (Digital-to-Collar) voltage to charge the 9635 battery. The C converter 9636 performs either a boost or a buck. Then, the display unit 9631 operates in accordance with the solar power. When power from battery 9633 is used, switch SW1 is turned ON, and converter 96 At step 37, the voltage is increased or decreased to the voltage required for the display unit 9631. Also, the display unit 96 If you do not want to display on 31, turn SW1 off and SW2 on and set the battery 96 A configuration that allows for 35 charges would be appropriate.

[0265] The solar cell 9633 is shown as an example of a power generation method, but it is not particularly limited to this method. Other power generation methods such as electrical elements (piezo elements) and thermoelectric elements (Peltier elements) The configuration may also include charging the Terry 9635. For example, power can be transmitted and received wirelessly (contactlessly). This configuration involves a contactless power transmission module that charges via a wireless connection, or a combination of other charging methods. That is also acceptable.

[0266] The configurations and methods shown in this embodiment may be combined with the configurations and methods shown in other embodiments as appropriate. They can be used together. [Examples]

[0267] In this example, the evaluation results of the film quality of silicon nitride films deposited by plasma CVD are as follows. Let me explain. Specifically, silicon nitride film deposited using a silane and nitrogen mixture as the supply gas. A film and a silicon nitride film deposited using a mixed gas of silane, nitrogen, and ammonia as the supply gas. The results of the ESR measurement are shown below.

[0268] In this embodiment, the method for preparing the sample used for ESR measurement is described below.

[0269] For ESR measurement, sample 1 to sample 2, each consisting of a silicon nitride film with a thickness of 300 nm deposited on a quartz substrate, were used. Material 5 was used. For the deposition of the silicon nitride film, a quartz substrate was placed in the deposition chamber of the plasma CVD apparatus. The film deposition chamber is then controlled to maintain a pressure of 100 Pa, and a 27.12 MHz high-frequency power supply is used to generate 2000 A power of W was supplied. The substrate temperature was set to 350°C. The plasma CVD apparatus was... Electrode area is 6000 cm² 2 This is a parallel-plate type plasma CVD apparatus. Sample 1 is provided. The supply gas was a mixture of silane and nitrogen. Furthermore, for samples 2 through 5, the supply gas was silane. A mixture of nitrogen and ammonia was used as the deposition gas. The film deposition conditions for each sample are shown in Table 1 below.

[0270] [Table 1]

[0271] ESR measurements were performed on the prepared samples 1 through 5. The ESR measurements were carried out under the following conditions. The measurement temperature was set to -170°C, and the high-frequency power (microwave power) was 9.2 GHz. The magnetic field strength was set to 1 mW, and the direction of the magnetic field was parallel to the surface of the silicon nitride film of the fabricated samples 1 to 5. This corresponds to the signal appearing at g=2.003, which originates from Nc centers contained in the silicon nitride film. The detection limit for spin density is 8.1 × 10⁻⁶. 15 spins / cm 3 That is the case.

[0272] The results of the ESR measurement are shown in Figure 12(A). From Figure 12(A), it can be seen that the supply gas contains ammonia. The spin density originating from the Nc center of sample 1 is 2.7 × 10⁻¹⁶. 17 spins / cm 3 It was confirmed that the silicon nitride film had many defects in the film. On the other hand, when the supplied gas was In samples 2 to 5 containing humonia, the spin density originating from the Nc center was 5.1 ×10 16 spins / cm 3 (Sample 2), 5.2 × 10 16 spins / cm 3 (sample 3) 6.0 × 10 16 spins / cm 3 (Sample 4), 5.5 × 10 16 spins / cm 3 (Sample 5) showed a uniformly low value regardless of the ammonia flow rate, indicating low membrane defects. It was confirmed that the silicon nitride film had been reduced.

[0273] Furthermore, the first derivative curve obtained by ESR measurement is shown in Figure 12(B). Furthermore, at a g value of 2.003, in sample 1, the signal originated from membrane defects (Nc centers). It was detected with high intensity. On the other hand, in samples 2 to 5, the g value was 2.003. The signal strength was confirmed to be low.

[0274] Based on the above, when depositing silicon nitride films by plasma CVD, the supply gas should be silane and nitrogen. By using a mixture of silicon dioxide and ammonia gas, silicon nitride films with reduced defects in the film can be deposited. It was demonstrated that this is possible. By using the silicon nitride film as a gate insulating layer, insulation A gate insulating layer with good voltage resistance can be realized, and a transistor including this gate insulating layer can be ES This suggests that it is possible to create transistors with good D tolerance. [Examples]

[0275] In this example, the silicon nitride film deposited by plasma CVD has the characteristics of a barrier film. The properties were evaluated. The evaluation results are shown in Figure 13. The evaluation method was as follows: temperature-induced desorption gas content Thermal Desorption Spectroscopy (TDS) Used.

[0276] In this example, sample 6 was prepared by depositing a silicon nitride film on a quartz substrate using plasma CVD. Evaluation was performed using sample 8. The method for preparing the samples is shown below.

[0277] Silicon nitride film deposition is performed by placing a quartz substrate in the deposition chamber of a plasma CVD apparatus, and then depositing the silicon nitride film in the deposition chamber. The pressure is controlled to 100 Pa, and 2000 W of power is supplied by a 27.12 MHz high-frequency power supply. The substrate temperature was set to 350°C. The plasma CVD apparatus has an electrode area of ​​60°C. 00cm 2 It is a parallel-plate type plasma CVD apparatus.

[0278] Sample 6 uses a mixed gas of silane, nitrogen, and ammonia (SiH4, flow rate 200 scc) as the supply gas. m:N2 flow rate 2000 sccm:NH3 flow rate 2000 sccm, film thickness 300 nm A silicon nitride film was deposited.

[0279] Sample 7 uses a mixed gas of silane, nitrogen, and ammonia (SiH4, flow rate 200 scc) as the supply gas. m:N2 flow rate 2000 sccm:NH3 flow rate 2000 sccm, film thickness 275 nm After the first silicon nitride film is deposited, the supply gas is a mixture of silane and nitrogen in the same deposition chamber. Assuming a gas mixture (SiH4 flow rate 200 sccm: N2 flow rate 5000 sccm), the film thickness is 50 nm. A second silicon nitride film was deposited.

[0280] Sample 8 uses a mixed gas of silane, nitrogen, and ammonia (SiH4, flow rate 200 scc) as the supply gas. m:N2 flow rate 2000 sccm:NH3 flow rate 2000 sccm, film thickness 275 nm After forming the first silicon nitride film, the ammonia flow rate is reduced in the same deposition chamber. SiH4 flow rate 200sccm: N2 flow rate 2000sccm: NH3 flow rate 100sccm Then, a second silicon nitride film with a thickness of 50 nm was deposited.

[0281] Figure 13 shows the evaluation results of TDS measurements for each sample at M / z=2(H2). ) refers to the TDS measurement of samples 6 and 7 prepared in this example at M / z=2(H2). The evaluation results are shown in Figure 13(B), which shows the TD of samples 6 and 8 at M / z=2(H2). This is the evaluation result of the S measurement.

[0282] As shown in Figures 13(A) and 13(B), a single layer of silicon nitride film with a high hydrogen concentration is provided. In sample 6, hydrogen release was confirmed by heat treatment. On the other hand, hydrogen in the membrane In samples 7 and 8, which had a silicon nitride film with reduced concentration laminated on top, hydrogen in sample 6 At around 450°C, where the release of hydrogen is observed, no hydrogen release was observed, and further heating treatment was performed. However, it has been confirmed that hydrogen emissions have been drastically reduced.

[0283] Therefore, when a silicon nitride film with a high hydrogen concentration is in contact with a silicon nitride film with a reduced hydrogen concentration, It has been shown that placing it in the upper layer provides a hydrogen blocking effect (barrier effect). .

[0284] As shown in Example 1, the plasma CVD method was performed using silane, nitrogen, and ammonia as the supply gases. The silicon nitride film formed by this method is a film with reduced defects and high dielectric strength. Then, a silicon nitride film with reduced defects in the film, and a silicon nitride film with reduced hydrogen concentration. A layered configuration can serve as a donor for the oxide semiconductor layer while maintaining high ESD resistance. Because it can reduce the release of hydrogen, it is preferable as a gate insulating layer for transistors. It can be applied. [Explanation of Symbols]

[0285] 300 transistors 310 transistors 320 transistors 330 transistors 400 circuit boards 402 Guard Layer 404 Gate Insulation Layer 404a Gate Insulation Layer 404b Gate Insulation Layer 404c gate insulation layer 406 oxide insulating layer 408 Oxide semiconductor layer 408a Oxide Semiconductor Layer 408b Oxide Semiconductor Layer 410a Source electrode layer 410b Drain electrode layer 412 Oxide insulating layer 414 Protective insulating layer 414a Protective insulating layer 414b Protective insulating layer 500 circuit boards 502 Gate Insulation Layer 504 Interlayer insulating layer 505 Color Filter Layer 506 Insulating layer 507 Bulkhead 510 transistors 511a Gridgate layer 511b Grid gate layer 512 Oxide insulating layer 513a conductive layer 513b Conductive layer 514 Oxide semiconductor layer 520 Capacitive elements 521a conductive layer 521b Conductive layer 522 Oxide insulating layer 523 Conductive layer 524 Insulating layer 525 Insulating layer 526 oxide semiconductor layer 530 Wiring layer intersection 533 Conductive layer 540 light-emitting elements 541 Electrode layer 542 Electroluminescent layer 543 Electrode layer 601 circuit board 602 Photodiode 606a Semiconductor film 606b Semiconductor film 606c semiconductor film 608 Adhesive layer 613 circuit board 620 Gate Insulation Layer 621 Oxide insulating layer 622 light 623 Oxide semiconductor layer 631 Insulating layer 632 Insulating layer 633 Interlayer insulating layer 634 Interlayer insulating layer 640 transistors 641a Electrode layer 641b Electrode layer 642 Electrode layer 643 Conductive layer 645 Conductive layer 656 transistors 658 Photodiode reset signal line 659 Gate signal line 671 Photosensor output signal line 672 Photosensor Reference Signal Line 4001 circuit board 4002 pixel section 4003 Signal Line Drive Circuit 4004 Scan Line Drive Circuit 4005 Sealant 4006 circuit board 4008 Liquid Crystal Layer 4010 Transistor 4011 Transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive layer 4020a Gate Insulation Layer 4020b Oxide Insulating Layer 4021 Insulating layer 4030 Oxide Insulating Layer 4031 Electrode layer 4032 Protective insulating layer 4033 Insulating layer 4034 Electrode layer 4035 Spacer 4038 Insulating layer 4510 Bulkhead 4511 Electroluminescent layer 4513 Light-emitting element 4514 Filling material 9000 Table 9001 enclosure 9002 Legs 9003 Display section 9004 Display button 9005 Power Cord 9033 Fastener 9034 Switch 9035 Power switch 9036 Switch 9038 Operation switch 9100 Television equipment 9101 enclosure 9103 Display section 9105 Stand 9107 Display section 9109 Operation Keys 9110 Remote Control Unit 9201 Main Unit 9202 enclosure 9203 Display section 9204 Keyboard 9205 External connection port 9206 Pointing device 9630 cabinet 9631 Display section 9631a Display section 9631b Display section 9632a area 9632b area 9633 Solar Cell 9634 Charge / Discharge Control Circuit 9635 Battery 9636 DC-DC converter 9637 Converter 9638 Operation Keys 9639 button

Claims

[Claim 1] The gate electrode layer, The gate insulating layer on the gate electrode layer, The first oxide insulating layer on the gate insulating layer, An oxide semiconductor layer in contact with the first oxide insulating layer and superimposed on the gate electrode layer, A source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer, A second oxide insulating layer covers the source electrode layer and the drain electrode layer and is in contact with a part of the oxide semiconductor layer, The material comprises a protective insulating layer on the second oxide insulating layer, The gate insulating layer and the protective insulating layer are composed of a silicon film containing nitrogen. The first oxide insulating layer and the second oxide insulating layer each contain one or more metal elements selected from the constituent elements of the oxide semiconductor layer. The thickness of the gate insulating layer is thicker than the thickness of the first oxide insulating layer. The thickness of the protective insulating layer is thicker than the thickness of the second oxide insulating layer. A semiconductor device in which the edges of the oxide semiconductor layer and the first oxide insulating layer coincide.

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