Manufacturing method of printed circuit boards

Abstract

Provided is a method for manufacturing a printed wiring board which has more effectively reduced pattern defects and excellent high frequency characteristics. This method for manufacturing a printed wiring board comprises: a step for preparing an insulating substrate having a roughened surface; a step for performing electroless plating on the roughened surface of the insulating substrate to form an electroless plating layer having a thickness of 1.0 μm or less and having a surface with a peak density Sds of 0.90 μm-2 to 1.30 μm-2 and an interface development area ratio Sdr of 3.00-12.00%; a step for laminating a photoresist on the surface of the electroless plating layer; a step for subjecting the photoresist to exposure and development to form a resist pattern; a step for electroplating the electroless plating layer through the resist pattern; a step for peeling the resist pattern; and a step in which unnecessary portions of the electroless plating layer exposed by peeling the resist pattern are removed by etching to form a wiring pattern.

Description

[Technical Field]

[0001] This invention relates to a method for manufacturing printed circuit boards. [Background technology]

[0002] In recent years, with the increasing demand for miniaturization and higher density in printed circuit boards, there has been a need for finer circuitry (fine pitch). The semi-additive process (SAP method) is widely used as a manufacturing method for printed circuit boards suitable for finer circuitry. The SAP method is suitable for forming extremely fine circuits, and one example of this is the use of carrier-attached roughened copper foil. For example, as shown in Figures 8 and 9, the roughened copper foil 110 is pressed onto an insulating resin substrate 111 equipped with a lower circuit 111b on a base material 111a using a prepreg 112 and a primer layer 113 (step (a)). After peeling off the carrier (not shown), via holes 114 are formed by laser drilling as needed (step (b)). Next, the roughened copper foil 110 is removed by etching to expose the primer layer 113 with a roughened surface profile (step (c)). After applying electroless copper plating 115 to the roughened surface (step (d)), the surface is masked in a predetermined pattern by exposure and development using a dry film 116 (step (e)), and then electroplated with copper plating 117 (step (f)). After removing the dry film 116 to form the wiring portion 117a (step (g)), the unnecessary electroless copper plating 115 between adjacent wiring portions 117a, 117a is removed by etching (step (h)) to obtain wiring 118 formed in a predetermined pattern.

[0003] In the SAP method using roughened copper foil, the roughened copper foil itself is removed by etching after laser drilling (step (c)). Since the uneven surface shape of the roughened copper foil is transferred to the laminate surface from which the roughened copper foil was removed, adhesion between the insulating layer (e.g., primer layer 113, or prepreg 112 if there is no primer layer) and the plated circuit (e.g., wiring 118) can be ensured in subsequent steps. However, surface profiles suitable for improving adhesion with the plated circuit tend to be rough and uneven, so the etching ability for electroless copper plating tends to decrease in step (h). In other words, because the electroless copper plating penetrates into the rough unevenness, more etching is required to remove the residual copper.

[0004] Therefore, a method has been proposed that, when used in the SAP method, can achieve good etching performance while ensuring the necessary adhesion to the plated circuit by reducing the size of the roughened particles and giving them a constricted shape. For example, Patent Document 1 (International Publication No. 2016 / 158775) discloses a roughened copper foil having a roughened surface on at least one side, wherein the roughened surface is provided with a plurality of substantially spherical protrusions made of copper particles, and the average height of the substantially spherical protrusions is 2.60 μm or less. Patent Document 2 (International Publication No. 2018 / 211951) also discloses a roughened copper foil having a roughened surface on at least one side, wherein the roughened surface is provided with primary roughened particles having a constricted portion and secondary roughened particles on the surface of the primary roughened particles, and the roughened surface has a low roughness with a ten-point average roughness Rz of 1.7 μm or less.

[0005] Furthermore, in order to further miniaturize the circuits, it is conceivable that in the SAP method, copper foil with a smooth surface and small roughening particles be used, and that a thin layer of electroless plating be applied to form the circuit. However, in circuits formed in this way, problems such as pattern defects such as short circuits and protrusions may occur. Methods for manufacturing printed circuit boards that address these problems have been proposed. For example, Patent Document 3 (International Publication No. 2020 / 196105) discloses a method for manufacturing a printed circuit board that includes a step of applying electroless plating to an insulating substrate with a roughened surface to form an electroless plating layer less than 1.0 μm thick having a surface with an arithmetic mean waviness Wa of 0.10 μm or more and 0.25 μm or less, and a crustosis Sku of 2.0 or more and 3.5 or less. Also, Patent Document 4 (International Publication No. 2020 / 196106) discloses a method for manufacturing a printed circuit board that has an arithmetic mean waviness Wa of 0.10 μm or more and 0.25 μm or less, and a valley void volume Vvv of 0.010 μm 3 / μm 2 The above 0.028 μm 3 / μm 2 It is also disclosed that an electroless plating layer having the following surface characteristics can be formed. According to the methods disclosed in Patent Documents 3 and 4, it is possible to manufacture printed wiring boards that effectively suppress pattern defects and have excellent fine circuit formation properties. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] International Publication No. 2016 / 158775 [Patent Document 2] International Publication No. 2018 / 211951 [Patent Document 3] International Publication No. 2020 / 196105 [Patent Document 4] International Publication No. 2020 / 196106 [Overview of the project]

[0007] When a printed wiring board is manufactured by the method disclosed in Patent Documents 3 and 4, the problem of pattern defects can be solved to some extent. However, further suppression of pattern defects is desired. In addition, with the recent high functionality of portable electronic devices and the like, the frequency of signals has been increasing for high-speed processing of a large amount of information, and printed wiring boards suitable for high-frequency applications such as 5G, millimeter waves, and base station antennas are also in demand. However, it is not easy to achieve both suppression of pattern defects and good high-frequency characteristics.

[0008] The inventors of the present invention have now found that by subjecting an insulating base material having a roughened surface to electroless plating to form an electroless plating layer having a surface in which the peak density Sds and the developed area ratio Sdr of the interface are each controlled within a predetermined range, pattern defects can be more effectively suppressed, and a printed wiring board excellent in high-frequency characteristics can be manufactured.

[0009] Therefore, an object of the present invention is to provide a method for manufacturing a printed wiring board that more effectively suppresses pattern defects and is excellent in high-frequency characteristics.

[0010] According to the present invention, the following aspects are provided. [Aspect 1] A method for manufacturing a printed wiring board, comprising: (a) a step of preparing an insulating base material having a roughened surface; (b) performing electroless plating on the roughened surface of the insulating base material to form an electroless plating layer having a surface with a peak density Sds measured in accordance with EUR15178N of 0.90 μm -2 or more and 1.30 μm -2 or less, and a developed area ratio Sdr of the interface measured in accordance with EUR15178N of 3.00% or more and 12.00% or less, and having a thickness of 1.0 μm or less; (c) a step of laminating a photoresist on the surface of the electroless plating layer; (d) a step of exposing and developing the photoresist to form a resist pattern. (e) A step of electroplating the electroless plating layer through the resist pattern; (f) A step of peeling the resist pattern; (g) A step of removing unnecessary portions of the electroless plating layer exposed by the peeling of the resist pattern by etching to form a wiring pattern; A method for manufacturing a printed wiring board, including the above steps. [Aspect 2] The peak curvature Ssc measured in accordance with EUR15178N on the surface of the electroless plating layer is 2.30 μm -1 or more and 3.50 μm -1 or less. The method for manufacturing a printed wiring board according to Aspect 1. [Aspect 3] The developed area ratio Sdr of the interface on the surface of the electroless plating layer is 5.00% or more and 10.00% or less. The method for manufacturing a printed wiring board according to Aspect 1 or 2. [Aspect 4] The step (a) is as follows: (a-1) Prepare a surface-treated copper foil having a treatment surface with a peak density Sds measured in accordance with EUR15178N of 1.00 μm -2 or more and 1.50 μm -2 or less, a peak curvature Ssc measured in accordance with EUR15178N of 4.00 μm -1 or more and 6.00 μm -1 or less, and a developed area ratio Sdr of the interface measured in accordance with EUR15178N of 20.00% or more and 40.00% or less. (a-2) Laminate an insulating substrate on the treatment surface of the surface-treated copper foil, transfer the surface shape of the treatment surface to the surface of the insulating substrate, and then (a-3) Remove the surface-treated copper foil by etching to obtain an insulating substrate with a roughened surface. ​​​​​​​​A method for manufacturing a printed circuit board according to any one of embodiments 1 to 5, wherein the photoresist includes a dry film resist. [Aspect 7] The method for manufacturing a printed circuit board according to embodiment 6, wherein the thickness of the dry film resist is 2 μm or more and 35 μm or less. [Aspect 8] A method for manufacturing a printed wiring board according to any one of embodiments 1 to 7, wherein the thickness of the wiring pattern is 2 μm or more and 30 μm or less. [Brief explanation of the drawing]

[0011] [Figure 1] This is a flowchart showing the first half of the manufacturing process (steps (a) to (c)) in an example of the manufacturing method of the present invention. [Figure 2] This is a flowchart showing the latter half of the manufacturing process (steps (d) to (g)) in an example of the manufacturing method of the present invention. [Figure 3] This is a process flowchart illustrating an example of the procedure for preparing an insulating substrate with a roughened surface. [Figure 4] This diagram illustrates the effects of surface contaminants during exposure and development when the surface after electroless plating does not have sufficient surface irregularities. [Figure 5] This diagram illustrates the effect of surface contaminants during exposure and development when the surface after electroless plating has sufficient surface irregularities. [Figure 6] This diagram illustrates the procedure for evaluating the number of detected debris particles in the example. [Figure 7A] This figure illustrates the summit density Sds measured in accordance with EUR15178N, and shows an example of the surface and summit when Sds = 5 μm⁻². [Figure 7B] This figure illustrates the summit density Sds measured in accordance with EUR15178N, and shows an example of the surface and summit when Sds = 1 μm⁻². [Figure 8] This is a process flow chart used to explain the SAP method, and it shows the first half of the process (processes (a) to (d)). [Figure 9]This is a process flow chart used to explain the SAP method, specifically showing the later stages of the process (stages (e) to (h)). [Modes for carrying out the invention]

[0012] definition The following are definitions of the parameters used to specify the present invention.

[0013] In this specification, "peak density Sds" or "Sds" is a parameter representing the number of peaks per unit area, measured in accordance with EUR15178N. As shown in Figures 7A and 7B, in calculating Sds, points higher than eight neighboring points N are considered peaks S. A larger value indicates a denser distribution of peaks (see Figure 7A). Conversely, a smaller value indicates a sparser distribution of peaks (see Figure 7B).

[0014] In this specification, "peak curvature Ssc" or "Ssc" is a parameter that represents the average of the principal curvatures at the peaks of a surface, measured in accordance with EUR15178N. A smaller value indicates that the points of contact with other objects are more rounded. Conversely, a larger value indicates that the points of contact with other objects are more pointed. Note that while the parameter specified in ISO25178 considers only significant peaks remaining after segmentation, the parameter specified in EUR15178N detects local peaks and significant peaks without distinguishing between them. Therefore, for identical surface shapes, the Ssc specified in EUR15178N will be larger than the Spc specified in ISO25178 (Spc <Ssc)。

[0015] In this specification, "interface development area ratio Sdr" or "Sdr" is a parameter measured in accordance with EUR15178N that represents how much the development area (surface area) of a defined region increases relative to the area of ​​the defined region. In this specification, the interface development area ratio Sdr is expressed as the increase in surface area (%). A smaller value indicates a surface shape that is closer to flat, with a perfectly flat surface having an Sdr of 0%. On the other hand, a larger value indicates a surface shape with more irregularities. For example, if the Sdr of a surface is 10%, it indicates that the surface area of ​​this surface has increased by 10% compared to a perfectly flat surface.

[0016] Sds, Ssc, and Sdr can be calculated by measuring the surface profile of a predetermined measurement area (e.g., a two-dimensional area of ​​64.397 μm × 64.463 μm) on the roughened surface using a commercially available laser microscope. In this specification, Sds, Ssc, and Sdr are measured under conditions without cutoff using S filters and L filters. Other preferred measurement and analysis conditions for surface profiles using a laser microscope are shown in the examples below.

[0017] Manufacturing method of printed circuit boards The present invention relates to a method for manufacturing printed circuit boards. The method of the present invention includes the steps of (a) preparing an insulating substrate, (b) forming an electroless plating layer, (c) laminating a photoresist, (d) forming a resist pattern, (e) forming an electroplating layer, (f) peeling off the resist pattern, and (g) forming a wiring pattern.

[0018] The following describes each of the steps (a) to (g) with reference to Figures 1 to 5.

[0019] (a) Preparation of insulating substrate As shown in Figure 1(a), an insulating substrate 20 having a roughened surface 20a is prepared. The insulating substrate 20 may have roughened surfaces 20a on both sides, or it may have roughened surfaces 20a on only one side. The insulating substrate 20 preferably contains an insulating resin. Furthermore, the insulating substrate 20 is preferably a prepreg and / or a resin sheet. A prepreg is a general term for a composite material in which a synthetic resin is impregnated into a substrate such as a synthetic resin plate, glass plate, glass woven fabric, glass nonwoven fabric, or paper. Preferred examples of insulating resins to be impregnated into the prepreg include epoxy resin, cyanate resin, bismaleimide triazine resin (BT resin), polyphenylene ether resin, and phenolic resin. Examples of insulating resins that constitute a resin sheet include epoxy resin, polyimide resin, and polyester resin. The insulating substrate 20 may contain filler particles made of various inorganic particles such as silica and alumina from the viewpoint of improving insulation properties. The thickness of the insulating substrate 20 is not particularly limited, but is preferably 1 μm to 1000 μm, more preferably 2 μm to 400 μm, and even more preferably 3 μm to 200 μm. The insulating substrate 20 may be composed of multiple layers.

[0020] The roughened surface 20a of the insulating substrate 20 may be formed by any method, but is typically formed by transferring the uneven shape of the treated surface of the surface-treated copper foil to the surface of the insulating substrate 20. According to a preferred embodiment of the present invention, the formation of the roughened surface 20a using surface-treated copper foil is performed by (a-1) preparing surface-treated copper foil having a predetermined treated surface, (a-2) laminating an insulating substrate onto the treated surface of the surface-treated copper foil to transfer the surface shape of the treated surface to the surface of the insulating substrate, and (a-3) removing the surface-treated copper foil by etching to obtain an insulating substrate with a roughened surface. The specific steps for each process are as follows.

[0021] (a-1) Preparation of surface-treated copper foil As shown in Figure 3(a-1), a surface-treated copper foil 10 is prepared having a treated surface 10a on at least one side. The treated surface 10a is a surface that has been subjected to some kind of surface treatment, and is typically a roughened surface. The treated surface 10a typically consists of a plurality of bumps (e.g., roughened particles). In any case, the surface-treated copper foil 10 may have treated surfaces 10a on both sides, or it may have treated surfaces 10a on only one side. If treated surfaces 10a are present on both sides, when used in the SAP method, the laser irradiation side (the side opposite to the side that is in contact with the insulating substrate) will also be surface-treated, resulting in increased laser absorption and thus improved laser perforation. The surface-treated copper foil 10 may also be in the form of a carrier-attached copper foil. In this case, the carrier-attached copper foil typically comprises a carrier, a release layer provided on the carrier, and a surface-treated copper foil 10 provided on the release layer with the treated surface 10a facing outwards. However, aside from using the surface-treated copper foil 10, any known layer configuration can be adopted for the carrier-attached copper foil.

[0022] The treated surface 10a of the surface-treated copper foil 10 has a peak density Sds of 1.00 μm -2 More than 1.50μm -2 Preferably, it is less than or equal to 1.00 μm, and more preferably 1.00 μm. -2 More than 1.40μm -2 More preferably 1.10 μm -2 More than 1.40μm -2 The following is particularly preferred: 1.20 μm -2 More than 1.40μm -2 The following applies. Furthermore, the treated surface 10a of the surface-treated copper foil 10 has a peak curvature Ssc of 4.00 μm. -1 More than 6.00μm -1 Preferably, it is less than or equal to 4.50 μm. -1 More than 6.00μm -1 More preferably 4.50 μm -1 More than 5.00μm -1The following applies. Furthermore, the treated surface 10a of the surface-treated copper foil 10 preferably has an interface development area ratio Sdr of 20.00% or more and 40.00% or less, and more preferably 20.00% or more and 25.00% or less. By using surface-treated copper foil 10 having a treated surface 10a in which Sds, Ssc, and Sdr are within these ranges to impart an uneven shape to the insulating substrate 20, it becomes easier to form an electroless plating layer 22 having the specific surface parameters described later on the roughened surface 20a of the insulating substrate 20. The treated surface 10a having the above surface parameters can be formed by applying a surface treatment (typically a roughening treatment) to the copper foil surface under known or desired conditions. Alternatively, commercially available copper foil having a treated surface 10a that satisfies the above conditions may be selectively obtained.

[0023] (a-2) Transfer of uneven shape to insulating substrate As shown in Figure 3(a-2), an insulating substrate 20' (i.e., an insulating substrate 20 without a roughened surface 20a) is laminated onto the treated surface 10a of the surface-treated copper foil 10 to form a copper-clad laminate 12. In this way, the surface shape of the treated surface 10a can be transferred to the surface of the insulating substrate 20'. The lamination of the insulating substrate 20' is preferably performed by hot pressing or hot lamination, and the processing temperature and processing time for this hot pressing or hot lamination can be appropriately determined based on known conditions depending on the type of insulating substrate 20' to be laminated. Preferred types of insulating substrate 20' are as described above with respect to the insulating substrate 20. The insulating substrate 20' may also be laminated onto the surface-treated copper foil 10 via a primer layer (not shown) that is applied to the treated surface 10a of the surface-treated copper foil 10 in advance. In this case, the primer layer is considered to constitute a part of the insulating substrate. The primer layer is preferably composed of a resin, and this resin preferably contains an insulating resin. If desired, via holes (not shown) may be formed in the copper-clad laminate 12 by laser drilling prior to the removal of the surface-treated copper foil 10, which is the next step.

[0024] (a-3) Removal of surface-treated copper foil As shown in Figure 3(a-3), the surface-treated copper foil 10 of the copper-clad laminate 12 is removed by etching to obtain an insulating substrate 20 having a roughened surface 20a. The etching of the surface-treated copper foil 10 can be carried out using, for example, a sulfuric acid-hydrogen peroxide-based etching solution, in accordance with etching methods and conditions commonly used in the manufacture of printed circuit boards, and is not particularly limited.

[0025] (b) Formation of electroless plating layer As shown in Figure 1(b), electroless plating (e.g., electroless copper plating) is performed on the roughened surface 20a of the insulating substrate 20 to form an electroless plating layer 22 with a thickness of 1.0 μm or less. The electroless plating can be performed using a commercially available electroless plating solution in accordance with methods and conditions commonly used in the manufacture of printed circuit boards, and is not particularly limited. The surface of the electroless plating layer 22 has a peak density Sds of 0.90 μm. -2 More than 1.30μm -2 The following conditions apply, and the interface development area ratio Sdr is 3.00% or more and 12.00% or less. In this way, by applying electroless plating to an insulating substrate 20 having a roughened surface 20a, an electroless plating layer 22 is formed having a surface in which the peak density Sds and the interface development area ratio Sdr are controlled within predetermined ranges, pattern defects can be suppressed more effectively, and a printed circuit board with excellent high-frequency characteristics can be manufactured.

[0026] As mentioned above, with the increasing miniaturization of circuits required in the SAP method in recent years, it is conceivable to use copper foil with a smooth surface and small roughening particles to impart a roughened surface profile to the insulating substrate in order to achieve excellent etching properties. Furthermore, if electroless plating can be applied thinly (e.g., 1.0 μm or less) to the surface of the insulating substrate with the roughened surface profile, it is advantageous because the amount of etching can be reduced, thereby enabling further miniaturization of the circuit. However, when attempting to form a circuit in the SAP method using copper foil with a smooth surface and small roughening particles, and applying a thin electroless plating, problems such as pattern defects such as short circuits and protrusions may occur in the formed circuit. The mechanism by which these pattern defects occur is not entirely clear, but it is presumed to be as follows.

[0027] In other words, when a surface shape is transferred to an insulating substrate using surface-treated copper foil, the roughened surface of the insulating substrate will generally reflect the surface profile of the surface-treated copper foil. Furthermore, when electroless plating is applied to this roughened surface of the insulating substrate with a thickness of 1.0 μm or less, the surface shape of the electroless plating layer will generally reflect the surface shape of the roughened surface of the insulating substrate. For this reason, if a copper foil with a smooth surface and small roughening particles (in other words, a copper foil with fine irregularities) is used as the copper foil to transfer the surface profile to the insulating substrate, it will be difficult to impart sufficient irregularities to the surface of the electroless plating layer. Incidentally, in the general manufacturing process of printed circuit boards, in order to form a circuit in a predetermined pattern, as shown in Figures 4(i) to (iv), a photoresist 24 (for example, including a dry film resist 24a and a support film 24b) is further laminated on the surface of the electroless plating layer 22 laminated on the insulating substrate 20, and exposure and development are performed to form a resist pattern 26. Here, as shown in Figure 4(i), during the lamination or exposure of the photoresist 24, foreign matter F (including, for example, dust or scratches on the photoresist surface, or air trapped during photoresist lamination) may adhere to or be mixed into the surface of the photoresist 24. For example, in printed circuit board manufacturing plants, the cleanliness of the cleanroom is operated at a level of approximately Class 100 to Class 1000, making it difficult to completely eliminate foreign matter present in the environment. Furthermore, it is difficult to detect minute scratches on the surface of the photoresist 24. In this regard, when a photoresist 24 laminated on the surface of an electroless plating layer 22 that does not have sufficient unevenness is exposed, as shown in Figure 4(ii), the exposure incident light I that enters from a direction perpendicular to the main surface of the laminate is reflected directly by the electroless plating layer 22 and exits as exposure reflected light R in the direction 180° opposite to the exposure incident light I. As a result, the portion of the photoresist 24 (e.g., dry film resist 24a) directly beneath the foreign object F, which should have been exposed, remains unexposed (see Figure 4(iii)), and a hole H is formed after development (see Figure 4(iv)).As a result, electroplating is applied to areas where circuits should not be formed, and it is believed that these unnecessary electroplated areas cause short circuits and protrusions in the circuits, leading to problems with faulty patterns.

[0028] Furthermore, polyethylene terephthalate (PET) film is commonly used as the support film 24b constituting the photoresist 24, and this PET film contains a lubricant to improve fluidity and release properties during heat molding. Typically, this lubricant has variations in particle size, and a certain proportion of particles of a large size (for example, 10 μm or larger in diameter) are present. As a result, due to the large foreign matter that inevitably exists in such PET films, areas that should be exposed remain unexposed, as described above, and pattern defects can occur. It is also conceivable to perform exposure with the PET film peeled off and the dry film exposed, but if exposure is performed in this manner, deformation of the dry film may occur due to oxygen. In other words, the above-mentioned pattern defect problem caused by the lubricant contained in the PET film is unavoidable. In this respect, conventional methods for manufacturing printed circuit boards, such as those disclosed in Patent Document 3 (International Publication No. 2020 / 196105) and Patent Document 4 (International Publication No. 2020 / 196106), have room for improvement in terms of canceling pattern defects caused by large foreign matter. On the other hand, it is conceivable to excessively increase the surface roughness of the electroless plating layer by using surface-treated copper foil with a high surface roughness and transferring the surface shape to the insulating substrate. However, adopting such a method would lead to a deterioration of high-frequency characteristics. Thus, achieving both suppression of pattern defects and good high-frequency characteristics is not easy.

[0029] In this respect, the method of the present invention makes it possible to achieve both further suppression of pattern defects and good high-frequency characteristics. The mechanism is not entirely clear, but it is thought to be as follows: The peak density Sds on the surface of the electroless plating layer 22 is 0.90 μm -2 More than 1.30μm -2By setting the following parameters, and the interface development area ratio Sdr to 3.00% or more and 12.00% or less, the surface of the electroless plating layer 22 will have an appropriate uneven shape (see Figure 5(i)). Therefore, during exposure, when the exposure incident light I that enters from a direction perpendicular to the main surface of the laminate reaches the surface of the electroless plating layer 22, it will be diffusely reflected by the uneven parts of the surface of the electroless plating layer 22 (see Figure 5(ii)). As a result, the exposure reflected light R can expose the portion of the photoresist 24 (e.g., dry film resist 24a) directly beneath the foreign matter F (see Figure 5(iii)). Typically, about 60-70% of the light of the wavelength used to expose the photoresist 24 is absorbed on the electroless plating layer 22, which is made of copper or the like. Therefore, if the angle between the exposure incident light I and the exposure reflected light R is too large, the exposure reflected light R may be absorbed by the electroless plating layer 22 (for example, in the uneven areas near the reflection points), resulting in a failure to eliminate pattern defects caused by foreign matter F. In this regard, by controlling the surface shape of the electroless plating layer 22 by combining the peak density Sds and the interface development area ratio Sdr so that it falls within the range described above, it becomes easier to control the angle between the exposure incident light I and the exposure reflected light R to a desired range, and as a result, it becomes possible to expose the portion of the photoresist 24 (for example, dry film resist 24a) directly beneath the foreign matter F very effectively. In other words, even if the foreign matter F present on and / or inside the photoresist 24 is enormous in size, its effect can be canceled out. In this way, the formation of unexposed areas of the photoresist 24 caused by foreign matter F is effectively prevented, and the formation of unnecessary holes H due to development is suppressed (see Figure 5(iv)). Thus, it is thought that problems such as short circuits and protrusions in the circuit will be less likely to occur. Nevertheless, the surface of the electroless plating layer 22, where the peak density Sds and the interface development area ratio Sdr are within the above range, has a surface shape with low roughness, which is effective in reducing the skin effect, and is therefore considered to be able to achieve excellent high-frequency characteristics.

[0030] From the above perspective, the surface of the electroless plating layer 22 has a peak density Sds of 0.90 μm. -2 More than 1.30μm -2The following, preferably 0.90 μm -2 More than 1.20μm -2 More preferably, 1.10 μm -2 More than 1.20μm -2 The following applies:

[0031] Furthermore, the surface of the electroless plating layer 22 has an interface development area ratio Sdr of 3.00% to 12.00%, preferably 5.00% to 10.00%, and more preferably 5.00% to 6.00%.

[0032] The surface of the electroless plating layer 22 has a peak curvature Ssc of 2.30 μm. -1 More than 3.50μm -1 Preferably, it is less than 2.30 μm, and more preferably 2.30 μm -1 More than 3.00μm -1 The following applies. Within these ranges, it is possible to achieve excellent high-frequency characteristics while further suppressing pattern defects caused by larger foreign matter F.

[0033] The electroless plating layer 22 having the above-described specific surface parameters can be formed by applying electroless plating to the roughened surface 20a of the insulating substrate 20 to a thickness of 1.0 μm or less. As described above, the surface shape of the electroless plating layer 22 can be said to generally reflect the surface shape of the roughened surface 20a of the insulating substrate 20. This roughened surface 20a can preferably be formed, for example, by transferring the surface shape of the surface-treated copper foil 10 having the surface parameters described in (a) above to the insulating substrate 20.

[0034] The thickness of the electroless plating layer 22 is 1.0 μm or less, preferably 0.3 μm or more and 1.0 μm or less. With such a thickness, it is possible to reduce the amount of etching during wiring pattern formation, making it extremely suitable for forming fine circuits.

[0035] (c) Photoresist layering As shown in Figure 1(c), a photoresist 24 is laminated on the surface of the electroless plating layer 22. The lamination speed when laminating the photoresist 24 is not particularly limited, but is typically 1.0 m / min or more and 2.0 m / min or less. The photoresist 24 can be any known material commonly used in the manufacture of printed circuit boards. The photoresist 24 may be either negative or positive type, and may be either film type or liquid type. Preferably, the photoresist 24 includes a dry film resist 24a. Furthermore, it is preferable that the photoresist 24 is a photosensitive film, for example, a photosensitive dry film. As shown in Figure 1(c), the photoresist 24 may have a support film 24b, such as a polyethylene terephthalate (PET) film, further laminated on the dry film resist 24a as a photosensitive layer. The support film 24b, such as a PET film, typically contains a lubricant from the viewpoint of improving fluidity and release properties during heat molding. In this regard, as described above, the present invention can effectively suppress pattern defects caused by lubricants and the like. The thickness of the photoresist 24 or dry film resist 24a is preferably 2 μm or more and 35 μm or less, and more preferably 5 μm or more and 24 μm or less.

[0036] (d) Formation of resist pattern As shown in Figure 2(d), a resist pattern 26 is formed by exposing and developing the photoresist 24. Exposure and development can be carried out according to known methods and conditions commonly used in the manufacture of printed circuit boards, and are not particularly limited. For example, as an exposure method, in addition to mask exposure using a negative or positive mask pattern, direct writing exposure methods such as Laser Direct Imaging (LDI) exposure and Digital Light Processing (DLP) exposure can be employed. The exposure amount during exposure is 5 mJ / cm². 2 More than 150mJ / cm 2The following is preferable. On the other hand, the development method may be either wet development or dry development. In the case of wet development, the developer used may be sodium carbonate, sodium hydroxide, amine-based aqueous solution, etc. If the photoresist 24 contains a support film 24b, it is preferable to remove the support film 24b before development.

[0037] (e) Formation of the electroplating layer Electroplating (e.g., electroplated copper) is applied to the electroless plating layer 22 via the resist pattern 26. In this way, an electroplated layer 28 can be formed between the resist patterns 26, as shown in Figure 2(e). The electroplating is not particularly limited and can be carried out according to various pattern plating methods and conditions commonly used in the manufacture of printed circuit boards, such as copper sulfate plating solution or copper pyrophosphate plating solution.

[0038] (f) Peeling off the resist pattern In this step, the resist pattern 26 is removed. As a result, as shown in Figure 2(f), the electroplating layer 28 remains in the shape of a wiring pattern, and the unnecessary parts of the electroless plating layer 22 that do not form a wiring pattern are exposed. The removal of the resist pattern 26 can be carried out using an aqueous sodium hydroxide solution, an amine-based solution or an aqueous solution thereof, and is not particularly limited and can be performed according to various removal methods and conditions commonly used for printed circuit boards.

[0039] (g) Formation of wiring patterns The wiring pattern 30 is formed by etching away the unnecessary portions of the electroless plating layer 22 (i.e., portions where the wiring pattern is not formed) that are exposed by peeling off the resist pattern 26. The etching of the unnecessary portions of the electroless plating layer 22 can be carried out using, for example, a sulfuric acid-hydrogen peroxide-based etching solution, in accordance with etching methods and conditions commonly used in the manufacture of printed circuit boards, and is not particularly limited. The thickness of the wiring pattern 30 (i.e., circuit height) is preferably 2 μm or more and 30 μm or less. The wiring pitch of the wiring pattern 30 is preferably in the range of 10 μm (e.g., line / space = 5 μm / 5 μm) to 20 μm (e.g., line / space = 10 μm / 10 μm). By forming a circuit on an electroless plating layer 22 with a thickness of 1.0 μm or less having the predetermined surface parameters described above, it is possible to form such a highly miniaturized wiring pattern. Furthermore, wiring patterns with wiring pitches within the above range are prone to pattern defects such as short circuits and the occurrence of protrusions, but as described above, the method of the present invention can effectively resolve such problems.

[0040] If necessary, an insulating layer and n wiring patterns (where n is an integer of 2 or more) may be alternately formed on the wiring pattern 30 to form a multilayer wiring board. Each wiring pattern constituting the multilayer wiring board can be referred to as the second wiring pattern, third wiring pattern, ..., nth wiring pattern, with wiring pattern 30 being the first wiring pattern. The sequentially laminated structure consisting of the first wiring pattern, nth wiring pattern, and insulating layer is generally referred to as a build-up layer or build-up wiring layer. The method for forming the build-up layers from the second wiring pattern onward is not particularly limited, and in addition to the SAP method described above, modified semi-additive method (MSAP method), fully additive method, subtractive method, etc., can be used. Furthermore, solder resist, mounting bumps such as pillars may be formed on the wiring pattern on the outermost surface of the build-up layer if necessary. In any case, known methods generally used in printed circuit boards can be added as appropriate, and are not particularly limited. [Examples]

[0041] The present invention will be further described in detail by the following examples.

[0042] Examples 1-15 Fifteen types of surface-treated copper foil were prepared, and the surface shape was transferred to an insulating substrate using this surface-treated copper foil. Electroless plating was applied to the roughened surface of the resulting insulating substrate to create evaluation laminates, and various evaluations were performed. Specifically, the details are as follows.

[0043] (1) Preparation of surface-treated copper foil Fifteen types of surface-treated copper foil 10 were prepared, each having a treated surface 10a with the parameters shown in Table 2 on at least one side. Some of these surface-treated copper foils 10 are commercially available, while others were manufactured separately based on known methods. The methods for measuring or calculating each parameter on the treated surface 10a of the prepared surface-treated copper foils 10 are as follows.

[0044] Surface roughness analysis was performed using a laser microscope to measure the treated surface 10a of the surface-treated copper foil 10 in accordance with EUR15178N. The specific measurement conditions are shown in Table 1.

[0045] [Table 1]

[0046] The measurement data acquired with the above laser microscope was read into analysis software (Olympus Corporation, "OLS5100 LEXT (version 2.1.2.215)"), converted to a LEXT file format as unprocessed data, and output. This LEXT file was then read into other analysis software (Digital Surf, "MountainsMap (version 9.0.9878)") and analyzed (analysis area: 64.397 μm × 64.463 μm). Specifically, the parameter analysis screen was displayed by selecting "Parameter Table" and then "Default Settings" from the Analysis Target tab. On the parameter analysis screen, "EUR15178N" was selected as the standard, "First-order surface" as the wavelength processing, "Least squares surface" as the F calculation (F operation) for shape removal, and "Sds", "Ssc", and "Sdr" as the parameters. On this screen, neither the S filter nor the L filter was selected (i.e., no cutoff by the S filter or L filter). Subsequently, the analysis results were saved by selecting "Export Analysis Results," and the peak density Sds, peak curvature Ssc, and interface development area ratio Sdr were read from these results. For each example, the above parameters were calculated in five different fields of view. The average values ​​across all fields of view were adopted as Sds, Ssc, and Sdr for the treated surface 10a of the surface-treated copper foil 10. The results are shown in Table 2.

[0047] (2) Preparation of evaluation laminates After laminating two sheets of prepreg (Mitsubishi Gas Chemical Co., Ltd., GHPL-830NSF, 100 μm thick), as shown in Figure 3, the surface-treated copper foil 10 prepared in (1) above is laminated onto this insulating substrate 20' so that the treated surface 10a is in contact with it, and the press temperature is 220°C, the press time is 90 minutes, and the press pressure is 40 kgf / cm². 2Pressing was performed under the specified conditions to obtain a copper-clad laminate 12. The surface-treated copper foil 10 of this copper-clad laminate 12 was completely removed with a sulfuric acid-hydrogen peroxide etching solution to obtain an insulating substrate 20 having a roughened surface 20a on which the surface shape of the treated surface 10a was transferred. Electroless copper plating was performed on this insulating substrate 20 using an electroless copper plating solution (Atotec MV+, manufactured by Atotec Co., Ltd.) to form an electroless plating layer 22 on the roughened surface 20a side. The thickness of the electroless plating layer 22 was as shown in Table 2. In this way, a laminate (hereinafter referred to as the evaluation laminate) immediately before the photoresist was laminated in the SAP method was obtained.

[0048] (3) Measurement of the surface profile of the evaluation laminate Using a laser microscope, surface roughness analysis was performed to measure the peak density Sds, peak curvature Ssc, and interface development area ratio Sdr on the electroless plating layer 22 side surface of the evaluation laminate obtained above, in accordance with EUR15178N. The measurement and analysis conditions for each parameter were the same as those for each parameter of the surface-treated copper foil in (1) above. The results are shown in Table 2.

[0049] (4) Various evaluations The following evaluations were performed on the obtained evaluation laminates or circuit boards to assess various characteristics.

[0050] <Number of detected waste items> The number of detected dust particles was evaluated as follows. First, a 19 μm thick negative-type photoresist 24 (manufactured by Hitachi Chemical Co., Ltd., RY-5319) was laminated onto the electroless plating layer 22 side surface of the evaluation laminate obtained above at a lamination speed of 1.5 m / min. Then, as shown in Figure 6(i), a glass mask 25 was laminated onto the surface of the photoresist 24. The glass mask 25 is provided with circular light-shielding sections B (diameter 8 μm to 15 μm (1 μm increments, 8 levels in total), 25 sections x 12 fields each) in the center of each 100 μm x 100 μm area, representing foreign matter such as dust. Therefore, light is transmitted through the parts of the glass mask 25 where the light-shielding sections B are not provided, while light is not transmitted through the parts of the glass mask 25 where the light-shielding sections B are provided. The evaluation laminate after the glass mask 25 was then exposed to light (70 mJ / cm²). 2 A resist pattern 26 was formed by 3D printing and development. The surface of the evaluation laminate on the resist pattern 26 side was observed with a digital microscope (VHX-7000, manufactured by Keyence Corporation) at a magnification of 700x, and the number of holes H formed in the resist pattern 26 was counted, as shown in Figure 6(ii). The number of holes detected in each field of view was then averaged according to the size of the light-shielding area B (i.e., a maximum of 25 holes for each size) to determine the number of detected dust particles. It should be noted that the more dust particles detected (i.e., the better the resolution), the higher the risk of unnecessary electroplating being applied to areas where circuits should not be formed, and the more likely pattern defects are to occur. For this reason, in each sample, the diameter of the largest light-shielding area B that resulted in 13 or fewer detected dust particles was considered to be the maximum size of dust particles that could cancel out pattern defects. The results are shown in Table 2.

[0051] <Evaluation of high-frequency characteristics> A high-frequency substrate (Panasonic Corporation, MEGTRON7, 68 μm thick x 2 sheets) was prepared as an insulating resin substrate. Carrier-equipped copper foils, each having the surface-treated copper foil 10 prepared in (1) above, were laminated on both sides of this insulating resin substrate so that the treated surface 10a of the surface-treated copper foil 10 was in contact with the insulating resin substrate. Pressing was performed using a vacuum press at a press pressure of 3 MPa, a temperature of 190°C, and a press time of 90 minutes, after which the carrier was peeled off together with the release layer. The surface-treated copper foil 10 was completely removed with a sulfuric acid-hydrogen peroxide etching solution to obtain an insulating substrate 20 having a roughened surface 20a on which the surface shape of the treated surface 10a was transferred. Subsequently, electroless copper plating was performed on this insulating substrate 20 using an electroless copper plating solution (Atotec MV+, Atotec Corporation), forming an electroless plating layer 22 with a thickness of 0.5 μm on the roughened surface side. Subsequently, copper plating was performed until the copper layer thickness reached 18 μm to fabricate a copper-clad laminate. Circuit formation (circuit height: 18 μm, circuit width: 320 μm, circuit length: 300 mm) was then performed on this copper-clad laminate using a cupric chloride etching solution via the subtractive method. In this way, a transmission loss measurement substrate was obtained in which microstrip lines were formed to achieve a characteristic impedance of 50 Ω ± 2 Ω. The transmission loss (dB) at 50 GHz was measured on the obtained transmission loss measurement substrate using a network analyzer (Keysight Technologies, N5225B) under the following settings. (Setting conditions) -IF Bandwidth:100Hz - Frequency: 10MHz~50GHz -Data points: 501 points - Average: Off -Calibration method: SOLT (e-cal)

[0052] The obtained transmission loss (absolute value) at 50 GHz was graded and evaluated according to the following criteria. The results are shown in Table 2. <High-Frequency Characteristic Evaluation Criteria> - Rating A (Best): Transmission loss (absolute value) is less than 13.5 dB - Rating B (Good): Transmission loss (absolute value) is 13.5 dB or more and less than 15.0 dB. - Rating C (Poor): Transmission loss (absolute value) is 15.0 or higher

[0053] [Table 2]

Claims

1. A method for manufacturing printed circuit boards, (a) A step of preparing an insulating substrate having a roughened surface, (b) Electroless plating is performed on the roughened surface of the insulating substrate, and the peak density Sds measured in accordance with EUR15178N is 0.90 μm －２ 1.30 μm or more －２ A step of forming an electroless plating layer with a thickness of 1.0 μm or less, having a surface that is as follows and has an interface development area ratio Sdr of 3.00% or more and 12.00% or less as measured in accordance with EUR15178N, (c) A step of laminating a photoresist on the surface of the electroless plating layer, (d) A step of exposing and developing the photoresist to form a resist pattern, (e) A step of electroplating the electroless plating layer via the resist pattern, (f) A step of peeling off the resist pattern, (g) A step of removing the unnecessary portion of the electroless plating layer exposed by peeling off the resist pattern by etching to form a wiring pattern, A method for manufacturing printed circuit boards, including the method described above.

2. The peak curvature Ssc on the surface of the electroless plating layer, measured according to EUR15178N, is 2.30 μm. －１ 3.50 μm or more －１ The method for manufacturing a printed circuit board according to claim 1, which is as follows:

3. A method for manufacturing a printed circuit board according to claim 1 or 2, wherein the developed area ratio Sdr of the interface on the surface of the electroless plating layer is 5.00% or more and 10.00% or less.

4. The above step (a) is, (a-1) The summit density Sds measured in accordance with EUR15178N is 1.00 μm －２ 1.50 μm or more －２ The following is true, and the peak curvature Ssc measured in accordance with EUR15178N is 4.00 μm －１ 6.00 μm or more －１ Prepare a surface-treated copper foil having the following characteristics, and having a treated surface in which the interface development area ratio Sdr measured in accordance with EUR15178N is 20.00% or more and 40.00% or less. (a-2) After laminating an insulating substrate onto the treated surface of the surface-treated copper foil and transferring the surface shape of the treated surface to the surface of the insulating substrate, (a-3) Remove the surface-treated copper foil by etching to obtain an insulating substrate having the roughened surface. A method for manufacturing a printed circuit board according to claim 1 or 2, including the method described above.

5. The method for manufacturing a printed circuit board according to claim 1 or 2, wherein the thickness of the electroless plating layer is 0.3 μm or more and 1.0 μm or less.

6. The method for manufacturing a printed circuit board according to claim 1 or 2, wherein the photoresist includes a dry film resist.

7. The method for manufacturing a printed circuit board according to claim 6, wherein the thickness of the dry film resist is 2 μm or more and 35 μm or less.

8. The method for manufacturing a printed circuit board according to claim 1 or 2, wherein the thickness of the wiring pattern is 2 μm or more and 30 μm or less.

Images