Gaming machine

JP7887210B2Active Publication Date: 2026-07-09SANSEI R&D KK

Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
SANSEI R&D KK
Filing Date
2025-09-29
Publication Date
2026-07-09

Smart Images

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    Figure 0007887210000001
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    Figure 0007887210000003
Patent Text Reader

Abstract

To achieve efficient control processing.SOLUTION: A CPU for inner frame side control executes processing in which information from a game control board received by an inner frame side control data register is saved in an inner frame side control buffer and, if the inner frame side control buffer includes a main frame matching verification value from main control game information transmission processing, the CPU executes: a first inner frame side control load instruction to set an address value which is an address value of the inner frame side control buffer plus one to a first inner frame side control pair register composed of a first inner frame side control register and a second inner frame side control register out of a plurality of inner frame side control general-purpose registers; and a first inner frame side control calling instruction to call and execute first frame matching check processing for checking a combination of the game control board and an inner frame side control board after the first inner frame side control load instruction.SELECTED DRAWING: Figure 326
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Claims

[Claim 1] The outer frame that is fixed to the gaming island, The aforementioned outer frame is attached to the front frame so as to be openable and closable, and the front frame has an opening, The front frame is attached in a manner that allows it to be opened and closed, and the inner frame is attached in a manner that allows it to be opened and closed, A game board that is detachably attached to the inner frame and in which a game area visible through the opening is formed, A launching device attached to the inner frame below the game board, capable of launching game balls toward the game area, A power supply board box that houses a power supply board, which is attached to the rear side of the inner frame below the game board, A game control board box, which houses a game control board mounted on the rear of the game board and on which a game control microprocessor for controlling the progress of the game is implemented, An inner frame control board box is installed at the rear of the inner frame below the game board, in a position different from the power supply board box, and houses an inner frame control board on which an inner frame control microprocessor that performs various controls based on commands from the game control board is mounted; A performance control board box is installed on the rear side of the game board, at a position different from the game control board box, and houses a performance control board on which a performance control microprocessor capable of controlling the progress of the performance based on commands from the game control board is mounted; A gaming machine equipped with, On the front side of the game board, a display unit is arranged that includes at least the display shown in Figure 1, the display shown in Figure 2, the game status display, and the win display, and the display unit is controlled by the game control microprocessor. The aforementioned game control microprocessor includes: Game control CPU, A game control program executed by the game control CPU, and a game control ROM in which information referenced by the game control program is stored, A game control RAM capable of storing information updated by the aforementioned game control program, A game control serial port that transmits and receives information bidirectionally between the game control board and the inner frame side control board as a serial signal using a game control data register, It is built in to at least The aforementioned game control CPU is Multiple 1-byte general-purpose game control registers, A 1-byte game control flag register, Having at least, The aforementioned game control CPU is In a state where a first data value is set in the first game control register among the plurality of general-purpose game control registers, and a second data value is set in the second game control register among the plurality of general-purpose game control registers, A first game control load instruction sets the transmission length in the third game control register among the plurality of general-purpose game control registers, A first game control call command that writes the transmission length, which is the value of the third game control register set by the first game control load command, to the game control data register, thereby calling and executing a frame transmission process that outputs the transmission length as a serial signal to the inner frame side control board, A second game control load instruction sets the first data value, which is the value of the first game control register, into the third game control register, A second game control call command calls and executes the frame transmission process, which outputs the first data value, which is the value of the third game control register set by the second game control load command, to the game control data register, thereby outputting the first data value as a serial signal to the inner frame side control board. A third game control load instruction sets the second data value, which is the value of the second game control register, into the third game control register, A third game control call command which calls and executes the frame transmission process which outputs the second data value, which is the value of the third game control register set by the third game control load command, to the game control data register, thereby outputting the second data value as a serial signal to the inner frame side control board, It is possible to perform a main control game information transmission process consisting of at least the following: The aforementioned game control CPU is A fourth game control load command sets a first predetermined game control value in a first game control pair register, which is composed of the first game control register and the second game control register. A first game control determination command that determines whether or not the symbol variation time is being shortened based on a game state flag stored in the game control RAM, When the symbol variation time is being shortened by the first game control determination command, the first game control bit set command sets a specific bit of the second game control register to 1, A first game control operation instruction compares the value of the second game control register with the value of the performance information comparison data stored in the game control RAM, The first game control return instruction returns to the calling process when the results of the comparison in the first game control calculation instruction match and the value of the zero flag in the game control flag register is 1, A fifth game control load instruction saves the value of the second game control register to the value of the performance information comparison data stored in the game control RAM when the results of the comparison in the first game control calculation instruction do not match and the value of the zero flag in the game control flag register is not 1. A first game control logic operation instruction performs a logical OR operation on the value of the second game control register with the main frame match verification value, which indicates the verification value of the match between the game control board and the inner frame side control board. A fourth game control call instruction calls and executes the main control game information transmission process, which transmits the value of the first game control pair register to the inner frame side control board, after the first game control logic operation instruction. When a periodic interrupt occurs, the performance information status notification process, which consists of at least the following, is executed: The inner frame side control microprocessor includes: Inner frame side control CPU, The inner frame control program executed by the inner frame control CPU, and the inner frame control ROM storing information referenced by the inner frame control program, An inner frame side control RAM capable of storing information updated by the inner frame side control program, An inner frame side control serial port that transmits and receives information bidirectionally between the game control board and the inner frame side control board as a serial signal using an inner frame side control data register, It is built in to at least The inner frame side control CPU is Multiple 1-byte general-purpose inner frame control registers, A 1-byte inner frame control flag register, Having at least, The inner frame side control RAM includes: Inner frame side control buffer There is at least one such instance. The inner frame side control CPU is The process of saving the information received from the game control board in the inner frame side control data register to the inner frame side control buffer, When the inner frame control buffer contains the main frame match verification value from the main control game information transmission process, a first inner frame control load instruction sets the address value obtained by adding 1 to the address value of the inner frame control buffer in the first inner frame control pair register, which is composed of the first inner frame control register and the second inner frame control register among the plurality of inner frame control general-purpose registers. Following the first inner frame side control load command, a first inner frame side control call command is issued to call and execute a main frame matching check process that checks the combination of the game control board and the inner frame side control board, The main control reception process, consisting of at least the following, is executed: The inner frame side control CPU is A first inner frame control operation instruction compares the value of the second inner frame control register with the first inner frame control predetermined value, If the results of the comparison in the first inner frame side control calculation instruction do not match and the value of the zero flag in the inner frame side control flag register is not 1, the first inner frame side control return instruction returns to the main control reception process, which is the calling process. If the results of the comparison in the first inner frame control operation instruction match and the value of the zero flag in the inner frame control flag register is 1, then a second inner frame control load instruction sets the value of the first inner frame control register in the third inner frame control register among the plurality of inner frame control general-purpose registers, A second inner frame control operation instruction that takes the logical AND of the value of the first inner frame control register and the second inner frame control predetermined value, A third inner frame control load instruction sets the value of the first inner frame control pair register in a second inner frame control pair register, which is composed of a fourth inner frame control register and a fifth inner frame control register from among the plurality of inner frame control general-purpose registers, A third inner frame control operation instruction that takes the logical AND of the value of the third inner frame control register and the third inner frame control predetermined value, A fourth inner frame control operation instruction compares the value of the third inner frame control register with the main frame match verification value, and if the comparison results in a match and the value of the zero flag in the inner frame control flag register is 1, returns to the main control reception process, which is the calling process. If the results of the comparison in the fourth inner frame side control calculation instruction do not match and the value of the zero flag in the inner frame side control flag register is not 1, a fourth inner frame side control load instruction sets the fourth inner frame side control predetermined value in the first inner frame side control pair register, A second inner frame side control call command calls and executes a main transmission process that outputs the value of the first inner frame side control pair register set by the fourth inner frame side control load command to the game control board, After the execution of the main transmission process is completed, a second inner frame side control return command is issued to return to the main control reception process, which is the calling process, The main frame matching check process, which consists of at least the following, is performed. A gaming machine characterized by the following features.