Red LED and manufacturing method

Abstract

The red light-emitting diode (LED) includes an n-doped portion, a p-doped portion, and a light-emitting region disposed between the n-doped portion and the p-doped portion. The light-emitting region includes an indium gallium nitride light-emitting layer that emits light at a peak wavelength between 600 and 750 nm under an electrical bias, a III-nitride layer disposed on the indium gallium nitride light-emitting layer, and a III-nitride barrier layer disposed on the III-nitride layer, and the light-emitting diode includes a porous region of III-nitride material. Red mini-LEDs, red micro-LEDs, arrays of micro-LEDs, and methods for manufacturing red LEDs are also provided.

Description

[Technical Field]

[0001] The present invention relates to a red LED and an improved method for manufacturing a red LED. [Background technology]

[0002] III-V semiconductor materials, particularly the group of III nitride semiconductor materials, are especially important in semiconductor device design.

[0003] Group III-V semiconductors include binary, ternary, and quaternary alloys of Group III elements such as Ga, Al, and In, and Group V elements such as N, P, As, and Sb, and are important in many application fields, including optoelectronics.

[0004] Of particular importance is the class of semiconductor materials known as "Group III nitrides," which includes gallium nitride (GaN), indium nitride (InN), aluminum nitride (AlN), and their ternary and quaternary alloys. (Al,In)GaN is a term that encompasses AlGaN, InGaN, and GaN. Group III nitride materials have not only achieved commercial success in semiconductor lighting and power electronics, but also offer special advantages in quantum light sources and light-matter interactions.

[0005] In optoelectronic semiconductor devices, doping GaN semiconductor material with indium (Indium) is of interest. This is because variations in the In content of the semiconductor change the material's electron bandgap, and therefore the emission wavelength of the semiconductor. However, variations in the In content of the material also affect the in-plane lattice constant of the semiconductor. For example, the in-plane lattice constant of InN is approximately 11% larger than that of GaN, and the lattice dimensions of the intermediate composition vary depending on the indium content. Therefore, when it is desirable to deposit the active semiconductor layer on substrate layers with different lattice dimensions, device design problems arise. This is because lattice mismatch at the layer boundaries introduces strain into the lattice, which in turn forms defects in the material that act as non-radiative recombination centers. This significantly impairs the performance of the device.

[0006] There is a very high demand for red LEDs, but manufacturers have historically struggled to make LEDs emit light at the red wavelength.

[0007] One of the major challenges in growing long-wavelength LEDs, such as red LEDs, on GaN-based platforms is the need for high indium (In) content to reduce the bandgap of the active region to a level suitable for long-wavelength emission. The required InGaN active region has larger lattice parameters than the underlying GaN layer, and the resulting strain forms defects that act as non-radiative recombination centers within the material, degrading device performance.

[0008] Therefore, due to the large lattice mismatch between InN and GaN, it is difficult to achieve high-quality InGaN (with a high indium content of over 20%). Furthermore, mismatch strain leads to a reduction in indium composition due to the compositional pull effect.

[0009] Relatively short-wavelength LEDs, such as green and yellow LEDs, can be fabricated much more easily because they use an InGaN light-emitting region with a lower indium content than required for red light emission.

[0010] Due to such problems, conventional attempts to generate red wavelength LEDs on GaN platforms have not been successful.

Summary of the Invention

[0011] This application relates to an improved manufacturing method for semiconductor devices, particularly red LEDs, and red LEDs manufactured using this method.

[0012] The present invention is defined in the independent claims, which are hereby incorporated by reference. Preferred or advantageous features of the invention are described in the appended dependent claims.

[0013] The light-emitting diodes, i.e., LEDs, described in this application are preferably formed from III-V semiconductor materials, particularly preferably from group III nitride semiconductor materials.

[0014] "III-V" group semiconductors include binary alloys, ternary alloys, and quaternary alloys of group III elements such as Ga, Al, and In, and group V elements such as N, P, As, and Sb, and are important in many application fields including optoelectronics.

[0015] Particularly important is the class of semiconductor materials known as "group III nitride" materials, which include gallium nitride (GaN), indium nitride (InN), aluminum nitride (AlN), and their ternary and quaternary alloys (Al,In)GaN. In the present invention, different crystal orientations such as the polar c-plane, non-polar, and semi-polar orientations can be used. There are two main non-polar orientations, namely the a-plane (11-20) and the m-plane (1-100). For semi-polar, there are (11-22) and the crystal plane family {2021}. Group III nitride materials have not only achieved commercial success in semiconductor lighting and power electronics but also have special advantages in quantum light sources and the interaction between light and matter.

[0016] Many group III nitride materials are of commercial interest, but gallium nitride (GaN) is widely recognized as one of the most important new semiconductor materials and is particularly important in many applications.

[0017] Introducing pores into bulk group III nitrides such as GaN is known to have a significant impact on their material properties (optical, mechanical, electrical, thermal, etc.). Therefore, by varying the porosity of GaN and group III nitride semiconductors, it may be possible to tune their various material properties, making porous GaN important in optoelectronic applications.

[0018] The present invention is described with reference to GaN and InGaN, but is also advantageously applicable to alternative combinations of group III nitride materials.

[0019] In the following description, the substrate for growth is a semiconductor structure, and additional semiconductor layers are grown thereon to obtain a semiconductor device. An exemplary substrate for growth in the present invention is a GaN semiconductor structure including a plurality of layers of doped GaN and undoped GaN.

[0020] Layers of a semiconductor structure can be made porous by electrochemical etching. This is described in International Patent Applications PCT / GB2017 / 052895 (published as International Publication No. WO 2019 / 063957) and PCT / GB2019 / 050213 (published as International Publication No. WO 2019 / 145728).

[0021] The inventors have found that the present invention can advantageously provide red light emitting diodes (LEDs).

[0022] (Semiconductor structure) According to a first aspect of the present invention, a red light emitting diode (LED) is provided. This is an n-doped portion, a p-doped portion, a light emitting region disposed between the n-doped portion and the p-doped portion, An indium gallium nitride light-emitting layer that emits light at a peak wavelength of 600-750 nm under electrical bias, A group III nitride layer disposed on an indium gallium nitride luminescent layer, and a group III nitride barrier layer disposed on the group III nitride layer, A light-emitting region including, A photoluminescent diode containing a porous region of a group III nitride material.

[0023] The inventors have found that electrochemical porosification of Group III nitride materials advantageously reduces strain within the Group III nitride lattice and overall wafer warping and curvature. Although we do not like theoretical constraints, it is thought that the process of porosifying the porous regions of Group III nitride materials also etches away structural defects such as threading dislocations that formed during the growth of this layer on top of a first Group III nitride material layer.

[0024] When dislocations are removed from the porous regions of a semiconductor material during porosity formation, the strain within the porous regions, particularly the strain that occurs when the lattice dimensions of the porous regions do not match those of the underlying material, is significantly reduced. Therefore, in the epitaxial growth of semiconductor structures, when a group III nitride material layer is deposited above a porous region, the porous material becomes more easily aligned with the lattice of the non-porous layer above it. As a result, the strain in the layer above the porous region is significantly smaller than in the case where no porous region exists.

[0025] As the strain of the second group III nitride material decreases, the number of structural defects within the non-porous layer that act as non-radiative recombination centers, which impair device performance, also decreases.

[0026] Compositional Entrapment Effect: Kawaguchi et al. reported on the so-called InGaN compositional entrapment effect. This effect describes how the proportion of indium is small in the early stages of growth but increases with increasing growth thickness. This observation was, to some extent, independent of the underlying GaN or AlGaN. The authors suggested that this effect arises from strain caused by lattice mismatch at the interface. The authors found that as the lattice mismatch between InGaN and the bottom epitaxial layer increases, the change in In content becomes larger.

[0027] Inatomi et al.'s "Theoretical study of the composition pulling effect in InGaN metalorganic vapor-phase epitaxy growth" (Journal of the Japan Society of Applied Physics, Vol. 56, No. 7) revealed that compressive strain suppresses InN uptake. On the other hand, tensile strain promotes InN uptake compared to relaxed bulk growth.

[0028] The inventors have found that using porous regions in a semiconductor structure induces "strain relaxation," which reduces strain within the layers of the semiconductor structure. This reduces intralayer strain in the semiconductor structure, resulting in an improvement in compositional incorporation effect. Porous formation reduces strain within the group III nitride layer, and the reduced strain in the semiconductor structure creates conditions for incorporating more indium. Therefore, the present invention facilitates the incorporation of a large amount of indium into the LED layer grown on top of the porous region, which is highly desirable for long-wavelength emission.

[0029] The n-doped region, the light-emitting region, and the p-doped region are preferably provided above the porous region. In other words, in the LED structure, the porous region is located below the n-doped region, the light-emitting region, and the p-doped region.

[0030] By incorporating porous regions of Group III nitride material within the LED, n-doped regions, light-emitting regions, and p-doped regions can be grown on top of the porous regions with less strain than would be possible in the absence of such porous regions. Therefore, reducing the strain level of such a layered semiconductor structure promotes the incorporation of a large amount of indium into one or more light-emitting layers of the LED, making it possible to grow high-quality InGaN light-emitting layers with a high indium content. As a result, sufficient indium can be incorporated into the indium gallium nitride light-emitting layer, and the LED emits light at a peak wavelength of 600-750 nm when an electrical bias is applied.

[0031] As mentioned in the background technology section above, there is a very large demand for red LEDs that emit light in the 600-750nm range. However, it has been difficult to complete red InGaN LEDs due to the technical challenges of incorporating sufficient indium into one or more light-emitting layers. Short-wavelength LEDs, such as green (500-500nm) and yellow (550-600nm) LEDs, can be manufactured using InGaN light-emitting regions with a lower indium content than required for red light emission, making them much easier to produce.

[0032] The inventors have found that when an LED structure is grown on a porous region of a group III nitride material, the emission wavelength shifts significantly to the longer wavelength side compared to when the same LED structure is grown on a non-porous substrate.

[0033] To demonstrate this, the inventors grew a conventional green / yellow (emitting in the 500-550 nm or 550 nm-600 nm range) InGaN LED structure on a non-porous GaN wafer and confirmed that this LED emitted green / yellow light as expected. Next, they grew the same "green / yellow" InGaN LED structure on a template containing porous regions. When an electrical bias was applied to this LED, the LED emitted light in the red range of 600-750 nm.

[0034] Therefore, since the present invention allows conventional easily manufactured LED structures to be shifted to emit long wavelengths, structures previously used as yellow or green LEDs can be made into red LEDs by incorporating porous regions within the structure. This makes it possible to advantageously manufacture red LEDs without causing many of the technical problems experienced in the design of the prior art.

[0035] The LED light-emitting region is an LED light-emitting region that emits light at peak wavelengths of 500-600nm, 500nm-550nm, 550nm-600nm, 510-570nm, 530nm-560nm, or 540nm-600nm. When the LED light-emitting region is not grown on a porous group III nitride layer, the LED light-emitting region emits light at peak wavelengths of 500-600nm, 510-570nm, 530nm-560nm, or 540nm-600nm. However, when the LED light-emitting layer is grown on a porous region of group III nitride material, the emission wavelength of the light-emitting region shifts to 600-750nm.

[0036] The luminescent region emits light at a peak wavelength of 600-750 nm under electrical bias, or at 600-700 nm, 615-675 nm, or 600-660 nm under electrical bias.

[0037] In one aspect of the present invention, a red light-emitting diode (LED) may be provided. n-doped section and, p-doped section, A light-emitting region between the n-doped portion and the p-doped portion, comprising an indium gallium nitride light-emitting layer that emits light at a peak wavelength of 500 nm to 550 nm or 550 nm to 600 nm, The light-emitting diode is placed on a porous region of a group III nitride material, and the porous region of the group III nitride material shifts the emission wavelength of the emission region to a peak wavelength of 600-750 nm under an electrical bias.

[0038] The red LED includes a yellow or green InGaN LED structure grown on a porous region of a group III nitride material.

[0039] The light-emitting diode includes at least one feature selected from the following: (a) The luminescent region includes 1, 2, 3, 4, 5, 6, 7, or 8 quantum wells (or at least 1 quantum well). Or, (b) The group III nitride layer has a composition of Al y Ga (1-y) It contains an aluminum gallium nitride layer where N is in the range of 0.1 to 1.0. Or, (c) Between the n-doped region and the light-emitting region, an ultraviolet-emitting or blue-emitting InGaN / GaN, an InGaN / inGaN superlattice, or an InGaN layer is arranged.

[0040] The thickness of the porous region is at least 1 nm, preferably at least 10 nm, and particularly preferably at least 50 nm. For example, the porous region has a thickness of 1 nm to 10,000 nm. The porous region is porous with a porosity of 1% to 99%.

[0041] The porous region is located below or beneath the n-type region, light-emitting region, and p-type region of the LED. Preferably, the n-type region, light-emitting region, and p-type region (LED structure) are located on or above the porous region, as defined by the growth order of the layers within the LED. The LED structure is preferably grown on the porous region so as to benefit from the strain relaxation of the porous group III nitride layer.

[0042] The red LED includes a connecting layer of a group III nitride material positioned between the n-doped region and the porous region. Preferably, the thickness of the connecting layer is at least 100 nm, but a smaller or larger thickness may be used.

[0043] The red LED preferably includes a non-porous intermediate layer in the porous region of a group III nitride material between the porous region and the light-emitting region. Since the porous region is preferably formed by electrochemical porosity through the non-porous layer of the group III nitride material, the non-porous layer of the group III nitride material typically forms a non-porous intermediate layer that is maintained on top of the porous region. This method is described in PCT / GB2017 / 052895 (published as International Publication 2019 / 063957) and PCT / GB2019 / 050213 (published as International Publication 2019 / 145728). The non-porous intermediate layer advantageously provides a smooth surface for subsequent further layer growth through the manufacturing process.

[0044] Preferably, the LED includes a non-porous intermediate layer of a group III nitride material between the porous region and the connecting layer. This is preferably a non-porous layer, and the electrochemical etching of the porous region is performed through this non-porous layer.

[0045] The porous region can be a single porous layer, in which case the light-emitting diode includes a porous layer of group III nitride material. Preferably, the porous region is a continuously porous layer formed from, for example, a continuous layer of porous group III nitride material.

[0046] The porous region may include multiple porous layers and optionally multiple non-porous layers. In a preferred embodiment of the present invention, the porous region is a stack of alternating porous and non-porous layers, where the top surface of the stack defines the top portion of the porous region and the bottom surface of the stack defines the bottom portion of the porous region. The light-emitting region is formed on top of the porous region, which includes a stack of porous layers of a group III nitride material.

[0047] In some embodiments, the light-emitting region is located on a stack of multiple porous layers of a group III nitride material. Therefore, the porous region is a stack of multiple layers of group III nitride material, where at least some layers are porous, rather than a single porous layer of the group III nitride material. The stack of porous layers is preferably a stack consisting of alternating layers of porous and non-porous layers.

[0048] Alternatively, the porous region is a group III nitride material layer containing one or more porous regions, for example, one or more porous regions contained within a non-porous layer of group III nitride material.

[0049] In a preferred embodiment, the porous region or porous layer has lateral dimensions (width or length) equivalent to those of the substrate on which the porous layer or porous region is grown. For example, conventional substrate wafer sizes vary, for instance, 1 cm. 2 , or diameters of 2 inches, 4 inches, 6 inches, 8 inches, 12 inches, or 16 inches. However, by patterning one or more layers and / or depositing regions with different charge carrier concentrations within the same layer, it is possible to form small porous regions that do not extend to the entire substrate. Therefore, the lateral dimensions of the porous layer or porous region can vary from about one-tenth the size of a pixel (e.g., 0.1 μm) to the lateral dimensions of the substrate itself. The n-doped portion preferably includes an n-doped group III nitride layer.

[0050] Preferably, the n-doped portion and / or n-doped layer includes a stack consisting of alternating layers of n-GaN, n-InGaN, or n-GaN / n-InGaN layers, or a stack consisting of alternating layers of n-InGaN / n-InGaN layers containing different concentrations of indium.

[0051] The n-doped portion includes a single-crystal n-doped group III nitride portion, and preferably the n-doped portion includes a single-crystal n-doped group III nitride layer having a flat top surface.

[0052] Each layer between the porous region and the single-crystal n-doped group III nitride layer is a flat layer having its own top surface and bottom surface, parallel to the flat top surface of the single-crystal n-doped group III nitride layer.

[0053] The indium gallium nitride light-emitting layer preferably comprises one or more InGaN quantum wells, and more preferably comprises 1 to 7 quantum wells.

[0054] The indium gallium nitride luminescent layer is an InGaN nanostructure layer containing quantum structures such as quantum dots, fragmentary quantum wells, or discontinuous quantum wells.

[0055] The indium gallium nitride light-emitting layer and / or quantum well preferably has the composition In x Ga 1-x N has the following properties: where 0.15 ≤ x ≤ 0.40, preferably 0.20 ≤ x ≤ 0.40 or 0.26 ≤ x ≤ 0.40, and particularly preferably 0.30 ≤ x ≤ 0.40.

[0056] The red LED preferably includes a group III nitride layer disposed on an indium gallium nitride light-emitting layer and a group III nitride barrier layer disposed on the group III nitride layer.

[0057] The group III nitride layer on the InGaN emissive layer is called the "cap layer." This cap layer is used for the following purposes: 1) to increase the quantum confinement effect against band bending, thereby achieving red shift and red emission; and 2) to protect the high In% in InGaN and ensure sufficient In% incorporation, thereby achieving long wavelengths and providing a large barrier.

[0058] The LED preferably includes a cap layer of a group III nitride material between the quantum well and the p-doped region. The cap layer is GaN, InGaN, AlGaN, or AlN.

[0059] The LED preferably includes a barrier layer of a group III nitride material between the quantum well and the p-doped region. The barrier layer is GaN, InGaN, AlGaN, or AlN.

[0060] The p-doped region includes a p-doped group III nitride layer and a p-doped aluminum gallium nitride layer disposed between the p-doped group III nitride layer and the light-emitting region. The p-doped aluminum nitride layer is preferably an electron blocking layer (EBL) disposed between the cap layer and the P-type layer, the electron blocking layer contains 5 to 25 at% aluminum, and preferably the thickness of the electron blocking layer is 10 to 50 nm.

[0061] The porous region is preferably not part of the distributed Bragg reflector (DBR).

[0062] (Red mini LED) A second aspect of the present invention provides a red mini-LED, which includes a red LED according to the first aspect of the present invention, wherein the light-emitting region has lateral dimensions (width and length) greater than 100 μm and less than 200 μm.

[0063] (Red micro LED) A third aspect of the present invention provides a red microLED, including a red LED according to the first aspect of the present invention, wherein the light-emitting region has a lateral dimension less than 100 μm. The microLED preferably has a lateral dimension of 80 μm, or 70 μm, or 60 μm, or 50 μm, or 30 μm, or 25 μm, or 20 μm, or 15 μm, or 10 μm, or 5 μm, or 3 μm, or less than 1 μm.

[0064] (Micro LED array) A fourth aspect of the present invention provides a microLED array including a plurality of red microLEDs according to a third aspect of the present invention.

[0065] (Manufacturing method) A fifth aspect of the present invention provides a method for manufacturing a red LED, the method comprising placing a porous region of a group III nitride material on top of the material. n-doped section and, p-doped section, A light-emitting region is positioned between an n-doped portion and a p-doped portion, and includes an indium gallium nitride light-emitting layer that emits light at a peak wavelength of 600-750 nm under an electrical bias, This includes steps to promote growth.

[0066] The n-doped region, p-doped region, and light-emitting region include a yellow or green InGaN LED structure, as further described below.

[0067] Alternatively, the method includes the step of growing a red LED structure on a porous region of a group III nitride material at a growth temperature higher than previously possible. Because the presence of the porous region of the group III nitride material relaxes the strain in the semiconductor lattice, a higher growth temperature than usual can be used for the purpose of incorporating the indium necessary when growing the InGaN light-emitting layer. The red LED structure grown on the porous region can be any known red LED structure, but in this case, by using a porous template, it is advantageous to grow a red LED light-emitting layer, such as an InGaN quantum well (QW), at a growth temperature higher than possible when growing on a non-porous substrate.

[0068] A sixth aspect of the present invention provides a method for manufacturing a red LED, the method comprising placing a porous region of a group III nitride material on top of the material. n-doped section and, p-doped section, An LED light-emitting region between an n-doped portion and a p-doped portion, comprising an indium gallium nitride light-emitting layer that emits light at a peak wavelength of 500 nm to 550 nm or 550 nm to 600 nm, The process includes a step of growing the material on a porous region of a group III nitride material, thereby shifting the emission wavelength of the emission region to a peak wavelength of 600-750 nm under electrical bias.

[0069] The following considerations apply to both the fifth and sixth aspects of the present invention.

[0070] The light-emitting region includes an indium gallium nitride light-emitting layer that emits light at peak wavelengths of 500-550 nm, 500-580 nm, 510-570 nm, 530-560 nm, or 550-600 nm. The indium gallium nitride light-emitting layer is one or more layers that are known to emit light at these wavelengths when grown with conventional LEDs, for example on a non-porous GaN substrate. However, the inventors have found that when a conventional yellow or green LED structure is grown on a porous group III nitride layer, an LED that emits light at a peak wavelength of 600-750 nm is obtained under electrical bias.

[0071] The method includes the step of growing a yellow or green LED structure on a porous region of a group III nitride material.

[0072] By growing it on a porous region of a group III nitride material, an emission region that emits light at a peak wavelength of 615-665 nm under electrical bias can be obtained.

[0073] The following features apply equally to both the fifth and sixth aspects of the present invention.

[0074] The method comprises a first step of electrochemically porosizing a layer of group III nitride material to form a porous region of the group III nitride material. This is achieved using a wafer-scale porosizing process, which is described in international patent applications PCT / GB2017 / 052895 (published as international publication 2019 / 063957) and PCT / GB2019 / 050213 (published as international publication 2019 / 145728).

[0075] The method preferably includes the step of forming a porous region of a group III nitride material by electrochemical porosity through a non-porous layer of the group III nitride material, thereby forming a non-porous intermediate layer. The non-porous intermediate layer advantageously provides a smooth surface for subsequent layer growth, such as one or more connecting layers of the group III nitride material.

[0076] Porous regions are formed by porousizing one or more layers or regions of a group III nitride material on a substrate. Substrates include silicon, sapphire, SiC, and β-Ga2O3. The crystal orientation of the substrate can be polar, semipolar, or nonpolar. The substrate thickness can typically vary between 100 μm and 1500 μm.

[0077] The porous region can be a single porous layer, and therefore the method includes the steps of growing n-doped portions, p-doped portions, and LED light-emitting regions on a porous layer of a group III nitride material. Preferably, the porous region is a continuously porous layer, for example, formed from a continuous layer of porous group III nitride material.

[0078] The porous region comprises multiple porous layers and optionally multiple non-porous layers. In a preferred embodiment of the present invention, the porous region is a stack consisting of alternating layers of porous and non-porous layers, where the top surface of the stack defines the top portion of the porous region and the bottom surface of the stack defines the bottom portion of the porous region.

[0079] Alternatively, the porous region is a group III nitride material layer containing one or more porous regions, for example, one or more porous regions contained within a non-porous layer of group III nitride material.

[0080] In a preferred embodiment, the porous region or porous layer has lateral dimensions (width or length) equivalent to those of the substrate on which the porous layer or porous region is grown. For example, conventional substrate wafer sizes can vary, for instance, 1 cm. 2、or 2 inches, 4 inches, 6 inches, 8 inches, 12 inches, or 16 inches in diameter. However, by patterning one or more layers and / or depositing regions with different charge carrier concentrations within the same layer, it is also possible to form small porous regions that do not extend across the entire substrate. Thus, the lateral dimension of the porous layer or region can vary from about one-tenth of a pixel (e.g., 0.1 μm) to the lateral dimension of the substrate itself.

[0081] Prior to the porosification step, a doped region of an n-doped group III nitride semiconductor material can be deposited on the substrate, preferably comprising a stack of one or more layers. The one or more group III nitride layers can comprise one or some combinations of the elements Al, Ga, In (ternary layer, quaternary layer). The thickness of the group III nitride stack is preferably 10 - 4000 nm. The group III nitride layer has a doping concentration of 1×10 17 cm -3 ~5×10 20 cm -3 .

[0082] Preferably, an intermediate layer of undoped group III nitride material is deposited on the doped material before the doped material is porosified. The thickness of the intermediate layer is preferably 1 nm - 3000 nm, preferably 5 nm - 2000 nm. Since the intermediate layer is undoped, it remains non-porous after the porosification step, which advantageously provides a good surface for the epitaxial growth of further layers of the semiconductor.

[0083] In a preferred embodiment, the doped region is composed of a stack of alternating doped and undoped layers. In a preferred embodiment, the stack comprises 5 - 50 pairs of layers. The thickness of each highly doped layer varies between 10 nm and 200 nm, and the thickness of the lowly doped or undoped layer is 5 - 180 nm.

[0084] As is known in the art, electrochemical porosification removes material from the n-type doped regions of the group III nitride material, creating empty pores in the semiconductor material.

[0085] In a preferred embodiment, the red LED structure is formed on a stack of multiple porous layers of a group III nitride material. Therefore, the porous region is a stack of multiple layers of group III nitride material, where at least some layers are porous, rather than a single porous layer of group III nitride material. The stack of porous layers is preferably a stack of alternating porous and non-porous layers.

[0086] The method preferably includes the step of depositing one or more connecting layers of group III nitride material on the surface of an intermediate layer of group III nitride material, prior to the step of growing n-doped regions, LED light-emitting regions, and p-doped regions on the connecting layer.

[0087] Alternatively, if there is no non-porous intermediate layer on the porous region, the method includes the step of depositing a connecting layer of group III nitride material on the surface of the porous region of group III nitride material.

[0088] The method includes the further step of growing n-doped regions, LED light-emitting regions, and p-doped regions on the connecting layer.

[0089] The red LED manufactured by this manufacturing method is preferably a red LED according to one of the first to fourth embodiments of the present invention.

[0090] Features described in relation to one aspect of the present invention are equally applicable to other aspects of the present invention. [Brief explanation of the drawing]

[0091] Embodiments of the present invention will now be described with reference to the drawings.

[0092] Figure 1 shows a porous template suitable for a red LED according to the present invention. Figures 2-13 illustrate the steps for manufacturing a red LED according to a preferred embodiment of the present invention. Figure 14 is a graph of normalized electroluminescence (EL) intensity and wavelength in an InGaN LED on a porous region according to a preferred embodiment of the present invention. Figure 15 shows graphs of normalized electroluminescence (EL) intensity and wavelength for various current injections in an InGaN LED on a non-porous substrate. Figure 16 is a graph of normalized electroluminescence (EL) intensity and wavelength for various current injections in the same InGaN LED as in Figure 15, grown on a porous region according to a preferred embodiment of the present invention. Figure 17 shows the IV curves measured for InGaN microLEDs of various pixel sizes on a non-porous substrate, with the inset plot showing yellow emission. Figure 18 shows the IV curves measured for InGaN microLEDs of various pixel sizes on a porous substrate, with the inset diagram showing red light emission.

[0093] Figure 1 shows a porous template suitable for a red LED according to the present invention.

[0094] The porous template includes a porous region of group III nitride material on a substrate, with a non-porous layer of group III nitride material positioned on the top surface of the porous region. Optionally, a further layer of group III nitride material may also be present between the substrate and the porous region.

[0095] As detailed below, a porous region can be provided by epitaxially growing an n-doped region of a group III nitride material, followed by an undoped layer of the same group III nitride material, and then porousizing the n-doped region using a porousization process. The porousization process is described in international patent applications PCT / GB2017 / 052895 (published as international publication 2019 / 063957) and PCT / GB2019 / 050213 (published as international publication 2019 / 145728).

[0096] As described above, this porosity relaxes the strain in the crystal lattice, meaning that subsequent growth of semiconductor layers benefits from the reduced compressive strain within the lattice.

[0097] The porous region may comprise one or more layers of one or more group III nitride materials, having a range of thicknesses, but in all cases, it provides a wavelength-shifting strain-relaxing benefit to an InGaN luminescent layer grown above the porous region. In a preferred embodiment, the porous region comprises, for example, GaN and / or InGaN.

[0098] Various LED structures can be grown on the template shown in Figure 1.

[0099] Specifically, an LED structure containing an InGaN light-emitting layer, known in the art as a yellow or green LED, can be grown on a porous template using standard LED manufacturing steps. However, when grown on a porous template, an LED structure that normally emits light at yellow or green wavelengths will emit light at red wavelengths of 600-750 nm.

[0100] In this way, red LEDs can be easily manufactured by using a porous region of a group III nitride material as a template or pseudo-substrate for growing yellow or green InGaN LEDs.

[0101] In a preferred embodiment, a red LED according to the present invention comprises the following layers and is manufactured using the stepwise process described below.

[0102] The following description of the LED structure relates to a top-emission architecture, described sequentially from bottom to top; however, the present invention is equally applicable to a bottom-emission architecture.

[0103] (Figure 2: Substrate and Group III nitride layer for porous structure) A suitable substrate is used as the starting surface for epitaxial growth. The substrate can be silicon, sapphire, SiC, β-Ga2O3, GaN, glass, or metal. The substrate's crystal orientation can be polar, semipolar, or nonpolar. The substrate size is 1 cm². 2 The diameter can vary from 2 inches, 4 inches, 6 inches, 8 inches, 12 inches, 16 inches, and beyond. The substrate thickness is greater than 1 μm, for example, from 1 μm to 15,000 μm.

[0104] One or more layers of a group III nitride material are epitaxially grown on a substrate. The group III nitride layer may contain one or more combinations of the elements Al, Ga, and In (a binary, ternary, or quaternary layer).

[0105] The thickness T of the group III nitride stack is preferably at least 10 nm, or at least 50 nm, or at least 100 nm, for example, 10 to 10000 nm.

[0106] Group III nitride layer: 1 × 10 17 cm -3 ~5×10 20 cm -3 It includes a doped region having an n-type doping concentration. The group III nitride layer may also include an undoped "cap" layer of group III nitride material above the doped region.

[0107] The doped region ends at the exposed upper surface of the group III nitride layer, in which case the surface of this layer becomes porous during electrochemical etching.

[0108] Alternatively, the doped region of the group III nitride material may be covered with an undoped "cap" layer of group III nitride material to set the doped region below the surface of the semiconductor structure. The starting depth (d) of the subsurface doped region is, for example, 1 to 2000 nm.

[0109] (Figure 3: Porousization of porous regions) A group III nitride layer (or a stack of multiple layers) is deposited on a substrate and then porousized by a wafer-scale porosization process. This is described in international patent applications PCT / GB2017 / 052895 (published as international publication 2019 / 063957) and PCT / GB2019 / 050213 (published as international publication 2019 / 145728). During this process, the doped regions of the group III nitride material become porous, while the undoped regions of the group III nitride material do not.

[0110] After the porosity modification step, the structure includes porous regions in the areas that were previously n-doped group III nitride material, and optionally also includes non-porous intermediate layers present on top of these porous regions.

[0111] The porosity of the porous region is controlled by an electrochemical etching process, resulting in a porosity of 1% to 99%, preferably 20% to 90% or 30% to 80%, although lower or higher porosities are also used.

[0112] The thickness of the porous region after porosity formation is preferably greater than 1 nm, more preferably greater than 10 nm, and particularly preferably at least 40 nm, 50 nm, or 100 nm. However, the thickness of the material required to obtain the strain relaxation benefits provided by the porous region varies depending on the type of group III nitride material forming the porous region.

[0113] The porous region formed by the porousization process is a bulk layer of a group III nitride material having a uniform composition and uniform porosity throughout the entire layer. Alternatively, the porous region comprises multiple porous material layers with different compositions and / or porosity, forming a porous stack of group III nitride material. For example, the porous region is a continuous layer of porous GaN, or a continuous layer of porous InGaN, or a stack containing one or more layers of porous GaN and / or one or more layers of porous InGaN. The inventors have found that the benefits of strain relaxation in porous regions during layer growth are obtained from diverse porous regions having stacks of different thicknesses, compositions, and layers.

[0114] In the embodiment shown in the drawing, the porous region is a single porous layer.

[0115] When an undoped cap layer of group III nitride material is present on top of a doped region, this undoped region remains non-porous even after the doped region below is porousized through the surface. The thickness D of this non-porous cap layer is preferably at least 2 nm, or at least 5 nm, or at least 10 nm, preferably 5 to 3000 nm. Placing an undoped cap layer on top of a doped region has the advantage that the non-porous layer of group III nitride material covering the porous region is maintained even after the porousization treatment. This non-porous cap layer provides the benefit of allowing further material to grow well above the porous region.

[0116] The porosity methods described in PCT / GB2017 / 052895 (published as International Publication No. 2019 / 063957) and PCT / GB2019 / 050213 (published as International Publication No. 2019 / 145728) can be performed on the entire semiconductor wafer, and therefore no processes / patterning / treatments are required to prepare a template for porosity.

[0117] (Figure 4: Connecting layer) After the formation of the porous layer, a group III nitride LED epitaxy structure can be grown on the porous template / pseudo-substrate provided by the porous layer and the non-porous cap layer.

[0118] The first layer used to grow the LED structure on the template is called the connection layer 1.

[0119] While it is possible to grow the LED epitaxial structure directly on the non-porous cap layer, it is preferable to provide a connecting layer 1 on the cap layer before growing the LED structure. The inventors have found that using a group III nitride connecting layer 1 between the porous region and the LED epitaxy structure advantageously ensures a good epitaxial relationship between the LED and the porous template / substrate. The growth of this layer ensures that subsequent growth on the connecting layer is smooth and epitaxial, resulting in high quality.

[0120] The connecting layer 1 is formed of a group III nitride material and contains one or more combinations of the elements Al, Ga, and In (a binary, ternary, or quaternary layer).

[0121] The connecting layer can be a doped or undoped layer. The connecting layer can optionally be doped with a suitable n-type dopant material such as Si, Ge, C, or O. The group III nitride layer has a thickness of 1 × 10⁻⁶. 17 cm -3 ~5×10 20 cm -3 It has a doping concentration of [value missing].

[0122] The thickness of this connecting layer is preferably at least 100 nm, for example, 100 to 10000 nm.

[0123] (Figure 5 N-doped region) After the connecting layer has grown, the bulk n-doped group III nitride region 2 is grown.

[0124] The n-doped region 2 includes, or is composed of, a stack of a group III nitride layer containing indium, or a stack of thin group III nitride layers that may or may not contain indium, or a bulk group III nitride layer or a stack of group III nitride layers in which the atomic percentage of indium fluctuates within the bulk layer or stack. For example, the n-doped region is a stack consisting of an n-GaN layer, an n-InGaN layer, or alternating n-GaN / n-InGaN layers, or an alternating n-InGaN layer containing different amounts of indium in each layer.

[0125] Preferably, the n-doped region 2 contains indium, so the crystal lattice of the n-doped region has lattice parameters similar to those of the InGaN light-emitting layer of the LED. The percentage of indium atoms in the n-doped region varies, for example, between 0.1 and 25%.

[0126] In a preferred embodiment, the indium content of the n-doped region is 20 at% or less, or 15 at% or less, or 10 at% or less, or 5 at% or less, of the indium content of the InGaN emissive layer. This ensures that the lattice parameters of the n-doped region are sufficiently similar to those of the InGaN emissive layer, thereby avoiding excessive strain between these layers.

[0127] The total thickness of the n-doped region is at least 2 nm, or at least 5 nm, or at least 10 nm, or at least 20 nm. The thickness of the n-doped region may vary, for example, between 2 nm and 5000 nm, or may be thicker. If the n-doped region includes a stack of multiple layers, the thickness of each individual layer in the stack is preferably 1 to 40 nm.

[0128] Preferably, the n-type doping concentration in the n-doped region is 1 × 10⁻⁶ 17 cm -3 ~5×10 20 cm -3 Preferably 1 × 10 18 cm -3 ~5×10 20 cm -3 And, particularly preferably, 1 × 1018 cm -3 Higher.

[0129] (Figure 6: Emitting region) After growing n-doped region 2, a substrate, prelayer, or prewell (not numbered in Figure 6) can be grown to release strain within one or more emissive layers. The substrate is a single or multi-layer stack of GaN or InGaN, or GaN / InGaN, or InGaN / InGaN. Alternatively, the substrate has a structure similar to an InGaN QW / GaN quantum barrier, but with a lower indium content. For example, before depositing an emissive layer with a relatively high indium content, a substrate consisting of a bulk InGaN layer with a lower indium content than the emissive layer can be grown. Alternatively, the substrate can take the form of an InGaN "dummy" QW with a lower indium content than the emissive layer, and one or more GaN quantum barriers.

[0130] After growing the n-doped region 2 and optionally the substrate, an emissive region 3 containing an InGaN emissive layer is grown.

[0131] The light-emitting region 3 includes at least one InGaN light-emitting layer. Each InGaN light-emitting layer is an InGaN quantum well (QW). Preferably, the light-emitting region includes 1 to 7 quantum wells. Adjacent quantum wells are separated by a barrier layer of a group III nitride material having a different composition from the quantum wells.

[0132] One or more light-emitting layers, referred to as “quantum wells” throughout this specification, can take various forms. For example, the light-emitting layer may be a continuous layer of InGaN, or a continuous layer, fragmented layer, discontinuous layer, containing gaps, or a nanostructured light-emitting layer that substantially contains multiple 3D nanostructures that behave as quantum dots.

[0133] Quantum wells and barriers are grown in a temperature range of 600-800°C.

[0134] Each quantum well consists of an InGaN layer having an atomic indium percentage of 15-40%. Preferably, one or more indium gallium nitride light-emitting layers and / or quantum wells have an InGaN composition. x Ga 1-x N has the following properties: where 0.15 ≤ x ≤ 0.40, preferably 0.20 ≤ x ≤ 0.40, or 0.26 ≤ x ≤ 0.40, and particularly preferably 0.30 ≤ x ≤ 0.40.

[0135] The thickness of each quantum well layer is 1.5 to 8 nm, preferably 1.5 nm to 6 nm, or 1.5 nm to 4 nm.

[0136] The quantum well may be covered with a thin (0.5-3 nm) group III nitride QW capping layer. This capping layer contains one or more combinations of the elements Al, Ga, and In (ternary layer, quaternary layer).

[0137] The QW capping layer is a layer added immediately after QW growth, and consists of AlN, AlGaN with an Al% of 0.01-99.9%, GaN, and InGaN with an In% of 0.01-30%.

[0138] The Group III nitride QW barrier separates the light-emitting layer (quantum well) and contains one or more combinations of the elements Al, Ga, and In (ternary layer, quaternary layer). The QW barrier is AlN, AlGaN with an Al% of 0.01 to 99.9%, GaN, and InGaN with an In% of 0.01 to 15%. Preferably, the QW barrier layer contains AlN and / or AlGaN.

[0139] Since one or more QW capping layers and QW barriers form part of the light-emitting region 3, these layers are not shown with individual reference numbers in the drawings.

[0140] The QW capping layer is grown after each QW growth and before the barrier growth. For example, if an LED contains three QWs, each of these QWs grows with a QW capping layer, and then a QW barrier layer is grown, so the light-emitting region contains three QW capping layers and three QW barrier layers.

[0141] 1. Caps can be grown under the same conditions as QW. 2. It is possible to grow this cap by raising the temperature to a high level without performing growth (this is essentially an annealing step), and the ramp here can be performed in different gas mixtures. 3. The lamp can be used to perform growth while the temperature is rising.

[0142] In the manufacturing of red LEDs, the importance of the capping layer increases because a large amount of indium is contained within one or more light-emitting layers. This is because previous attempts to manufacture red LEDs have failed due to insufficient indium incorporation. Therefore, capping is extremely important to ensure that sufficient indium is captured within the light-emitting region.

[0143] (Figure 7: Cap layer) After the growth of one or more light-emitting layers, an undoped cap layer 4 is grown. The undoped cap layer 4 is called the light-emitting region cap layer. This is because it is formed after the growth of the complete light-emitting region, for example, after the growth of the stack of QW, QW capping layer, and QW barrier layer.

[0144] The cap layer (light-emitting region cap layer) 4 is a standard layer that is very well known in the growth scheme of Group III nitride LEDs.

[0145] The thickness of the cap layer is 5 to 30 nm, preferably 5 to 25 nm or 5 to 20 nm.

[0146] The purpose of the luminescence region capping layer 4 is to protect the indium within the luminescence region (QW stack) and prevent this indium from desorbing / evaporating during subsequent processing. Typically, QWs in InGaN are grown at low temperatures, which is undesirable for GaN / AlGaN, so a temperature increase step is usually required before growing additional layers above the luminescence region. The capping layer is used to ensure that one or more InGaN luminescence layers are properly capped and protected, thereby providing an opportunity and time to change the growth conditions of the p-doped layer to improve material quality. The luminescence region capping layer 4 also ensures that Mg dopant does not enter the QW region during the growth of the p-type layer.

[0147] (Electron Block Layer (EBL)) After growing the quantum well, capping layer, and barrier layer, an aluminum-containing electron block group III nitride (EBL) 5 layer is grown. The Al% is, for example, 5-25%, but higher Al content is also possible.

[0148] EBLs are doped with appropriate p-type doping materials. The p-type doping concentration of EBLs is preferably 5 × 10⁻⁶. 18 cm -3 ~8×10 20 cm -3 That is the case.

[0149] The thickness of the EBL is 10 to 50 nm, preferably 20 nm.

[0150] (Figure 8 P-doped layer) A p-doped layer 6 is grown above the electron block layer (EBL) 5.

[0151] The p-type region is preferably doped with Mg, and the p-type doping concentration in the p-type layer is preferably 5 × 10⁻¹⁰ 18 cm -3 ~8×10 20 cm -3 That is the case.

[0152] The p-doped Group III nitride layer contains In and Ga.

[0153] The doping layer is preferably 20-200 nm thick, and particularly preferably 50-100 nm thick. The doping concentration varies within the p-type layer, but to enable better p-contact, the last 10-30 nm portion of the p-type layer closer to the LED surface has a spike in the doping level.

[0154] To activate the Mg acceptors in the p-doped layer, the structure is annealed in an MOCVD reactor or annealing oven. The annealing temperature should be in the range of 700-850°C in an N2 or N2 / O2 atmosphere.

[0155] Since both the EBL and the p-doped layer are p-doped, these layers are called p-doped regions.

[0156] (Figure 9 Transparent conductive layer) Next, the stack of active semiconductor layers is covered with a transparent conductive layer 7. The transparent conductive layer can be made from Ni / Au, indium tin oxide, indium zinc oxide, graphene, Pd, Rh, silver, ZnO, etc., or a combination of these materials.

[0157] The thickness of the transparent conductive layer can be 10 to 250 nm.

[0158] Transparent conductive layers are well known in this art, and any suitable material and thickness can be used.

[0159] An annealing step is necessary to make the p-contact ohmic.

[0160] (Figure 10) Depending on the LED structure to be manufactured, the semiconductor structure can be processed to create LEDs, mini-LEDs, or micro-LED devices.

[0161] Standard LEDs are typically larger than 200 μm (referring to the lateral dimensions of the LED structure, width and length). Mini LEDs typically have a lateral size of 100-200 μm, while micro LEDs are typically smaller than 100 μm.

[0162] Figures 10 onward show the semiconductor structure after etching layers 2-7 of the semiconductor structure to form individual LED stacks or mesas, each having the same structure.

[0163] In the next step, the transparent conductive layer 7 is structured to cover only the top surface of the active light-emitting element. This structuring can be performed using standard semiconductor processing methods, including resist coating and photolithography. The transparent conductive layer is etched by a wet chemical etching process or a sputter etching process using argon. After this step, wet or dry etching of the group III nitride structure is performed. Mesas are created in the group III nitride layer using inductively coupled plasma reactive ion etching, reactive ion etching alone, or neutral beam etching. The dry etching process includes one or more of the following gases: Cl, Ar, BCl3, and SiCl4.

[0164] The purpose of this step is to isolate the individual light-emitting elements and access the embedded n-doped layer of the pn junction.

[0165] After the dry etching process, a wet etching process is performed to remove dry etching damage from the mesa sidewalls. The wet chemicals include KOH (1-20%), TMAH, or other basic chemicals.

[0166] (Figure 11 Passivation) The next step is to deposit one passivation layer or a combination of multiple passivation layers. The initial passivation layer can be Al2O3 (10-100 nm) (deposited by atomic layer deposition), followed by the deposition of SiO2, SiN, or SiN (50-300 nm) by sputtering or plasma-enhanced chemical vapor deposition.

[0167] Al2O3 can be deposited at temperatures between 50 and 150°C.

[0168] SiO2, SiN, and SiN can be deposited at temperatures of 250-350°C.

[0169] The sputtering process can be carried out at room temperature.

[0170] (Figure 12) The next step is to create openings in the oxide passivation layer 8 to expose p-GaN and n-GaN. This can be done by wet etching, dry etching, or a combination of both.

[0171] In oxide etching buffer wet etching, diluted hydrofluoric acid, phosphoric acid, or mixtures thereof can be used.

[0172] (Figure 13) The final step in device manufacturing is to cover the oxide openings with a metal layer 9. This covering can be performed in a single step or multiple steps. In this example, a single step is used for simplicity.

[0173] The metals include Ti, Pt, Pd, Rh, Ni, and Au. The thickness of a complete metal stack can be 200-2000 nm.

[0174] After all processing is complete, the substrate is thinned and / or porous areas are removed so that the connecting layer 1 is exposed.

[0175] The substrate surface can be structured or textured in porous areas or layer 1 on the substrate, thereby increasing the light output and allowing control over the emission angle and other optical design elements.

[0176] Finally, the wafer / device can be flipped over and bonded to a carrier substrate of either silicon / sapphire or passive device type. Alternatively, the device can be bonded to a CMOS silicon backplane for an active matrix microLED display panel.

[0177] (Figures 14-18) Figure 14 shows that an InGaN LED on a porous layer according to a preferred embodiment of the present invention emits light at a peak wavelength of approximately 625 nm.

[0178] Figures 15 and 16 compare the luminescence characteristics of an InGaN LED on a non-porous substrate (Figure 15) and the same InGaN LED grown on a template containing a porous layer of Group III nitride material. Comparing these two graphs demonstrates that the presence of the porous lower layer causes a shift in the emission wavelength toward longer wavelengths. Specifically, the luminescence of the LED on the porous template is consistently shown to be 21 nm to 45 nm longer than that of the same LED on a non-porous template.

[0179] Figures 17 and 18 compare the IV characteristics of an InGaN microLED on a non-porous substrate (Figure 17) and an InGaN microLED on a template containing a porous layer.

Claims

1. A red light-emitting diode (LED) including an LED structure, The aforementioned LED structure is n-doped section, p-doped section, It includes a light-emitting region positioned between the n-doped portion and the p-doped portion, The aforementioned light-emitting region is An indium gallium nitride light-emitting layer that emits light at a peak wavelength of 600-750 nm under electrical bias, The indium gallium nitride luminescent layer comprises a group III nitride layer disposed on the group III nitride layer, The LED structure further comprises a porous region of a group III nitride material, and a non-porous intermediate layer of a group III nitride material between the porous region and the LED structure. The porous region is formed by electrochemical porosity through the non-porous intermediate layer, and the light-emitting region is positioned above the porous region. Red light-emitting diode.

2. A red LED according to claim 1, wherein the light-emitting diode has at least one feature selected from the following: (a) The light-emitting region includes 1 or 2 or 3 or 4 or 5 or 6 or 7 or 8 quantum wells (or at least 1 quantum well), (b) The group III nitride layer has the composition Al ｙ Ga （１－ｙ） It includes an aluminum gallium nitride layer represented by N, where y is in the range of 0.1 to 1.0, or (c) Between the n-doped portion and the light-emitting region, an ultraviolet-emitting or blue-emitting InGaN / GaN, an InGaN / InGaN superlattice, or an InGaN layer is arranged.

3. A red LED according to claim 1 or 2, The light-emitting region is a red LED that emits light at a peak wavelength of 600-700 nm or 615-675 nm under electrical bias.

4. A red LED according to any one of claims 1 to 3, A red LED in which the thickness of the porous region is at least 1 nm, or at least 10 nm, or at least 50 nm.

5. A red LED according to claim 4, A red LED comprising a connecting layer of group III nitride material disposed between the n-doped portion and the porous region.

6. A red LED according to claim 5, A red LED comprising a non-porous intermediate layer of a group III nitride material disposed between the porous region and the connecting layer.

7. A red LED according to claim 4, 5, or 6, The n-doped portion comprises an n-doped group III nitride layer, or the n-doped portion comprises a stack consisting of alternating layers of n-GaN, n-InGaN, or n-GaN / n-InGaN layers, or a stack consisting of alternating layers of n-InGaN / n-InGaN layers containing different concentrations of indium, in a red LED.

8. A red LED according to claim 7, The n-doped portion includes a single-crystal n-doped group III nitride portion, or the n-doped portion includes a single-crystal n-doped group III nitride layer having a flat top surface, in a red LED.

9. A red LED according to claim 8, A red LED in which the porous region and each layer between the porous region and the single-crystal n-doped group III nitride layer are flat layers having a top surface and a bottom surface parallel to the flat top surface of the single-crystal n-doped group III nitride layer.

10. A red LED according to any one of claims 1 to 9, The indium gallium nitride light-emitting layer comprises one or more InGaN quantum wells, or a red LED comprising 1 to 7 quantum wells.

11. A red LED according to claim 10, The indium gallium nitride light-emitting layer is an InGaN nanostructure layer containing quantum structures such as quantum dots, fragmentary or discontinuous quantum wells, in a red LED.

12. A red LED according to claim 10 or 11, The indium gallium nitride light-emitting layer and / or the quantum well is composed of In ｘ Ga １－ｘ A red LED having N such that 0.15 ≤ x ≤ 0.40, or 0.20 ≤ x ≤ 0.40, or 0.26 ≤ x ≤ 0.40, or 0.30 ≤ x ≤ 0.

40.

13. A red LED according to claim 10, 11, or 12, The red LED includes a cap layer of a group III nitride material between the quantum well and the p-doped portion.

14. A red LED according to any one of claims 1 to 13, The p-doped portion is a red LED comprising a p-doped group III nitride layer and a p-doped aluminum gallium nitride layer disposed between the p-doped group III nitride layer and the light-emitting region.

15. A red LED as described in claim 13 and claim 14, The p-doped aluminum gallium nitride layer is an electron blocking layer (EBL) disposed between the cap layer and the p-doped portion, and the electron blocking layer contains 5 to 25 at% aluminum, or the thickness of the electron blocking layer is 10 to 50 nm, in a red LED.

16. A red LED according to any one of claims 1 to 15, The aforementioned porous region is a red LED that is not part of a distributed Bragg reflector (DBR).

17. It is a red mini LED, A red LED as described in any one of claims 1 to 16, The aforementioned light-emitting region is a red mini-LED having a lateral dimension greater than 100 μm and less than 200 μm.

18. It is a red microLED, The red LED is provided according to any one of claims 1 to 16. The light-emitting region is a red micro-LED having a lateral dimension smaller than 100 μm.

19. A red microLED array comprising a plurality of red microLEDs as described in claim 18.

20. A method for manufacturing a red LED, By electrochemical porosity formation through the non-porous region of the group III nitride material, a porous region of the group III nitride material is formed, thereby forming a non-porous intermediate layer in the non-porous region of the group III nitride material. Above the non-porous intermediate layer and the porous region of the group III nitride material n-doped section, p-doped section, A light-emitting region disposed between the n-doped portion and the p-doped portion, the light-emitting region including an indium gallium nitride light-emitting layer that emits light at a peak wavelength of 600 to 750 nm under an electrical bias, A method that includes steps to promote growth.

21. A method according to claim 20, comprising the step of depositing one or more connecting layers of group III nitride material on the surface of the non-porous intermediate layer of group III nitride material prior to growing the n-doped portion, the light-emitting region, and the p-doped portion on one or more connecting layers.

22. A method according to any one of claims 20 or 21, wherein the red LED is a red LED, a red mini-LED, a red micro-LED, or a red micro-LED array as defined in any one of claims 1 to 19.

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