Indium phosphide with low etch pit density, low slip line density, and low strain.

Abstract

Methods and wafers for low etch pit density, low slip line density, and low strain indium phosphide are disclosed, having a diameter of 10.16 cm (4 inches) or greater and a surface roughness of 500 cm as measured by x-ray diffraction imaging. -2 The wafer may include an indium phosphide single crystal wafer having a measured etch pit density of less than 200 cm and having less than five dislocations or slip lines. -2 Below, 100cm -2 Less than or equal to 10cm -2 The wafer may have a measured etch pit density of at least 80% of the total surface area. The wafer may have a diameter of 6 inches or greater. The area of ​​the wafer with a measured etch pit density of zero may be at least 80% of the total surface area. The area of ​​the wafer with a measured etch pit density of zero may be at least 90% of the total surface area.

Description

[Technical Field]

[0001] Cross-referencing / incorporation by reference of related applications

[0001] This application claims priority and advantages over U.S. Provisional Application No. 62 / 983,244 filed on 28 February 2020.

[0002]

[0002] Specific embodiments of this disclosure relate to semiconductor substrates. More specifically, specific embodiments of this disclosure relate to indium phosphide with low etch pit density, low slip line density, and low strain. [Background technology]

[0003]

[0003] Semiconductor substrates, particularly III-V semiconductor substrates, are used in the manufacture of electronic and optoelectronic devices such as heterojunction bipolar transistors (HBTs), pseudo-morphic high-electron mobility transistors (pHEMTs), lasers, and detectors. Defects in the substrate can reduce yield and increase costs.

[0004]

[0004] By comparing such systems with the present disclosure as described in the following portions of the present application with reference to the drawings, further limitations and shortcomings of conventional and ordinary approaches will become apparent to those skilled in the art. [Overview of the Initiative] [Means for solving the problem]

[0005]

[0005] A system and / or method for indium phosphide with low etch pit density, low slip line density, and low strain, substantially illustrated and / or described in connection with at least one of the figures and more fully described in the claims.

[0006]

[0006] With the various advantages, aspects, and novel features of the present disclosure, the details of its illustrated embodiments will be more fully understood from the following description and the drawings.

Brief Description of the Drawings

[0007] [Figure 1]

[0007] A diagram illustrating a vertical gradient freeze reactor according to an exemplary embodiment of the present disclosure. [Figure 2]

[0008] A diagram illustrating a method for fabricating an indium phosphide wafer using the vertical gradient freeze furnace 100 shown in FIG. 1. [Figure 3A]

[0009] A diagram showing X-ray diffraction imaging results for indium phosphide substrates from different growth techniques according to an exemplary embodiment of the present disclosure. [Figure 3B] A diagram showing X-ray diffraction imaging results for indium phosphide substrates from different growth techniques according to an exemplary embodiment of the present disclosure. [Figure 3C] A diagram showing X-ray diffraction imaging results for indium phosphide substrates from different growth techniques according to an exemplary embodiment of the present disclosure. [Figure 3D] A diagram showing X-ray diffraction imaging results for indium phosphide substrates from different growth techniques according to an exemplary embodiment of the present disclosure. [Figure 4A]

[0010] A diagram showing a resistivity distribution map for a 10.16 cm (4-inch) InP substrate according to an exemplary embodiment of the present disclosure. [Figure 4B]

[0011] A diagram showing an etch pit density measurement for a 10.16 cm (4-inch) VGF InP substrate according to an exemplary embodiment of the present disclosure. [Figure 4C]

[0012] A diagram showing an etch pit density measurement for a 15.24 cm (6-inch) VGF sulfur-doped InP substrate according to an exemplary embodiment of the present disclosure. [Figure 4D]

[0013] A diagram showing the etch pit density measurement of a 15.24 cm (6-inch) VGF iron-doped InP substrate according to an exemplary embodiment of the present disclosure. [Figure 5A]

[0014] A diagram showing the optical luminescence measurement of a substrate for defect detection according to an exemplary embodiment of the present disclosure. [Figure 5B]

[0015] A diagram showing the resistivity, optical luminescence, and etch pit density measurements of a non-VGF 7.62 cm (3-inch) InP substrate according to an exemplary embodiment of the present disclosure. [Figure 5C]

[0016] A diagram showing the comparison between etch pit density measurement and X-ray diffraction imaging according to an exemplary embodiment of the present disclosure. [Figure 6]

[0017] A diagram showing the photoelastic measurement of an indium phosphide substrate according to an exemplary embodiment of the present disclosure. [Figure 7]

[0018] A diagram showing the results of phase shift and stress direction for optoelectronic measurement of a substrate according to an exemplary embodiment of the present disclosure. [Figure 8]

[0019] A diagram showing an element fabricated on an indium phosphide wafer with a low etch pit density according to an exemplary embodiment of the present disclosure.

Mode for Carrying Out the Invention

[0008]

[0020] Certain aspects of the present disclosure can be found in methods and wafers for indium phosphide with low etch pit density, low slip line density, and low strain.

[0021] Figure 1 illustrates a vertical gradient freezing reactor according to an exemplary embodiment of the present disclosure. Referring to Figure 1, a vertical gradient freezing (VGF) system 100 is shown comprising an ampoule 110, a support 107, a heating coil 120, and a crucible 130. Within the ampoule 110, growth can proceed using a seed crystal 101 and a melt 105 in a vertical configuration, and a solid 103 is generated due to the very slow cooling of the melt 105. The crucible 130 may contain, for example, pyrolysis boron nitride (PBN) and may contain the melting material and seed material during processing.

[0009]

[0022] The VGF system 100 comprises a configuration for growth charge, a heating device, insulation, and a support structure. The heating coil 120 may be configured to provide direct radiation above the height of the cone in the crystal growth charge and seed crystal 101. The VGF system 100 may further comprise a support structure 107 for supporting the ampoule 110 within the heating coil 120. Furthermore, insulation 109 may be placed within the support structure 107 to facilitate inward radial heat flux during growth and heat removal during post-growth processes and cooling. The support structure 107 may comprise a cylinder for the growth ampoule 110, which may comprise a hollow core below the seed pocket holding the seed crystal 101 to provide a downward conductive heat channel through the center. The larger the diameter of the quartz rod to the bottom of the heating device, the more the downward heat flow is facilitated and the more stable it becomes.

[0010]

[0023] In the VGF process, the seed crystal 101, which is a polycrystalline charge in the crucible 130 of the ampoule 110, can be heated using a multi-band furnace, such as one indicated by a heating coil 120. Crystal growth is initiated by melting the charge in the seed crystal 101, thereby generating a melt 105, and slowly lowering the temperature to cool the melt 105 in the seed crystal 101. The crystallization process that generates a solid 103 can be controlled with high precision by changing the gradually changing temperature in different bands of the furnace, such as by applying different currents to different parts of the heating coil 120. Accordingly, the heating coil 120 may be equipped with a multi-band heating device capable of different temperatures, heating / cooling rates, and ambient temperature profiles.

[0011]

[0024] The VGF process offers several advantages over other processes such as liquid sealing Czochralski (LEC) and horizontal Bridgman (HB). Firstly, the thermal environments of the crystal and melt are radially symmetric, allowing for high-precision control of the planar growth interface and temperature profile. Secondly, growth in low axial and radial temperature gradients, combined with diameter control imposed by the crucible, and the elimination of the need to use large temperature gradients to rapidly freeze the crystal, significantly reduces strain and, consequently, dislocations in the crystal. Thirdly, the liquid-solid interface proceeds upward through the melt, initiating crystallization at the seed crystal 101 at the bottom of the crucible. The system is cooler at the bottom and thermally stabilized against convection. In the cooling process as well, easily controllable cooling brings the crystal to room temperature at a rate that minimizes stress, and therefore dislocations and slip lines.

[0012]

[0025] Prior to crystal growth, polycrystalline indium phosphide (InP) can be pre-fabricated by polyintegration. This polyintegration process can be carried out in a quartz reaction tube using the boat method. Once polycrystalline InP is produced, VGF crystal growth can proceed. Several VGF parameters are carefully controlled to achieve low EPD. The first parameter may include the shape of the melt / crystal interface 140, which can be controlled to be recessed, flat, or protruding relative to the melt. For example, the interface 140 may be recessed or protruding by 10 mm, and its center may be about 5 mm to 20 mm lower or higher than the crystal edge. This can be controlled using different temporal and / or spatial temperature profiles.

[0013]

[0026] Secondly, the crystallization rate, which is controlled by the cooling rate, can be configured to be, for example, less than 1°C / hour. Different solidification rates can be configured in different parts of the ingot. The temperature gradient along the growing crystal generates stress in the bowl, causing the tip to cool earlier, and in some cases, the tip may be about 100 degrees Celsius or less colder than the end, so high-precision control is desirable.

[0014]

[0027] Finally, the temperature gradient at the melt / crystal interface may be configured to control the melt / crystal interface, in which case, while many processes utilize a planar interface, a curved interface may be used in this disclosure. In this case as well, multi-zone heating may enable high-precision temperature control throughout the crucible 130. After overall solidification is complete, the heating temperature may be reduced to room temperature in different heating zones at rates of approximately 1-2°C / hour, 2-4°C / hour, and 10-15°C / hour, respectively. As a result of this process, an InP single crystal with a cylindrical portion, approximately 50 cm or longer in length, is obtained, exhibiting low dislocation density, low slip density, and low strain. The dislocation density obtained as a result of this process is 2 cm -2 Less than 20cm -2 Less than 200cm -2 Less than 500cm -2The result will be less than the specified size. This bowl diameter is determined by the size of the crucible 130 and may be 10.16 cm (4 inches), resulting in wafers smaller than 10.16 cm (4 inches), 15.24 cm (6 inches) may result in wafers smaller than 15.24 cm (6 inches), and 20.32 cm (8 inches) may result in wafers smaller than 20.32 cm (8 inches). Larger sizes are possible depending on the diameters of the crucible 130 and the heating coil 120.

[0015]

[0028] Figure 2 illustrates a method for fabricating InP wafers using the vertical gradient freezing furnace 100 shown in Figure 1. This process, when measured using the various techniques described below, results in wafers of 2, 20, 200, and 500 cm². -2 InP substrates with diameters of 10.16 cm (4 inches), 15.24 cm (6 inches), or 20.32 cm (8 inches) or larger, free of slip line defects, can be obtained with an etch pit density of less than 1.5 cm. This process can also be used to fabricate gallium arsenide (GaAs), gallium phosphide (GaP), or other related III-V compound semiconductors.

[0016]

[0029] In step 201, the raw material InP can be obtained, and testing may be performed on the raw material before it is placed in a boat in a quartz tube for polyintegration in order to produce polycrystalline InP. Once polycrystalline InP is produced, vertical gradient freeze-freezing (VGF) crystal growth occurs in step 203, in which case the temporal and spatial temperature profiles are 20, 200, and 500 cm on crystals with a diameter of 10.16 cm (4 inches) or 15.24 cm (6 inches) or more. -2The curvature of the melt / crystal interface is strictly controlled to result in fewer than 1°C / hour crystals. Several VGF parameters are carefully controlled to achieve low EPD. The first parameter may include the shape of the melt / crystal interface, which can be controlled to be concave, flat, or protruding. This can be controlled using different temporal and / or spatial temperature profiles. Secondly, the crystallization rate, when controlled by the cooling rate, can be configured to be in the range of less than 1°C / hour. Different solidification rates can be configured in different parts of the ingot.

[0017]

[0030] Once the VGF crystals have grown in step 205 (and optionally tested), an ingot forming process may be performed to obtain, for example, a rounded ingot with a desired flat surface, which may be further tested. Once the ingot is formed, it may be sliced ​​into wafers in step 207, and these wafers may optionally be tested.

[0018]

[0031] Once low-EPD wafers are sliced ​​from the ingot, they may proceed to wafer processing step 209. Any wafer annealing process may be performed. In an exemplary wafer annealing process, one or more annealing steps may be used, in which case the wafers may be loaded vertically into a horizontal quartz boat and inserted into a horizontal quartz ampoule together with a phosphorus lump. The phosphorus lump may be configured to achieve the required vapor pressure at the annealing temperature to avoid any phosphorus dissociation from the InP substrate. Due to the high vapor pressure of phosphorus, the pressure may increase during annealing. The ampoule and its contents may then be inserted into, for example, a horizontal three-band furnace, and heating of the ampoule and its contents to a desired platform temperature may be initiated.

[0019]

[0032] After annealing and optionally testing of the low-EPD wafer, a wafer polishing process may be performed to polish the low-EPD wafer, and the polished wafer may optionally be tested again. Once the wafer is polished, it may be cleaned, and then the process proceeds to step 211, where the polished and cleaned wafer may be packaged for shipment to the customer. The above process may also be used to produce gallium arsenide (GaAs) or other compound semiconductor wafers. As a result of this process, low-EPD, low-slip density and low-strain InP wafers of 10.16 cm (4 inches), 15.24 cm (6 inches) or larger are produced.

[0020]

[0033] Various defect measurements may be used to evaluate wafer quality, such as average EPD, maximum EPD, and the ratio of areas with, for example, zero EPD. Regarding slip lines, a certain number of EPD measurement squares in a row, or nearly linear shape, exceeding a threshold length, may indicate the presence of slip lines. Similarly, a certain number of adjacent measurement areas exceeding a threshold number may be used to reject the wafer. The strain level in the wafer may be used to determine whether the wafer is likely to become defective in subsequent processing steps.

[0021]

[0034] To evaluate substrate quality, photoluminescence mapping may be used, where areas or linear regions with low or high intensity may indicate defects. Defects may emit cold light at different wavelengths and may have different spectral shapes, half-wave height (HWHM) values, and / or intensity patterns. Linear defects may also be measured, in which case slip lines may enhance the PL signal.

[0022]

[0035] Since doping changes can correlate with the strain field in a crystal, resistivity measurements may be used to determine wafer quality in relation to slip lines, dislocations, or other strain-related defects. Similarly, photoelastic measurements allow for the direct measurement of strain in a crystal, which can correlate with dislocations, slip lines, and other defects. X-ray diffraction imaging is another characterization technique that can detect structural defects both on the surface and within the crystal.

[0023]

[0036] Figures 3A–3D show X-ray diffraction imaging results for indium phosphide substrates from different growth techniques according to exemplary embodiments of the present disclosure. X-ray diffraction imaging (XRDI) uses X-rays to image bulk and surface crystal defects in single-crystal substrates. The X-ray beam may pass through the substrate in transmission mode or be reflected from the substrate in reflection mode. In this way, invisible crystal defects can be detected, even single dislocations ranging from tens of microns in size. These crystal defects can lead to breakage during processing.

[0024]

[0037] Referring to Figure 3A, reflection-mode and transmission-mode images of a 10.16 cm (4 inch) InP substrate grown by the VGF process are shown, and apart from two marginal defects in the transmission-mode image, no slip lines, dislocations, or other structural defects are observed in the reflection-mode or transmission-mode measurements. Fewer than five slip line and dislocation defects are consistently achieved in the 10.16 cm (4 inch) and 15.24 cm (6 inch) InP substrates disclosed herein.

[0025]

[0038] Figure 3B shows the X-ray diffraction results for a 15.24 cm (6 inch) indium phosphide substrate according to an exemplary embodiment of the present disclosure. Referring to Figure 3B, the transmission-mode XRDI results for a 15.24 cm (6 inch) sulfur-doped InP substrate grown by a VGF process are shown, and apart from a few marginal defects, no slip lines, dislocations, or other structural defects are observed in the transmission-mode measurements. Fewer than five slip line and dislocation defects are consistently achieved in 10.16 cm (4 inch) and 15.24 cm (6 inch) substrates.

[0026]

[0039] Figure 3C shows XRDI reflection-mode and transmission-mode images of InP substrates grown using other techniques. The reflection-mode image shows a small number of defects, while the transmission-mode image shows numerous defects and prominent distortion features / patterns. Note that defects present in the reflection-mode image also appear in the transmission-mode image.

[0027]

[0040] Figure 3D shows XRDI reflection-mode and transmission-mode images of an InP substrate grown by other techniques. In this case, the reflection-mode image shows no defects at all, while the transmission-mode image shows a significant amount of slip lines. These defects can lead to wafer breakage during handling or other processing, especially when temperature cycling is occurring, such as during epitaxial growth. Therefore, it is important to protect single-crystal semiconductor substrates from such dislocations / defects. XRDI analysis is effective when measuring substrates with respect to slip lines and strain, in which case the wafer specification may include a count of the number of defects with linear characteristics, such as a specific number of pixels lined up in a row to show slip lines or pixel regions showing high strain areas.

[0028]

[0041] The InP substrates in Figures 3A and 3B, fabricated using the VGF process disclosed herein, exhibit significantly higher structural quality than wafers grown by other techniques, as shown in Figures 3C and 3D. The configured liquid / melt interface consequently reduces residual strain in the wafer's crystal lattice, resulting in a state free of slip lines and dislocations, as shown in the XRDI results. Other techniques, such as LEC, VCZ, and VB, consequently generate a significant strain field, as shown in Figure 3C, which can lead to significant wafer breakage during subsequent wafer / device processing. The areas with higher strain in Figure 3C can be used as specifications for wafer acceptance / rejection, with the wafers in Figures 3A and 3B having high strain of 0% or none, while the wafer in Figure 3C has high strain of 10-30% and some strain throughout the wafer. Similarly, the numerous defects in Figure 3D may cause wafer breakage during wafer / device processing, and these slip lines, along with other defects near them, may cause device failure during operation even if the wafer withstands wafer / device processing. A large number of such slip lines are permitted by specification, in which case there are zero or none on the wafer in Figures 3A and 3B, and dozens of slip lines around the outer periphery in Figure 3D.

[0029]

[0042] Figure 4A shows a resistivity distribution diagram for a 10.16 cm (4 inch) InP substrate according to an exemplary embodiment of the present disclosure. Referring to Figure 4A, resistivity distribution diagrams for two InP wafers having different types of heterogeneity are shown. The resistivity change is a measure of the doping uniformity of the wafer and may show different patterns depending on the growth technique, melt-crystal interface, convection in the melt, and / or the location of the wafer cut from the bowl. In the plot on the left, the resistivity change has a “bullseye” pattern, slightly off-center, while the plot on the right has a linear change across the wafer. These changes may be influenced, for example, by melt / crystal interface shape, melt convection, and dopant diffusion.

[0030]

[0043] The wafer with a left plot having a "bull's eye" resistivity change has an EPD of 14 cm with a resistivity change of about 3% or less at the tip and an EPD of 17 cm with a resistivity change of about 8% or less at the end. The wafer from another bowl with a more linear change has an EPD of 100 cm at the tip with a resistivity change of 2.3 - 2.5% and an EPD of 150 cm at the end. -2 Another bowl having an EPD of 17 cm with a resistivity change of about 8% or less at the end. -2 The wafer from another bowl with a more linear change has an EPD of 100 cm at the tip with a resistivity change of 2.3 - 2.5% and an EPD of 150 cm at the end. -2 at the end. -2 Another bowl having a linear resistivity change across the diameter of the wafer has an EPD of 400 cm at the tip and an EPD of 450 cm at the end when the resistivity change is less than 3%. -2 at the end. -2 Thus, the wafer may or may not show a correlation between the change in doping and the EPD.

[0031]

[0044] A flat melt - crystal interface has conventionally been believed to result in the best material, but the VGF method disclosed herein shows that a non - planar interface results in a material with reduced dislocations, although the non - uniformity of doping increases compared to crystals grown with a flat interface. Since dislocations and strains can have a greater impact on wafer processing yield and device performance, the trade - off with doping uniformity is acceptable, and the melt - crystal interface is an important parameter.

[0032]

[0045] FIG. 4B is a diagram showing etch pit density measurements of three VGF InP substrates according to an exemplary embodiment of the present disclosure. Referring to FIG. 4B, EPD measurements for three 10.16 cm (4 - inch) InP substrates grown by VGF are shown, showing near - zero defects and having an average EPD of 1 - 2 cm, and the area of zero EPD ranges from 93% to 98%. An EPD having an average of less than 1 cm and from about 0.3 cm to 3 cm indicates high - quality InP made possible by performing the VGF process described herein. -2 and having an average EPD of from 1 - 2 cm, and the area of zero EPD ranges from 93% to 98%. -2 less than 1 cm -2 and from about 0.3 cm to 3 cm -2 having an average indicates high - quality InP made possible by performing the VGF process described herein. -2 less than 150 cm, -2 less than 50 cmLess than 20cm -2 Less than 10cm -2 Less than 5cm -2 Less than, and 2cm -2 Wafers with less than 0 EPD are obtained as a result of the VGF process. Furthermore, it is typical for wafers with zero EPD to have at least 50%, at least 60%, at least 70%, at least 80%, and at least 90% of their area.

[0033]

[0046] Figure 4C shows an etch pit density measurement of a 15.24 cm (6 inch) VGF sulfur-doped InP substrate according to an exemplary embodiment of the present disclosure. Referring to Figure 4B, two 69-point EPD results for sulfur-doped InP are shown, one of which is a 67 cm wafer. -2 The EPD is shown, and the other is 171cm -2 The EPD is shown. These plots show very low EPD at most points in the scan, except for a few points close to the corners.

[0034]

[0047] Figure 4D shows an etch pit density measurement of a 15.24 cm (6 inch) VGF iron-doped InP substrate according to an exemplary embodiment of the present disclosure. Referring to Figure 4B, two 69-point EPD results for iron-doped InP are shown, with one wafer at the tip of the bowl measuring 1261 cm². -2 The EPD is shown, and the other end is 431 cm. -2 This shows the EPD. As a result of the VGP process described herein, in 10.16 cm (4 inch) and 15.24 cm (6 inch) wafers, depending on the type of dopant, 500 cm -2 Below, 200cm -2 Below, 100cm -2 Below, 10cm -2 Below, and even 2cm -2 This indicates that the following EPD can be obtained.

[0035]

[0048] Figure 5A shows a photoluminescence measurement of a substrate for defect detection according to an exemplary embodiment of the present disclosure. Referring to Figure 5A, photoluminescence (PL) intensity distribution maps for an InP substrate and a GaAs substrate are shown. PL measurement involves irradiating the substrate with a light source, such as a laser, having a wavelength long enough to be absorbed by the semiconductor, and generating electron-hole pairs that subsequently recombine to produce photons measured by a PL facility. PL mapping, as shown in Figure 5A, can be obtained by rotating the substrate and moving the light source radially from the center to the edge or from the edge to the center.

[0036]

[0049] While measured light intensity values ​​from a substrate may not be reliable for determining the presence of slip lines, dislocations, or other defects, relative intensity can indicate defects through specific features and abrupt transitions, for example. As shown in Figure 5A, the InP substrate certainly exhibits some intensity variation across the wafer, but does not show clear slip lines in the intensity distribution diagram, which is indicated by a narrow range of large differences in intensity. However, the absence of slip line features is not necessarily conclusive, as slip lines may not emit light in PL measurements depending on the wavelength of the light source relative to the defect state.

[0037]

[0050] The GaAs substrate has distinct slip lines extending from the edges around most of the outer circumference of the wafer, as indicated by the additional black lines. In these areas, the PL intensity is significantly increased compared to adjacent areas because numerous defects may be located along the slip lines, and in this case, the defects may have high light absorption and fast recombination rates.

[0038]

[0051] Furthermore, InP slip lines may exist at wavelengths different from those of the main InP luminescence peak, and therefore PL measurement systems can be adapted to detect these slip lines. Once detected, the total number of slip lines of a specific threshold length and / or width can be used to evaluate whether the substrate passes or fails the specifications. For example, a certain number of slip lines may be counted, or slip lines less than 10 mm may be counted, and further slip lines between 10 mm and 20 mm, as well as slip lines greater than 20 mm, may also be counted. A trade-off between wafer yield and device yield may be made to optimize overall yield and cost efficiency.

[0039]

[0052] Figure 5B shows resistivity, photoluminescence, and etch pit density measurements of a non-VGF 7.62 cm (3 inch) InP substrate according to an exemplary embodiment of the present disclosure. Referring to Figure 5B, resistivity plots, photoluminescence intensity plots, and EPD plots for a non-VGF InP substrate are shown. The resistivity change is only 1.55%, but the average EPD is 300 cm -2 The proportion of wafer area measured without using etch pits is 25%. High EPD regions can correlate with the presence of slip lines and other such dislocations. Patterns in the EPD plot can be used to determine the presence of slip lines, such as by measuring linearly formed high EPD regions, or high EPD 2D regions may correlate with slip lines, thereby the threshold area exceeding the EPD level can be used to pass / fail the wafer in terms of slip lines.

[0040]

[0053] Similarly, PL intensity plots can be used alone or in conjunction with resistivity and EPD plots to identify slip lines and other defects. Areas of high or low PL intensity relative to the surrounding area, as well as high EPD regions, can indicate the presence of defects, and linear structures and / or regions of high or low intensity can indicate slip lines.

[0041]

[0054] Figure 5C shows a comparison of etch pit density measurement and X-ray diffraction imaging according to exemplary embodiments of the present disclosure. Referring to Figure 5C, EPD measurements and the XRDI measurements described above are shown for four non-VGF InP wafers. As seen in the four EPD measurements, high-density defects are present at the wafer edges at the four corners of the "X" pattern, and the "X" pattern coincides with the slip lines / dislocations shown in the XRDI image, showing a correlation between EPD and slip lines. Thus, each measurement technique can be used to determine wafer quality with respect to slip lines, EPD, and strain.

[0042]

[0055] Figure 6 shows a photoelastic measurement of an indium phosphide substrate according to an exemplary embodiment of the present disclosure. Referring to Figure 6, single-polarization transmission and shear stress equivalent measurements of an InP wafer are shown. Stress in a semiconductor substrate can cause fracture, warping, and cracking, and may also exhibit high-density dislocations. The wavelength of the light source in the photoelastic measurement is within the transmission range for the material of interest. The photoelastic measurement is based on induced birefringence in the wafer, which is proportional to the stress in the crystal. Thus, the phase shift of light passing through the substrate is a function of stress, and the magnitude of the stress can be determined from the modulation of the signal measured by a photodetector that receives the optical signal through the substrate.

[0043]

[0056] The transmission measurements shown in Figure 6 reveal a region of defects near the wafer edge that correlates with a region of higher shear stress, as indicated by the shear stress equivalent measurements. Furthermore, several slip lines are evident in the shear stress equivalent measurements in the uniaxial stress field at the lower right corner and in the region with many slip lines, as shown by the linear change in stress. The number of such slip lines detected by the photoelastic measurements is available to evaluate the wafer for subsequent processing, and this particular wafer reveals two or three slip lines.

[0044]

[0057] Figure 7 shows the phase shift and stress direction results for photoelectron measurement of a substrate according to an exemplary embodiment of the present disclosure. Referring to Figure 7, the multipolar analysis of an InP wafer is shown with the calculated phase shift plot and principal stress direction plot. Some of the features in the phase shift plot can be interference fringes caused by changes in wafer thickness, particularly when both sides of the substrate are polished.

[0045]

[0058] The direction of stress measurement can be used to detect dislocations / slip lines, and a sudden reversal of stress orientation may indicate such defects. Furthermore, photoelastic measurements may reveal stress rings in the substrate, as shown by the annular pattern in Figure 7, showing an outer ring under tensile stress. Thus, slip lines, dislocations, and other defects can be illuminated in photoelastic measurements, and the amount of strain intensity, strain orientation reversal, or strained area can be used, for example, to evaluate wafer quality.

[0046]

[0059] Figure 8 shows an element fabricated on a low etch pit density indium phosphide wafer according to an exemplary embodiment of the present disclosure. Referring to Figure 8, a 10.16 cm (4 inch) InP wafer 801 is shown, which is manufactured using the process described above and further processed with electrical and / or optoelectronic elements on die 803. Further shown are flat areas 805 that may be formed during wafer fabrication to indicate crystal planes, for example. The number of dies 803 on wafer 801 can be defined by the area of ​​each die, and the size shown in Figure 8 is just an example.

[0047]

[0060] Wafer processing is a very expensive process, and having substrates free of slip lines, dislocations, or strain is crucial, as it can significantly improve process yield. By providing InP substrates free of these defects, wafer processing can proceed without or with limited wafer damage caused by substrate quality.

[0048]

[0061] In one embodiment of this disclosure, an indium phosphide wafer with low etch pit density, low slip line density, and low strain has a diameter of 10.16 cm (4 inches) or more and measures 500 cm when measured by X-ray diffraction imaging. -2 This may include indium phosphide single crystal wafers having a measured etch pit density of less than 200 cm² and fewer than 5 dislocations or slip lines. -2 Below, 100cm -2 Below, or 10cm -2 The wafer may have the following measured etch pit densities. The wafer may have a diameter of 15.24 cm (6 inches) or more. The area of ​​a wafer with zero measured etch pit density may be at least 80% of the total surface area. The area of ​​a wafer with zero measured etch pit density may be at least 90% of the total surface area. The resistivity plot of the wafer may have a bullseye pattern with regions where resistivity increases from the center to the outer edge of the wafer. Electronic and / or optoelectronic elements may be formed on the first surface of the wafer. The wafer may have a thickness of 300 μm or more.

[0049]

[0062] In other embodiments of the present disclosure, a process for indium phosphide wafers with low etch pit density, low slip line density, and low strain comprises: sealing a charge material comprising a polycrystalline indium phosphide seed crystal, a B2O3 encapsulating material, and a dopant in a crucible; sealing the crucible in a quartz ampoule; performing a vertical gradient freeze crystal growth process by heating the ampoule using a multi-band heating device to gradually melt the charge material until a portion of the seed crystal melts; initiating growth from the partially melted seed by implementing controlled cooling of the multi-band heating device; applying a temperature gradient between 1°C / cm and 8°C / cm at the melt-crystal interface; and controlling the shape of the interface to be recessed relative to the melt using the cooling rate in the multi-band heating device to form a solidified indium phosphide crystal, and 500 cm -2 This may include slicing a crystal to create an indium phosphide wafer with a diameter of 10.16 cm (4 inches) or more having the following etch pit density.

[0050]

[0063] Cooling of the multi-zone heating apparatus can be controlled at a rate of 0.1 to 2°C / h. The crucible can be evacuated before sealing the crucible in a quartz ampoule. The solidified charge material can be cooled at a rate of 0.5 to 5°C / h, 1 to 10°C / h, and 5 to 20°C / h for different heating zones relative to the first 300°C, and then at a rate of 20 to 50°C / h to room temperature. The interface shape may be controlled to be recessed relative to the molten material, with the center being only about 10 mm or less lower than the edge of the solidified crystal. The wafer may have a diameter of 15.24 cm (6 inches) or more. The wafer may be 200 cm -2 Below, 100cm -2 Below, or 10cm -2 The following etch pit densities may be present.

[0051]

[0064] Although the present invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various modifications may be made and equivalents may be substituted without departing from the scope of the present disclosure. Furthermore, many modifications may be made without departing from the scope to adapt the teachings of the present disclosure to specific circumstances or materials. Thus, the present disclosure is not limited to the specific embodiments disclosed, and the present disclosure is intended to include all embodiments within the scope of the appended claims.

Claims

1. Diameter of 10.16 cm (4 inches) or more, and 500 cm －２ An indium phosphide single-crystal wafer having a measured etch pit density of less than 5 and fewer than 5 dislocations or slip lines as measured by transmission-mode X-ray diffraction imaging.

2. The aforementioned wafer is 200 cm －２ The wafer according to claim 1, having the following measured etch pit density.

3. The aforementioned wafer is 100 cm －２ The wafer according to claim 1, having the following measured etch pit density.

4. The wafer is 10 cm －２ The wafer according to claim 1, having the following measured etch pit density.

5. The wafer according to claim 1, wherein the area of ​​the wafer having zero measured etch pit density is at least 80%.

6. The wafer according to claim 1, wherein at least 90% of the wafer area has a measured etch pit density of zero.

7. The wafer according to claim 1, wherein the resistivity plot of the wafer has a bullseye pattern having a region where the resistivity increases from the center to the outer edge of the wafer.

8. The wafer according to claim 1, wherein an electronic element and / or an optoelectronic element is formed on the first surface of the wafer.

9. The wafer is the wafer according to claim 1, wherein the wafer has a thickness of 300 μm or more.

10. A semiconductor substrate, Diameter of 10.16 cm (4 inches) or more, and 50 cm －２ The indium phosphide single crystal wafer has an etch pit density of less than 5 and fewer than 5 dislocations or slip lines as measured by transmission mode X-ray diffraction imaging, Semiconductor substrate.

11. The semiconductor substrate is 10 cm －２ The wafer according to claim 10, having the following measured etch pit density.

12. The semiconductor substrate according to claim 10, wherein the area of ​​the semiconductor substrate having zero measured etch pit density is at least 80%.

13. The semiconductor substrate according to claim 10, wherein the area of ​​the semiconductor substrate having zero measured etch pit density is at least 90%.

14. The semiconductor substrate according to claim 10, wherein the resistivity plot of the semiconductor substrate has a bullseye pattern having a region where the resistivity increases from the center to the outer edge of the semiconductor substrate.

15. The semiconductor substrate according to claim 10, wherein an electronic element and / or an optoelectronic element is formed on the first surface of the semiconductor substrate.

16. The semiconductor substrate according to claim 10, wherein the semiconductor substrate has a thickness of 300 μm or more.

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