Semiconductor device and method for manufacturing the same

Abstract

This semiconductor apparatus includes: a semiconductor chip; a support body having an upper surface and a lower surface, the semiconductor chip being secured to the upper surface; a sealing resin for sealing the semiconductor chip and the support body; and a heat sink bonded to the lower surface of the support body, wherein a recessed portion is formed in an upper surface of the heat sink, the lower surface of the support body is bonded to a bottom surface of the recessed portion via a bonding structure, and the sealing resin enters a gap between at least the bonding structure and a side surface of the recessed portion out of the support body and the bonding structure.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] A semiconductor device including a semiconductor chip, a support on which the semiconductor chip is fixed on the upper surface, a sealing resin for sealing the semiconductor chip and the support, and a heat sink joined to the lower surface of the support has been developed (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In this type of semiconductor device, there is a problem that the bonding interface between the support and the heat sink deteriorates over time, and the heat dissipation effect decreases.

[0005] An object of the present disclosure is to provide a semiconductor device and a method for manufacturing the same that can suppress the deterioration over time of the bonding interface between the support and the heat sink.

Means for Solving the Problems

[0006] One embodiment of the present disclosure provides a semiconductor device comprising: a semiconductor chip; a support having an upper surface and a lower surface, the semiconductor chip being fixed to the upper surface; a sealing resin for sealing the semiconductor chip and the support; and a heat sink bonded to the lower surface of the support, wherein a recess is formed on the upper surface of the heat sink, the lower surface of the support is bonded to the bottom surface of the recess via a bonding structure, and the sealing resin is contained in the gap between at least the bonding structure and the side surface of the recess.

[0007] This configuration can suppress the deterioration of the bonding interface between the support and the heat sink over time.

[0008] One embodiment of the present disclosure provides a method for manufacturing a semiconductor device, comprising a semiconductor chip, a support having an upper surface and a lower surface, the semiconductor chip being fixed to the upper surface, a heat sink bonded to the lower surface of the support, and a sealing resin for sealing the semiconductor chip and the support, the method comprising a bonding step of bonding the semiconductor chip, the support, and the heat sink, and a sealing step of sealing the semiconductor chip and the support with the sealing resin.

[0009] This manufacturing method makes it possible to produce semiconductor devices that can suppress the deterioration of the bonding interface between the support and the heat sink over time.

[0010] The above-mentioned or further other purposes, features, and effects of this disclosure will be made apparent by the following description of embodiments with reference to the accompanying drawings. [Brief explanation of the drawing]

[0011] [Figure 1] Figure 1 is an illustrative cross-sectional view illustrating the configuration of a semiconductor device according to the first embodiment of this disclosure. [Figure 2] Figure 2 is an enlarged cross-sectional view of section A in Figure 1. [Figure 3A]Figure 3A is a cross-sectional view showing an example of the manufacturing process of the semiconductor device shown in Figure 1, and is a cross-sectional view corresponding to the cross-section in Figure 1. [Figure 3B] Figure 3B is a cross-sectional view showing the next step after Figure 3A. [Figure 3C] Figure 3C is a cross-sectional view showing the next step after Figure 3B. [Figure 3D] Figure 3D is a cross-sectional view showing the next step after Figure 3C. [Figure 4] Figure 4 is an enlarged cross-sectional view showing a modified example of the insulating substrate. [Figure 5A] Figure 5A is an enlarged cross-sectional view showing a modified heat sink. [Figure 5B] Figure 5B is an enlarged cross-sectional view showing another variation of the heat sink. [Figure 6] Figure 6 is an enlarged cross-sectional view showing a modified example of the shape of the side surface of the recess. [Figure 7] Figure 7 is an enlarged cross-sectional view showing a modified example of the depth of the recess. [Figure 8] Figure 8 is a schematic cross-sectional view illustrating the configuration of a semiconductor device according to the second embodiment of this disclosure. [Figure 9] Figure 9 is an enlarged cross-sectional view of section A in Figure 8. [Figure 10] Figure 10 is a schematic cross-sectional view illustrating the configuration of a semiconductor device according to the third embodiment of this invention. [Figure 11] Figure 11 is an enlarged cross-sectional view of section A in Figure 10. [Modes for carrying out the invention]

[0012] [Description of Embodiments in this Disclosure] One embodiment of the present disclosure includes a semiconductor chip, a support having an upper surface and a lower surface, the semiconductor chip being fixed to the upper surface, a sealing resin for sealing the semiconductor chip and the support, and a heat sink joined to the lower surface of the support. A recess is formed on the upper surface of the heat sink, the lower surface of the support is joined to the bottom surface of the recess via a joining structure, and the sealing resin enters a gap between at least the joining structure and the side surface of the recess among the support and the joining structure, providing a semiconductor device.

[0013] With this configuration, it is possible to suppress the aging deterioration of the joining interface between the support and the heat sink.

[0014] In one embodiment of the present disclosure, the side surface of the recess is formed in a curved surface shape or an inclined surface shape in which the cross-sectional area of the recess gradually increases from the bottom surface of the recess toward the opening of the recess on the upper surface of the heat sink.

[0015] In one embodiment of the present disclosure, the joining structure includes a solid-phase diffusion joining sheet.

[0016] In one embodiment of the present disclosure, the solid-phase diffusion joining sheet includes an Al layer, a first laminated film in which a Ni layer and an Ag layer are formed in this order on the lower surface of the Al layer, and a second laminated film in which a Ni layer and an Ag layer are formed in this order on the upper surface of the Al layer.

[0017] In one embodiment of the present disclosure, the joining structure includes a first solid-phase diffusion joining sheet, a second solid-phase diffusion joining sheet disposed above the first solid-phase diffusion joining sheet, and a stress buffer layer provided between the first solid-phase diffusion joining sheet and the second solid-phase diffusion joining sheet.

[0018] In one embodiment of the present disclosure, each solid-phase diffusion joining sheet includes an Al layer, a first laminated film in which a Ni layer and an Ag layer are formed in this order on the lower surface of the Al layer, and a second laminated film in which a Ni layer and an Ag layer are formed in this order on the upper surface of the Al layer.

[0019] In one embodiment of the present disclosure, the stress buffer layer consists of a CuMo layer.

[0020] In one embodiment of the present disclosure, the bonding structure includes sintered silver.

[0021] In one embodiment of the present disclosure, the joining structure includes solder.

[0022] In one embodiment of the present disclosure, the support includes an insulating substrate and a metal substrate disposed on the insulating substrate, wherein the semiconductor chip is fixed to the surface of the metal substrate opposite to the insulating substrate side.

[0023] In one embodiment of the present disclosure, the support is made of an insulating substrate.

[0024] In one embodiment of the present disclosure, the heat sink is a water cooler.

[0025] In one embodiment of the present disclosure, the heat sink is an air cooler.

[0026] In one embodiment of the present disclosure, the heat sink is made of a Cu block.

[0027] One embodiment of the present disclosure provides a method for manufacturing a semiconductor device, comprising a semiconductor chip, a support having an upper surface and a lower surface, the semiconductor chip being fixed to the upper surface, a heat sink bonded to the lower surface of the support, and a sealing resin for sealing the semiconductor chip and the support, the method comprising a bonding step of bonding the semiconductor chip, the support, and the heat sink, and a sealing step of sealing the semiconductor chip and the support with the sealing resin.

[0028] This manufacturing method makes it possible to produce semiconductor devices that can suppress the deterioration of the bonding interface between the support and the heat sink over time.

[0029] In the bonding process, of the bonding between the semiconductor chip and the support and the bonding between the support and the heat sink, at least the bonding between the support and the heat sink is performed by solid-phase diffusion bonding.

[0030] [Detailed description of embodiments of this disclosure] Embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0031] Figure 1 is a schematic cross-sectional view illustrating the configuration of a semiconductor device according to the first embodiment of this disclosure. Figure 2 is an enlarged cross-sectional view of part A in Figure 1. For convenience of explanation, the left side of Figure 1 will be referred to as "left," and the right side of Figure 1 will be referred to as "right."

[0032] The semiconductor device 1 is a power module. The semiconductor device 1 includes a heat sink 2, a support 3 bonded to the upper surface of the heat sink 2, semiconductor chips 4A and 4B fixed to the upper surface of the support 3, and a sealing resin 5 that seals the semiconductor chips 4A and 4B and the support 3. The main part of the semiconductor device 1, excluding the heat sink 2 (the module part), has a rectangular parallelepiped shape.

[0033] In this embodiment, the heat sink 2 is a water cooler that flows a cooling liquid such as cooling water or oil through holes formed inside the heat sink 2.

[0034] The support 3 includes an insulating substrate 6 joined to the upper surface of the heat sink 2 via a first bonding structure 11, and a pair of left and right metal substrates 7A and 7B joined to the insulating substrate 6 via a pair of left and right second bonding structures 12A and 12B.

[0035] In this embodiment, the insulating substrate 6 is made from a DBC (Direct Bonded Copper) substrate and consists of a ceramic plate 61, a copper foil 62 formed on the lower surface of the ceramic plate 61, and a pair of left and right copper foils 62A and 62B arranged at intervals on the upper surface of the ceramic plate 61.

[0036] The metal substrate 7A on the right is bonded to the upper surface of the copper foil 62A on the right via the second bonding structure 12A on the right. The metal substrate 7B on the left is bonded to the upper surface of the copper foil 62B on the left via the second bonding structure 12B on the left. In this embodiment, the metal substrates 7A and 7B are made of copper.

[0037] A semiconductor chip 4A is bonded to the metal substrate 7A on the right side via a third junction structure 13A (the third junction structure 13A on the right). A semiconductor chip 4B and a spacer 8 (described later) are bonded to the metal substrate 7B on the left side via a third junction structure 13B (the third junction structure 13B on the left). The semiconductor chip 4A on the right side is a high-side switching element, and the semiconductor chip 4B on the left side is a low-side switching element.

[0038] The first bonding structure 11, the second bonding structures 12A, 12B, and the third bonding structures 13A, 13B include a solid-phase diffusion bonding sheet. In other words, in this embodiment, the insulating substrate 6 and the heat sink 2 are bonded by solid-phase diffusion bonding. The insulating substrate 6 and the metal substrates 7A, 7B are also bonded by solid-phase diffusion bonding. The semiconductor chip 4A is bonded to the metal substrate 7A by solid-phase diffusion bonding. The semiconductor chip 4B and the spacer 8 are bonded to the metal substrate 7B by solid-phase diffusion bonding.

[0039] In this embodiment, the solid-phase diffusion bonding sheet consists of an Al preform sheet, as shown in Figure 2. The Al preform sheet consists of an Al layer 31, a first laminated film 32 formed on the lower surface of the Al layer 31, and a second laminated film 33 formed on the upper surface of the Al layer. The first laminated film 32 consists of a Ni layer formed on the lower surface of the Al layer 31 and an Ag layer formed on the lower surface of the Ni layer. The second laminated film 33 consists of a Ni layer formed on the upper surface of the Al layer 31 and an Ag layer formed on the upper surface of the Ni layer.

[0040] The semiconductor device 1 includes a spacer 8 placed on the left metal substrate 7B, wiring 9 connected to the spacer 8 and semiconductor chips 4A and 4B, and terminals 10. Terminals 10 include positive power supply terminals, negative power supply terminals, output terminals, gate terminals, etc., but only a portion of them are shown in Figure 1.

[0041] On the upper surface of the heat sink 2, a recess 21 is formed, which, in a plan view, has an outer peripheral edge (opening edge) that surrounds the lower surface of the support 3. The lower surface of the support 3 (the lower surface of the insulating substrate 6) is joined to the bottom surface 21a of the recess 21 via the first bonding structure 11. In this embodiment, almost the entirety of the first bonding structure 11 is located within the recess 21. In other words, the side surface 21b of the recess 21 is positioned to surround the outer peripheral surface of the first bonding structure 11.

[0042] In this embodiment, the side surface 21b of the recess 21 is formed in a curved shape, where the area of ​​the cross-sectional surface of the recess 21 gradually increases from the bottom surface of the recess 21 toward the opening of the recess 21 on the upper surface of the heat sink 2. In this embodiment, as will be described later, the recess 21 is formed during the process of manufacturing the semiconductor device 1, more specifically when the heat sink 2, insulating substrate 6, metal substrates 7A, 7B, semiconductor chips 4A, 4B and spacer 8 are joined together.

[0043] The sealing resin 5 has a rectangular shape that is slightly larger than the support 3 in a plan view, and is formed to cover a portion of the terminal 10, the wiring 9, the support 3, and the area near the support 3 on the upper surface of the heat sink 2. A portion of the sealing resin 5 extends into the entire space between the portion of the first bonding structure 11 and the support 3 located within the recess 21 (in this embodiment, almost the entire first bonding structure 11) and the side surface 21b of the recess 21. The portion of the terminal 10 that protrudes from the sealing resin 5 becomes the external wiring connection portion for connecting the terminal 10 to the external wiring. The sealing resin 5 is made of, for example, epoxy resin.

[0044] In the semiconductor device 1 of this embodiment, a recess 21 is formed on the upper surface of the heat sink 2, and the lower surface of the support 3 is joined to the bottom surface 21a of the recess 21 via a first bonding structure 11. A portion of the sealing resin 5 is contained within the entire space between the first bonding structure 11 and the portion of the support 3 located within the recess 21 (in this embodiment, almost the entire first bonding structure 11) and the side surface 21b of the recess 21. This creates a so-called anchoring effect, making it difficult for the sealing resin 5 to peel off from the heat sink 2. This increases the bonding strength between the heat sink 2 and the support 3 (insulating substrate 6). This suppresses the deterioration of the bonding interface between the support 3 and the heat sink 2 over time.

[0045] Furthermore, in the semiconductor device 1 of this embodiment, the heat sink 2 and the support 3 (insulating substrate 6) are joined by solid-phase diffusion bonding. Compared to cases where they are joined by solder bonding or silver firing bonding, the deterioration of these bonding interfaces over time can be suppressed.

[0046] Figures 3A to 3D are illustrative cross-sectional views illustrating the manufacturing process of the semiconductor device 1 shown in Figures 1 and 2, and correspond to the cross-sectional view in Figure 1.

[0047] First, as shown in Figure 3A, an Al preform sheet 91 for forming the first bonding structure 11 is placed on the heat sink 2, and an insulating substrate 6 is placed on the Al preform sheet 91. The insulating substrate 6 is made from a DBC substrate and consists of a ceramic plate 51, a copper foil 62 formed on the lower surface of the ceramic plate 51, and a pair of left and right copper foils 62A and 62B placed on the upper surface of the ceramic plate 51 with a gap between them.

[0048] Furthermore, Al preform sheets 92A and 92B for forming the second bonding structures 12A and 12B are placed on the pair of copper foils 62A and 62B on the upper side of the insulating substrate 6, and metal substrates 7A and 7B are placed on the Al preform sheets 92A and 92B.

[0049] Also, an Al preform sheet 93A for forming a third bonding structure 13A is disposed on a metal substrate 7A, and a semiconductor chip 4A is disposed on the Al preform sheet 93A. Further, an Al preform sheet 93B for forming a third bonding structure 13B is disposed on a metal substrate 7B, and a semiconductor chip 4B and a spacer 8 are disposed on the Al preform sheet 93B.

[0050] Then, in a temperature environment of 150°C to 400°C, the members disposed on the heat sink 2 are pressed at a pressure of 20 MPa or more. As a result, as shown in FIG. 3B, a recess 21 is formed in the heat sink 2, and the lower surface of the insulating substrate 6 is joined (in this embodiment, solid-phase diffusion bonding) to the bottom surface of the recess 21 via a first bonding structure 11 including an Al preform sheet 91. Also, the metal substrates 7A and 7B are joined (in this embodiment, solid-phase diffusion bonding) to the upper surfaces of 62A and 62B on the upper layer side of the insulating substrate 6 via second bonding structures 12A and 12B including Al preform sheets 91A and 91B. Further, the semiconductor chip 4A is joined (in this embodiment, solid-phase diffusion bonding) to the upper surface of the metal substrate 7A via a third bonding structure 13A including an Al preform sheet 93A. Also, the semiconductor chip 4B and the spacer 8 are joined (in this embodiment, solid-phase diffusion bonding) to the upper surface of the metal substrate 7B via a third bonding structure 13B including an Al preform sheet 93B.

[0051] Note that the joining of the heat sink 2 and the insulating substrate 6, the joining of the insulating substrate 6 and the metal substrates 7A and 7B, and the joining of the metal substrates 7A and 7B and the semiconductor chips 4A and 4B and the spacer 8 may be performed separately in time.

[0052] Next, as shown in FIG. 3C, the wiring 9 is joined to the semiconductor chips 4A and 4B and the spacer 8.

[0053] Next, as shown in FIG. 3D, the terminals 10 are joined to the metal substrates 7A and 7B, the wiring 9, etc.

[0054] Finally, a sealing resin 5 is formed to cover a portion of the terminal 10, the wiring 9, the support 3, and the area near the support 3 on the upper surface of the heat sink 2. This results in a semiconductor device 1 as shown in Figures 1 and 2.

[0055] The advantages of this manufacturing method will be explained. In general manufacturing methods, the parts other than the heat sink (the module part including the sealing resin 5) are manufactured first, and then the module part is joined to the heat sink. If the joining of the module part and the heat sink is to be performed by solid-phase diffusion bonding, the heat sink and module part must be heated to a relatively high temperature (around 300°C), which degrades the sealing resin 5. For this reason, in general manufacturing methods, it is difficult to solid-phase diffuse bond the heat sink 2 and the support 3 (insulating substrate 6) under a temperature environment suitable for solid-phase diffusion bonding.

[0056] In contrast, in the manufacturing method according to this embodiment, the heat sink 2 and the support 3 (insulating substrate 6) are solid-phase diffusion bonded before the sealing resin 5 is formed. Therefore, the heat sink 2 and the support 3 (insulating substrate 6) can be solid-phase diffusion bonded under a temperature environment suitable for solid-phase diffusion bonding. This makes it possible to firmly bond the heat sink 2 and the support 3 (insulating substrate 6).

[0057] Alternatively, instead of solid-phase diffusion bonding, the heat sink 2 and the support 3 (insulating substrate 6) may be bonded by silver firing. In this case as well, by manufacturing the semiconductor device in the same order as shown in Figures 3A to 3D, the heat sink 2 and the support 3 (insulating substrate 6) can be bonded by silver firing under a temperature environment suitable for silver firing. This allows for a strong bond between the heat sink 2 and the support 3 (insulating substrate 6).

[0058] Furthermore, in the manufacturing method of this embodiment, a portion of the sealing resin 5 can be inserted into the entire space between the portion of the first bonding structure 11 and the support 3 located within the recess 21 (in this embodiment, almost the entire first bonding structure 11) and the side surface 21b of the recess 21. This creates a so-called anchoring effect, making it difficult for the sealing resin 5 to peel off from the heat sink 2. This increases the bonding strength between the heat sink 2 and the support 3 (insulating substrate 6). This suppresses the deterioration of the bonding interface between the support 3 and the heat sink 2 over time.

[0059] In the above-described embodiment, the insulating substrate 6 consists of a ceramic plate 61, a copper foil 62 formed on the lower surface of the ceramic plate 61, and a pair of left and right copper foils 62A and 62B arranged at intervals on the upper surface of the ceramic plate 61.

[0060] However, the insulating substrate 6 may consist of a pair of left and right insulating substrates 6A and 6B arranged with a gap between them in the left-right direction, as shown in Figure 4. One insulating substrate 6A is made from a DBC substrate and consists of a ceramic plate 61A, a copper foil 63A formed on the lower surface of the ceramic plate 61A, and a copper foil 62A formed on the upper surface of the ceramic plate 61A. The other insulating substrate 6B is made from a DBC substrate and consists of a ceramic plate 61B, a copper foil 63B formed on the lower surface of the ceramic plate 61B, and a copper foil 62B formed on the upper surface of the ceramic plate 61B. In Figure 4, parts corresponding to each part in Figure 1 are indicated by the same reference numerals as in Figure 1.

[0061] Furthermore, in the embodiment described above, the heat sink 2 is a water cooler. However, the heat sink 2 may be an air cooler with fins, as shown in Figure 5A. Also, the heat sink 2 may be composed of a copper block, as shown in Figure 5B. In Figures 5A and 5B, parts corresponding to each part in Figure 1 are denoted by the same reference numerals as in Figure 1.

[0062] Furthermore, in the embodiment described above, the side surface 21b of the recess 21 is formed in a curved shape in which the area of ​​the cross-section of the recess 21 gradually increases from the bottom surface of the recess 21 toward the opening of the recess 21 on the upper surface of the heat sink 2. However, as shown in Figure 6, the side surface 21b of the recess 21 may be formed in an inclined surface shape (tapered surface shape) in which the area of ​​the cross-section of the recess 21 gradually increases from the bottom surface of the recess 21 toward the opening of the recess 21 on the upper surface of the heat sink 2.

[0063] Figure 6 is an enlarged cross-sectional view corresponding to Figure 2. In Figure 6, the parts corresponding to Figure 2 are denoted by the same reference numerals as in Figure 2. In this modified example as well, a portion of the sealing resin 5 fills the entire space between the first bonding structure 11 and the portion of the support 3 located within the recess 21 (in the example of Figure 6, almost the entire first bonding structure 11) and the side surface 21b of the recess 21.

[0064] Furthermore, in the embodiment described above, the depth of the recess 21 is approximately equal to the thickness of the first bonding structure 11, but the depth of the recess 21 may be less than the thickness of the first bonding structure 11. Also, as shown in Figure 7, the depth of the recess 21 may be deep enough to accommodate the entire first bonding structure 11 and the lower end of the support 3. In other words, the depth of the recess 21 may be greater than the thickness of the first bonding structure 11.

[0065] Figure 7 is an enlarged cross-sectional view corresponding to Figure 2. In Figure 7, the parts corresponding to Figure 2 are denoted by the same reference numerals as in Figure 2. In this modified example, a portion of the sealing resin 5 is contained within the entire space between the first bonding structure 11 and the portion of the support 3 located within the recess 21, and the side surface 21b of the recess 21.

[0066] Figure 8 is a schematic cross-sectional view illustrating the configuration of a semiconductor device according to a second embodiment of the present disclosure. Figure 9 is an enlarged cross-sectional view of part A in Figure 8. In Figures 8 and 9, parts corresponding to Figures 1 and 2 are denoted by the same reference numerals as in Figures 1 and 2.

[0067] In the semiconductor device 1A according to the second embodiment, the first bonding structure 11 consists of a lower bonding structure 41 disposed on the bottom surface 21a of the heat sink 2, an upper bonding structure 42 disposed above the lower bonding structure 41, and a stress buffer layer 43 interposed between the lower bonding structure 41 and the upper bonding structure 42. The lower bonding structure 41 and the upper bonding structure 42 each have the same structure as the first bonding structure 11 of the semiconductor device 1 according to the first embodiment. Other configurations are the same as those of the semiconductor device 1 according to the first embodiment. The stress buffer layer 43 is made of, for example, a CuMo layer.

[0068] In the semiconductor device 1A according to the second embodiment, a portion of the sealing resin 5 is contained within the entire space between the first bonding structure 11 and the portion of the support 3 located within the recess 21 (in the example of Figures 8 and 9, almost the entire lower bonding structure 41) and the side surface 21b of the recess 21.

[0069] In the second embodiment, since the first bonding structure 11 includes a stress buffer layer 43, the deterioration of the bonding interface between the support 3 and the heat sink 2 over time can be suppressed more effectively than in the first embodiment.

[0070] Figure 10 is an illustrative cross-sectional view illustrating the configuration of a semiconductor device according to the third embodiment of this disclosure. Figure 11 is an enlarged cross-sectional view of part A in Figure 10. In Figures 10 and 11, parts corresponding to Figures 1 and 2 are denoted by the same reference numerals as in Figures 1 and 2.

[0071] In the semiconductor device 1B according to the third embodiment, the insulating substrate 6 is composed of an insulating layer 65 and a metal layer (metallized layer) 66 formed beneath the insulating layer 65. Metal substrates 7A and 7B are arranged on the insulating layer 65 with a gap between them. The insulating layer 65 and the metal substrates 7A and 7B are bonded not by solid-state diffusion bonding, but by ceramic coating such as thermal spraying or aerosol deposition. Therefore, the semiconductor device 1B according to the third embodiment does not have the second bonding structures 12A and 12B. Other configurations are the same as those of the semiconductor device 1 according to the first embodiment.

[0072] The insulating layer 65 is, for example, made of an Al2O3 layer. The insulating layer 65 may also be a Si3N4 layer or an AlN layer. The metal layer 66 is, for example, made of a Cu layer, an Ag layer, an Au layer, a Ni layer, an Al layer, etc.

[0073] In the semiconductor device 1B according to the third embodiment, a portion of the sealing resin 5 is contained within the entire space between the first bonding structure 11 and the portion of the support 3 located within the recess 21 (in the example of Figures 10 and 11, almost the entire first bonding structure 11) and the side surface 21b of the recess 21.

[0074] In the first to third embodiments described above, the first bonding structure 11 includes a solid-phase diffusion bonding sheet, but the first bonding structure 11 may also include sintered silver or solder. In other words, the heat sink 2 and the support 3 (insulating substrate 6) may be bonded by silver firing bonding or by solder bonding.

[0075] Similarly, in the first to third embodiments described above, the third bonding structures 13A and 13B include a solid-phase diffusion bonding sheet, but the third bonding structures 13A and 13B may also include sintered silver or solder. In other words, the support 3 (metal substrates 7A and 7B) and the semiconductor chips 4A and 4B may be bonded by silver sintering bonding or by solder bonding.

[0076] Furthermore, in the first and second embodiments, the second bonding structures 12A and 12B include a solid-phase diffusion bonding sheet, but the second bonding structures 12A and 12B may also include sintered silver or solder. In other words, the insulating substrate 6 (copper foil 62A, 62B) and the metal substrates 7A and 7B may be joined by silver firing bonding or by solder bonding.

[0077] In the first to third embodiments described above, the recess 21 is formed on the upper surface of the heat sink 2 by joining the heat sink 2 and the support 3 (insulating substrate 6) in a press-fit state. However, the recess 21 may be formed on the upper surface of the heat sink 2 before joining the support 3 (insulating substrate 6) to the upper surface of the heat sink 2.

[0078] Although embodiments of this disclosure have been described in detail above, these are merely examples used to illustrate the technical content of this disclosure, and this disclosure should not be construed as being limited to these examples. The scope of this disclosure is limited only to the attached claims.

[0079] This application corresponds to Japanese Patent Application No. 2021-143182, filed with the Japan Patent Office on September 2, 2021, and the full disclosures of those applications are incorporated herein by reference. [Explanation of Symbols]

[0080] 1,1A,1B Semiconductor equipment 2 Heatsink 3 Support 4A, 4B semiconductor chips 5 Sealing resin 6, 6A, 6B Insulating substrate 61, 61A, 61B Ceramic Plates 62,62A,62B,63A,63B Copper foil 7A,7B Metal substrate 8 Spacers 9 Wiring 10 terminals 11 First joint structure 12A,12B 2nd joint structure 13A,13B 3rd joint structure 21 Recess 21a Bottom 21b Side 31 Al layer 32. First layered film 32. Second layered artery 41 Lower joint structure 42 Upper joint structure 43. Stress buffer layer 91, 92A, 92B, 93A, 93B Al preform sheet

Claims

1. Semiconductor chips and A support having an upper surface and a lower surface, the semiconductor chip being fixed to the upper surface, A sealing resin for sealing the semiconductor chip and the support, The heat sink is bonded to the lower surface of the support, A recess is formed on the upper surface of the heat sink. The lower surface of the support is joined to the bottom surface of the recess via a bonding structure. The sealing resin is contained in the gap between at least the bonding structure and the side surface of the recess, among the support and the bonding structure. A semiconductor device wherein the side surface of the recess is formed in a curved or inclined shape, such that the area of ​​the cross-sectional surface of the recess gradually increases from the bottom surface of the recess toward the opening of the recess on the upper surface of the heat sink.

2. The semiconductor device according to claim 1, wherein the bonding structure includes a solid-phase diffusion bonding sheet.

3. The semiconductor device according to claim 2, wherein the solid-phase diffusion bonding sheet comprises an Al layer, a first laminated film in which a Ni layer and an Ag layer are formed in that order on the lower surface of the Al layer, and a second laminated film in which a Ni layer and an Ag layer are formed in that order on the upper surface of the Al layer.

4. The semiconductor device according to claim 1, wherein the bonding structure includes a first solid-phase diffusion bonding sheet, a second solid-phase diffusion bonding sheet disposed above the first solid-phase diffusion bonding sheet, and a stress buffer layer provided between the first solid-phase diffusion bonding sheet and the second solid-phase diffusion bonding sheet.

5. The semiconductor device according to claim 4, wherein each solid-phase diffusion bonding sheet comprises an Al layer, a first laminated film in which a Ni layer and an Ag layer are formed in that order on the lower surface of the Al layer, and a second laminated film in which a Ni layer and an Ag layer are formed in that order on the upper surface of the Al layer.

6. The semiconductor device according to claim 4 or 5, wherein the stress buffer layer is made of a CuMo layer.

7. The semiconductor device according to claim 1, wherein the bonding structure includes sintered silver or solder.

8. The support comprises an insulating substrate and a metal substrate disposed on the insulating substrate. The semiconductor device according to claim 1, wherein the semiconductor chip is fixed to the surface of the metal substrate opposite to the insulating substrate side.

9. The semiconductor device according to claim 1, wherein the support is made of an insulating substrate.

10. The semiconductor device according to claim 1, wherein the heat sink is a water cooler or an air cooler.

11. The semiconductor device according to claim 1, wherein the heat sink is made of a Cu block.

12. A method for manufacturing a semiconductor device, comprising: a semiconductor chip; a support having an upper surface and a lower surface, the semiconductor chip being fixed to the upper surface; a heat sink being bonded to the lower surface of the support; and a sealing resin for sealing the semiconductor chip and the support, A bonding step for joining the semiconductor chip, the support, and the heat sink, The process includes sealing the semiconductor chip and the support with the sealing resin, A recess is formed on the upper surface of the heat sink. In the bonding process, the lower surface of the support is bonded to the bottom surface of the recess via a bonding structure. In the sealing step, the sealing resin enters the gap between at least the bonding structure and the side surface of the recess, A method for manufacturing a semiconductor device, wherein the side surface of the recess is formed in a curved or inclined shape, such that the area of ​​the cross-sectional surface of the recess gradually increases from the bottom surface of the recess toward the opening of the recess on the upper surface of the heat sink.

13. The method for manufacturing a semiconductor device according to claim 12, wherein in the bonding step, at least the bonding between the support and the heat sink, of which the bonding between the semiconductor chip and the support and the bonding between the support and the heat sink is performed by solid-phase diffusion bonding.

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