Field-effect transistor with multiple stepped field plates

Abstract

Transistor elements according to some embodiments include a semiconductor barrier layer, a surface dielectric layer on the semiconductor barrier layer, and a gate on the surface dielectric layer. The surface dielectric layer includes an opening therein that is laterally spaced from the gate. The element includes an interlayer dielectric layer on the surface dielectric layer that extends over the gate and into the opening in the surface dielectric layer, and a multi-step field plate on the interlayer dielectric layer. The multi-step field plate is laterally spaced from the gate. The embedded portion of the multi-step field plate is above the opening in the surface dielectric layer, and the multi-step field plate includes a first step adjacent to the embedded portion of the field plate on the side surface of the field plate on the side opposite the gate, and a second step adjacent to the first step.

Description

Technical Field

[0001] The present disclosure relates to transistor structures, and more particularly to field effect transistors including field plates.

Background Art

[0002] Narrow bandgap semiconductor materials such as silicon (Si) and gallium arsenide (GaAs) are widely used for semiconductor devices for low power applications and, in the case of Si, for low frequency applications. However, these semiconductor materials have a relatively small bandgap (1.12 eV for Si and 1.42 eV for GaAs at room temperature) and a relatively small breakdown voltage, and thus may not be very suitable for high power and / or high frequency applications.

[0003] Due to the interest in high power, high temperature, and / or high frequency applications and devices, wide bandgap semiconductor materials such as silicon carbide (3.2 eV for 4H-SiC at room temperature) and group III nitrides (e.g., 3.36 eV for GaN at room temperature) have received attention. These materials can have a higher breakdown field strength and a higher electron saturation velocity than GaAs and Si.

[0004] Particularly interesting devices for high power and / or high frequency applications are high electron mobility transistors (HEMTs), also known as modulation doped field effect transistors (MODFETs). In HEMT devices, a two-dimensional electron gas (2DEG) can be formed at the hetero-junction of two semiconductor materials with different bandgap energies, where the material with the smaller bandgap has a higher electron affinity than the wide bandgap material. The 2DEG is the accumulation layer of the undoped small bandgap material and has a relatively high sheet electron concentration, e.g., 10 13 carriers / cm 2It can contain sheet electron concentrations exceeding 2DEG. Furthermore, electrons originating from the wider bandgap semiconductor can transition to 2DEG, and relatively high electron mobility is possible due to reduced scattering of ionized impurities. This combination of relatively high carrier concentration and carrier mobility can give HEMTs relatively large transconductance, resulting in a performance advantage over metal-semiconductor field-effect transistors (MESFETS) for high-frequency applications.

[0005] HEMTs fabricated from gallium nitride / aluminum gallium nitride (GaN / AlGaN) material systems can generate large amounts of RF power due to a combination of material properties such as a relatively high dielectric breakdown field, a relatively wide band gap, a relatively large conduction band offset, and / or a relatively high saturation electron drift rate. The majority of electrons in 2DEG may be due to polarization in the AlGaN.

[0006] Field plates are used to improve the performance of GaN-based HEMTs at microwave frequencies, resulting in improved performance compared to devices without field plates. Many field-plate approaches involve connecting the field plate to the transistor's source, with the field plate placed on the drain side of the channel. This can lower the electric field on the gate-drain side of the transistor, thereby increasing the breakdown voltage and potentially reducing the high-field trapping effect. However, some transistors with gate-drain field plates may exhibit relatively poor reliability performance, particularly in Class C (or higher) operations where the electric field on the source side of the gate is critical.

[0007] Figure 1 shows a GaN-based HEMT 10 formed on a silicon carbide substrate 12. A GaN channel layer 16 is present on the substrate 12, and an AlGaN barrier layer 18 is present on the channel layer 16. A two-dimensional electron gas (2DEG) 20 is generated within the channel layer 16 adjacent to the barrier layer 18. A source contact 22 and a drain contact 24 are formed on the channel layer 16. The conductivity of the 2DEG 20 is modulated by applying a voltage to a gate 26 formed on the barrier layer 18 between the source contact 22 and the drain contact 24. As shown in Figure 1, the gate 26 may have a mushroom configuration or a T-top configuration in which the gate 26 contacts the barrier layer 18 in a relatively narrow contact region extending through the surface dielectric layer 25.

[0008] The HEMT10 includes a field plate 28 connected to the source contact 22. The field plate 28 is separated from the gate 26 by an interlayer dielectric layer 21 and separated from the barrier layer 18 by the interlayer dielectric layer 21 and the surface dielectric layer 25. The field plate 28 extends above the gate 26 and laterally toward the drain contact 24.

[0009] The field plate 28 is connected to the source contact 22. Connecting the field plate 28 to the source contact 22 reduces the gate-to-drain capacitance (Cgd), thereby increasing the gain of the device. In addition to reducing the gate-to-drain capacitance Cgd, the presence of the field plate 28 can improve the linearity of the device and / or reduce the drain bias dependence of the capacitance. GaN-based HEMTs generally exhibit good linearity, but further improvement may be desired in high-power RF applications. Furthermore, while the structure shown in Figure 1 can reduce the gate-to-drain capacitance Cgd compared to a structure without a field plate, the gate-to-drain capacitance Cgd may still be highly dependent on the bias of the drain contact 24. [Prior art documents] [Patent Documents]

[0010] [Patent Document 1] U.S. Patent No. 6,849,882 [Patent Document 2] U.S. Patent No. 7,230,284 [Patent Document 3] U.S. Patent No. 7,501,669 [Patent Document 4] U.S. Patent No. 7,126,426 [Patent Document 5] U.S. Patent No. 7,550,783 [Patent Document 6] U.S. Patent No. 7,573,078 [Patent Document 7] U.S. Patent Application Publication No. 2005 / 0253167 [Patent Document 8] U.S. Patent Application Publication No. 2006 / 0202272 [Patent Document 9] U.S. Patent Application Publication No. 2008 / 0128752 [Patent Document 10] U.S. Patent Application Publication No. 2010 / 0276698 [Patent Document 11] U.S. Patent Application Publication No. 2012 / 0049973 [Patent Document 12] U.S. Patent Application Publication No. 2012 / 0194276 [Patent Document 13] U.S. Patent No. 9,847,411 [Overview of the project] [Means for solving the problem]

[0011] Transistor elements according to some embodiments include a semiconductor barrier layer, a surface dielectric layer on the semiconductor barrier layer, and a gate on the surface dielectric layer. The surface dielectric layer includes an opening therein that is laterally spaced from the gate. The element includes an interlayer dielectric layer on the surface dielectric layer that extends into the opening in the surface dielectric layer over the gate, and a multiple-stepped field plate on the interlayer dielectric layer. The multiple-stepped field plate is laterally spaced from the gate.

[0012] The embedded portion of the multiple-stepped field plate is above the opening in the surface dielectric layer, and the multiple-stepped field plate includes a first step adjacent to the embedded portion of the field plate on the side surface of the field plate on the opposite side of the gate, and a second step adjacent to the first step. The embedded portion of the field plate is vertically spaced from the semiconductor barrier layer by a first distance, the first step is vertically spaced from the semiconductor barrier layer by a second distance, and the second step is vertically spaced from the semiconductor barrier layer by a third distance. The second distance is greater than the first distance, and the third distance is greater than the second distance.

[0013] In some embodiments, the first distance is equal to the thickness of the interlayer dielectric layer. In some embodiments, the second distance is equal to the sum of the thickness of the interlayer dielectric layer and the thickness of the surface dielectric layer.

[0014] The interlayer dielectric layer may include a first interlayer dielectric layer. In this case, the third distance is equal to the sum of the thickness of the first interlayer dielectric layer, the thickness of the surface dielectric layer, and the thickness of the second interlayer dielectric layer on the first interlayer dielectric layer.

[0015] The opening in the surface dielectric layer may extend completely through the surface dielectric layer to expose the semiconductor barrier layer, and the gate may extend through the surface dielectric layer to contact the semiconductor barrier layer.

[0016] In some embodiments, the transistor element may include a source contact and a drain contact on a semiconductor barrier layer, in which case the gate is between the source contact and the drain contact, and the field plate includes a source side wing extending over the semiconductor barrier layer and toward the source contact.

[0017] The first distance may be from about 0.1 to 0.3 microns, the second distance may be from about 0.15 to 0.4 microns. The third distance may be from about 0.25 to 0.5 microns. The width of the embedded portion of the field plate may be from about 0.3 to 0.6 microns.

[0018] The width of the first step may be from about 0.3 to 0.6 microns, and the width of the second step may be from about 0.3 to 0.6 microns.

[0019] The interlayer dielectric layer has a vertical thickness, and the field plate may be laterally spaced from the gate by a distance approximately equal to the vertical thickness of the interlayer dielectric layer.

[0020] The transistor element may include a third step adjacent to the second step, in which case the third step is vertically spaced from the semiconductor by a fourth distance greater than the third distance.

[0021] A method for forming a transistor element according to some embodiments includes the steps of: forming a surface dielectric layer on a semiconductor barrier layer; forming an opening in the surface dielectric layer to expose the semiconductor barrier layer; forming a gate on the surface dielectric layer, spaced laterally apart from the opening; forming an interlayer dielectric layer on the surface dielectric layer and the gate, wherein the interlayer dielectric layer extends beyond the gate into the opening in the surface dielectric layer; and forming a multi-stepped field plate on the interlayer dielectric layer. The multi-stepped field plate is spaced laterally apart from the gate. The embedded portion of the multi-stepped field plate is above the opening in the surface dielectric layer. The multi-stepped field plate includes a first step adjacent to the embedded portion of the multi-stepped field plate on the side of the multi-stepped field plate opposite to the gate, and a second step adjacent to the first step. The embedded portion of the multi-step field plate is separated vertically from the semiconductor barrier layer by a first distance, the first step is separated vertically from the semiconductor barrier layer by a second distance, and the second step is separated vertically from the semiconductor barrier layer by a third distance. The second distance is greater than the first distance, and the third distance is greater than the second distance.

[0022] In some embodiments, a high electron-mobility transistor element includes a channel layer, a semiconductor barrier layer on the channel layer, a surface dielectric layer on the semiconductor barrier layer, and a gate on the surface dielectric layer. The surface dielectric layer contains an opening that is spaced laterally from the gate.

[0023] The element further includes a source contact and a drain contact on a semiconductor barrier layer, the gate being located between the source contact and the drain contact, and an interlayer dielectric layer on a surface dielectric layer, the interlayer dielectric layer extending over the gate into an opening in the surface dielectric layer.

[0024] The element further includes a field plate on an interlayer dielectric layer between the gate contact and the drain contact, in which case the field plate is spaced laterally from the gate. The embedded portion of the field plate is above the opening in the surface dielectric layer, and the field plate includes a first step adjacent to the embedded portion of the field plate on the side of the field plate opposite the gate, and a second step adjacent to the first step.

[0025] The embedded portion of the field plate is separated vertically from the semiconductor barrier layer by a first distance, the first step is separated vertically from the semiconductor barrier layer by a second distance, and the second step is separated vertically from the semiconductor barrier layer by a third distance. The second distance is greater than the first distance, and the third distance is greater than the second distance. [Brief explanation of the drawing]

[0026] [Figure 1] This is a cross-sectional view of a conventional transistor element, including the field plate. [Figure 2A] This is a cross-sectional view of a transistor element, including a field plate according to several embodiments. [Figure 2B] This is a cross-sectional view of a transistor element, including a field plate according to several embodiments. [Figure 2C] This is a cross-sectional view of a transistor element, including a field plate according to several embodiments. [Figure 3A] This is a cross-sectional view of a transistor element, including a field plate according to yet another embodiment. [Figure 3B] This is a cross-sectional view of a transistor element, including a field plate according to yet another embodiment. [Figure 4A] This is a graph of the simulated off-state leakage current for elements in several embodiments. [Figure 4B] This is a graph of the simulated drain-source capacitance Cds for elements in several embodiments. [Figure 5A] This is a cross-sectional view illustrating the operation for manufacturing a transistor element including a field plate according to several embodiments. [Figure 5B] This is a cross-sectional view illustrating the operation for manufacturing a transistor element including a field plate according to several embodiments. [Figure 5C] This is a cross-sectional view illustrating the operation for manufacturing a transistor element including a field plate according to several embodiments. [Figure 5D] This is a cross-sectional view illustrating the operation for manufacturing a transistor element including a field plate according to several embodiments. [Figure 5E] This is a cross-sectional view illustrating the operation for manufacturing a transistor element including a field plate according to several embodiments. [Figure 5F] This is a cross-sectional view illustrating the operation for manufacturing a transistor element including a field plate according to several embodiments. [Figure 5G] This is a cross-sectional view illustrating the operation for manufacturing a transistor element including a field plate according to several embodiments. [Figure 5H] This is a cross-sectional view illustrating the operation for manufacturing a transistor element including a field plate according to several embodiments. [Figure 5I] This is a cross-sectional view illustrating the operation for manufacturing a transistor element including a field plate according to several embodiments. [Figure 5J] This is a cross-sectional view illustrating the operation for manufacturing a transistor element including a field plate according to several embodiments. [Figure 6] This block diagram shows the operation for forming a transistor element according to several embodiments. [Figure 7A] This is a schematic block diagram of a multi-stage amplifier circuit that can use an RF transistor amplifier incorporating transistor elements according to the embodiment. [Figure 7B] This is a schematic block diagram of a multi-stage amplifier circuit that can use an RF transistor amplifier incorporating transistor elements according to the embodiment. [Figure 7C] This is a schematic block diagram of a multi-stage amplifier circuit that can use an RF transistor amplifier incorporating transistor elements according to the embodiment. [Modes for carrying out the invention]

[0027] Next, embodiments of the concept of the present invention will be described in relation to the accompanying drawings. Some embodiments described herein provide a transistor element including a field plate which is automatically aligned with respect to the gate so as not to overlap with the gate in the vertical direction, and in some embodiments, is spaced laterally from the gate. In some embodiments, the field plate is embedded toward the barrier layer in the embedded region. In yet another embodiment, the field plate may be connected to a source outside the active region of the element by a non-crossing connection over the gate of the element.

[0028] In this specification, various elements may be described using ordinal numbers, such as 1st, 2nd, 3rd, etc., but it should be understood that these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, the 1st element may also be called the 2nd element, and similarly, the 2nd element may also be called the 1st element without departing from the scope of this disclosure.

[0029] Furthermore, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship between one element and another, as shown in the drawings. It should be understood that relative terms are intended to encompass different orientations of elements in addition to the orientation depicted in the drawings. For example, if an element is turned upside down in one of the drawings, a feature described as being on the "lower" side of the element will be oriented towards the "upper" side of that element. Thus, the exemplary term "lower" can describe both downward and upward orientations, depending on the specific orientation of the element. Similarly, if an element is turned upside down in one of the drawings, an element described as "below" or "below" other elements will be oriented above those other elements. Thus, the exemplary terms "downward" or "lower" can describe both upward and downward orientations.

[0030] The terms used in the description of the disclosure herein are intended solely to describe specific embodiments and are not intended to limit the disclosure. Where used in the description of the disclosure and the accompanying claims, the singular forms "an" and "the" are intended to include the plural form unless the context explicitly indicates otherwise. It should also be understood that the terms "and / or" as used herein refer to and encompass any and all possible combinations of one or more of the related enumerated items. Where used herein, the terms "comprise" and "comprising" indicate the presence of the described steps, operations, features, elements, and / or components, but do not preclude the presence or addition of one or more other steps, operations, features, elements, components, and / or groups thereof.

[0031] The embodiments of this disclosure are described herein with reference to schematic cross-sectional views of idealized embodiments of this disclosure. Therefore, variations from the shapes shown in the figures are to be expected, for example, as a result of manufacturing techniques and / or tolerances. Accordingly, the embodiments of this disclosure should not be construed as being limited to specific shapes of the regions shown herein, but should include, for example, deviations in shape resulting from manufacturing. The regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the elements, nor are they intended to limit the scope of the disclosure unless otherwise specified. Furthermore, for schematic reasons, lines that appear straight, horizontal, or vertical in the following drawings are often inclined, curved, non-horizontal, or non-vertical. Furthermore, it is understood that the thickness of the elements is schematic in nature.

[0032] Unless otherwise defined, all terms used in disclosing the embodiments of this disclosure, including technical and scientific terms, have the same meaning as commonly understood by those skilled in the art and are not necessarily limited to any specific definition known at the time of this disclosure. These terms may include equivalent terms created after such time. Furthermore, terms such as those defined in commonly used dictionaries should be understood to have meanings consistent with those in the context of this specification and the art.

[0033] Referring to Figure 2A, several transistor elements according to various embodiments are illustrated. In particular, Figure 2A shows a high electron mobility transistor element 100A formed on a substrate 112. A channel layer 116 is formed on the substrate 112, and a barrier layer 118 is located on the channel layer 116.

[0034] Source contact 122 and drain contact 124 are formed on the channel layer 116. The gate 126 is formed on the barrier layer 118 between the source contact 122 and the drain contact 124. As shown in Figure 2A, the gate 26 may have a mushroom configuration or a T-top configuration, in which the gate 126 contacts the barrier layer 118 in a relatively narrow contact area of ​​the embedded contact portion 127 of the gate 126, and the embedded contact portion 127 extends through the surface dielectric layer 125 inside the gate opening 162 that passes through the surface dielectric layer 125. The width of the gate opening 162 may be about 0.09 microns to about 0.4 microns.

[0035] The surface dielectric layer 125 also includes a field plate opening 164 that passes through the surface dielectric layer 125, exposing the barrier layer 118.

[0036] In some embodiments, the substrate 112 contains silicon carbide, the channel layer 116 contains GaN, and the barrier layer contains AlGaN. However, it will be understood that other materials or combinations of materials can also be used. Furthermore, the channel layer 116 and / or the barrier layer 118 may be Al x Ga 1-x It may include alloys such as N, where 0 ≤ x ≤ 1. Although a HEMT element is shown, it will be further understood that element 100A may be other types of transistor elements such as a metal-semiconductor field-effect transistor (MESFET), a junction field-effect transistor (JFET), or a metal oxide semiconductor field-effect transistor (MOSFET).

[0037] In the embodiment illustrated in Figure 2A, the field plate 140 is laterally spaced from the gate 126 by the first interlayer dielectric layer 121 and does not overlap or extend over and beyond the gate 126, as in the structure shown in Figure 1, which could result in insufficient step coverage and cracking of the metallization of the field plate. However, it will be understood that in some embodiments, the field plate 140 may overlap the gate 126 in its lateral dimension. The field plate 140 may also be electrically connected to the source contact 122 outside the active region of the element (and outside the plane shown in Figure 2A).

[0038] Similar to the gate 126, the field plate 140 may have a mushroom configuration or a T-top configuration, which is partially embedded and comprises a central embedded portion 144 and one or more wing portions extending laterally from the embedded portion 144. The central embedded portion 144 is located above the field plate opening 164 and is vertically separated from the barrier layer 118 by a distance d1 equal to the thickness of the first interlayer dielectric layer 121 within the region above the field plate opening 164.

[0039] In the embodiment shown in Figure 2A, the field plate 140 includes a source-side wing 146 extending laterally toward the source contact 122 and a drain-side wing 148 extending laterally toward the drain contact 124. The central embedded portion 144 of the field plate 140 may be spaced from the barrier layer 118 by a distance d1 of about 0.1 to about 0.3 microns, and its width L3 may be about 0.3 to about 0.6 microns.

[0040] The drain-side wing 148 of the field plate 140 has a multi-step structure, including a first stepped portion 148A adjacent to the central embedded portion 144.

[0041] The central embedded portion 144 of the field plate 140 is separated from the barrier layer 118 in an overall vertical direction by the surface dielectric layer 125. The first stepped portion 148A of the field plate 140 is separated from the barrier layer 118 by the surface dielectric layer 125 and the first interlayer dielectric layer 121. The source-side wing 146 and the second stepped portion 148B of the field plate 140 are separated from the barrier layer 118 by the surface dielectric layer 125, the first interlayer dielectric layer 121, and the second interlayer dielectric layer 123.

[0042] In some embodiments, the first stepped portion 148A is spaced a distance d2 from the barrier layer 118, and the second stepped portion 148B adjacent to the first stepped portion 148A is spaced a distance d3 greater than d2 from the barrier layer 118. The distance d2 may be about 0.15 microns to about 0.4 microns. The distances d3 and d4 may be about 0.25 microns to about 0.5 microns.

[0043] The width L4A of the first stepped section 148A is approximately 0.3 microns to approximately 0.6 microns, and the width L4B of the second stepped section 148B is approximately 0.3 microns to approximately 0.6 microns. The total width L4 of the drain-side wing 148 is approximately 0.6 microns to approximately 1.2 microns.

[0044] In the embodiment shown in Figure 2A, the distance d4 between the source-side wing 146 of the field plate 140 and the barrier layer 118 is equal to the sum of the thicknesses of the first interlayer dielectric layer 121, the second interlayer dielectric layer 123, and the surface dielectric layer 125.

[0045] The field plate 140 has a total width L1. The source-side wing 146 of the field plate 140 has a width L2, the embedded portion 144 of the field plate 140 has a width L3, and the drain-side wing 148 of the field plate 140 has a width L4. The field plate 140 is laterally spaced L5 away from the gate 126. By adjusting the distances d1 to d4 and the widths L1 to L5, several degrees of freedom are provided for modulating the gate-source capacitance and gate-drain capacitance of the element, as will be described below.

[0046] A passivation layer 132 is formed on the first interlayer dielectric layer 121, the second interlayer dielectric layer 123, and the field plate 140, and a field dielectric layer 134 is formed on the passivation layer 132. The passivation layer 132 may fill the gap between the field plate 140 and the gate 126 that is not filled by the first interlayer dielectric layer 121.

[0047] The surface dielectric layer 125, the first interlayer dielectric layer 121, the second interlayer dielectric layer 123, the passivation layer 132, and the field dielectric layer 134 may include one or more layers of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, or other atomic layer deposited films, or a multilayer insulating structure such as an oxide-nitride-oxide layer. In a particular embodiment, the surface dielectric layer 125, the first interlayer dielectric layer 121, and the second interlayer dielectric layer 123 contain silicon nitride, the passivation layer 132 contains silicon oxynitride, and the field dielectric layer 134 contains silicon nitride.

[0048] Figure 2B illustrates a high electron-mobility transistor element 100B according to yet another embodiment. Element 100B is similar to element 100A shown in Figure 2A, except that the second interlayer dielectric layer 123 is removed from the source side of the structure between the field plate 140 and the source contact 122, and as a result, the distance d4 between the source-side wing 146 and the barrier layer 118 is defined only by the thickness of the surface dielectric layer 125 and the first interlayer dielectric layer 121. Therefore, the distance d4 in element 100B may be from about 0.15 microns to about 0.4 microns.

[0049] Figure 2C illustrates a high electron mobility transistor element 100C according to yet another embodiment. Element 100C is similar to element 100A shown in Figure 2A, except that a third interlayer dielectric layer 147 is provided on the drain side of the structure on the second interlayer dielectric layer between the field plate 140 and the drain contact 124, and as a result the field plate has a third stepped portion 148C adjacent to the second stepped portion 148B. The third stepped portion 148A is at a distance d5 from the barrier layer 118, which is greater than d3. The third stepped portion 148C is spaced away from the barrier layer 118 by the combined thickness of the surface dielectric layer 125, the first interlayer dielectric layer 121, the second interlayer dielectric layer 123, and the third interlayer dielectric layer 147. It is understood that the field plate 140 may have more than three stepped portions by providing an additional interlayer dielectric layer on the drain side of the structure.

[0050] Figure 3A shows a HEMT transistor element structure 200A according to yet another embodiment. Element 200 is similar to element 100A shown in Figure 2A, with the same numbering referring to the same elements, except that element 200 does not include the source wing 146. That is, the distance between the embedded portion 144 of the field plate 140 and the gate 126 defines the distance L5 between the field plate 140 and the gate 126, and the width L2 of the source wing 146 is zero.

[0051] In some embodiments, the distance d1 between the embedded portion 144 of the field plate 140 and the barrier layer 118 is approximately 60 nm to approximately 300 nm, and in some embodiments, it is between approximately 100 nm and 200 nm. As described herein, embedding a portion of the field plate 140 can reduce the gate-drain capacitance Cgd, which can improve the efficiency, linearity, gain, and / or bandwidth of amplifiers fabricated using this device. Furthermore, by using an etching process to form a field plate opening 164 in the surface dielectric layer 125 that defines the position of the embedded portion 144 of the field plate 140, precise control over the position of the embedded portion 144 is possible, thereby improving the process repeatability and manufacturability of the device while also providing more precise control over the electrical characteristics of the device.

[0052] The overall width of the field plate 140 (L1 in Figures 2A and 3A) may be approximately 0.6 to 1.5 microns.

[0053] Figure 3B illustrates a high electron mobility transistor element 200B according to yet another embodiment. Element 200B is similar to element 200A shown in Figure 3A, except that a third interlayer dielectric layer 147 is provided on the drain side of the structure on the second interlayer dielectric layer 123 between the field plate 140 and the drain contact 124, and as a result the field plate has a third stepped portion 148C. The third stepped portion 148C is spaced apart from the barrier layer 118 by the combined thickness of the surface dielectric layer 125, the first interlayer dielectric layer 121, the second interlayer dielectric layer 123, and the third interlayer dielectric layer 147.

[0054] Isolating the field plate 140 laterally from the gate 126 (for example, by not overlapping the field plate 140 and the gate 126) can reduce the gate-drain capacitance Cgd and / or drain-source capacitance Cds of the device by improving the field plate 140's ability to block the gate-to-drain feedback capacitance. In other words, overlapping the field plate 140 and the gate 126 can result in additional parasitic capacitance without any additional benefit.

[0055] Providing the recessed portion 144 of the field plate 140 changes the drain-source capacitance Cds and gate-drain capacitance Cgd of the element. In particular, providing the recessed portion 144 of the field plate 140 can reduce the gate-drain capacitance Cgd of the element for a certain level of drain voltage, sometimes at the expense of increasing the drain-source capacitance Cds at low drain voltages.

[0056] It is thought that laterally separating the field plate 140 from the gate 126 can improve the drain-source capacitance Cds while compromising the effect of the field plate 140 on the gate-drain capacitance Cgd. Therefore, the distance of the gap L5 between the field plate 140 and the gate 126 (as shown in Figures 2A and 3A) can be selected to reduce the gate-drain capacitance Cgd without adversely affecting the drain-source capacitance Cds. For example, in some embodiments, the gap L5 between the field plate 140 and the gate 126 may be between 0.2 microns and 0.7 microns. If the gap is less than 0.2 microns, reliability issues may arise, and if the gap exceeds 0.7 microns, the gate-drain capacitance Cgd may become undesirably high. In some embodiments, the gap L5 may be between approximately 0.2 microns and approximately 0.4 microns.

[0057] In some embodiments, the gate opening 162 and the field plate opening 164 may be formed to have chamfered or rounded edges. Chamfering or rounding the edges of the gate opening 162 and the field plate opening 164 results in shapes corresponding to the embedded contact portion 127 of the gate 126 and the embedded portion 144 of the field plate 140, which helps to reduce field crowding around the gate 126 and the field plate 140.

[0058] The widths L2 and L4 of the source wing 146 and drain wing 148 of the field plate 140 may also affect the gate-drain capacitance Cgd and / or drain-source capacitance Cds of the element. The lengths of the wings 146 and 148 may involve a trade-off between the gate-drain capacitance Cgd and the drain-source capacitance Cds. For example, the drain wing 148 may decrease the gate-drain capacitance Cgd but increase the drain-source capacitance Cds. In particular, as described above, the drain wing 148 may have a length L4 of about 0.6 to about 1.2 microns. The source wing 146 may have a length L2 between about zero and 0.3 microns (Figures 2A and 3A). In particular, the source wing 146 may have a length L2 of zero microns.

[0059] Furthermore, because of the reduced parasitic capacitance, the field plate 140 does not need to handle the same high levels of current and may therefore be formed to have a smaller thickness than would otherwise be required.

[0060] By providing the stepped drain-side wing 148, the off-state dielectric breakdown voltage of elements 100A, 100B, and 200 can be increased while keeping the gate-drain capacitance Cgd and gate-source capacitance Cgs low. This enables higher operating voltages, higher frequency operation, and / or higher power-added efficiency than can be achieved without such features.

[0061] In some embodiments, this element has an off-state current of 1 × 10⁻⁶ -3 At A / mm, the dielectric breakdown voltage in the off state can be greater than 230V. In some embodiments, this element has an off-state leakage current of 1 × 10⁻⁶ -3 At A / mm, the dielectric breakdown voltage in the off state can be greater than 250V. In some embodiments, this element has an off-state leakage current of 1 × 10⁻⁶ -3 In A / mm, the dielectric breakdown voltage in the off state can be made greater than 275V.

[0062] Compared to an element without the stepped drain wing 148, the addition of the stepped drain wing 148 may slightly increase the drain-source capacitance Cds, which may limit the operation of this element for higher frequency applications (e.g., above approximately 10 GHz). However, this increased Cds does not substantially impede the operation of the element at frequencies below approximately 10 GHz.

[0063] For example, Figure 4A is a graph of the simulated drain current (Id) as a function of drain voltage (Vd) for elements with and without multi-stage field plates (curve 402) and (curve 404). As shown in Figure 4A, the dielectric breakdown voltage of the element with multi-stage field plates is approximately 60V higher (at a drain current of 1mA / mm) than that of the element without multi-stage field plates.

[0064] Figure 4B shows a graph of the simulated drain-source capacitance (Cds) as a function of drain-source voltage (Vds) for elements with and without multi-stage field plates (curve 412 and curve 414). As shown in Figure 4B, the Cds of the elements with multi-stage field plates is slightly higher than that of the elements without multi-stage field plates for Vds lower than approximately 130V. As mentioned above, this may limit the performance of the elements in high-frequency applications, but the increased Cds does not substantially impede the operation of the elements at frequencies lower than approximately 10GHz.

[0065] Figures 5A to 5H are cross-sectional views illustrating the operation for manufacturing a transistor element including a field plate according to several embodiments.

[0066] Referring to Figure 5A, a substrate 112 is provided on which a channel layer 116 and a barrier layer 118 are formed. A preliminary surface dielectric layer 125' is formed on the barrier layer 118. A layer of photoresist 52 is formed on the preliminary surface dielectric layer 125' and patterned to form two holes 54 and 56 within it.

[0067] Referring to Figure 5B, the preliminary surface dielectric layer 125' is selectively etched through two holes 54, 56 using, for example, reactive ion etching or inductively coupled plasma, to form two corresponding holes 154, 156 inside.

[0068] Referring to Figure 5C, the sacrificial dielectric layer 165 is blanket-deposited on the preliminary surface dielectric layer 125' to fill the holes 154 and 156. The sacrificial dielectric layer 165 may be formed from the same material as the preliminary surface dielectric layer 125'. For example, both the sacrificial dielectric layer 165 and the preliminary surface dielectric layer 125' may be formed from silicon nitride.

[0069] Referring to Figure 5D, the sacrificial dielectric layer 165 is anisotropically etched using, for example, reactive ion etching or inductively coupled plasma 167 to remove portions of the sacrificial dielectric layer 165, except for the lateral portions 166 on the inner surface of the hole 154 of the preliminary surface dielectric layer 125' and the lateral portions 168 on the inner surface of the hole 156 of the preliminary surface dielectric layer 125', to form a gate opening 162 and a field plate opening 164 with rounded or chamfered edges, as shown in Figure 5E. Together with the lateral portions 166 and 168, the preliminary surface dielectric layer 125' forms the surface dielectric layer 125 on the barrier layer 118. With the lateral portions 166 present, the width of the gate opening 162 is approximately 250 nm.

[0070] Referring to Figure 5F, a metal such as gold is deposited and patterned on the surface dielectric layer 125 to form a mushroom gate or T-top gate 126. The embedded contact portion of the gate 126 extends through the gate opening 162 and contacts the barrier layer 118. Next, the first interlayer dielectric layer 121 is blanket-deposited on the surface dielectric layer 125 and the gate 126. The first interlayer dielectric layer 121 extends through the field plate opening 164 and contacts the barrier layer 118.

[0071] Referring to Figure 5G, the second interlayer dielectric layer is blanket-deposited on the first interlayer dielectric layer 121, masked, and then anisotropically etched, for example by timed etching, to form the second interlayer dielectric layer 123 on the drain region portion of the structure. In some embodiments, the first interlayer dielectric layer 121 and the second interlayer dielectric layer 123 may be formed of different materials, so that the first interlayer dielectric layer 121 can act as an etching stop layer for etching the second interlayer dielectric layer 123. As described above, in some embodiments, the second interlayer dielectric layer 123 can be excluded from the source side of the structure.

[0072] Next, a metal such as gold is deposited on the first interlayer dielectric layer 121 above the field plate opening 164 and patterned to form the field plate 140. The field plate extends at least partially onto the second interlayer dielectric layer 123, forming a number of stepped profiles on the drain side of the field plate 140.

[0073] The field plate 140 is separated from the barrier layer 118 within the field plate opening 164 by a distance d1 corresponding to the thickness of the first interlayer dielectric layer 121. In the drain-side wing 148 of the field plate 140, the field plate 140 may be separated from the barrier layer 118 by a distance d2 corresponding to the sum of the thicknesses of the first interlayer dielectric layer 121 and the surface dielectric layer 125 in the first stepped region 148A, and by a distance d3 corresponding to the sum of the thicknesses of the first interlayer dielectric layer 121, the second interlayer dielectric layer 123, and the surface dielectric layer 125 in the second stepped region 148B.

[0074] The field plate 140 is spaced laterally from the gate 126 by a distance L6 that is approximately equal to the thickness of the first interlayer dielectric layer 121. Therefore, the field plate 140 is automatically aligned with respect to the gate 126 by a distance L6.

[0075] Referring to Figure 5H, a passivation layer 132, such as a silicon dioxide layer, is formed on the field plate 140 and the first interlayer dielectric layer 121. Finally, a field dielectric layer 134, such as silicon nitride, is formed on the passivation layer 132.

[0076] Referring to Figure 5I, in some embodiments, after the formation of the second interlayer dielectric layer 123, the third dielectric layer may be blanket-deposited on the first interlayer dielectric layer 121 and the second interlayer dielectric layer 123, masked, and then anisotropically etched, for example by time-controlled etching, to form the third interlayer dielectric layer 127 on the drain region portion of the structure. In some embodiments, the third interlayer dielectric layer 147 can be excluded from the source side of the structure.

[0077] Next, a metal such as gold is deposited on the first interlayer dielectric layer 121 above the field plate opening 164 and patterned to form the field plate 140. The field plate extends at least partially over the second interlayer dielectric layer 123 and the third interlayer dielectric layer 147, forming a multi-stepped profile on the drain side of the field plate 140. It is understood that a similar operation may be performed to form a field plate with more than three steps.

[0078] Referring to Figure 5J, a passivation layer 132, such as a silicon dioxide layer, is formed on the field plate 140 and the first interlayer dielectric layer 121. Finally, a field dielectric layer 134, such as silicon nitride, is formed on the passivation layer 132.

[0079] Figure 6 is a block diagram illustrating the operation of forming a transistor element according to several embodiments. Referring to Figures 6 and 5A to 5H, a method for forming a transistor element according to several embodiments includes the steps of forming a surface dielectric layer 125 on a semiconductor layer (block 602), forming an opening 164 within the surface dielectric layer (block 604), forming a gate 126 on the surface dielectric layer 125, the gate being laterally spaced from the opening 164 (block 606), forming a first interlayer dielectric layer 121 on the gate and the surface dielectric layer 125, the surface dielectric layer extending into the opening 164 (block 608), and forming a multi-stepped field plate 140 on the first interlayer dielectric layer 121 above the opening 164 (block 610). The multi-stepped field plate 140 is laterally spaced from the gate. The embedded portion 144 of the multi-step field plate 149 is located above the opening 164 in the surface dielectric layer, and the multi-step field plate 1140 includes a first stepped portion 148A adjacent to the embedded portion of the multi-step field plate 140 on the side of the multi-step field plate opposite the gate 126, and a second stepped portion 148B adjacent to the first stepped portion 148A.

[0080] The embedded portion 144 of the multi-step field plate is vertically separated from the barrier layer 118 by a first distance, the first stepped portion 148A is vertically separated from the barrier layer 118 by a second distance, and the second stepped portion 148B is vertically separated from the barrier layer 118 by a third distance. The second distance is greater than the first distance, and the third distance is greater than the second distance.

[0081] The method further includes the step of forming a second opening 162 in a surface dielectric layer, wherein the first and second openings 164, 162 are spaced laterally apart from each other. A gate 126 is formed on the second opening 162, and the gate 126 includes an embedded contact portion 127 that passes through the second opening 162. The embedded contact portion 127 of the gate may be in contact with a barrier layer 118.

[0082] The method may further include the step of forming source contacts and drain contacts 122, 124 on a barrier layer 118, wherein the gate 126 is located between the source contacts and drain contacts 122, 124. The field plate 140 may include a recessed portion 144 above the opening 164 and a drain-side wing 148 extending over the barrier layer 118 toward the drain contact 124. In some embodiments, the field plate 140 includes a source-side wing 146 extending over the barrier layer 118 toward the source contact 122.

[0083] The embedded portion 144 of the field plate 140 may be spaced perpendicularly from the barrier layer 118 by the thickness of the first interlayer dielectric layer 121.

[0084] The drain-side wing 148 of the field plate may include a first stepped portion 148A that is spaced perpendicularly from the barrier layer 118 by the combined thickness of the first interlayer dielectric layer 121 and the surface dielectric layer 125, and a second stepped portion 148B that is spaced perpendicularly from the barrier layer 118 by the combined thickness of the first interlayer dielectric layer 121, the second interlayer dielectric layer 123, and the surface dielectric layer 125.

[0085] The steps for forming the first and second openings may include: forming a preliminary surface dielectric layer 125' on the barrier layer 118; selectively etching the preliminary surface dielectric layer 125' to form the first and second holes 156 and 154 within the preliminary surface dielectric layer 125'; and depositing a sacrificial dielectric layer 165 on the barrier layer 118 and the preliminary surface dielectric layer 125', wherein the sacrificial dielectric layer 165 fills the first and second holes 156 and 154. The sacrificial dielectric layer 165 may be subjected to anisotropic etching to expose portions of the barrier layer 118 within the first and second holes 156 and 154, while leaving the lateral portions of the sacrificial dielectric layer 165 on the inner sidewalls of the holes 156 and 154.

[0086] The transistor elements described herein can be used in amplifiers operating in a wide variety of different frequency bands. In some embodiments, an RF transistor amplifier incorporating such transistor elements can be configured to operate at frequencies above 1 GHz. In other embodiments, the RF transistor amplifier can be configured to operate at frequencies above 2.5 GHz. In yet another embodiment, the RF transistor amplifier can be configured to operate at frequencies above 3.1 GHz. In yet another embodiment, the RF transistor amplifier can be configured to operate at frequencies above 5 GHz. In some embodiments, the RF transistor amplifier can be configured to operate in at least one of the frequency bands of 2.5–2.7 GHz, 3.4–4.2 GHz, 5.1–5.8 GHz, 12–18 GHz, 18–27 GHz, 27–40 GHz, or 40–75 GHz, or sub-bands thereof.

[0087] While embodiments of the present invention have been discussed above in relation to HEMT devices, it will be understood that the inventive concepts described herein may be applied to other types of semiconductor devices such as MOSFETs, DMOS transistors, and / or laterally diffused MOS (LDMOS) transistors.

[0088] RF transistor amplifiers incorporating the transistor elements described herein can be used in standalone RF transistor amplifiers and / or multiple RF transistor amplifiers. Examples of how RF transistor amplifiers according to several embodiments can be used in applications involving multiple amplifiers are discussed with reference to Figures 7A-7C.

[0089] Referring to Figure 7A, the RF transistor amplifier 1000A is schematically illustrated, which includes a preamplifier 1010 and a main amplifier 1030 electrically connected in series. As shown in Figure 7A, the RF transistor amplifier 1000A includes an RF input 1001, a preamplifier 1010, an interstage impedance matching network 1020, a main amplifier 1030, and an RF output 1002. The interstage impedance matching network 1020 may include, for example, inductors and / or capacitors arranged in an optional, appropriate configuration to form a circuit that improves impedance matching between the output of the preamplifier 1010 and the input of the main amplifier 1030. Although not shown in Figure 7A, the RF transistor amplifier 1000A may further include an input matching network interposed between the RF input 1001 and the preamplifier 1010, and / or an output matching network interposed between the main amplifier 1030 and the RF output 1002. The RF transistor amplifier according to this embodiment may be used to implement either or both of the preamplifier 1010 and the main amplifier 1030.

[0090] Referring to Figure 7B, an RF transistor amplifier 1000B is schematically illustrated, which includes an RF input 1001, a pair of preamplifiers 1010-1 and 1010-2, a pair of interstage impedance matching networks 1020-1 and 1020-2, a pair of main amplifiers 1030-1 and 1030-2, and an RF output 1002. A splitter 1003 and a combiner 1004 are also provided. Preamplifier 1010-1 and main amplifier 1030-1 (which are electrically connected in series) are electrically connected in parallel with preamplifier 1010-2 and main amplifier 1030-2 (which are electrically connected in series). Similar to the RF transistor amplifier 1000A in Figure 9A, the RF transistor amplifier 1000B may further include an input matching network interposed between the RF input 1001 and preamplifiers 1010-1 and 1010-2, and / or an output matching network interposed between the main amplifiers 1030-1 and 1030-2 and the RF output 1002.

[0091] As shown in Figure 7C, RF transistor amplifiers according to some embodiments can also be used to implement Doherty amplifiers. As is known in the art, a Doherty amplifier circuit includes first and second (or higher) power-coupled amplifiers. The first amplifier is called the “main” amplifier or “carrier” amplifier, and the second amplifier is called the “peaking” amplifier. The biases of the two amplifiers may be different. For example, in one common Doherty amplifier implementation, the main amplifier may be a Class AB or Class B amplifier, while the peaking amplifier may be a Class C amplifier. Doherty amplifiers can operate more efficiently than balanced amplifiers when operating at power levels retreated from saturation. The RF signal input to the Doherty amplifier is split (e.g., using a quadrature coupler), and the outputs of the two amplifiers are coupled. The main amplifier is configured to turn on first (i.e., at a lower input power level), so that only the main amplifier operates at lower power levels. As the input power level increases towards saturation, the peaking amplifier is turned on, and the input RF signal is split between the main amplifier and the peaking amplifier.

[0092] As shown in Figure 7C, the Doherty RF transistor amplifier 1000C includes an RF input 1001, an input splitter 1003, a main amplifier 1040, a peaking amplifier 1050, an output combiner 1004, and an RF output 1002. The Doherty RF transistor amplifier 1000C includes a 90° transformer 1007 at the input of the peaking amplifier 1050 and a 90° transformer 1005 at the input of the main amplifier 1040, and may optionally include an input matching network and / or an output matching network (not shown). The main amplifier 1040 and / or the peaking amplifier 1050 can be implemented using any of the above-described RF transistor amplifiers according to the embodiment.

[0093] The RF transistor amplifiers according to the embodiments may be formed as discrete components or as part of a monolithic microwave integrated circuit (MMIC). An MMIC is an integrated circuit that operates on radio frequency and / or microwave frequency signals, in which all the circuits for a specific function are integrated on a single semiconductor chip. An example MMIC element is a transistor amplifier, including associated matching circuits, power supply networks, etc., all mounted on a common substrate. An MMIC transistor amplifier typically includes multiple unit cell HEMT transistors connected in parallel.

[0094] Many modifications are possible to the features of the above embodiment. Transistor structures having features that can be used in embodiments of the present invention are disclosed in the following generally assigned publications, the contents of which are fully incorporated herein by reference: U.S. Patent No. 6,849,882, Chavarkar et al., "Group-III Nitride Based High Electron Mobility Transistor (HEMT) With Barrier / Spacer Layer"; U.S. Patent No. 7,230,284, Parikh et al., "Insulating Gate AlGaN / GaN HEMT"; U.S. Patent No. 7,501,669, Parikh et al., "Wide Bandgap Transistor Devices With Field Plates"; U.S. Patent No. 7,126,426, Mishra et al., "Cascode Amplifier Structures Including Wide Bandgap Field Effect Transistor With Field Plates"; U.S. Patent No. 7,550,783, Wu et al., "Wide Bandgap HEMTs With Source Connected Field Plates"; U.S. Patent No. 7,573,078, Wu et al., "Wide Bandgap Transistors "With Multiple Field Plates"; U.S. Patent Application Publication No. 2005 / 0253167, Wu et al.; "Wide Bandgap Field Effect Transistors With Source Connected Field Plates"; U.S. Patent Application Publication No. 2006 / 0202272, Wu et al.; "Wide Bandgap Transistors With Gate-Source Field Plates"; U.S. Patent Application Publication No. 2008 / 0128752, Wu; "GaN Based HEMTs With Buried Field Plates"; U.S. Patent Application Publication No. 2010 / 0276698, Moore et al.; "Gate Electrodes For Millimeter-Wave Operation and Methods of Fabrication";U.S. Patent Application Publication No. 2012 / 0049973, Smith, Jr. et al., "High Power Gallium Nitride Field Effect Transistor Switches"; U.S. Patent Application Publication No. 2012 / 0194276, Fisher, "Low Noise Amplifiers Including Group III Nitride Based High Electron Mobility Transistors"; and U.S. Patent No. 9,847,411, Sriram et al., "Recessed field plate transistor structures."

[0095] While embodiments of the concept of the present invention have been described in considerable detail with reference to their specific configurations, other versions are also possible. The field plate and gate can also have many different shapes and can be connected to the source contacts in various ways. Therefore, the spirit and scope of the present invention should not be limited to the specific embodiments described above.

Claims

1. Semiconductor barrier layer, The surface dielectric layer on the semiconductor barrier layer, A gate on the surface dielectric layer, wherein the surface dielectric layer includes an opening spaced laterally apart from the gate, A first interlayer dielectric layer on the surface dielectric layer, wherein the first interlayer dielectric layer extends over the gate into the opening in the surface dielectric layer, The second interlayer dielectric layer on the first interlayer dielectric layer, A field plate on the first interlayer dielectric layer and the second interlayer dielectric layer, wherein the field plate is spaced laterally from the gate, the embedded portion of the field plate is above the opening in the surface dielectric layer, and the field plate includes a first step adjacent to the embedded portion of the field plate on the side of the field plate opposite to the gate, and a second step adjacent to the first step. Equipped with, The embedded portion of the field plate is separated vertically from the semiconductor barrier layer by a first distance, the first step is separated vertically from the semiconductor barrier layer by a second distance, the second step is separated vertically from the semiconductor barrier layer by a third distance, the second distance is greater than the first distance, and the third distance is greater than the second distance. A transistor element in which the height of the first step adjacent to the embedded portion of the field plate is defined by the thickness of the surface dielectric layer, and the height of the second step adjacent to the first step is defined by the thickness of the second interlayer dielectric layer.

2. The first distance is equal to the thickness of the first interlayer dielectric layer, The transistor element according to claim 1, wherein the second distance is equal to the sum of the thickness of the first interlayer dielectric layer and the thickness of the surface dielectric layer.

3. The transistor element according to claim 2, wherein the third distance is equal to the sum of the thickness of the first interlayer dielectric layer, the thickness of the surface dielectric layer, and the thickness of the second interlayer dielectric layer located on the first interlayer dielectric layer.

4. The transistor element according to claim 1, wherein the opening in the surface dielectric layer extends completely through the surface dielectric layer to expose the semiconductor barrier layer.

5. The transistor element according to claim 1, wherein the gate extends through the surface dielectric layer and contacts the semiconductor barrier layer.

6. The first distance is 0.1 to 0.3 microns. The second distance is 0.15 to 0.4 microns. The transistor element according to claim 1, wherein the third distance is 0.25 to 0.5 microns.

7. The width of the embedded portion of the field plate is 0.3 to 0.6 microns. The width of the first step is 0.3 to 0.6 microns. The transistor element according to claim 1, wherein the width of the second step is 0.3 to 0.6 microns.

8. The transistor element according to claim 1, wherein the first interlayer dielectric layer has a vertical thickness, and the field plate is spaced laterally from the gate by a distance substantially equal to the vertical thickness of the first interlayer dielectric layer.

9. The transistor element according to claim 1, further comprising a third step adjacent to the second step, wherein the third step is spaced vertically from the semiconductor barrier layer by a fourth distance greater than the third distance.

10. The steps include forming a surface dielectric layer on a semiconductor barrier layer, The steps include forming an opening in the surface dielectric layer in order to expose the semiconductor barrier layer, The steps include forming a gate on the surface dielectric layer, which is spaced laterally apart from the opening, A step of forming a first interlayer dielectric layer on the surface dielectric layer and the gate, wherein the first interlayer dielectric layer extends beyond the gate into the opening in the surface dielectric layer, The steps include forming a second interlayer dielectric layer on the first interlayer dielectric layer, A step of forming a multi-step field plate on the first interlayer dielectric layer and the second interlayer dielectric layer, wherein the multi-step field plate is spaced laterally apart from the gate, the embedded portion of the multi-step field plate is above the opening in the surface dielectric layer, and the multi-step field plate includes a first step adjacent to the embedded portion of the multi-step field plate and a second step adjacent to the first step on the side surface of the multi-step field plate opposite to the gate. Includes, The embedded portion of the multi-step field plate is spaced vertically from the semiconductor barrier layer by a first distance, the first step is spaced vertically from the semiconductor barrier layer by a second distance, the second step is spaced vertically from the semiconductor barrier layer by a third distance, the second distance is greater than the first distance, and the third distance is greater than the second distance, forming a transistor element. A method wherein the height of the first step adjacent to the embedded portion of the multi-step field plate is defined by the thickness of the surface dielectric layer, and the height of the second step adjacent to the first step is defined by the thickness of the second interlayer dielectric layer.

11. The method according to claim 10, wherein the first distance is equal to the thickness of the first interlayer dielectric layer.

12. The method according to claim 11, wherein the second distance is equal to the sum of the thickness of the first interlayer dielectric layer and the thickness of the surface dielectric layer.

13. The method according to claim 12, wherein the third distance is equal to the sum of the thickness of the first interlayer dielectric layer, the thickness of the surface dielectric layer, and the thickness of the second interlayer dielectric layer located on the first interlayer dielectric layer.

14. The method according to claim 10, wherein the opening in the surface dielectric layer extends completely through the surface dielectric layer to expose the semiconductor barrier layer.

15. The method according to claim 10, wherein the multi-step field plate further includes a third step adjacent to the second step, the third step being spaced perpendicularly from the semiconductor barrier layer by a fourth distance greater than the third distance.

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