Fail-safe power management to prevent short circuits from water damage in solid-state drives using conductivity detectors

Abstract

This invention provides a method and apparatus for detecting the presence of conductive liquid in a data storage device such as an M.2 solid-state device (SSD) and triggering a fail-safe mode. [Solution] The SSD includes a non-volatile memory (NVM) array and a data storage controller, wherein a linear resistance strip or other resistivity sensor is mounted adjacent to the NVM array and the data storage controller, and the conductivity detector uses the linear resistance strip to detect the presence of a conductive liquid, and a power management unit (PMU) activates a fail-safe processing mode in response to the detection of the conductive liquid. In fail-safe mode, power to the NVM array and the data storage controller is disabled to prevent corrosion and short circuits, and a signal is sent to the laptop or other host on which the SSD is installed, requesting the laptop to shut down.

Description

Technical Field

[0001] The subject matter described in this specification relates to data storage devices and controllers. More particularly, the subject matter relates, in some embodiments, to techniques for preventing short circuits in solid state data storage devices due to water damage.

[0002] (Introduction) Data storage devices (DSDs), such as solid-state devices (SSDs), can be damaged by water, potentially leading to short circuits, corrosion, and metal layer damage within the DSD. For example, water condensation within an SSD, including the NAND die or data storage controller, can cause these problems. More specifically, water condensation on a ball grid array (BGA) mounted on the printed circuit board (PCB) of a NAND-based SSD (e.g., for the NAND die or data storage controller) can lead to corrosion between the NAND die and its BGA pins, or between the data storage processor and its BGA pins. Similar problems can occur in other surface-mount packages (SMPs). This increases the risk of hardware damage and data loss. This can be a significant issue in internal M.2 SSDs installed as components in laptops. M.2 is a specification for internally mounted computer expansion cards and associated connectors. M.2 SSDs are Peripheral Component Interconnect Express (PCIe) native devices originally designed to be inserted into M.2 internal slots in laptops or desktop personal computers (PCs). Such laptops often have numerous vents for cooling and airflow around the laptop motherboard, processor, and circuitry, which can allow water or humid air into the internal M.2 SSD within the laptop, potentially leading to corrosion within the SSD.

[0003] In many cases, the data stored on an SSD is far more valuable to the user than the SSD itself. For example, a state-of-the-art SSD can store terabytes of data, including millions of project files, financial records, or other confidential and valuable data. Therefore, protecting SSDs from water damage is particularly important for protecting the stored data. Such protection is especially difficult with M.2 form factor SSDs due to their small size and thin profile. At least some aspects of this disclosure relate to mitigating the risk of water-related damage and data loss in such devices, or achieving other objectives. [Overview of the Initiative]

[0004] The following provides a simplified overview of certain aspects of the Disclosure to give a basic understanding of those aspects. This overview is not intended to be a comprehensive overview of all the features intended in the Disclosure, nor to identify key or important elements of all aspects of the Disclosure, nor to define the scope of any or all aspects of the Disclosure. Its sole purpose is to present a simplified version of various concepts of some aspects of the Disclosure as a prelude to more detailed explanations that will follow.

[0005] One aspect of the present disclosure provides a data storage device (DSD) comprising: a non-volatile memory (NVM) array mounted on a printed circuit board (PCB) using a first surface mount package (SMP); one or more processors mounted on the PCB using a second SMP and communicating with the NVM array; sensors mounted adjacent to one or both of the first and second SMPs; and detectors configured to use the sensors to detect a conductive liquid, wherein the one or more processors are configured individually or in combination to activate a failsafe processing mode in response to the detection of a conductive liquid.

[0006] Another aspect of the present disclosure provides a DSD comprising an NVM array mounted on a printed circuit board (PCB), a resistor strip mounted on the PCB, a conductivity detector coupled to the resistor strip, and one or more processors, the one or more processors being configured to individually or in combination to receive signals from the conductivity detector indicating whether the amount of metal ions in a liquid in contact with the resistor strip exceeds an impurity threshold, to deactivate the power supply of a data storage device in response to the amount of metal ions in the liquid exceeding the impurity threshold, and then to reactivate the power supply in response to the amount of metal ions in the liquid no longer exceeding the impurity threshold.

[0007] A further aspect of the present disclosure provides a data storage device comprising: means for detecting aqueous metal ions within the data storage device; means for determining whether the aqueous metal ions exceed an impurity threshold; means for deactivating the power supply of the data storage device in response to the aqueous metal ions exceeding an impurity threshold; and means for reactivating the power supply in response to the aqueous metal ions no longer exceeding an impurity threshold. [Brief explanation of the drawing]

[0008] [Figure 1] This schematic block diagram shows an exemplary data storage device (DSD) embodied as a solid-state device (SSD) comprising one or more resistance strip sensors and other components for detecting the presence of conductive liquid in the DSD using resistance strips, according to some aspects of the present disclosure. [Figure 2] Selected components of an exemplary M.2 SSD according to several aspects of this disclosure are shown. [Figure 3] The following illustrates the physical configuration of an exemplary M.2 SSD according to several aspects of this disclosure. [Figure 4]The present disclosure shows a NAND array die having a ball grid array (BGA) according to several aspects of this disclosure, and a resistor strip mounted adjacent to the BGA of the NAND die. [Figure 5A] This disclosure describes exemplary procedures that may be performed by an SSD to detect and respond to conductive liquid within the SSD, according to several aspects of this disclosure. [Figure 5B] This disclosure describes exemplary procedures that may be performed by an SSD to detect and respond to conductive liquid within the SSD, according to several aspects of this disclosure. [Figure 6] The present disclosure describes exemplary procedures that may be performed by an SSD to detect conductive liquid within the SSD, by converting an electrical resistance signal into a conductivity value for comparison against a conductivity threshold. [Figure 7] This is a schematic block diagram showing an exemplary data storage device configured according to some aspects of this disclosure. [Figure 8] This is a schematic block diagram showing another exemplary data storage device configured according to some aspects of the present disclosure. [Figure 9] This is a schematic block diagram showing yet another exemplary data storage device configured according to some aspects of the present disclosure. [Figure 10] This flowchart shows a method or procedure for use with DSD or SSD according to some aspects of this disclosure. [Modes for carrying out the invention]

[0009] The following detailed description will refer to the accompanying drawings, which form part of it. In addition to the exemplary aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by referring to the drawings and the following detailed description. Descriptions of elements in each figure may refer to elements in subsequent figures. Similar numbers may refer to similar elements in the figures, including alternative embodiments of similar elements.

[0010] The embodiments described herein relate to data storage devices (DSDs) and data storage controllers for DSDs. In the main embodiments described herein, data is stored in a non-volatile memory (NVM) array. A DSD having an NVM array may be called a solid-state device (SSD) or flash drive. Some SSDs use NAND memory, referred to herein as "NAND". NAND is a type of non-volatile storage technology that does not require power to hold data. It utilizes a negative logical conjunction, i.e., NAND logic. For brevity, an SSD having one or more NAND dies is used as a non-limiting example of a DSD in the description of various embodiments. In particular, a NAND SSD having an M.2 form factor is used as an example. It will be understood that at least some embodiments described herein may also be applicable to other forms of DSDs. For example, at least some embodiments described herein may be applicable to DSDs having a phase-change memory (PCM) array, a magneto-resistive random access memory (MRAM) array, and a resistive random access memory (ReRAM) array. In yet other embodiments, data may be stored in a hard disk drive (HDD).

[0011] overview As mentioned above, SSDs can be damaged by water, which can lead to short circuits, corrosion, and damage to the metal layers within the SSD. For example, water condensation in the ball grid array (BGA) of the printed circuit board (PCB) within an SSD can lead to corrosion between the NAND array die and its BGA pins, or between the data storage controller and its BGA pins, increasing the risk of hardware damage and resulting data loss. Similar problems can occur with other surface mount packages (SMPs). This is particularly problematic in internal M.2 SSDs used as components in laptops.

[0012] There are several relatively expensive techniques that attempt to protect PCBs from water damage, including conformal coatings, waterproofing layers, manual spraying, immersion processes, or the use of enclosed enclosures. These methods can have various drawbacks. For example, coatings and enclosures increase additional costs based on the PCB area requiring special materials, selective spraying, selective flow, protection, or vapor coating. Coatings on SSD components can be extremely difficult to remove, making them much harder to clean and repair in case of rework, which increases the manual costs of rework and reapplication of coatings. If all routing is coated, significant problems can arise when component issues require debugging. There are also environmental and safety regulations to consider regarding SSDs. Coating chemicals must be used only in accordance with local regulations. If an SSD is not considered safe to the environment, it may not be able to obtain the appropriate licenses for import / export or sale.

[0013] This specification provides a fail-safe power management mechanism for use with M.2 SSDs or other DSDs. In exemplary embodiments, the fail-safe mechanism includes an intelligent power management device (sometimes referred to as a "PMU IP" or simply a "PMU"), a programmable power relay, a linear resistance strip sensor, and a conductivity detector for detecting conductive liquid around one or more SMPs of the SSD. The PMU cuts off power to the NAND dies and data storage controller when conductive liquid is detected.

[0014] Not all liquids are conductive. Only these conductive liquids pose a significant risk of corrosion or short circuits within the SSD. Such liquids contain electrically conductive metal ions or other impurities. Therefore, conductivity detectors are configured to detect the presence of metal ions or other impurities in the liquid, thereby distinguishing non-conductive (and harmless) liquids from potentially harmful conductive liquids. In some embodiments, the fail-safe mechanism is activated only when a conductive liquid with sufficient conductivity to pose a significant risk of damage is detected. In other embodiments, the fail-safe mechanism may be activated when any amount of liquid is detected.

[0015] In some embodiments, the conductivity detector collects and analyzes various parameters to detect conductive liquid within the SSD and sends a signal to the PMU to turn off (or on) a programmable power relay that turns off (or on) power to specific modules such as the NAND array die and the data storage controller. In some embodiments, the procedure involves coordination and synchronization between the PMU and the data storage controller to send and receive requests and acknowledgments to / from the laptop (or other host) to give the PMU sufficient time to request a safe shutdown of the laptop by suspending the reception of data packets and sending an interrupt request (IRQ). Thereafter, this procedure protects the NAND array die and the data storage controller from damage or short circuits, and thereby also protects the data stored in the NAND array. The SSD may also be equipped with an internal lithium-ion battery to power a fail-safe mode circuit, which helps to re-enable power to the NAND and controller.

[0016] These and other features will be explained in more detail below.

[0017] Exemplary M.2 SSD and Failsafe Procedure Figure 1 is a schematic block diagram showing an exemplary DSD embodied as an SSD (e.g., M.2 SSD) according to several aspects of the present disclosure, including one or more resistance strip sensors, a conductivity detector, and a power management controller (PMU) configured to activate and control a failsafe mode in response to the detection of a conductive liquid (e.g., ionized water) in the SSD. System 100 includes a host 102 and an SSD 104 (or other DSD, but referred to herein as an SSD for simplicity) coupled to the host 102. The host 102 provides the SSD 104 with commands for transferring data between the host 102 and the SSD 104. For example, the host 102 may provide the SSD 104 with write commands to write data to the SSD 104, and may provide the SSD 104 with read commands to read data from the SSD 104. The host 102 may be any system or device requiring data storage or retrieval and may be a compatible interface for communicating with the SSD 104. For example, host 102 could be, in just a few examples, a computing device, a personal computer, a portable computer, a workstation, a server, a personal digital assistant, a digital camera, or a digital telephone. In the primary example herein, the host is a laptop with an SSD installed.

[0018] The SSD 104 includes a host interface 106, a data storage controller 108, a working memory 110 (such as dynamic random access memory (DRAM) or other volatile memory), a physical storage (PS) interface 112 (e.g., a flash interface module (FIM)), and a non - volatile memory (NVM) array 114 having one or more NAND dies for storing data. The host interface 106 is coupled to the data storage controller 108 to facilitate communication between the host 102 and the data storage controller 108. The data storage controller 108 is coupled to the working memory 110 and the NVM array 114 via the PS interface 112. The host interface 106 can be any suitable communication interface such as a Non - Volatile Memory express (NVMe) interface, a Universal Serial Bus (USB) interface, a Serial Peripheral (SP) interface, an ATA (Advanced Technology Attachment) or SATA (Serial Advanced Technology Attachment) interface, a Small Computer System Interface (SCSI), an IEEE 1394 (Firewire) interface, etc. In some embodiments, the host 102 includes the SSD 104. In other embodiments, the SSD 104 is remote from the host 102 or is included in a remote computing system communicatively coupled to the host 102. For example, the host 102 can communicate with the SSD 104 through a wireless communication link. The NVM array 114 can include a plurality of dies.

[0019] In the embodiment shown in FIG. 1, SSD 104 includes a single channel between data storage controller 108 and NVM array 114 via PS interface 112, but the subject matter described herein is not limited to having a single memory channel. For example, in some NAND memory system architectures, depending on the capabilities of the controller, two, four, eight, or more NAND channels couple the controller and the NAND memory devices. In any of the embodiments described herein, even if a single channel is shown in the drawings, two or more channels can be used between the controller and the memory die. Data storage controller 108 can be implemented within a single integrated circuit chip and can communicate with different layers of memory within NVM 114 via one or more command channels.

[0020] Data storage controller 108 controls the operation of SSD 104. In various aspects, data storage controller 108 receives commands from host 102 via host interface 106 and executes the commands to transfer data between host 102 and NVM array 114. Further, data storage controller 108 manages reads from and writes to working memory 110 to perform various functions affected by the controller, and can maintain and manage cached information stored in working memory 110.

[0021] The data storage controller 108 may include any type of processing device, such as a microprocessor, microcontroller, embedded controller, logic circuit, software, or firmware, for controlling the operation of the SSD 104. In some embodiments, some or all of the functions described herein as being performed by the data storage controller 108 may instead be performed by another element of the SSD 104. For example, the SSD 104 may include any type of processing device for performing one or more of the functions described herein as being performed by the data storage controller 108, such as a microprocessor, microcontroller, embedded controller, logic circuit, software, firmware, ASIC, or other processing device. In other embodiments, one or more of the functions described herein as being performed by the data storage controller 108 may instead be performed by the host 102. In even further embodiments, some or all of the functions described herein as being performed by the data storage controller 108 may instead be performed by another element, such as a controller in a hybrid drive that includes both non-volatile memory elements and magnetic storage elements.

[0022] The main power source for SSD104 is the host 102, which supplies power to SSD104 (via appropriate power connections (not shown)). A power relay 122 relays power from the host 102 to various components, such as the data storage controller 108 and the NVM array 114. SSD104 includes a power management controller (e.g., PMU) 113, which in this embodiment includes a conductive liquid detection controller 115 and a short-circuit fail-safe controller 116. The conductive liquid detection controller 115 is configured to receive signals from conductivity detectors 118 connected to one or more resistance strip sensors 120 (e.g., linear resistance strips). Based on the information provided by the conductivity detectors 118, the conductive liquid detection controller 115 detects the presence of conductive liquid in SSD104. (In some embodiments, the conductivity detectors 118 are configured to detect conductive liquid and notify the power management controller 113. In other embodiments, the power management controller 113 may also receive signals directly from the strip sensors 120.)

[0023] When conductive liquid is detected within the SSD, the short-circuit fail-safe controller 116 may cut off (or disable or deactivate) power from the host 102 to prevent a short circuit that may occur within the SSD 104. This can be achieved by controlling the power relay 122. If the main power is cut off, a backup Li-ion battery 124 can be used as a secondary power source to continue supplying sufficient power, thereby allowing at least some components of the device (e.g., the power management controller 113 and the conductivity detector 118) to continue operating to detect subsequent liquid drying so that the main power can be reactivated. For example, the detector may be configured to detect the amount of conductive liquid that decreases below a threshold indicating sufficient drying. In some embodiments, the power management controller 113 and the conductivity detector 118 can be implemented using any combination of hardware, software, and firmware (e.g., the implementation options described above for the SSD controller 108).

[0024] The resistive strip sensor 120 is shown in block diagram form in Figure 1, but it should be understood that these components may be placed directly adjacent to certain hardware components of the SSD 104, such as the data storage controller 108 and the NVM array 114. Although not shown in Figure 1, the data storage controller 108 and the NVM array 114 may be mounted on the PCB via a BGA (or other SMP), and the resistive strips are placed adjacent to these BGAs to detect liquids on or near the BGAs that could cause corrosion and / or short circuits. Also note that in some embodiments, the power management controller 113 is shown connected to the host interface 106, so that if conductive liquid is detected inside the SSD 104, the power management controller 113 sends a signal to the host 102 requesting the laptop to shut down (the laptop may then shut down, for example, until the liquid dries).

[0025] The working memory 110 can be any suitable memory, computing device, or system capable of storing data. For example, the working memory 110 may be ordinary RAM, DRAM, double data rate (DDR) RAM, static RAM (SRAM), synchronous dynamic RAM (SDRAM), flash storage, erasable programmable read-only memory (EPROM), electrically erasable programmable (EEPROM), etc. In various embodiments, the controller 108 uses the working memory 110 or a portion thereof to store data during data transfer between the host 102 and the NVM array 114. For example, the working memory 110 or a portion of the volatile memory 110 may be cache memory. The NVM array 114 receives data from the controller 108 via the PS interface 112 and stores that data. In some embodiments, the working memory 110 may be replaced by non-volatile memory such as MRAM, PCM, or ReRAM to act as working memory for the entire device.

[0026] The NVM array 114 may be implemented using NAND flash memory. In one embodiment, the NVM array 114 may be implemented using any combination of NAND flash, PCM array, MRAM array, and / or ReRAM. In one embodiment, six NAND flash chips are provided. The PS interface 112 provides an interface to the NVM array 114. For example, when the NVM array 114 is implemented using NAND flash memory, the PS interface 112 may be a flash interface module. In one embodiment, the PS interface 112 may be implemented as a component of the SSD controller 108.

[0027] Although not shown in Figure 1, in some embodiments, a temperature sensor is provided within the SSD 104 to enable temperature compensation for conductivity measurements performed by the conductivity detector 118. The temperature sensor is shown in Figure 7 and is described below.

[0028] Figure 1 shows an exemplary SSD used as an exemplary embodiment throughout this description, but the various embodiments disclosed are not necessarily limited to SSD applications / implementations. For example, the disclosed NVM array and associated processing components may be implemented as part of a package including other processing circuits and / or components. For example, a processor may include an embedded NVM array and associated circuits, or be otherwise coupled with them. In one embodiment, the processor may offload certain operations to the NVM array and associated circuits and / or components. In another embodiment, the SSD controller 108 may be a controller in another type of device, which may still be configured to perform some or all of the other functions described herein.

[0029] Figure 2 shows selected components of an exemplary M.2 SSD200 configured to communicate with an M.2 connector 202 (which may be a component of the laptop in which the SSD200 is installed), and communication utilizes PCIe and NVMe via a Peripheral Component Interconnect Express (PCIe) NVMe interface (I / F) bus 204. As shown, the SSD200 includes a conductivity detector 206 and a resistive linear strip 208. An intelligent PMU 210 is provided, which may correspond to the power management controller 113 in Figure 1. The SSD200 also includes a controller power supply 211 (which can receive power from the host), a programmable relay 212, and a controller and NAND switch 214. Furthermore, the SSD200 includes a NAND 216 (which may correspond to the NVM array 114 in Figure 1) and a storage controller (which may correspond to the data storage controller 108 in Figure 1). The components of the SSD200 are interconnected using various buses shown in the figure but not individually numbered. Furthermore, it should be noted that in some embodiments, the conductivity detector 206 is directly connected to the resistive linear strip 208 to receive voltage signals directly from the resistive linear strip 208. Although the resistive linear strip 208 is shown in block diagram form in Figure 2, it should be understood that the resistive linear strip 208 may be placed directly adjacent to certain hardware components of the SSD 200, such as the NAND 216 and the storage controller 218.

[0030] In this configuration, the conductivity detector 206 uses a resistive linear strip 208 to detect conductive liquid in the SSD 200 and sends a signal to the PMU 210, which can then cut off power (from the power supply 211) and / or control power supply to selected components such as the NAND 216 and the storage controller 218. If power is cut off, the PMU 210 sends a signal to the programmable relay 212 to turn off power to the specific module, such as the NAND 216 and the storage controller 218. The PMU 210 can also send and receive requests and acknowledgments to / from the host via the connector 202 to pause the reception of data packets and provide sufficient time to request a safe shutdown of the host (laptop) by sending an IRQ. In this way, the NAND 216 and the data storage controller 218 can be protected from serious damage or short circuits, which also protects the data stored in the NAND. As shown in Figure 1, the SSD may be equipped with an internal Li-ion battery to power various components such as the PMU 210 and conductivity detector 206, and to re-enable power supply to the NAND and controller once the SSD has dried out again. A temperature sensor may also be provided to enable temperature compensation for conductivity measurement.

[0031] In some embodiments, power may be deactivated for the NAND 216 and storage controller 218 if an active signal is received by the PMU 210 from the resistor strip 208, signaling a voltage above a programmable threshold voltage to indicate the presence of a liquid (e.g., water present near the BGA pins of the NAND 216 and storage controller 218). In some embodiments, the PMU 210 also receives a signal from the conductivity detector 206 indicating the presence (or absence) of metal ions in the liquid. Power is deactivated only if the liquid has high levels of ions (impurities) that pose a significant risk of short circuit. For example, the signal from the conductivity detector 206 may be compared to an appropriate conductivity threshold.

[0032] In some embodiments, the PMU210 operates to turn off the NAND216, enable fail-safe power management procedures, enter critical or fail-safe mode, and then wait for water to dry near the BGA pins. In some embodiments, the PMU210 is always active (along with conductivity detector 206 and resistor strip 208) to make real-time decisions. Continuous voltage changes and measurements can be recorded using analog-to-digital conversion (ADC) values ​​synchronized with the PMU210.

[0033] Figure 3 shows an M.2 SSD 300 with selected components. The SSD 300 includes a NAND chip 302 (or NVM array), a conductivity detector 304, a Li-ion battery 306, a programmable relay 308, a data storage controller 310, other electrical components 312, and a connector 314. A first resistive linear strip 3161 extends along the first edge of the SSD from the distal end (near the NAND 302) to the proximal end (near the data storage controller 310). The resistive linear strip 3161 approaches and passes along a portion of the data storage controller 310 to detect moisture in its vicinity. The resistive linear strip 3161 is also coupled to the conductivity detector 304, which inputs and processes the signal received from the resistive strip to detect water and evaluate impurities. A second resistive linear strip 3162 extends along the opposing second edge side of the SSD, approaches and passes along a portion of the NAND 302 to detect moisture in its vicinity. A third resistive linear strip 3163 is coupled between strips 3161 and 3162 and extends along the side of the NAND 302 to detect any moisture along that side of the NAND. By being coupled to both strips 3161 and 3162, strip 3163 allows a signal to be conducted from strip 3162 through strip 3161 to the conductivity detector 304. A fourth resistive linear strip 3164 is coupled between strips 3161 and 3162 and extends along the side of the data storage controller 310 to detect any moisture along that side of the data storage controller. A fifth resistive linear strip 3165 is coupled to strip 3162 and extends along another side of the data storage controller 310 to detect any moisture along that side of the data storage controller.

[0034] In other embodiments, more or fewer strips may be provided. Note that in the embodiment of Figure 3, there is unused space 318 in the center of the SSD to accommodate additional NAND chips (thus the SSD may provide additional memory; for example, two additional NAND chips could be placed in the available space). To enable the detection of moisture in the vicinity of these additional NAND chips, an additional strip passing along the additional NAND chips may be provided.

[0035] Figure 4 shows a partial side view of SSD400, illustrating the positioning of resistor strips adjacent to the BGA of the NAND array die. In short, SSD400 includes a NAND array die 402 mounted on PCB404 via a BGA consisting of solder balls 406. A first resistor strip 408 is mounted on PCB404 adjacent to a first side of the NAND array die 402 and senses moisture near the BGA along that side of the NAND array die. A second resistor strip 410 is mounted on PCB404 adjacent to a second, opposite side of the NAND array die 402 and senses moisture near the BGA along that side of the NAND array die. More or fewer strips may be provided. For example, additional strips can be provided along the other two sides of a square NAND array die, although these are not shown. It should also be noted that if moisture enters the BGA through the chip, at least some of that moisture will be along the side edges of the chip and therefore detectable by the resistor strips adjacent to the chip. Therefore, often only one strip adjacent to the chip is sufficient. Using more strips can provide more complete moisture detection.

[0036] Figures 5A and 5B provide flowcharts illustrating an exemplary procedure 500 that can be performed by a properly equipped SSD, such as the M.2 SSD shown in Figure 1 or Figure 2. Beginning with the M.2 socket stage 502, the M.2 SSD determines whether it is connected to a socket in a host device, such as a laptop computer, and if so, in 504, the SSD detects whether power is being supplied by the host device. If power is not detected, the process does not proceed, as there is not enough power supply to operate the data storage controller and NAND array die, as indicated by block 506. (Note that the power referred to here is the power provided by the host, and not the power provided by an additional Li-ion battery in the SSD to power some SSD components during failsafe mode.)

[0037] Assuming power is detected in block 504, in 508 the fail-safe intelligent PMU (e.g., PMU 210 in Figure 2) is initialized, and in block 510 a power signal is sent (e.g., from PMU 210 to power controller 211 in Figure 2) to control the power supply to the data storage controller (e.g., controller 218 in Figure 2). The data storage controller is initialized in 512, which also triggers activation to the NAND chip (e.g., NAND 216 in Figure 2) via a NAND detection procedure in 514. The NAND detection verifies and activates the NAND. Connectivity with the laptop is established in 516, and laptop-SSD data transfer may be performed in 518.

[0038] Simultaneously, following the initialization of the PMU in block 508, power is supplied to the conductivity detector / sensor by the PMU in 520, and the conductivity and linear resistance sensor components are initialized in 522 (for example, detector 206 in Figure 2 is initialized). In 524, the values ​​from the conductivity detector / sensor are read by the PMU. If no metal ions are detected (or no moisture is detected at all) in block 526, safe operation is permitted as indicated by block 528. If metal ions are present in the detected moisture, the failsafe mode is activated in block 530. Note that following block 508, the PMU also enables the Li-ion power supply in block 532 to enable the operation of the PMU and conductivity detector / sensor during failsafe mode. Note that blocks 520-528 may be performed before blocks 510-518 to ensure the safe operation of the data storage controller and NAND chip. In other words, the PMU operates to verify that there is no conductive liquid before power is applied to the data storage controller and NAND chip.

[0039] If failsafe mode is activated in block 530, the PMU determines in block 534 whether data is currently being transferred to / from the host. If data is being transferred, the transfer is interrupted in block 536. It is then safe to send an IRQ to shut down the laptop. The IRQ is sent to the laptop in block 538 to request a laptop shutdown. The laptop shutdown is requested because if moisture is detected in the M.2 SSD inside the laptop, other components of the laptop may also have moisture, thus ensuring a complete laptop shutdown. When the laptop shuts itself down, the power supply from the laptop to the SSD is disabled, as detected in block 540. If power has not yet been disabled, the IRQ shutdown request is resent to the laptop in block 542. Finally, in block 544, power is disabled and the laptop shutdown is complete. In block 546, a signal is sent to a program relay (e.g., relay 212 in Figure 2) to turn off power to the data storage controller and NAND. Next, in block 548, power to the data storage controller and NAND is disabled. Note that although power from the laptop has already been disabled (as detected in block 540), it is still worthwhile to control relay 212 to disable power to the data storage controller and NAND again. This is done to prevent the power from being routed to the data storage controller and NAND if the laptop starts supplying power to the SSD again during failsafe mode, thus preventing damage to those devices.

[0040] Failsafe mode continues to run in block 550. During failsafe mode, the PMU and conductivity / resistivity detectors / sensors continue to run in block 554 using power from the Li-ion battery to collect data to determine whether moisture containing metal ions is still present. That is, the conductivity detector continues to run during failsafe mode. Assuming that liquid containing metal ions is still detected, as determined in block 556, the PMU continues to wait in block 558 for the PCB to dry. Once the PCB is dry, it is safe to restart the SSD in 560. Power to the data storage controller and NAND is re-enabled in block 562. Failsafe mode is disabled in block 564. Processing returns to 504, and normal operation resumes.

[0041] Conductivity evaluation procedure As described above, the conductivity detector (e.g., detector 304 in Figure 3) is connected to at least one resistance strip (e.g., strip 316 in Figure 3) and configured to detect conductive liquids. In some embodiments, the conductivity detector may also identify the presence of aqueous metal ions in acids, bases, and salts. For this purpose, the conductivity detector adjusts the timing and sequence of measurements as the resistivity changes within or around the resistance strip. The conductivity detector may also include a built-in data filter to remove noise from the raw ADC data to ensure more accurate measurements. Note that metal ions are sometimes referred to as impurities.

[0042] In an exemplary procedure, the resistance value (R) is received from a resistance strip by a conductivity detector. The resistivity value (ρ) is calculated from the resistance value (R). Then, the conductivity value (σ) is calculated from the resistivity value (ρ). The conductivity value (σ) is compared to one or more conductivity thresholds to detect the presence of metal ions or other impurities. More specifically, in some embodiments, the conductivity value is processed to identify ions from salts (e.g., sodium chloride), acids (e.g., hydrochloric acid), and bases (e.g., sodium hydroxide). If the value exceeds a threshold, a metal ion is detected, and the fail-safe mode is activated. Otherwise, normal operation is performed (i.e., the SSD remains operational). It should be noted that many aqueous solutions are not conductive. For example, non-electrolyte solutions such as sugar or ethanol do not conduct electricity because they lack sufficient ions. Therefore, in some embodiments, the fail-safe mode is not activated simply upon detection of any liquid. It is activated upon detection of potentially harmful levels of metal ions that could cause corrosion, short circuits, or other problems. (In other embodiments, as already stated, the fail-safe can be activated upon detection of any water, regardless of the level of ions in the water.)

[0043] In some embodiments, the following impurities can be analyzed.

[0044] [ka]

[0045] The detection procedure may be programmed to allow the conductivity detector to automatically compensate for temperature fluctuations by adjusting either the conductivity value or a threshold. A verification procedure may be performed following the manufacture of the test SSD to verify that the SSD's sensor is properly calibrated to detect metal ions. The threshold or temperature compensation parameter may be adjusted as needed.

[0046] Here, the conductivity treatment may include the following processes and features. - Power Supply: The intelligent PMU activates when the SSD is connected to the laptop, supplying power to the resistance strip and conductivity detector, ensuring the system is ready for measurement. - Continuous measurement: The conductivity detector continuously monitors the change in resistance of the resistance strip and detects fluctuations due to the presence of ions in the liquid detected near the BGA and near the passive components. - ADC value conversion: The analog values ​​of the resistance strip are converted to digital values ​​using the built-in ADC in the conductivity detector for further processing. - Noise filtering: The conductivity detector employs digital signal processing (DSP) technology to remove noise from raw ADC data, ensuring more accurate resistance and conductance measurements. - Calculation of conductivity: The conductivity detector determines the conductivity (σ) of the liquid in the SSD using the formula σ = 1 / ρ. The resistivity (ρ) is given by the formula ρ = R * It is calculated using A / L, where R is the resistance, A is the cross-sectional area of ​​the resistance strip, and L is its length. This procedure takes advantage of the precise geometric calibration of the resistance strip and cell constants performed during SSD design and manufacturing. -Temperature compensation: Since the conductivity of a liquid increases with temperature, a temperature coefficient constant is used for accurate conductivity readings. Adjusted conductivity = (σ / (1+tc * (Temperature -25.0))). In the formula, tc = temperature coefficient constant / °C, Temperature = Value read from the onboard temperature sensor. - Ion Analysis: Conductivity detectors analyze conductivity values ​​to identify the presence of specific ions from salts, acids, and bases. This is achieved by comparing the measured values ​​with pre-programmed (built-in) thresholds stored in the conductivity detector's memory, enabling the detection of substances such as sodium chloride, hydrochloric acid, acetic acid, and sodium hydroxide. - Threshold comparison: The conductivity value is compared to a predetermined threshold stored in the conductivity detector's memory. The comparison determines whether the solution is sufficiently conductive to pose a risk to SSD operation. - The results of conductivity measurement and ion analysis are stored in the NVM of the conductivity detector for further processing. The sensor then sends a control signal to the PMU, which activates a programmable relay to disable power to the NAND array die and data storage controller, ensuring that the SSD operates safely once liquid is detected.

[0047] As far as cell constants are concerned, the cell constant K (known as conductivity probe or electrode) refers to the ratio of the distance between two conductive plates to their surface area. The constant is calculated for different liquids during a calibration procedure performed during product design and then stored in SSD memory for use by conductivity detectors. The cell constant is expressed in units per centimeter (e.g., 1 / cm), where the value represents the ratio of the distance (d) between electrode plates to the surface area (A) of the plates. The cell constant can be measured as follows: 1. Conductivity probes are calibrated with standard solutions having known conductivity values. 2. The distance (d) and surface area (A) between the probes are measured using the formula K = d / A. 3. The measured values ​​are stored in SSD memory for use by the conductivity detector.

[0048] Figure 6 illustrates some of these features. In block 602, the conductivity detector senses an analog resistance value (R) using a linear resistance strip, converts the analog value to a digital value using an ADC, and smooths the digital value using a DSP noise processing filter. In block 604, the conductivity detector calculates or determines the resistivity value (ρ) from the resistance value (R) based on the cross-sectional area (A) and length (L) of the resistance strip, as described above. In block 606, the conductivity detector calculates or determines the conductivity value (σ) from the resistivity value (ρ), as described above. In block 608, the conductivity detector adjusts the conductivity value (σ) to compensate for temperature using the temperature and temperature coefficient measured by the SSD, as described above. In block 610, the conductivity detector detects metal ions by comparing the temperature-adjusted conductivity value (σ) with one or more conductivity thresholds, and in some embodiments, identifies specific metal ions. (The conductivity threshold may also be called the impurity threshold.) In block 612, the conductivity detector sends a signal to the PMU to activate failsafe mode if the temperature-controlled conductivity value (σ) exceeds at least one of the thresholds. Note that in some embodiments, a single threshold is used, and failsafe mode is activated if the conductivity value exceeds that threshold. In other embodiments, multiple thresholds may be defined so that the sensor can distinguish between different types of metal ions, as described above. The detected metal ion types can be stored in memory.

[0049] The specific threshold programmed into the SSD conductivity detector can be determined during SSD design, for example, by applying a liquid containing a known amount of metal ions to a resistance strip within the test device and the BGA of the test device, and evaluating the amount of corrosion or short circuit while also reading the corresponding measured conductivity value. The threshold can then be set based on the measured conductivity value to trigger a fail-safe mode and avoid any significant risk of corrosion or short circuit. The calibration procedure can also be performed by applying known amounts of different types of metal ions (bases, acids, etc.) to establish different thresholds for different metal ions, and it should be noted that this allows the device to identify different types of metal ions, if desired. It should also be noted that conductivity is expressed in siemens per meter (S / m), while resistivity, the reciprocal of conductivity, is expressed in ohms per meter (Ω·m).

[0050] Table I provides exemplary conductivity and resistivity values ​​for various fluids that can be used to set thresholds for detecting and identifying various metal ions. For example, pairs of thresholds can be programmed into the conductivity detector of the SSD, with each pair of thresholds grouping the corresponding conductivity values ​​in the table so that the conductivity detector can detect and identify a particular fluid. For example, the threshold for the first pair may be set to bracket σ = 0.0000055 S / m, and as a result, ultrapure water (non-corrosive and therefore not triggering fail-safe mode) is detected if the measured conductivity falls between the thresholds of the first pair. In one particular embodiment, the listed conductivity values ​​may be grouped using thresholds set to +10% and -10% (or +20% and -20%, etc.) of the listed values. For fluids where a range of values ​​is listed in the table, the lower threshold may be set below the lower conductivity value, and the upper threshold may be set above the upper conductivity value. If there may be some overlap between the thresholds for different fluids, the detector may not be able to distinguish between the different fluids, but it still determines whether the conductivity level is sufficient to trigger fail-safe mode.

[0051] [Table 1]

[0052] Entire data storage device Figure 7 shows one embodiment of an exemplary device 700 configured according to one or more aspects of the present disclosure. The device 700 or its components may be embodied or implemented in an M.2 SSD having one or more temperature sensors 750, one or more resistive linear strips 752, and a NAND die 701 or other type of NVM array supporting data storage. In various implementations, the device 700 or its components may be components of a processor, controller, computing device, personal (laptop) computer, portable device, workstation, server, personal digital assistant, digital camera, digital telephone, entertainment device, medical device, autonomous vehicle control device, edge device, or any other electronic device that stores, processes, or uses data. In particular, the device may be an M.2 SSD installed in a laptop computer.

[0053] The device 700 includes a communication interface 702 and is coupled to an NVM 701 (e.g., a NAND die). The NVM 701 includes a physical memory array 704. The communication interface 702 is further coupled to one or more temperature sensors 750 and one or more resistive linear strips 752. These components may be coupled to each other and / or arranged to communicate with each other via appropriate components, generally represented by the connection lines in Figure 7. Although not shown, other circuits such as timing sources, peripherals, voltage regulators, and power management circuits may be provided and will not be described further. Note also that, as described above, the resistive linear strips may be located adjacent to the BGA of the NAND die and / or adjacent to the BGA of the DSD data storage controller and / or adjacent to other components of the SSD.

[0054] The communication interface 702 of device 700 provides means for communicating with other devices via a transmission medium. In some implementations, the communication interface 702 includes circuitry and / or programming (e.g., a program) adapted to facilitate bidirectional communication of information with respect to one or more devices in the system. In some implementations, the communication interface 702 may be configured for wire-based communication. For example, the communication interface 702 may be a bus interface, a transmit / receive interface, or some other type of signal interface including circuitry for outputting and / or acquiring signals (e.g., outputting signals from and / or receiving signals to a DSD).

[0055] The physical memory array 704 may include one or more NAND blocks 740. The physical memory array 704 may be accessed by processing components 710. Some of the processing components 710 may be part of the DSD data storage controller. Other components may be separate components such as the conductivity detector and PMU described above.

[0056] In one embodiment, the device 700 may also include a volatile memory for storing instructions and other information to support the operation of the processing component 710.

[0057] The device 700 includes various processing components 710 arranged or configured to acquire, process and / or transmit data, control data access and storage, issue or respond to commands, and control other desired operations. For example, a processing component 710 may be implemented as one or more processors, one or more controllers, and / or other structures configured to perform functions. According to one or more aspects of this disclosure, a processing component 710 may be adapted to perform any or all of the features, processes, functions, operations, and / or routines relating to DSD and SSD described herein. For example, a processing component 710 may be configured to perform any of the steps, functions, and / or processes described with respect to Figures 1, 2, 3, 4, 5A, 5B, 6, 8, 9, and 10. As used herein, the term “adapted” with respect to a processing component 710 may mean that the component is configured, adopted, implemented, and / or programmed to perform certain processes, functions, operations, and / or routines according to the various features described herein. The circuit may include a dedicated processor, such as an ASIC, which functions as a means (e.g., structure) for performing any one of the operations described in relation to Figures 1, 2, 3, 4, 5A, 5B, 6, 8, 9, and 10. The processing component 710 functions as one embodiment of the means for processing. In various implementations, the processing component 710 may at least partially provide and / or incorporate the functions described above for the conductivity detector 206 in Figure 2 and the PMU 210 components in Figure 2.

[0058] According to at least one embodiment of the apparatus 700, the processing component 710 includes a circuit / module 719 configured to detect conductive liquid (or to control the detection of conductive liquid performed by other components), a circuit / module 720 configured to detect a resistance signal from the strip 752, a circuit / module 722 configured to convert the resistance signal into a resistivity value, a circuit / module 724 configured to convert the resistivity value into a conductivity value, a circuit / module 726 configured to adjust the conductivity value to compensate for temperature (such as detected by the temperature sensor 750), and a comparison of the conductivity value with a threshold to indicate, for example, the presence of aqueous metal ions or other liquids in the DSD that could damage the DSD. The system may include one or more of the following: a circuit / module 728 configured to detect the presence of a pure substance; a circuit / module 730 for activating a failsafe mode (e.g., when the conductivity value exceeds one or more thresholds); a circuit / module 732 configured to deactivate the failsafe mode (e.g., when the conductivity value no longer exceeds a threshold); a circuit / module 734 configured to request a laptop shutdown (e.g., when entering failsafe mode); and a circuit / module 736 configured to identify the type of metal ion in the conductive liquid (when the device is programmed with different conductivity thresholds that distinguish different types of metal ions or other impurities). Note that circuits / modules 720, 722, 724, 726, and 728 may be components of circuit / module 719 that operate to detect the conductive liquid (or may operate under the control of circuit / module 719).

[0059] In at least some embodiments, means may be provided for carrying out the functions shown in Figure 7 and / or other functions illustrated or described herein. For example, means may include a circuit / module 719 for detecting conductive liquid (or for controlling the detection of conductive liquid carried out by other components); a circuit / module 720 for detecting a resistance signal from the strip 752; a circuit / module 722 for converting the resistance signal to a resistivity value; a circuit / module 724 for converting the resistivity value to a conductivity value; a circuit / module 726 for adjusting the conductivity value to compensate for temperature (such as detected by a temperature sensor 750); and means for comparing the conductivity value to a threshold to detect, for example, the presence of aqueous metal ions or other impurities indicating the presence of liquid in the DSD that could damage the DSD. The system may include one or more of the following: a circuit / module 728 for entering a failsafe mode; a circuit / module 730 for activating a failsafe mode (for example, when the conductivity value exceeds one or more thresholds); a circuit / module 732 for deactivating a failsafe mode (for example, when the conductivity value no longer exceeds a threshold); a circuit / module 734 for requesting a laptop shutdown (for example, when entering failsafe mode); and a circuit / module 736 for identifying the type of metal ion in a conductive liquid (when the device is programmed with different conductivity thresholds that distinguish different types of metal ions).

[0060] Further exemplary devices Figure 8 broadly illustrates a data storage device 800 configured according to one or more aspects of the present disclosure. The data storage device 800 includes an NVM array 802 mounted on a PCB using a first surface mount package (SMP). The NVM array 802 may be mounted on the PCB of the data storage device using, for example, a first BGA. The NVM array may be, for example, NAND 216 in Figure 2. The data storage device 800 also includes one or more processors mounted on the PCB using a second SMP and communicating with the NVM array. One or more processors 804 are configured individually or in combination to activate failsafe processing modes in response to the detection of conductive liquid. A sensor 806 (e.g., a resistance strip for sensing electrical resistance values) is mounted adjacent to one or both of the first and second SMPs. A detector 808 (e.g., a conductivity detector) is configured to detect conductive liquid using a sensor, for example, the detector 808 detects conductive liquid on one or both of the first and second SMPs. In some embodiments, one of the processors 804 may be the intelligent PMU 210 shown in Figure 2. Another of the processors 804 may be the data storage controller 218 shown in Figure 2. Note that the second SMP may include one or more SMPs, each containing one or more BGAs.

[0061] As explained above, the fail-safe mode prevents damage to the BGA or other SMP that may occur due to the presence of conductive liquids in the BGA or other SMP, such as aqueous metal ions or liquids containing other conductive impurities.

[0062] Figure 9 broadly illustrates a data storage device 900 configured according to one or more aspects of the present disclosure. The data storage device 900 includes an NVM array 902 mounted on a PCB. A resistor strip 904 is also mounted on the PCB (for example, it may be mounted adjacent to the NVM array 902). A conductivity detector 906 is coupled to the resistor strip 904. One or more processors 908 are configured to receive signals from the conductivity detector indicating whether the amount of metal ions in the liquid in contact with the resistor strip exceeds an impurity threshold (and thus, for example, indicating that the liquid is conductive), and to deactivate the power supply of the data storage device in response to the amount of metal ions in the liquid exceeding the impurity threshold, and then to reactivate the power supply in response to the amount of metal ions in the liquid no longer exceeding the impurity threshold.

[0063] The data storage device 900 may also include various other components such as a data storage controller, and the resistor strip 904 may also be mounted adjacent to such other devices to detect metal ions in the liquid within or around those devices. Disconnecting the power prevents damage (e.g., corrosion or short circuit) to the NVM array 902 and other devices that may occur due to the presence of liquid containing metal ions.

[0064] Figure 10 broadly illustrates a method 1000 according to one or more embodiments of the present disclosure for use by a data storage device. In block 1002, a component of the data storage device (e.g., a conductivity detector) detects the presence of aqueous metal ions within the data storage device (e.g., near the NAND chip or data storage controller). In block 1004, the component of the data storage device (e.g., the conductivity detector) determines whether the amount (e.g., concentration) of aqueous metal ions exceeds an impurity threshold. In block 1006, a component of the data storage device (e.g., a fail-safe PMU) deactivates the power supply of the data storage device in response to the amount of aqueous metal ions exceeding the impurity threshold. Subsequently, in block 1008, the component of the data storage device (e.g., the fail-safe PMU) reactivates the power supply in response to the amount of aqueous metal ions no longer exceeding the impurity threshold.

[0065] In some embodiments, an apparatus may be provided that includes components for performing the operation shown in Figure 10. For example, an apparatus may be provided that includes means for detecting the presence of aqueous metal ions in a data storage device (e.g., a resistor strip 208 in Figure 2), means for determining whether the amount of aqueous metal ions exceeds an impurity threshold (e.g., a conductivity detector 206 in Figure 2), means for deactivating the power supply of the data storage device in response to the amount of aqueous metal ions exceeding an impurity threshold (e.g., a relay 212 in Figure 2), and means for reactivating the power supply in response to the amount of aqueous metal ions no longer exceeding an impurity threshold (e.g., a PMU 210 in Figure 2).

[0066] In summary, in some embodiments, the system and procedures are provided to do the following: - Various processing circuits (e.g., firmware), relays, PMUs, conductive detectors, and linear resistor strips are used to enable a fail-safe power management mechanism that protects the M.2 SSD NAND die and data storage controller BGA from water damage. - Measure water impurities such as metal ions, salts, acids, and bases that may cause corrosion or damage to the BGA pins. - Determine if the water impurity level (e.g., metal ion level) is above a threshold, and if so, protect the SSD from short-circuiting by cutting off the main power until the water dries or the impurities decrease to a safe level. -When water is deionized or distilled, such water does not cause corrosion or short circuits, thus maintaining power. - It uses a built-in lithium battery to maintain backup power, which allows for timely detection of the presence or absence of liquid, enabling it to power on the SSD once it is dry, even if, for example, the SSD is not connected to the laptop or the laptop is turned off. - Manage sending IRQ signals to the laptop during a safe shutdown.

[0067] Additional aspects At least some of the processing circuits described herein can generally be adapted for processing that involves the execution of programming code stored on a storage medium. Where used herein, the terms “code” or “programming” are to be interpreted broadly to include, without limitation, instructions, instruction sets, data, code, code segments, program code, programs, programming, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, execution threads, procedures, functions, etc., whether they are called software, firmware, middleware, microcode, hardware description languages, etc.

[0068] At least some of the processing circuits described herein may be configured to acquire, process, and / or transmit data, control data access and storage, issue commands, and control other desired operations. In at least one embodiment, a processing circuit may include a circuit configured to implement a desired program provided by a suitable medium. For example, a processing circuit may be implemented as one or more processors, one or more controllers, and / or other structures configured to execute executable programming. Embodiments of processing circuits may include general-purpose processors, digital signal processors (DSPs), ASICs, field-programmable gate arrays (FPGAs) or other programmable logic components, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. General-purpose processors may include microprocessors, as well as any conventional processors, controllers, microcontrollers, or state machines. At least some of the processing circuits may also be implemented as combinations of computing components, such as a combination of a controller and a microprocessor, several microprocessors, an ASIC and one or more microprocessors working in conjunction with a microprocessor, or any other number of different configurations. The various embodiments of the processing circuits mentioned herein are illustrative, and other suitable configurations within the scope of this disclosure are also contemplated.

[0069] Embodiments of the subject matter described herein can be implemented in any suitable NVM, including NAND flash memory such as 3D NAND flash memory. More generally, semiconductor memory devices include working memory devices such as DRAM or SRAM devices, NVM devices, ReRAM, EEPROM, flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (FRAM), and MRAM, as well as other semiconductor elements capable of storing information. Each type of memory device may have a different configuration. For example, flash memory devices may be configured in NAND or NOR configurations.

[0070] Memory devices can be formed from any combination of passive and / or active elements. In non-limiting embodiments, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity switching storage elements such as antifuses and phase change materials, and optionally steering elements such as diodes. Furthermore, in non-limiting embodiments, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements with charge storage regions such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0071] Multiple memory elements may be configured to be connected in series or so that each element is individually accessible. In a non-limiting embodiment, a flash memory device with a NAND configuration (NAND memory) typically includes memory elements connected in series. A NAND memory array may be configured such that the array consists of multiple memory strings, each string consisting of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements may be configured so that each element is individually accessible (e.g., a NOR memory array). NAND and NOR memory configurations are illustrative, and memory elements may be configured in other ways. Semiconductor memory elements located in and / or on a substrate may be arranged in two or three dimensions, such as a two-dimensional memory structure or a three-dimensional memory structure.

[0072] Associated circuitry is typically required for the operation of memory elements and for communication with them. In non-limiting embodiments, a memory device may have circuitry used to control and drive memory elements to achieve functions such as programming and reading. This associated circuitry may be on the same substrate as the memory elements and / or on a separate substrate. For example, a controller for memory read / write operations may be located on a separate controller chip and / or on the same substrate as the memory elements. Those skilled in the art will recognize that the subject matter described herein is not limited to the two-dimensional and three-dimensional exemplary structures described herein, but encompasses all relevant memory structures within the spirit and scope of the subject matter as described herein and understood by those skilled in the art.

[0073] The embodiments described herein are provided to illustrate the specific concepts of this disclosure. Apparatus, devices, or components shown above may be configured to carry out one or more of the methods, features, or steps described herein. Those skilled in the art will understand that these are merely illustrative and that other embodiments may be included within the scope of this disclosure and the appended claims. Based on the teachings herein, those skilled in the art should understand that embodiments disclosed herein may be implemented independently of any other embodiments, and that two or more of these embodiments may be combined in various ways. For example, an apparatus may be implemented or a method may be carried out using any number of embodiments described herein. In addition, such an apparatus may be implemented or a method may be carried out using other structures, functions, or structures and functions in addition to or in addition to one or more of the embodiments described herein.

[0074] Aspects of the present disclosure have been described above with reference to schematic flowcharts and / or schematic block diagrams of methods, apparatus, systems, and computer program products according to embodiments of the present disclosure. It will be understood that each block in the schematic flowcharts and / or schematic block diagrams, and combinations of blocks within the schematic flowcharts and / or schematic block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a computer processor or other programmable data processing device so that instructions executed via the processor or other programmable data processing device can create means for implementing functions and / or operations specified in one or more blocks of the schematic flowcharts and / or schematic block diagrams.

[0075] The subject matter described herein may be implemented in hardware, software, firmware, or any combination thereof. Therefore, terms such as “function” and “module” as used herein may also refer to hardware, which may also include software and / or firmware components, for implementing the described features. In one exemplary implementation, the subject matter described herein may be implemented using a computer-readable medium storing computer-executable instructions that control a computer (e.g., a processor) to perform the function described herein when executed by the computer. Examples of computer-readable mediums suitable for implementing the subject matter described herein include non-temporary computer-readable media such as disk memory devices, chip memory devices, programmable logic devices, and application-specific integrated circuits. In addition, the computer-readable medium implementing the subject matter described herein may reside on a single device or computing platform, or may be distributed across multiple devices or computing platforms.

[0076] It should also be noted that in some alternative implementations, the functions described within a block may be performed in a different order than that shown in the diagram. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or blocks may sometimes be executed in reverse order depending on the functions they contain. Other steps and methods may be conceivable that are equivalent in function, logic, or effect to one or more blocks or parts thereof in the shown diagram. Various arrow and line types may be employed in flowcharts and / or block diagrams, but it should be understood that they do not limit the scope of the corresponding embodiment. For example, arrows may indicate waiting or monitoring periods of unspecified duration between enumerated steps in the shown embodiment.

[0077] The various features and processes described above may be used independently of each other or combined in various ways. All possible combinations and subcombinations are intended to be included within the scope of this disclosure. In addition, certain methods, events, states, or process blocks may be omitted in some implementations. The methods and processes described herein are also not limited to any particular order, and the blocks or states associated therewith may be performed in other appropriate orders. For example, the described tasks or events may be performed in an order other than that specifically disclosed, or multiple tasks or events may be combined into a single block or state. Exemplary tasks or events may be performed in series, in parallel, or in any other appropriate way. Tasks or events may be added to or removed from the disclosed exemplary embodiments. Exemplary systems and components described herein may be configured differently from those described. For example, elements may be added, removed, or rearranged compared to the disclosed exemplary embodiments.

[0078] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips, which may be referenced throughout the above description, can be represented by voltage, electric current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0079] The term “exemplary” is used herein to mean “serving as an example, case, or illustration.” Any embodiment described herein as “exemplary” should not necessarily be construed as being preferable or advantageous to any other embodiment. Similarly, the term “embodiment” does not require that all embodiments include the features, advantages, or modes of operation described.

[0080] The above description includes many specific embodiments of the present invention, but these should not be construed as limitations on the scope of the invention, but rather as examples of those specific embodiments. Accordingly, the scope of the invention should be determined not by the exemplary embodiments, but by the appended claims and their equivalents. Furthermore, throughout this specification, references to “one embodiment,” “in one embodiment,” “in one aspect,” or similar words mean that certain features, structures, or characteristics described in relation to an embodiment are included in at least one embodiment of this disclosure. Accordingly, throughout this specification, the phrases “in one embodiment,” “in one embodiment,” “in one aspect,” and similar words mean “one or more embodiments, but not all,” although they may all refer to the same embodiment, unless otherwise expressly specified.

[0081] The terms used herein are intended solely to describe specific aspects and not to limit them. Where used herein, the singular forms “a,” “an,” and “the” are intended to include the plural form (i.e., one or more) unless the context explicitly indicates otherwise. The list of enumerated items does not mean that any or all of the items are mutually exclusive and / or mutually inclusive unless expressly otherwise specified. It will be further understood that the terms “comprises,” “comprising,” “includes,” “including,” and “having,” and their variations, where used herein, mean “includes, but not limited to,” unless expressly otherwise specified. That is, these terms may specify the existence of a described feature, integer, step, action, element, or component, but do not exclude the existence or addition of one or more other features, integers, steps, actions, elements, components, or groups thereof. Furthermore, please understand that the word "or" has the same meaning as the Boolean operator "OR," that is, it encompasses the possibilities of "either" and "both," and is not limited to "exclusive OR" ("XOR") unless otherwise specified. Also, please understand that the symbol " / " between two adjacent words has the same meaning as "or" unless otherwise specified. Furthermore, phrases such as "connected to," "joined with," or "communicating with" are not limited to direct connections unless otherwise specified.

[0082] Any reference to elements in this specification using designations such as “first,” “second,” etc., does not generally limit the quantity or order of those elements. Rather, these designations can be used in this specification as a convenient way to distinguish two or more elements or examples of elements. Thus, references to first and second elements do not mean that only two elements may be used therein, or that the first element must precede the second element in any way. Also, unless otherwise stated, a set of elements may include one or more elements. In addition, terms of the form “at least one of A, B, or C,” “A, B, C, or any combination thereof,” or “one or more of A, B, or C” used in the description or claims mean “A, B, or C, or any combination of these elements.” For example, this term may include A, or B, or C, or A and B, or A and C, or A and B and C, or 2A, or 2B, or 2C, or 2A and B, etc. In a further embodiment, “at least one of A, B, or C” or “one or more of A, B, or C” is intended to cover A, B, C, AB, AC, BC, and ABC, as well as any multiple of the same members (e.g., any list including AA, BB, or CC). Similarly, “at least one of A, B, and C” or “one or more of A, B, or C” is intended to encompass A, B, C, AB, AC, BC, and ABC, as well as any multiple of the same members. Similarly, when used herein, a phrase referring to a list of items linked with “and / or” refers to any combination of items. In an embodiment, “A and / or B” is intended to encompass A only, B only, or A and B together. In another embodiment, “A, B, and / or C” is intended to encompass A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, or a combination of A, B, and C.

[0083] As used herein, the term “decision-making” encompasses a wide range of actions. For example, “decision-making” may include calculating, calculating, processing, deriving, investigating, looking up (e.g., looking up a table, data store, or another data structure), and confirming. It may also include receiving (e.g., receiving information), accessing (e.g., accessing data in memory), and resolving, selecting, choosing, and establishing.

Claims

1. A data storage device, A non-volatile memory (NVM) array mounted on a printed circuit board (PCB) using a first surface mount package (SMP), One or more processors, which are mounted on the PCB using a second SMP and communicate with the NVM array, A sensor mounted adjacent to one or both of the first SMP and the second SMP, A detector configured to detect a conductive liquid using the aforementioned sensor, A data storage device in which one or more processors are configured to activate a fail-safe processing mode in response to the detection of the conductive liquid, individually or in combination.

2. The sensor comprises at least one resistive linear strip, The data storage device according to claim 1, wherein the detector includes a conductivity detector coupled to the at least one resistance linear strip.

3. The data storage device according to claim 2, wherein the at least one resistive linear strip has a first portion adjacent to the first SMP and a second portion adjacent to the second SMP.

4. The data storage device according to claim 2, wherein the conductivity detector is further configured to detect aqueous metal ions based on electrical resistance signals received from the at least one resistance linear strip, thereby enabling detection of the conductive liquid.

5. The conductivity detector, The electrical resistance signal is received from at least one of the resistor linear strips. The aforementioned electrical resistance signal is converted into a resistivity value, Convert the resistivity value to a conductivity value, The data storage device according to claim 4, further configured to detect aqueous metal ions by comparing the conductivity value with one or more conductivity thresholds indicating the presence of aqueous metal ions.

6. The data storage device according to claim 5, further comprising a temperature sensor, wherein the conductivity detector is further configured to adjust the conductivity value based on the temperature value measured by the temperature sensor.

7. The data storage device according to claim 1, wherein one or more processors are further configured to deactivate a power supply that provides power to the NVM array in response to the activation of the failsafe processing mode.

8. The data storage device according to claim 7, wherein one or more processors are further configured to reactivate the power supply in response to the detector detecting that the amount of conductive liquid has decreased to below a threshold indicating a sufficient drying amount.

9. The data storage device according to claim 7, wherein the power is supplied by a host.

10. The data storage device according to claim 1, wherein one or more processors are further configured to send a signal to the host requesting the host to shut down in response to the activation of the failsafe processing mode.

11. The data storage device according to claim 10, wherein one or more processors are further configured to send a signal to the host requesting reactivation of the host in response to the detector detecting that the amount of conductive liquid has decreased to below a threshold indicating a sufficient amount of dryness.

12. The data storage device according to claim 1, further comprising a secondary power supply that remains active during the failsafe processing mode in order to supply power to at least the detector.

13. The data storage device according to claim 1, wherein the data storage device includes a solid-state device (SSD) in an M.2 form factor.

14. The data storage device according to claim 1, wherein one or both of the first SMP and the second SMP include a ball grid array (BGA).

15. A data storage device, A non-volatile memory (NVM) array mounted on a printed circuit board (PCB), The resistor strip mounted on the aforementioned PCB, A conductivity detector coupled to the resistance strip, A system comprising one or more processors, wherein the one or more processors are individually or in combination A signal indicating whether the amount of metal ions in the liquid in contact with the resistance strip exceeds the impurity threshold is received from the conductivity detector. In response to the amount of metal ions in the liquid exceeding the impurity threshold, the power supply to the data storage device is deactivated. A data storage device configured to subsequently reactivate the power supply in response to the amount of metal ions in the liquid no longer exceeding the impurity threshold.

16. The conductivity detector, Receiving an electrical resistance signal from the aforementioned resistance strip, The aforementioned electrical resistance signal is converted into a resistivity value, Convert the resistivity value to a conductivity value, The data storage device according to claim 15, further configured to detect metal ions by comparing the conductivity value with one or more conductivity thresholds indicating the presence of metal ions in the liquid.

17. The data storage device according to claim 16, further comprising a temperature sensor, wherein the conductivity detector is further configured to adjust the conductivity value based on the temperature value measured by the temperature sensor.

18. The data storage device according to claim 15, wherein the resistor strip has a portion adjacent to the NVM array.

19. The data storage controller is further provided, and the resistor strip has a portion adjacent to the data storage controller. The data storage device according to claim 15, wherein the data storage device includes a solid-state device (SSD) in an M.2 form factor.

20. A data storage device, Means for detecting aqueous metal ions in the data storage device, Means for determining whether the aqueous metal ion exceeds an impurity threshold, Means for deactivating the power supply of the data storage device in response to the aqueous metal ions exceeding the impurity threshold, A data storage device comprising means for reactivating the power supply in response that the aqueous metal ions no longer exceed the impurity threshold.

Images