Semiconductor equipment

Abstract

To provide a programmable logic device (PLD) having a less number of switches and high reliability.SOLUTION: A PLD includes: first to third columns each having a plurality of logic elements (LE); a plurality of first to third wiring lines to which a signal output from LE of the first to third columns are respectively given; a plurality of fourth wiring lines to which a signal inputted to LE on the second column are respectively given; a plurality of groups each of which has at least a first switch and a second switch for selecting a conduction state or a non-conduction state according to a potential of a node to which a signal is given through the first switch; a fifth wiring line to which a predetermined potential is given; and a third switch for controlling electrical connection between the plurality of fourth wiring lines and the fifth wiring line. The plurality of first to third wiring lines are respectively provided between the first column and the second column or between the second column and the third column, and in one group of the plurality of groups selected according to the signal, and when the second switch becomes a conduction state, one of the plurality of first to third wiring lines is connected to one of the plurality of fourth wiring lines.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to a product, a method, or a method of manufacturing; or to a process, a machine , relating to manufacture or composition of matter. In particular The present invention relates to, for example, semiconductor devices, display devices, light-emitting devices, energy storage devices, and methods for driving them. Or, the invention relates to a method for manufacturing them. In particular, one aspect of the present invention changes the hardware configuration. A programmable logic device that can be modified, and the above programmable logic device This relates to semiconductor devices using vises, etc. [Background technology]

[0002] Programmable Logic Device (PLD) evice) is a system in which logic circuits are composed of logic elements (basic blocks) of an appropriate size. The functions of each logic element and the connection structure between logic elements are determined after manufacturing. It is characterized by being changeable in the above PLD, It has a jack, wiring resources to control the connections between logic elements, and registers. The above registers are composed of the function of each logic element and the wiring resources. Data (configuration data) for defining the connection structure between elements. However, it is stored.

[0003] The registers for storing configuration data are the configuration registers. It is called Mori. The arrangement of configuration data into configuration memory. This is called configuration. In particular, the configuration memory The new storage of configuration data is called reconfiguration. It'll be found out.

[0004] By the way, there is a process called dynamic reconfiguration during operation. PLDs that allow for the reconfiguration of logic circuits have higher area efficiency compared to ordinary PLDs. It has advantages. The multi-context approach is related to logic elements or wiring resources. The corresponding configuration memory reads the data from the memory element. This method achieves dynamic reconstruction by storing configuration data. The context method sequentially loads configuration data from memory elements into the log. Send to the configuration memory corresponding to the jack element or wiring resource. Compared to configuration information distribution methods that achieve dynamic reconfiguration, this method enables high-speed reconfiguration of logic circuits. It is possible.

[0005] Patent Document 1 below describes DRAM (Dynamic Random Access Memory). The configuration data sent from mory is sent to SRAM (Static Configuration Mechanism (Random Access Memory) By storing it in Mori, this programmable LSI can be reconfigured in a short amount of time. It is described as follows. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 10-285014 [Overview of the project] [Problems that the invention aims to solve]

[0007] By the way, since the PLD using the above multi-context method requires a configuration memory in addition to the memory element, compared with other methods for realizing dynamic reconfiguration such as a configuration information distribution method, the area occupied by the storage devices such as the memory element and the configuration memory in the PLD is large, and the advantage of dynamic reconfiguration of high area efficiency cannot be fully utilized. In particular, since SRAM has a large number of elements per memory cell, it is difficult to reduce the area of the storage device. Also, since DRAM has fewer elements per memory cell than SRAM, it is advantageous for reducing the area of the storage device, but it is difficult to suppress power consumption because refreshing is required.

[0008] <000D089> Increasing the design freedom in a programmable logic device tends to increase the number of switches included in the wiring resources. Since the selection (switching) of the conduction state or non-conduction state of the switches in the wiring resources is determined by the configuration data, when the number of the above switches increases, the capacity of the configuration data corresponding to a single circuit configuration becomes large relative to the circuit scale of the programmable logic device. Therefore, it takes time to transmit the configuration data to the configuration memory. Also, when the number of the switches increases, a memory element or a configuration memory with a large storage capacity is required, and it becomes difficult to reduce the area of the storage device. Also, when the number of switches increases, within the programmable logic device,

[0009] As a result, the delay of signals passing through switches becomes significant, and the high performance of programmable logic devices Rapid movement is hindered.

[0009] Furthermore, the various wires connected to the wiring resource switch are programmable logic devices After the power to the device is turned off, its potential may become unstable. Furthermore, the configuration Depending on the configuration of the memory elements used in the cyclic memory, the switches included in the wiring resources may The configuration data that defines the switching of the programmable logic The data may be lost when the power to the vice is turned off. For example, the p In configurable LSIs, the configuration memory is made of SRAM. Therefore, when the power to a programmable logic device is cut off, the configuration data The signal disappears. And if the potential of the wiring becomes uncertain, furthermore, the configuration If the data is lost, the wires that are normally electrically isolated during operation will not connect. After powering on the programmable logic device, the above switch is used to establish a conductive state. This can happen. In this case, if there is a difference in potential between the above wires, a large amount of energy will be lost between these wires. The flow of current could potentially cause damage to programmable logic devices. There is.

[0010] Given the technical background described above, one aspect of the present invention increases the degree of design freedom while also improving logic Programmable switches that control the connections between elements can be kept to a minimum. One of the challenges is to provide a reliable logic device. Furthermore, one aspect of the present invention provides a highly reliable One of the challenges is to provide programmable logic devices.

[0011] Furthermore, the present invention enables high-speed operation, or by using the above-mentioned programmable logic device. One of its challenges is to provide semiconductor devices that can achieve high reliability.

[0012] Furthermore, as the circuit size of programmable logic devices increases, larger memory capacity is required. Because it requires configuration memory, programmable logic devices It becomes difficult to keep the area of ​​the smudges small.

[0013] Therefore, one aspect of the present invention is to keep the layout area small even when the circuit size increases. One of our challenges is to provide programmable logic devices that can do this.

[0014] Furthermore, one aspect of the present invention relates to a programmable robot that can keep the area of ​​the storage device small. One of the challenges is to provide a JIC device. Another aspect of the present invention is the restructuring of a logic circuit. Programmable, which can perform operations at high speed and keep the memory area small. One of the challenges is to provide logic devices. Furthermore, one aspect of the present invention relates to the regeneration of logic circuits. Configuration can be performed quickly, the memory area can be kept small, and high-speed operation can be achieved. One of our challenges is to provide programmable logic devices that can perform the required tasks.

[0015] Furthermore, one aspect of the present invention involves miniaturizing by using the above-mentioned programmable logic device. One of our challenges is to provide semiconductor devices that can achieve high functionality.

[0016] Alternatively, one aspect of the present invention aims to provide a novel semiconductor device or the like. The description of these problems does not preclude the existence of other problems. Furthermore, one aspect of the present invention is It is not necessary to solve all of these issues. Furthermore, other issues are clearly defined. This will become clear from the description in the detailed specifications, drawings, and claims, and the specifications, drawings, and claims will become clear from the description, drawings, and claims. It is possible to extract other issues from the descriptions of the requested terms and conditions. [Means for solving the problem]

[0017] In a first aspect of the present invention, the switching circuit included in the wiring resource maintains its conductivity. It adds the function of a memory device. Specifically, the above switch circuit has wiring or terminals A first transistor that functions as a first switch to control the electrical connections of the cow, and The amount of charge determined by the figuring data is transferred to the first transistor's gauge. A second transistor that functions as a second switch for supplying, holding, and releasing in the tank. There are multiple sets having the above. And according to the configuration data, the above multiple In one of several sets, the first transistor becomes conductive, which connects multiple wires and logic The connection structure between the element and its input terminals, via a switch circuit, is determined.

[0018] Semiconductor films with a wider band gap and lower intrinsic carrier density than silicon. In addition, transistors having a channel formation region are typically made of materials such as silicon or germanium. Compared to transistors with a channel formation region in the conductor, the off-current is made extremely small. It can do that. It has a wider band gap than silicon and a higher intrinsic carrier density than silicon. Examples of semiconductors that can have a low band gap include those with a band gap that is more than twice that of silicon. Examples include oxide semiconductors, silicon carbide, and gallium nitride.

[0019] The second transistor prevents the charge held at the gate of the first transistor from leaking out. To prevent this, it is desirable that the off-current be extremely small. Therefore, as described above, In semiconductor films with a wider band gap than silicon and a lower intrinsic carrier density than silicon, A transistor having a channel formation region is suitable for use as a second transistor. .

[0020] In a switch circuit having the above configuration, the wiring and The conduction state of the first transistor, which controls the electrical connection between terminals, is determined, and the off state is activated. The above conduction state is maintained by the second transistor, which has a significantly low current. Therefore, the present invention In a programmable logic device according to one embodiment, the switch circuit is configured It combines the functions of both a memory unit and a memory element, and Furthermore, since the number of elements in each set is smaller than that of SRAM, the configuration memory and Compared to conventional programmable logic devices that have both a molybdenum and a molybdenum, The area required for storage of configuration data can be kept small. Cut.

[0021] Furthermore, the off-current of the second transistor is a transistor having a channel formation region in the silicon film. Because it is smaller than a transistor, the data retention time in this switch circuit is longer than that of DRAM. It can also be made longer. Therefore, the frequency of data rewriting can be reduced, and thus deletion Power consumption can be kept to a minimum.

[0022] Furthermore, the programmable logic device according to the first aspect of the present invention includes a plurality of first logic A column having a logic element, a column having multiple second logic elements, and multiple third It has at least a column having a logic element. Also, according to one aspect of the present invention, A Logicable Logic Device is an output device in which multiple first logic elements each have an output Multiple first wires and multiple second logic elements are electrically connected to the terminal. Multiple second wires and multiple third logic elements are electrically connected to the output terminals. Each output terminal has multiple third wires electrically connected to it. The first and second wirings connect a plurality of first logic elements and a plurality of second logic elements. The third wiring is provided between the vertices and connects multiple first logic elements and multiple second logic elements. It is provided between elements, and also has multiple second logic elements and multiple third logic It is located between the lock elements.

[0023] Furthermore, in a first aspect of the present invention, the first wiring, the second wiring, and the third wiring, and the plurality of second The electrical connections of the input terminals of each logic element are connected via multiple switches. It is controlled by the circuit. Specifically, in each switch circuit, the configuration According to the data, the first transistor becomes conductive in one of the above multiple sets. , the first wiring, the second wiring, and the third wiring, and the plurality of second logic elements described above, respectively The electrical connection structure between the input terminals is defined.

[0024] In a first aspect of the present invention, the above configuration provides a second logic element and a second logic The electrical connections of the lock elements can be controlled by a single switch circuit. The electrical connection between the first logic element and the second logic element is made by the first... It can be controlled by a switch circuit. Also, one second logic element and one third The electrical connections of logic elements can be controlled by a single switch circuit. Therefore, in one aspect of the present invention, the degree of design freedom in a programmable logic device is It is possible to increase efficiency while reducing the number of switch circuits included in the wiring resources.

[0025] In a second aspect of the present invention, the switch circuit included in the wiring resource comprises a first switch and an upper A node to which a signal containing configuration data is provided via the first switch. A set having at least a second switch that controls the electrical connection between wires according to their potential. It shall have multiple such items. And, according to the configuration data, the above multiple items In one of the sets, the second switch becomes conductive, and multiple logic elements One of several wires connected to the output terminals and the input terminal of one logic element A connection structure is defined for the child device, via a switch circuit, to one of the electrically connected wires.

[0026] Furthermore, the programmable logic device according to the second aspect of the present invention includes a plurality of first logic A column having a logic element, a column having multiple second logic elements, and multiple third It has at least a column having a logic element, and a plurality of first logic elements Multiple wires electrically connected to the output terminals of the rement are designated as the first wires, and multiple Multiple wires electrically connected to the output terminals of each of the second logic elements. This is designated as the second wiring, and is electrically connected to the output terminals of each of the multiple third logic elements. If the connected multiple wires are referred to as the third wire, then in one aspect of the present invention, the multiple first wires and multiple The second wiring consists of a column having multiple first logic elements and multiple second logic elements Provided between rows having a terminal, multiple third wirings have multiple first logic elements It is provided between the column and the column having multiple second logic elements, and also has multiple second logic elements. It is placed between a column with two logic elements and a column with multiple third logic elements. It is assumed that it is being treated as such.

[0027] Then, the input terminals of each of the multiple second logic elements are electrically connected. If multiple wires are designated as the fourth wire, then in one aspect of the present invention, multiple first wires, multiple second wires , and the electrical connections between the multiple third wires and the multiple fourth wires are multiple switch circuits. It is controlled by, specifically, according to the configuration data, each switch When the second switch becomes conductive in one of the above-mentioned sets of circuits, the multiple first switches One of the following: a wire, multiple second wires, and multiple third wires, and any of the multiple fourth wires. An electrical connection structure with one of them is defined.

[0028] In a second aspect of the present invention, the above configuration provides one second logic element and another one The electrical connection of two logic elements can be controlled by a single switch circuit. Furthermore, the electrical connection between the first logic element and the second logic element is It can be controlled by a single switch circuit. Also, a second logic element and a single The electrical connection of the third logic element can be controlled by a single switch circuit. Therefore, in one aspect of the present invention, the design of a programmable logic device is made possible. This allows for increased flexibility while reducing the number of switch circuits included in the wiring resources.

[0029] Furthermore, the programmable logic device according to the second aspect of the present invention comprises the first to third B A wire electrically connected to the input terminal of any one of the magic elements, and a predetermined A switch is provided to control the electrical connection with the wiring to which an electric potential is applied. In one embodiment, the above configuration allows the potential of the wiring electrically connected to the input terminal to be set to a predetermined It can be initialized to the height of [this]. Therefore, the programmable logic device After the power is cut off, the potential of the wiring electrically connected to the input terminal becomes undefined. As a result, and furthermore, the configuration data is lost when the power is turned on. Furthermore, the above wiring is electrically connected to the input terminal, and multiple wirings are electrically connected to the output terminal. Even if the wires are electrically connected, the current flowing between the above wires will not be transmitted from the input terminal to the logic element. This prevents it from flowing into the programmable logic device. This can prevent damage from occurring. Also, programmable logic devices Immediately after power is turned on, the input terminals of the logic element are high level and low level In some cases, the potential may become an intermediate potential between the two. When given, through-currents are likely to occur in the CMOS circuit of the logic element. However, in one aspect of the present invention, with the above configuration, the input terminal is intermediate after the power is turned on. Since it is possible to prevent the potential from being reached, the above-mentioned through-current can be prevented from occurring.

[0030] In addition to the above-mentioned switch for initialization, a programmer according to the second aspect of the present invention The Bull Logic device sets the potential of the wiring electrically connected to the input terminal to a high level or A latch may be provided that has the function of maintaining the level at either the low or low level. In one embodiment, with the above configuration, after the power is turned on, the potential of the input terminal is set to a high level or low. - It can be kept at either one of the two levels, thus preventing the above-mentioned through-current from occurring. can.

[0031] Furthermore, in a third aspect of the present invention, the configuration included in the logic element The memory connects to the first switch and, via the first switch, receives configuration data. According to the potential of the first node to which the first signal is given, the first wiring to which the first potential is given , a second switch that controls the electrical connection with the second wiring, a third switch, and the above third switch A second node receives a second signal via a switch, which has the polarity reversed with respect to the first signal. A third wiring to which a second potential lower than the first potential is given according to the potential of the first wiring, and the second wiring A fourth switch controls the electrical connection to the wire, and controls the output of the potential of the second wire to the fourth wire. The system shall have multiple fifth switches to control. The logical operations performed on the above logic elements are defined according to the data.

[0032] In a third aspect of the present invention, with the above configuration, according to the configuration data, A potential of 1 or a second potential can be applied to the fourth wire. Therefore, the configuration Before reading the configuration data from the configuration memory, pre-charge the fourth wire. It is possible to read the configuration data accurately without having to perform any further operations. Therefore, a circuit for pre-charging is provided in the configuration memory drive circuit. This eliminates the need for additional processing, allowing for a smaller area for programmable logic devices.

[0033] Furthermore, in a fourth aspect of the present invention, the above-described configuration memory is used Each of the multiple logic elements has a row of elements, and the above multiple logic elements The configuration memories contained in each are arranged in a matrix. Furthermore, in a fourth aspect of the present invention, a plurality of switch circuits included in the wiring resources are also performed. They are arranged in rows.

[0034] In the third form of configuration memory, a first switch and a second switch are configured The part that is performed and the part consisting of the third switch and the fourth switch are the switches of the second embodiment. In the switch circuit, the part consisting of the first switch and the second switch, and the contact of each switch The configuration remains the same. Therefore, in the fourth aspect of the present invention, the configuration memory By arranging the switch circuit in a matrix, the operation of the configuration memory and Therefore, the operation of the switch circuit and the drive circuit can be controlled by the same drive circuit. When the drive circuit for the switch circuit and the drive circuit for the configuration memory are provided separately. Compared to that, the area of ​​the programmable logic device can be kept small. [Effects of the Invention]

[0035] According to one aspect of the present invention, a programmable log can be created that can reduce the area of ​​the storage device. A clock device can be provided. Furthermore, according to one aspect of the present invention, the reconfiguration of logic circuits can be performed at high speed. This allows for a smaller memory area, and the programmable logic device A chair can be provided. Furthermore, according to one aspect of the present invention, the reconfiguration of logic circuits can be performed at high speed. This allows for a smaller storage area and enables high-speed operation. A programmerable logic device can be provided. In one aspect of the present invention, the programmer By using Bull Logic devices, miniaturization or increased functionality can be achieved. We can provide semiconductor devices.

[0036] According to one aspect of the present invention, the connection between logic elements is controlled while increasing the degree of design freedom. We can provide a programmable logic device that can reduce the number of switches required. Furthermore, according to one aspect of the present invention, a highly reliable programmable logic device is provided. It is possible. Furthermore, according to one aspect of the present invention, high-speed operation or high reliability can be achieved. We can provide semiconductor devices.

[0037] Furthermore, according to one aspect of the present invention, even if the circuit size increases, the layout area can be kept small. A programmable logic device that can do this can be provided. Furthermore, according to one aspect of the present invention This allows us to provide miniaturized semiconductor devices. [Brief explanation of the drawing]

[0038] [Figure 1] A diagram showing the configuration of the PLD and switch circuit. [Figure 2] A diagram showing the configuration of a switch circuit. [Figure 3] A diagram showing the configuration of a switch circuit. [Figure 4] A diagram showing the configuration of a switch circuit. [Figure 5] Timing chart. [Figure 6]A diagram showing the configuration of a switch circuit. [Figure 7] Timing chart. [Figure 8] A diagram showing the configuration of a switch circuit. [Figure 9] A diagram showing the configuration of a switch circuit. [Figure 10] A diagram showing the configuration of a switch circuit. [Figure 11] Timing chart. [Figure 12] A diagram showing the configuration of a switch circuit. [Figure 13] A diagram showing the structure of a cell. [Figure 14] A diagram showing the configuration of a latch. [Figure 15] A diagram showing the configuration of a PLD. [Figure 16] A diagram showing the configuration of logic elements. [Figure 17] Top view of a PLD. [Figure 18] A diagram showing the configuration of the LUT. [Figure 19] Cross-section of a cell. [Figure 20] Cross-section of a transistor. [Figure 21] A diagram showing the stacked structure of a transistor. [Figure 22] A diagram showing the stacked structure of a transistor. [Figure 23] A diagram showing the stacked structure of a transistor. [Figure 24] Circuit diagram of the configuration memory. [Figure 25] A diagram showing an example of the configuration of logic elements. [Figure 26] A diagram showing an example of an I / O configuration. [Figure 27] Circuit diagram of a tristate buffer. [Figure 28] PLD mask drawing. [Figure 29] A diagram showing an example of a PLD configuration. [Figure 30] The circuit diagram and timing chart for the cell. [Figure 31]A diagram showing the relationship between overdrive voltage and delay time. [Figure 32] Microscopic image of a PLD. [Figure 33] A diagram showing the change in oscillation frequency over time in a ring oscillator. [Figure 34] A diagram of an electronic device. [Modes for carrying out the invention]

[0039] The embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is... Not limited to the following description, the present invention may have forms and characteristics that do not depart from the spirit and scope of the invention. Those skilled in the art will readily understand that the details can be modified in various ways. Therefore, the present invention This shall not be interpreted as being limited to the contents of the embodiments described below.

[0040] The programmable logic device of the present invention includes a microprocessor and an image processing circuit. , controllers for semiconductor display devices, DSP (Digital Signal Processor) Various semiconductor integrated circuits using semiconductor elements, such as essors and microcontrollers. It is included in that category. Furthermore, the semiconductor device of the present invention is an RF tag using the above semiconductor integrated circuit. This category includes various devices such as semiconductor display devices. Semiconductor display devices include liquid crystal display devices. , a light-emitting device equipped with light-emitting elements such as organic light-emitting diodes (OLEDs) in each pixel, electronic paper Par, DMD(Digital Micromirror Device), PDP(P lasma Display Panel), FED(Field Emission Display devices, etc., and other semiconductor display devices that have semiconductor elements in their driving circuits, It falls into that category.

[0041] <Example of PLD configuration> A PLD according to one aspect of the present invention has a column having multiple LEs (logic elements), Several are arranged, with multiple wires and multiple switch circuits placed between each row. (See diagram) 1(A) illustrates a part of PLD100 according to one aspect of the present invention.

[0042] Figure 1(A) shows a first row 102-1 having multiple LE101s, and multiple LE101s The second column 102-2, which has multiple LE101s, and the third column 102-3, which has multiple LE101s, It is located at D100. In Figure 1(A), starting from the left side of the drawing, the first column 1 If column 02-1, the second column 102-2, and the third column 102-3 are arranged in parallel: This illustrates the point.

[0043] Also, in Figure 1(A), there are multiple wires 103, multiple wires 104, and multiple wires 105. , multiple wires 106, multiple wires 107, multiple wires 108, multiple wires 109 However, this is provided in the PLD100.

[0044] Then, the first output terminal of each LE101 in the first row 102-1 is connected to multiple wires 103 Each of the following is connected to one of them. Each LE101 of the first column 102-1 The second output terminals are connected to one of the multiple wires 104.

[0045] Furthermore, the first output terminal of each LE101 in the second row 102-2 is connected to multiple wires 106 Each is connected to one of them. Each LE101 that the second column 102-2 has Each second output terminal is connected to one of the multiple wires 107.

[0046] Furthermore, the first output terminal of each LE101 in the third row 102-3 is connected to multiple wires 105 Each is connected to one of them. Each LE101 that the third column 102-3 has Each second output terminal is connected to one of the multiple wires 109.

[0047] Note that the number of first output terminals and second output terminals on each LE101 are not necessarily one. It is not limited to this; either one may be multiple, or both may be multiple. However, Even if there are multiple first output terminals or multiple second output terminals, one wire must always One output terminal is assumed to be connected. That is, the number of LE101s in column 102 is Y. If (Y is a natural number), then the PLD100 has Y wires connected to the first output terminal and It has at least Y wires connected to the second output terminal.

[0048] Furthermore, in this specification, "connection" means an electrical connection, and current, voltage, or potential is This corresponds to a state where it can be supplied or transmitted. Therefore, a connected state is a state where it is directly connected. It does not necessarily refer to a state in which current, voltage, or potential is available or To enable transmission, circuit elements such as wiring, resistors, diodes, and transistors are used. This category also includes situations where the connection is indirect.

[0049] Then, the first row 102-1 is positioned between multiple wires 103 and multiple wires 104. The second column 102-2 is located between multiple wires 106 and multiple wires 107. The third column 102-3 is located between multiple wires 105 and multiple wires 109. .

[0050] Furthermore, multiple connections are made to the first output terminal of each LE101 in the second row 102-2. Line 106 is between the first column 102-1 and the second column 102-2, and between the first column 102-1 and In the diagram of Figure 1(A), the column LE101 is located to the left of the first column 102-1 (Figure It is arranged to straddle the space between (not shown). Each LE10 of the third column 102-3 Multiple wires 105 connected to the first output terminal of 1 are in the first row 102-1 and the second row 10 It is positioned to straddle the space between 2-2 and between the second column 102-2 and the third column 102-3. In addition, each L located to the right of the third column 102-3 in the view of Figure 1(A) Multiple wires 108 connected to the first output terminal of E101 (not shown) are in the second row 10 Between 2-2 and the third column 102-3, and between the third column 102-3 and to the right of the third column 102-3 It is positioned to straddle the rows (not shown) of the LE101 that are being placed.

[0051] In other words, if we focus on the Nth column (where N is a natural number greater than or equal to 3), each LE101 in the above column Multiple wires connected to the first output terminal are between the Nth column and the (N-1)th column, and the (N It is positioned so as to straddle the space between column (-1) and column (N-2). Note that N is 2. In this case, the multiple wires connected to the first output terminal of each LE101 in the second row are the second It is positioned to straddle the space between the first column and the first column, and between the first column and the I / O element (IO). The above I / O is used for signal input from outside the PLD to LE101, or from LE101. It functions as an interface that controls the output of signals to the outside of the PLD.

[0052] The positional relationship between row 102, which has LE101 as shown in Figure 1(A), and the various types of wiring is as follows: This corresponds to one example in one embodiment of the present invention. In one aspect of the present invention, LE101 is included. It is sufficient if row 102 and multiple various types of wiring are arranged in parallel.

[0053] Furthermore, in one aspect of the present invention, if we focus on the (N-1)th column (where N is a natural number greater than or equal to 3), then Multiple wires connected to the first output terminal of each LE101 in the row, and the Nth row Multiple wires connected to the first output terminal of each LE101, and each L in the (N-2) row Multiple wires connected to the second output terminal of E101 are connected via the switch circuit 110. Each LE101 in column (N-1) is connected to multiple input terminals.

[0054] Specifically, in the case of Figure 1(A), for example, the first LE101 of each LE101 in the second column 102-2 Multiple wires 106 connected to the output terminal and each LE101 in the third row 102-3 Multiple wires 105 connected to the first output terminal, and each LE10 of the first row 102-1 Multiple wires 104 connected to the second output terminal of 1 are connected via the switch circuit 110. It is connected to multiple input terminals of each LE101 in column 2, 102-2.

[0055] Figure 1(B) shows the multiple wires 104, multiple wires 105, and multiple wires shown in Figure 1(A). The connection between wiring 106 and the multiple input terminals of each LE101 in the second row 102-2. The circuit diagram of the switch circuit 110 that controls the multiple The wiring 111 connects to multiple input terminals of one LE101 in the second row 102-2. They are connected. And the switch circuit 110 has multiple switch circuits 120. Figure 1(C) shows a more specific configuration example of the switch circuit 110 shown in Figure 1(B). The switch circuit 110 shown in Figure 1(B) is, as shown in Figure 1(C), a switch circuit 1 The three switch circuits shown in 20-1, switch circuit 120-2, and switch circuit 120-3 It has road 120.

[0056] Figure 1(C) illustrates a switch circuit 110 corresponding to the three wires 111. Therefore, switch circuit 110 is connected to switch circuit 120-1, switch circuit 120-2, and The diagram shows a case where switch circuit 120-3 has three switch circuits 120. The number of switch circuits 120 in switch circuit 110 is equal to the number of inputs LE101 has It can be determined according to the number of terminals.

[0057] Furthermore, in Figures 1(B) and 1(C), there are multiple wires 104, multiple wires 105, and multiple The diagram shows a switch circuit 110 that controls the connection between wiring 106 and multiple wirings 111. However, in Figure 1(A), a switch circuit 1 controls the connection between multiple wires. 10 shall have a similar configuration.

[0058] Next, Figure 2 shows a more specific configuration example of the switch circuit 110 shown in Figure 1(C). Figure 2 shows multiple wires 104, multiple wires 105, and multiple wires 106, and a switch circuit The connection relationship with path 110 is shown more clearly. As shown in Figure 2, each switch circuit 120 includes all of the multiple wires 104, multiple wires 105, and multiple wires 106, and multiple Controls the connection between one of the wires 111.

[0059] Specifically, in Figure 2, multiple wires 104 are wire 104-1, wire 104-2, wire 10 It has 4-3, and multiple wires 105 are wire 105-1, wire 105-2, wire 105-3 It has a plurality of wires 106, each having wire 106-1, wire 106-2, and wire 106-3. This illustrates the case where... Also, in Figure 2, multiple wires 111 are wire 111-1, wire 1 11-2 illustrates the case where wiring 111-3 is present.

[0060] Then, in Figure 2, the switch circuit 120-1 is connected to multiple wires 104, multiple wires 105, And controls the connection between all of the multiple wires 106 and wire 111-1. Specifically, The switch circuit 120-1 consists of multiple wires 104, multiple wires 105, and multiple wires 106 From among them, select one wiring according to the configuration data, and the selected one It has the function of connecting the wiring and wiring 111-1.

[0061] Furthermore, the switch circuit 120-2 has multiple wires 104, multiple wires 105, and multiple wiring Controls the connection between all of line 106 and wiring 111-2. Specifically, the switch circuit 120-2 is one of the multiple wires 104, multiple wires 105, and multiple wires 106. Select the wiring according to the configuration data, and the selected wiring and wiring It has the function of connecting to 111-2.

[0062] Furthermore, the switch circuit 120-3 has multiple wires 104, multiple wires 105, and multiple wiring Controls the connection between all of line 106 and wiring 111-3. Specifically, the switch circuit 120-3 is one of the multiple wires 104, multiple wires 105, and multiple wires 106. Select the wiring according to the configuration data, and the selected wiring and wiring It has the function of connecting to 111-3.

[0063] <Example of a switch circuit configuration> Next, an example of the configuration of the switch circuit 120 will be described. Figure 3 shows one aspect of the present invention. The configuration of the switch circuit 120 is illustrated below. The switch circuit 120 consists of a switch 131 and a switch There are multiple sets, each having at least one switch 130. In Figure 3, each of the above sets is shown in cell 14 It is shown as 0. In Figure 3, the switch circuit 120 is connected to cell 140-1 to cell 140- This example illustrates the case where there are multiple cells, 140 in total, denoted by n (where n is a natural number).

[0064] Switch 131 contains configuration data to the node FD in cell 140. It has a function to control the supply of potential to the signal. Specifically, when switch 131 is in a conductive state When (ON), the signal containing the configuration data given to wiring 121 The potential is supplied to node FD. Also, switch 131 is in a non-conductive state (off). At that time, the potential of node FD is maintained.

[0065] The selection of a conductive or non-conductive state in switch 131 is determined by the signal given to wiring 122. This is done according to the potential of the number. In Figure 3, in cells 140-1 to 140-n, The selection of the conductive or non-conductive state of switch 131 is determined by the wiring 122-1 to wiring 122-n If this is done according to the potential of the signal applied to each of the multiple wires 122 shown, This is an example.

[0066] Switch 130 controls the electrical connection between wire 123 and wire 111 according to the potential of node FD. It has a function to control the following. Specifically, when switch 130 is in a conductive state, wiring 12 3 and wiring 111 are electrically connected. Also, when switch 130 is in a non-conductive state. Therefore, wiring 123 and wiring 111 are electrically isolated. In Figure 3, cell 140-1 In cell 140-n, switch 130 is connected to wiring 123-1 through wiring 123-n. When controlling the electrical connections between the multiple wires 123 and wire 111, respectively: This is an example.

[0067] Note that wiring 123 is electrically connected to the output terminals of LE and IO, and wiring 111 is It is electrically connected to the LE and IO input terminals. Therefore, configuration data According to the instructions, in at least one of cells 140-1 to 140-n, switch 13 When 0 becomes conductive, multiple wires 1, indicated by wires 123-1 to 123-n, become conductive. At least one of the 23, i.e., at least one of the LE or IO output terminals, is a switch. Selected by circuit 120, the selected output terminal is connected to wiring 111, i.e., LE or It will be electrically connected to the I / O input terminal.

[0068] In this specification, "input terminal" refers to a node such as a wire to which an input signal is applied. The potential, voltage, current, etc. of the input signal are supplied to the circuit via this node. The wiring electrically connected to the power terminals can also be considered part of the input terminals. In this specification, "output terminal" means a node such as wiring to which an output signal is supplied. The potential, voltage, current, etc. of the output signal are output from the circuit via this node. The wiring electrically connected to the terminal can also be considered part of the output terminal.

[0069] Furthermore, in one aspect of the present invention, the PLD100 is provided with wiring 111 and a predetermined potential. A switch 126 is provided to control the electrical connection with the wiring 125. Switch 126 performs switching according to the signal INIT. Specifically, switch 126 is conductive. When this state is reached, the potential of wiring 125 is applied to wiring 111, and switch 126 is in a non-conductive state. In this case, the potential of wiring 125 is not supplied to wiring 111.

[0070] In one aspect of the present invention, by making the switch 126 conductive, the potential of the wiring 111 is predetermined It can be initialized to the height of [value]. Note that the potential of wiring 111 and wiring 123 is P The LD100 tends to enter an unstable state after its power is cut off. Also, when the PLD's power is cut off... Afterwards, depending on the configuration of the memory elements in the configuration memory, Simulation data may be lost. In this case, when power is turned on to the PLD, distribution The wire 111 and the multiple wires 123 become electrically connected via the switch circuit 120, and wire 11 If the potential is different between wire 1 and multiple wires 123, a large amount of current will flow through these wires. Yes. However, in one aspect of the present invention, as described above, the potential of the wiring 111 is initialized. This prevents a large amount of current from flowing between wire 111 and multiple wires 123. This can be done. This prevents damage to the PLD.

[0071] Furthermore, immediately after power is turned on to the PLD100, the input terminal of the LE101 is high level and Sometimes the potential becomes an intermediate level between low levels. When applied, a shoot-through current is likely to occur in the CMOS circuit of the LE101. However, Furthermore, in one aspect of the present invention, as described above, the potential of the wiring 111 can be initialized. Therefore, to prevent the input terminal of the LE101 from becoming an intermediate potential immediately after the power is turned on... This is possible, and therefore, the above-mentioned through-current can be prevented.

[0072] Furthermore, in one aspect of the present invention, power is supplied to the PLD100, and wiring After initializing the potential of 111, all cells 140 of the switch circuit 120 are switched Configure the switch 130 to be in a non-conductive state. It is also possible to write to the memory. With the above configuration, wiring 111 and multiple wiring Since the wire 123 can be electrically isolated, the wiring 111 and the multiple wires 123 can be separated. When the potentials are different, a large amount of current flows through these wires via the switch circuit 120. This can be prevented. This will prevent damage to the PLD100. can.

[0073] Note that the switch circuit 120 shown in Figure 3 is used as the switch circuit 120-1 shown in Figure 2. In this case, the multiple wires 104, multiple wires 105, and multiple wires 106 shown in Figure 2 are as shown in Figure 3 This corresponds to wiring 123-1 to wiring 123-n shown in Figure 2, and wiring 111-1 shown in Figure 3 This corresponds to the wiring 111 shown.

[0074] Furthermore, the switch circuit 120 shown in Figure 3 is used as the switch circuit 120-2 shown in Figure 2. In this case, the multiple wires 104, multiple wires 105, and multiple wires 106 shown in Figure 2 are as shown in Figure 3 The wiring shown corresponds to wiring 123-1 to 123-n, and the wiring shown in Figure 2 corresponds to wiring 111-2 in Figure 3. This corresponds to the wiring 111 shown.

[0075] Furthermore, the switch circuit 120 shown in Figure 3 is used as the switch circuit 120-3 shown in Figure 2. In this case, the multiple wires 104, multiple wires 105, and multiple wires 106 shown in Figure 2 are as shown in Figure 3 The wiring shown corresponds to wiring 123-1 to 123-n, and the wiring shown in Figure 2 corresponds to wiring 111-3 in Figure 3. This corresponds to the wiring 111 shown.

[0076] As described above, in one aspect of the present invention, wiring electrically connected to the output terminal of LE101 Among multiple wires such as wire 104, wire 105, and wire 106, configure one wire. Select according to the configuration data, and connect the selected wiring to the input terminal of the LE101. The wires that are directly connected, such as the wire 111, are electrically connected by the switch circuit 120. Connect. And, in one aspect of the present invention, a switch circuit 120 having the above configuration is included. The switch circuit 110 and the various wirings whose electrical connections are controlled by the switch circuit 110. LE101 such as the first column 102-1, the second column 102-2, the third column 102-3, etc. By providing it between the columns including, in PLD100 shown in Figure 1(A), the second column 102 The electricity of one LE101 in row -2 and another LE101 in row 2 102-2 The typical connection can be controlled by a single switch circuit 120. Also, the first row 10 The electrical relationship between the first LE101 in 2-1 and the first LE101 in the second row 102-2 The connection can be controlled by a single switch circuit 120. Also, the second row 102- Electrical connection between one LE101 in 2 and one LE101 in the third row 102-3 This can be controlled by a single switch circuit 120. Therefore, in one aspect of the present invention, , increasing the design flexibility in PLD100, and the switch circuits included in the wiring resources. This can reduce the number of them.

[0077] <Specific example of switch circuit configuration 1> Next, a specific example of the configuration of the switch circuit 120 shown in Figure 3 will be described. Figure 4 shows, The circuit configuration of the switch circuit 120 is shown as an example. The switch circuit 120 is wired or terminal A transistor 130t controls the electrical connection between the child units, and a configuration The amount of charge determined by the data is supplied and held at the gate of transistor 130t. It has multiple sets of transistors 131t with extremely low off-currents for dissipation.

[0078] In Figure 4, each of the above sets is shown as cell 140. The switch circuit 120 shown in Figure 4 is Cells corresponding to multiple wires 104, multiple wires 105, and multiple wires 106, respectively. 140 is provided. Note that in Figure 2, there are multiple wires 104, multiple wires 105, and Since Figure 4 illustrates a case where the total number of wires 106 is 9, the configuration in Figure 4 matches that of Figure 2. In addition, the switch circuit 120 consists of 9 cells, from cell 140-1 to cell 140-9. It has 40 and corresponds to multiple wirings 104, multiple wirings 105, and multiple wirings 106 An example is given where there are nine wires 123 (wires 123-1 to 123-9).

[0079] And each cell 140 has transistors 130t and 131t, in addition to It has a capacitive element 132 connected to the gate of the transistor 130t. 32 has the function of holding the charge stored in the gate of transistor 130t, as well as the transistor While keeping the gate of transistor 130t floating, the change in potential of wiring 127 is controlled by the transistor It has the function of adding to the gate potential of 130t.

[0080] Specifically, the source and drain of transistor 130t are connected to wiring 111, one of which is connected to the source and drain. The other party is connected to one of the multiple wires 104, multiple wires 105, and multiple wires 106. It is connected to wire 123, which corresponds to wire 1. Transistor 131t has The source and drain are connected as follows: one is connected to the gate of transistor 130t, and the other to wiring 1. It is connected to 21. The gate of transistor 131t is connected to multiple wires 122 (wire 12 It is connected to one of the wirings 2-1 to 122-9). The pair of electrical components of the capacitive element 132 One end of the pole is connected to one of several wires 127 (wires 127-1 to 127-9). The other end is connected to the gate of transistor 130t.

[0081] The source of a transistor is the source region, which is a part of the semiconductor film that functions as the active layer. This refers to a region, or a source electrode electrically connected to the above semiconductor film. Similarly, transient The drain of a stylus is a drain region that is part of the semiconductor film that functions as the active layer, or This refers to the drain electrode electrically connected to the semiconductor film mentioned above. The gate, on the other hand, refers to the gate electrode. It means...

[0082] The source and drain of a transistor are supplied to the channel and each terminal of the transistor. The name changes depending on the level of the potential being generated. Generally, n-channel type transients In a stator, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the dot. It is called rain. Also, in p-channel transistors, the terminal to which a low potential is applied is The terminal to which a high potential is applied is called the source, and is called the drain. Above, assuming the source and drain are fixed, we will explain the connection relationship of the transistor. Although it may be clarified in some cases, in practice the names of source and drain are assigned according to the potential relationship described above. It will change.

[0083] Cell 140 can be used as needed to include transistors, diodes, resistors, capacitive elements, and industrial components. It may also have other circuit elements such as kuta.

[0084] Next, regarding an example of the operation of the switch circuit 120 shown in Figure 4, the timing shown in Figure 5 is used. This will be explained using a chart. However, in the timing chart shown in Figure 5, the transistor This example illustrates the case where transistors 130t and 131t are of the n-channel type.

[0085] First, the first configuration data is processed at times T1 to T6. Let me explain the writing process. Between time T1 and time T6, the wiring 127 has a ground potential G Assume that ND is given.

[0086] Between time T1 and time T2, among the multiple wires 122, wire 122-1 is at ground potential. It provides a high-level potential VDD that is higher than GND, and the other wire 122 is connected to ground potential GND. It provides a low-level potential VSS that is lower than the given value. It also provides a potential VSS to wiring 121. As a result of the above operation, the gate (FD1) of transistor 130t in cell 140-1 has A potential VSS is given. Therefore, cell 140-1 corresponds to the digital value "0". Configuration data is stored there.

[0087] Between time T3 and time T4, among the multiple wirings 122, wiring 122-2 has a high level The wire 122 is given a potential VDD, and a low-level potential VSS. A high level of potential VDD is applied to 121. As a result of the above operation, the to The gate (FD2) of the 130t transistor is given a potential VDD. Therefore, cell 1 40-2 stores configuration data corresponding to the digital value "1". ru.

[0088] Between time T5 and time T6, among the multiple wirings 122, wiring 122-3 has a high level The wire 122 is given a potential VDD, and a low-level potential VSS. A potential VSS is applied to 121. Through the above operation, transistor 1 of cell 140-3 is activated. The 30t gate (FD3) is given a potential VSS. Therefore, cell 140-3 Configuration data corresponding to the digital value "0" is stored.

[0089] In addition, the timing chart shown in Figure 5 shows the connections to cells 140-1 through 140-3. This only shows the first write of the figuring data, but cell 140-4 Similarly, the first write of configuration data to cells 140-9 is performed in the same manner. However, among cells 140-1 to 140-9, the first write operation results in a value of "1". There is only one cell 140 where configuration data corresponding to the digital value is stored. That is the case.

[0090] Next, the configuration data stored in cell 140 by the first write operation is The switching of the first logic circuit, which is performed accordingly, will now be explained.

[0091] Between times T7 and T8, a high-level potential VDD is applied to wiring 127. Between time T7 and time T8, in cell 140-1, transistor 130t is in a non-conductive state. In cell 140-2, transistor 130t is in a conductive state, and in cell 140-3, transistor 130t is in a non-conductive state. Therefore, wiring 123-2 and wiring 111 are in a conductive state. Then, the potential of wiring 123-2 is applied to wiring 111. Specifically, the timing shown in Figure 5 The chart illustrates the case where the potential VDD is applied to wiring 111.

[0092] Next, the configuration data is processed between time T8 and time T13. Let's explain the writing of item 2. Between time T8 and time T13, wiring 127 is connected to ground. Assume that a potential GND is provided.

[0093] Between time T8 and time T9, among the multiple wirings 122, wiring 122-1 has a high level The wire 122 is given a potential VDD, and a low-level potential VSS. A high level of potential VDD is applied to 121. As a result of the above operation, the to The gate (FD1) of the 130t transistor is given a potential VDD. Therefore, cell 1 40-1 stores configuration data corresponding to the digital value "1". ru.

[0094] Between time T10 and time T11, among the multiple wirings 122, wiring 122-2 has a high frequency The bell is given a potential VDD, and the other wire 122 is given a low-level potential VSS. Also, A potential VSS is applied to wiring 121. As a result of the above operation, the transistors of cell 140-2 The gate (FD2) of the 130t cell is given a potential VSS. Therefore, cell 140-2 This stores configuration data corresponding to the digital value "0".

[0095] Between time T12 and time T13, among the multiple wirings 122, wiring 122-3 has a high frequency The bell is given a potential VDD, and the other wire 122 is given a low-level potential VSS. Also, A potential VSS is applied to wiring 121. As a result of the above operation, the transistors of cell 140-3 The gate (FD3) of the 130t cell is given a potential VSS. Therefore, cell 140-3 This stores configuration data corresponding to the digital value "0".

[0096] In addition, the timing chart shown in Figure 5 shows the connections to cells 140-1 through 140-3. This only shows the second write of the figuring data, but cell 140-4 Similarly, the second write of configuration data to cells 140-9 is performed in the same manner. However, among cells 140-1 to 140-9, the second write operation results in a value of "1". There is only one cell 140 where configuration data corresponding to the digital value is stored. That is the case.

[0097] Next, the configuration data stored in cell 140 is written in the second write operation. The subsequent switching of the second logic circuit will now be explained.

[0098] Between times T14 and T15, a high-level potential VDD is applied to wiring 127. Between time T14 and time T15, transistor 130t conducts in cell 140-1. In the current state, in cell 140-2, transistor 130t is in a non-conductive state, and in cell 140-3, The inverter 130t is in a non-conductive state. Therefore, wiring 123-1 and wiring 111 are in a conductive state. This state occurs, and the potential of wiring 123-1 is applied to wiring 111. Specifically, as shown in Figure 5, The timing chart illustrates the case where the ground potential GND is applied to wiring 111.

[0099] Note that when writing configuration data, wiring 123-1 to wiring 123 It is desirable to keep the potential of -9 and the potential of wiring 111 at the same level. During the writing of configuration data, transistor 130t becomes conductive. However, excessive current flows through transistor 130t through wiring 123-1 to wiring 123-9 This prevents current from flowing between either of them and wiring 111.

[0100] Furthermore, it is preferable to maintain the potential of the wiring 111 at a predetermined height using a latch circuit or the like. The above configuration prevents the potential of wiring 111 from becoming unstable, and wiring 111 In an LE where a potential is applied to the input terminal, it is possible to prevent excessive current from being generated. Cut.

[0101] As described above, according to the configuration data, the switch circuit 120 has When any one of the above multiple cells 140 becomes conductive, the switch circuit 120 is activated. Then, the connection structure between one of the multiple wires 123 and wire 111 is determined.

[0102] In one aspect of the present invention, with the above configuration, in the PLD 100 shown in FIG. 1(A), a first LE 101 included in the second column 102-2 and another first LE 1 01 can be controlled by one switch circuit 120 for electrical connection. Also, the first LE 101 included in column 102-1 and the first LE 101 included in column 102-2 can be controlled by one switch circuit 120 for electrical connection. Also, the first LE 101 included in column 102-2 and the first LE 101 included in column 102-3 can be controlled by one switch circuit 120 for electrical connection. Thus, in one aspect of the present invention, while increasing the design freedom in the PLD 100, the number of switch circuits included in the wiring resources can be suppressed.

[0103] Note that the transistor 131t having an extremely small off-current has a channel formation region formed in a semiconductor film having a wider bandgap than silicon and a lower intrinsic carrier density than silicon. Such a semiconductor includes, for example, an oxide semiconductor, silicon carbide, gallium nitride, etc., having a bandgap more than twice that of silicon.

[0104] The transistor having such a semiconductor can make the off-current extremely small compared to a transistor formed of a semiconductor such as ordinary silicon or germanium. Thus, by using the transistor 131t having the above configuration, it is possible to prevent the charge held in the gate of the transistor 130t that controls the electrical connection between the wirings or terminals from leaking.

[0105] In the switch circuit 120 having the above configuration, according to the configuration data, the distribution The conduction state of transistor 130t, which controls the electrical connection between wires or terminals, is determined. Therefore, the above conduction state is maintained by transistor 131t, which has an extremely small off-current. Therefore, in one aspect of the present invention, the switch circuit 110 has a configuration memory and It combines the functions of a memory element with the functions of a memory element, and each cell has 14 The number of zero elements is smaller than that of SRAM. Therefore, configuration memory and Compared to conventional PLD configurations that include both a Mori element and a configuration day The area required for the memory device used to store the data can be kept small.

[0105] Furthermore, the off-current of the transistor 131t is due to the presence of a channel formation region in the silicon film. Because it is smaller than a transistor, the data retention time in the switch circuit 110 is DRA It can be made longer than M. Therefore, the frequency of data rewriting can be reduced, and This allows for lower power consumption.

[0106] <Specific example of switch circuit configuration 2> Next, a specific example of the configuration of the switch circuit 120 shown in Figure 3 will be described. The switch circuit 120 includes a transistor 131t that functions as a switch 131, and a switch A transistor 130t functions as a switch 130, and an electric current is supplied to the gate of transistor 130t. The system has multiple cells 140, each having a capacitive element 132 that is electrically connected. Specifically, see Figure 6. So, the n cells 140, represented by cells 140-1 through 140-n, are used in a switch circuit. This example illustrates the case where 120 is present.

[0107] Specifically, the gate of transistor 131t is electrically connected to wiring 122. Also, one of the source and drain of transistor 131t is electrically connected to wiring 121 and the other is electrically connected to the gate of transistor 130t. One of the source and drain of transistor 130t is electrically connected to wiring 123 and the other is electrically connected to wiring 1 11.

[0108] One of the pair of electrodes of capacitor element 132 is electrically connected to the gate of transistor 130t and the other is electrically connected to one of the plurality of wirings 12 7 indicated by wirings 127-1 to 127-n. In addition to the function of holding the charge stored in node FD, capacitor element 132 has a function of adding the change in the potential of wiring 127 to the potential of node FD while keeping node FD in a floating state.

[0109] Cell 140 may further include other circuit elements such as transistors, diodes, resistor elements, capacitor elements, and inductors as required.

[0110] <Example of Operation of Switching Circuit> Next, an example of the operation of the switching circuit 120 shown in FIG. 6 will be described using the timing chart shown in FIG. 7. However, in the timing chart shown in FIG. 7, the case where transistors 131t and 130t are n-channel type is illustrated. However, it is assumed that a low-level potential VSS lower than the ground potential GND is applied to wiring 125.

[0111] First, after power is applied to the PLD, the operations performed at times T1 to T8 on wiring 111 This section explains the initialization of the potential and the potential of node FD.

[0112] Before time T1, it is immediately after power is turned on to the PLD, so there are multiple wires 123 and wires The potential of 111 is in an undefined state, and the potential of node FD of each cell 140 is also in an undefined state. Let's assume this. In Figure 7, the period during which the potential is in an indeterminate state is indicated by a shaded area.

[0113] Between time T1 and time T8, the signal INI is input to the gate of transistor 126t. The potential of T becomes high, and transistor 126t becomes conductive. Therefore, The potential VSS is applied to the wiring 111 via the zista 126t. Note that the PLD is powered by Simultaneously with the power being turned on, the potential of signal INIT is set to a high level, thereby changing the potential of wiring 111. The period during which the potential is uncertain can be further shortened. In one aspect of the present invention, the potential of the wiring 111 is By applying VSS, the potential of wiring 111 can be initialized, so the input terminal of LE The child does not enter an indeterminate state, and in the CMOS circuit of the LE, shoot-through current can be prevented. This prevents damage to the PLD. Also, time T1 At time T8, by providing ground potential GND to wiring 127, the wiring 123 is connected to wiring 127. This prevents electrical contact with wire 111, and even if the potentials of wiring 123 and wiring 111 are different, wiring 1 This can suppress the flow of a large amount of current between 23 and wiring 111.

[0114] Then, from time T1 to time T8, the potential VSS is applied to the wiring 111. Then, initialize the potential of all 140 cells' node FDs. Specifically, in Figure 7, first, Between time T2 and time T3, among the multiple wires 122, wire 122-1 has a ground potential G A high-level potential VDD is given, which is higher than ND, and the other wiring 122 has a potential VSS. It is given. Also, the potential VSS is applied to the wiring 121. Due to the above operation, cell 140 At -1, a potential VSS is applied to node FD1, so transistor 130t is non-conductive. This is the state it is in.

[0115] Next, at times T4 to T5, among the multiple wirings 122, wiring 122-2, A high-level potential VDD, which is higher than the ground potential GND, is applied to the other wiring 122, and electricity A potential VSS is applied. Also, a potential VSS is applied to wiring 121. Due to the above operation, In cell 140-2, a potential VSS is applied to node FD2, so transistor 130 t becomes a non-conductive state.

[0116] Next, at times T6 to T7, among the multiple wirings 122, wiring 122-3, A high-level potential VDD, which is higher than the ground potential GND, is applied to the other wiring 122, and electricity A potential VSS is applied. Also, a potential VSS is applied to wiring 121. Due to the above operation, In cell 140-3, a potential VSS is applied to node FD3, so transistor 130 t becomes a non-conductive state.

[0117] In the timing chart shown in Figure 7, cells 140-1 to 140-3 This only shows the initialization of the potential of node FD, but cells 140-4 to cell 140- The initialization of the potential of node FD at n is performed in the same manner. Through the above series of operations, all cells At 140, the potential of node FD is initialized, and transistor 130t is in a non-conductive state. Yes.

[0118] Next, at time T8, the potential of signal INIT becomes low, and transistor 12 6t will be in a non-conductive state.

[0119] Next, the configuration data will be written at times T9 to T15. Let's explain the input. Between time T9 and time T15, wiring 127 has ground potential G Assume that ND is given. Also, between time T9 and time T15, signal INI The potential of T remains at a low level, and transistor 126t remains in a non-conducting state.

[0120] First, between time T9 and time T10, among the multiple wirings 122, wiring 122-1 is A low-level potential VDD is applied, and a low-level potential VSS is applied to the other wiring 122. Furthermore, a high-level potential VDD is applied to wiring 121. Due to the above operation, the cell In 140-1, the potential VDD is applied to node FD1. That is, cell 140-1 is This indicates that configuration data corresponding to the digital value "1" is stored. It can be said that...

[0121] Next, between time T11 and time T12, among the multiple wirings 122, wiring 122-2 A high-level potential VDD is applied to the first wire 122, while a low-level potential VSS is applied to the other wire 122. It can be obtained. Also, a low-level potential VSS is applied to the wiring 121. Due to the above operation, In cell 140-2, the potential VSS is applied to node FD2. That is, cell 140- 2 is in a state where configuration data corresponding to the digital value "0" is stored. It can be said that it is possible.

[0122] Next, at times T13 to T14, among the multiple wirings 122, wiring 122-3 A high-level potential VDD is applied to the first wire 122, while a low-level potential VSS is applied to the other wire 122. It can be obtained. Also, a low-level potential VSS is applied to the wiring 121. Due to the above operation, In cell 140-3, the potential VSS is applied to node FD3. That is, cell 140- 3 is in a state where configuration data corresponding to the digital value "0" is stored. It can be said that it is possible.

[0123] In addition, the timing chart shown in Figure 7 shows the connections to cells 140-1 through 140-3. This only shows how to write figuration data, but cells 140-4 and beyond Writing configuration data to the Ru140-n is done in the same way. However, Among the cells 140-1 to 140-n, the digital value corresponding to "1" is written. There is only one cell 140 where the configuration data is stored.

[0124] Next, according to the configuration data stored in cell 140 by writing This section explains the switching of logic circuits.

[0125] Between times T15 and T16, a high-level potential VDD is applied to wiring 127. Then, the potential difference between the ground potential GND and the potential VDD is added to node FD of each cell 140. That is, at time T9 to time T15, the configuration corresponding to the digital value "1" Only in cell 140, where the OC data is stored, does the potential of node FD become sufficiently high. Transistor 130t becomes conductive. Specifically, the timing chart shown in Figure 7 In this case, at times T9 to T15, cell 140-1 corresponds to the digital value "1". Since the configuration data is stored, the power of wiring 123-1 and wiring 111 The transistor 130t, which controls the electrical connection, becomes conductive, and the potential of the wiring 123-1 It is supplied to wiring 111 via transistor 130t.

[0126] As described above, according to the configuration data, the switch circuit 120 has When any one of the above multiple cells 140 becomes conductive, the switch circuit 120 is activated. Then, the connection structure between one of the multiple wirings 123 and wiring 111 is determined.

[0127] Figure 7 illustrates the case where the potential of node FD is initialized sequentially for each cell 140. However, the potential of node FD may be initialized simultaneously in all 140 cells.

[0128] <Specific example of switch circuit configuration 3> Next, we will discuss another specific configuration example of the switch circuit 120 shown in Figure 3, which differs from that shown in Figure 4. I will explain.

[0129] Figure 8 shows an example of the circuit configuration of the switch circuit 120. The switch circuit 120 is wired Alternatively, transistor 130t controls the electrical connection between terminals, and configuration The amount of charge determined by the data is supplied to the gate of transistor 130t. A transistor 131t with extremely low off-current for supplying, holding, and releasing, and It has multiple sets of transistors 133t connected in series with transistor 130t.

[0130] In this specification, the state in which transistors are connected in series means, for example, the first Only one of the sources or drains of the first transistor, or the source of the second transistor This means that only one of the drains is connected. Also, when the transistors are connected in parallel... The state in which the transistor is connected is when either the source or drain of the first transistor is connected to the second transistor. Connected to either the source or drain of the first transistor, and the source or The other side of the drain is connected to the source or the other side of the drain of the second transistor. It means "state" or "attitude."

[0131] In Figure 8, each of the above sets is illustrated as cell 140. The switch circuit 120 shown in Figure 8 includes: Cell 1 corresponding to multiple wires 104, multiple wires 105, and multiple wires 106, respectively. 40 is provided. Note that in Figure 2, multiple wires 104, multiple wires 105, and multiple Since the example shows a case where the total number of wires 106 is 9, Figure 8 does not match the configuration in Figure 2. Then, the switch circuit 120 consists of 9 cells 140-1 to 140-9. Wiring having 0, corresponding to multiple wires 104, multiple wires 105, and multiple wires 106 Let's take the example of a case where there are nine 123s.

[0132] Specifically, the source and drain of transistor 133t are connected to wiring 111, one of which is connected to the source and drain. The other end is connected to one of the source and drain of transistor 130t. It is. The source and drain of transistor 130t are connected to multiple wires 123( It is connected to one of the wirings 123-1 to 123-9. Transistor 131t The source and drain of the transistor are connected, one of which is connected to the gate of transistor 130t, and the other is connected to the gate of transistor 130t. It is connected to wiring 121. The gate of transistor 131t is connected to multiple wirings 122( It is connected to one of the wires (122-1 to 122-9). Transistor 133t The gate is connected to one of several wires 128 (wires 128-1 to 128-9). Yes, they are.

[0133] Cell 140 can be used as needed to include transistors, diodes, resistors, capacitive elements, and industrial components. It may also have other circuit elements such as kuta.

[0134] The operation of the switch circuit 120 shown in Figure 8 can be described by referring to the timing chart shown in Figure 5. This is possible. However, in the timing chart shown in Figure 5, transistor 130t, This corresponds to the case where transistor 131t and transistor 133t are of the n-channel type.

[0135] <Specific example of switch circuit configuration 4> Next, we will describe a different configuration example of the switch circuit 120 shown in Figure 3 from that shown in Figure 6. The switch circuit 120 shown in Figure 9 consists of transistor 131t and transistor 130t, It has multiple cells 140, each having a transistor 133t. Specifically, in Figure 9, A switch circuit 120 has n cells 140, represented by cells 140-1 to 140-n. This provides an example of what to do.

[0136] Transistor 131t sends a signal containing configuration data to node FD. It has a function to control the supply of potential. Transistor 130t is controlled according to the potential of node FD. Then, a conductive or non-conductive state is selected. Transistor 133t is connected to wiring 128 Depending on the potential, a conductive or non-conductive state is selected. And transistor 130t And transistor 133t is connected in series, together with wiring 123 and wiring 111 It has the function of controlling electrical connections.

[0137] Specifically, transistor 131t has its gate electrically connected to wiring 122. Furthermore, the source and drain of transistor 131t are electrically connected to wiring 121 on one side. The other end is connected to the gate of transistor 130t. The source and drain of the 130t are electrically connected to wiring 123 on one side and to the other side. It is electrically connected to either the source or drain of transistor 133t. The source and drain of the 33t are electrically connected to wiring 111. The gate of the 133t platform is electrically connected to wiring 128.

[0138] Cell 140 can be used as needed to include transistors, diodes, resistors, capacitive elements, and industrial components. It may also have other circuit elements such as kuta.

[0139] <Example 5 of a specific switch circuit configuration> Next, using the circuit configuration of the switch circuit 120 shown in Figure 2 as an example, the switch circuit 120 Next, we will explain another specific configuration example that differs from Figure 4.

[0140] Figure 10 shows an example of the circuit configuration of the switch circuit 120. The switch circuit shown in Figure 10 120 is similar to the switch circuit 120 shown in Figure 8, in that it is an electrical connection between wiring or terminals. A transistor 130t controls the connection, and the configuration data is determined To supply, hold, and release the amount of charge at the gate of transistor 130t, A transistor 131t with extremely low current and a transistor 130t are connected in series. It has multiple sets of transistors 133t. However, in Figure 10, there are multiple wirings 104. In cases where two sets are provided for each of the multiple wires 105 and multiple wires 106 This illustrates the combination.

[0141] In Figure 10, each of the above sets is shown as cell 140. The switch circuit 120 shown in Figure 10 These correspond to multiple wires 104, multiple wires 105, and multiple wires 106, respectively. A cell 140 is provided. Note that in Figure 2, multiple wires 104 and multiple wires 10 5. Since the example shows the case where the total number of wires 106 is 9, Figure 10 is shown in Figure 2. In accordance with the configuration, the switch circuit 120 is located from cell 140-1 to cell 140-18. It has 18 cells 140, a plurality of wirings 104, a plurality of wirings 105, and a plurality of wirings 10 Let's take an example where there are nine wires 123 corresponding to 6.

[0142] Furthermore, each of the multiple wires 104, multiple wires 105, and multiple wires 106 corresponds to The number of cells 140 is not limited to two. Three or more cells 140 can be used in multiple wiring configurations. It may correspond to each of the following: 104, multiple wires 105, and multiple wires 106.

[0143] Specifically, in Figure 10, two of the multiple cells 140 are connected to multiple wirings 123 It is connected to one of them. For example, in the case of cells 140-1 and 140-2, two traces The source and drain of the inverter 130t are both connected to wiring 123-1. It is.

[0144] Cell 140 can be used as needed to include transistors, diodes, resistors, capacitive elements, and industrial components. It may also have other circuit elements such as kuta.

[0145] In Figures 8 and 10, transistor 133t has the same properties as transistor 130t. This example illustrates a case where one of the drains and the other is electrically connected to the wiring 111. Transistor 133t has the same source and drain as transistor 130t. It may also be electrically connected to one of the multiple wires 123.

[0146] Next, regarding an example of the operation of the switch circuit 120 shown in Figure 10, the timing shown in Figure 11 This will be explained using a timing chart. However, in the timing chart shown in Figure 11, The transistor 130t, transistor 131t, and transistor 133t are of the n-channel type. This provides examples of situations where this might occur.

[0147] First, the writing of configuration data takes place between time T1 and time T8. Let me explain. Between time T1 and time T8, the multiple wires 128 have ground potential G Given ND, the transistors 133t present in all cells 140 are in a non-conductive state. It shall be considered as such.

[0148] Between time T1 and time T2, among the multiple wirings 122, wiring 122-1 has a high level The wire 122 is given a potential VDD, and a low-level potential VSS. A potential VDD is applied to 121. As a result of the above operation, transistor 1 of cell 140-1 The gate (FD1) of the 30t is given a potential VDD. Therefore, cell 140-1 The first configuration data corresponding to the digital value "1" is stored.

[0149] Between time T3 and time T4, among the multiple wirings 122, wiring 122-2 has a high level The wire 122 is given a potential VDD, and a low-level potential VSS. A potential VSS is applied to 121. Through the above operation, transistor 1 of cell 140-2 is activated. The 30t gate (FD2) is given a potential VSS. Therefore, cell 140-2 A second configuration data corresponding to the digital value "0" is stored.

[0150] Between time T5 and time T6, among the multiple wirings 122, wiring 122-3 has a high level The wire 122 is given a potential VDD, and a low-level potential VSS. A potential VSS is applied to 121. Through the above operation, transistor 1 of cell 140-3 is activated. The 30t gate (FD3) is given a potential VSS. Therefore, cell 140-3 The first configuration data corresponding to the digital value "0" is stored.

[0151] Between time T7 and time T8, among the multiple wirings 122, wiring 122-4 has a high level The wire 122 is given a potential VDD, and a low-level potential VSS. A potential VDD is applied to 121. As a result of the above operation, transistor 1 of cell 140-4 The gate (FD4) of the 30t cell is given a potential VDD. Therefore, cell 140-4 The second configuration data corresponding to the digital value "1" is stored.

[0152] In the timing chart shown in Figure 11, the sequence of cells 140-1 to 140-4 is as follows: For writing 1 configuration data or 2 configuration data Only the first configuration for cells 140-5 to 140-18 is shown, but Writing the configuration data or the second configuration data is done in the same way. Furthermore, multiple cells represented by 140-M (where M is a natural number and an odd number less than or equal to 18) Of the 140 cells, the writing of the first configuration data resulted in a "1" digital There is only one cell 140 where the configuration data corresponding to the value is stored. Also, the complex represented by cell 140-L (where L is a natural number and an even number less than or equal to 18) Of the 140 cells, the writing of the second configuration data resulted in "1". There is only one cell 140 where configuration data corresponding to the digital value is stored. That is the case.

[0153] Next, the first logic circuit is switched according to the first configuration data. Let me explain about "e".

[0154] Between times T9 and T10, multiple wires 128 represented by wire 128-M receive high A level potential VDD is given. Multiple wires 128, represented by wire 128-L, are connected. The ground potential GND is then applied. Then, at times T9 to T10, cell 1 Of the multiple cells 140 represented by 40-M, cell 140-1 is in a conductive state, while the others are Wire 140 is in a non-conductive state. Therefore, wires 123-1 and 111 are in a conductive state. Then, the potential of wiring 123-1 is applied to wiring 111. Specifically, the timing shown in Figure 11 The diagram illustrates the case where the ground potential GND is applied to wiring 111.

[0155] Next, the switching of the second logic circuit is performed according to the second configuration data. Let me explain about "e".

[0156] Between time T11 and time T12, multiple wires 128 represented by wire 128-L are connected. A potential VDD of level 1 is applied. Multiple wires 128 represented by wire 128-M are A ground potential GND is applied. Then, at times T11 to T12, cell 140 Of the multiple cells 140 represented by -L, cell 140-4 is in a conductive state, and the other cells 1 40 is in a non-conductive state. Therefore, wire 123-2 and wire 111 become conductive. The potential of wiring 123-2 is applied to wiring 111. Specifically, the timing shown in Figure 11. The chart illustrates the case where the potential VDD is applied to wiring 111.

[0157] Note that the first configuration data or the second configuration data document When installing, the potential of wiring 123-1 to wiring 123-18 and the potential of wiring 111 are compared. It is desirable to keep them at the same height. With the above configuration, the first configuration data Alternatively, during the writing of the second configuration data, transistor 130t becomes conductive. Even in this state, excessive current flows through transistor 130t through wiring 123-1 to wiring 12 This prevents current from flowing between any of 3-18 and wiring 111.

[0158] Furthermore, it is preferable to maintain the potential of the wiring 111 at a predetermined height using a latch circuit or the like. The above configuration prevents the potential of wiring 111 from becoming unstable, and wiring 111 In an LE where a potential is applied to the input terminal, it is possible to prevent excessive current from being generated. Cut.

[0159] Note that in the case of the switch circuit 120 shown in Figure 10, multiple configuration data It stores the configuration data used for configuration. You can freely select the data. Therefore, one configuration data While operating a PLD with a more defined logic circuit, other configurations The data can be rewritten.

[0160] <Specific example of switch circuit configuration 6> Next, we will describe a different configuration example of the switch circuit 120 shown in Figure 3 from that shown in Figure 6. The switch circuit 120 shown in Figure 12 is similar to the switch circuit 120 shown in Figure 9, and Cell 140 having transistor 131t, transistor 130t, and transistor 133t It has multiple such connections. However, in Figure 12, the two cells 140 share each of the multiple connections 123. This illustrates the configuration of the switch circuit 120.

[0161] Specifically, in Figure 12, there are 2n cells represented by cells 140-1 to 140-2n. The example shows the case where 40 is present in the switch circuit 120. And there are 2n cells 140. Of these, cells 140-i and 140-i+1 (where i is a natural number less than or equal to 2n-1) are distributed Of the lines 123-1 through 123-n, one of the lines 123 is shared.

[0162] Furthermore, the number of cells 140 that share multiple wirings 123 is not limited to two. It can be three or more. Multiple cells 140 may share multiple individual wires 123.

[0163] Specifically, Figure 12 shows the source and drain of transistor 130t in cell 140-1. One side of the input and one of the source and drain of transistor 130t of cell 140-2 This example illustrates the case where both are electrically connected to wiring 123-1.

[0164] Cell 140 can be used as needed to include transistors, diodes, resistors, capacitive elements, and industrial components. It may also have other circuit elements such as kuta.

[0165] In Figures 9 and 12, transistor 133t has the same properties as transistor 130t. An example is when there is an electrical connection between the other end of the drain and the wiring 111. Transistor 133t is one of the source and drains of transistor 130t. One of the wires 123 may be electrically connected to the other.

[0166] In the switch circuit 120 shown in Figure 12, multiple connections are electrically connected to a single wire 123. In cell 140, configuration data corresponding to multiple circuit configurations is entered, It can be stored. And the logical cycle is performed according to the configuration data. The circuit switching is performed by storing configuration data corresponding to one circuit configuration. In cell 140, transistor 133t is set to conduct, corresponding to other circuit configurations. In cell 140 where configuration data is stored, transistor 13 This can be done by making 3t non-conductive.

[0167] Therefore, in the case of the switch circuit 120 shown in Figure 12, multiple configuration days The data is stored, and the configuration used for the configuration You can freely select the data. Therefore, one configuration data While the logic circuit is operating the PLD defined by this, other configurations The data can be rewritten.

[0168] In the case of the aforementioned Patent Document 1, the configuration in the multi-context method To switch the configuration data, it is necessary to read the configuration data from DRAM. For this reason, a sense amplifier is required to read the configuration data. In one aspect of the present invention shown in Figure 10 or Figure 12, a multi-context method is used. And to switch the configuration data, the configuration data is taken from DRAM, etc. There is no need to read the data, and therefore there is no need to use a sense amplifier. No. Therefore, the time required to switch configuration data can be shortened, This allows for high-speed reconfiguration of logic circuits in programmable logic devices. Cut.

[0169] In the switch circuit 120, transistor 131t maintains the potential of node FD. Because it has this function, it is desirable to use a transistor with extremely low off-current. A semiconductor with a wider band gap and lower intrinsic carrier density than silicon. A transistor characterized by the formation of a channel-forming region in the film has a significantly reduced off-current. Because it is small, it is suitable for use as a transistor 131t. Such semiconductor and For example, oxide semiconductors that have a band gap more than twice that of silicon, Examples include gallium nitride. Transistors having the above semiconductors are made of ordinary silicon or Compared to transistors made of semiconductors such as germanium, the off-current is extremely small. Therefore, by using transistor 131t having the above configuration, This prevents the charge held in the FD from leaking out.

[0170] In the switch circuit 120 having the above configuration, according to the configuration data, The conductive or non-conductive state of transistor 130t, which controls the electrical connection between wires. Selected, and by making transistor 131t non-conductive, the above node FD is connected. In this case, the potential of the signal containing the configuration data is maintained. Therefore, the present invention In one embodiment, the switch circuit 120 included in the wiring resource is configured to determine whether it is conducting or not. It has been given the added function of a configuration memory that holds information about the state selection. It can be said that... And, since the number of elements in each cell (140) is smaller than that of SRAM, the configuration... Compared to conventional PLDs that have both ration memory and switches, the configuration The area of ​​the memory can be kept small.

[0171] In particular, multi-context PLDs support configurations for multiple circuit configurations. By storing configuration data in configuration memory, dynamic reconfiguration is achieved. Therefore, multi-context PLDs use dynamic reconfiguration methods such as configuration information distribution methods. Compared to other methods for achieving this, the area occupied by the configuration memory in the PLD However, the switch circuit 120 having the configuration shown in Figure 10 or Figure 12 In the case of a PLD according to one aspect of the present invention using the above, even in a multi-context system, As mentioned above, the area required for configuration memory can be kept small.

[0172] Furthermore, impurities such as water or hydrogen, which act as electron donors, are reduced, and acid Oxide semiconductors with reduced elemental defects (purified OS) It is a type i (intrinsic semiconductor) or very close to type i. Therefore, highly purified oxide semiconductors Transistors with a channel-forming region in the membrane have significantly low off-current and high reliability. Therefore, the above transistor is used as transistor 131t in the switch circuit 120. This allows for a longer data retention period.

[0173] Specifically, a transistor having a channel formation region in a highly purified oxide semiconductor film The small current can be proven through various experiments. For example, if the channel width is 1 × 1 0 6 Even with a μm element and a channel length of 10 μm, the voltage between the source electrode and the drain electrode When the drain voltage is in the range of 1V to 10V, the off-current is measured by the semiconductor parameter analyzer. Below the measurement limit of the riser, i.e., 1 × 10⁻⁶ -13 It is possible to obtain the characteristic of being A or less. In this case, the off-current normalized by the transistor channel width is 100 Hz A / μm or less. It can be seen that there is a capacitive element and a transistor are connected so that the current flows into the capacitive element or The off-current is measured using a circuit that controls the charge flowing out of a capacitive element with the transistor. The measurement was performed using a highly purified oxide semiconductor film as the channel of the transistor. Used in the formation region, the transistor's off state is determined from the change in the amount of charge per unit time of the capacitive element. The current was measured. As a result, the voltage between the source and drain electrodes of the transistor was 3V. In some cases, it was found that even smaller off-currents, such as tens of yA / μm, can be obtained. Therefore Therefore, transistors that use a highly purified oxide semiconductor film in the channel formation region are off-voltage. The current is significantly lower compared to transistors using crystalline silicon.

[0174] Furthermore, among oxide semiconductors, there are In-Ga-Zn oxides, In-Sn-Zn oxides, etc. Unlike silicon carbide, gallium nitride, or gallium oxide, it is produced by sputtering or The wet process makes it possible to fabricate transistors with excellent electrical characteristics, and is highly suitable for mass production. It has advantages such as being able to do so. Also, unlike silicon carbide, gallium nitride, or gallium oxide In contrast, the above oxide semiconductor (In-Ga-Zn-based oxide) is used on a glass substrate or silicon It is possible to fabricate transistors with excellent electrical characteristics on integrated circuits using this technology. Furthermore, it can accommodate larger circuit board sizes.

[0175] Furthermore, the oxide semiconductor contains at least indium (In) or zinc (Zn). It is preferable to do so. Also, variations in the electrical characteristics of transistors using the oxide semiconductor. In addition to those, gallium (Ga) is used as a stabilizer to reduce them. Preferably. Also, it is preferable to have tin (Sn) as a stabilizer. It is preferable to have hafnium (Hf) as a stabilizer. It is preferable to have aluminum (Al) as the stabilizer. Also, it is preferable to have Zirconia as the stabilizer. It is preferable that it contains conium (Zr).

[0176] Also, other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce, praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Lu It may contain one or more types of tecium (Lu).

[0177] For example, as oxide semiconductors, indium oxide, gallium oxide, tin oxide, zinc oxide, I n-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides, S n-Mg oxides, In-Mg oxides, In-Ga oxides, In-Ga-Zn oxides Materials (also written as IGZO), In-Al-Zn oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides, Sn-Al-Zn oxides, I n-Hf-Zn oxides, In-La-Zn oxides, In-Pr-Zn oxides, In -Nd-Zn oxides, In-Sm-Zn oxides, In-Eu-Zn oxides, In- Gd-Zn oxides, In-Tb-Zn oxides, In-Dy-Zn oxides, In-H o-Zn oxides, In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb -Zn oxides, In-Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, In- Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn-Al-Zn In-Sn-Hf-Zn oxides and In-Hf-Al-Zn oxides are used. It is possible.

[0178] For example, an In-Ga-Zn oxide is an oxide containing In, Ga, and Zn. This is about taste, and the ratio of In, Ga, and Zn is not important. Also, metal elements other than In, Ga, and Zn are not considered. It may contain. In-Ga-Zn oxides have sufficiently high resistance in the absence of an electric field and are off-electric. It is possible to significantly reduce the flow rate, and it also has high mobility.

[0179] For example, In:Ga:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn acid with an atomic ratio of a:Zn = 2:2:1 (= 2 / 5:2 / 5:1 / 5) Oxides or oxides with a similar composition can be used. Alternatively, In:Sn:Zn=1 :1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5 (=1 / 4:1 / 8:5 / 8) It is preferable to use In-Sn-Zn oxides with a specific atomic ratio or oxides with a similar composition.

[0180] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. However, Furthermore, even with In-Ga-Zn oxides, mobility can be increased by reducing the bulk defect density. It is possible to do so.

[0181] The structure of oxide semiconductor films will be described below.

[0182] In this specification, "parallel" means that two straight lines are positioned at an angle of -10° or more and 10° or less. This refers to a state where something is positioned vertically. Therefore, it also includes cases where the angle is between -5° and 5°. This refers to a state where two straight lines are positioned at an angle of 80° to 100°. Therefore, This also includes cases where the angle is between 85° and 95°.

[0183] Furthermore, in this specification, if a crystal is trigonal or rhombohedral, it will be represented as a hexagonal crystal system. .

[0184] Oxide semiconductor films are broadly classified into single-crystal oxide semiconductor films and non-single-crystal oxide semiconductor films. Single-crystal oxide semiconductor films include amorphous oxide semiconductor films, microcrystalline oxide semiconductor films, and polycrystalline oxide films. Physical semiconductor film, CAAC-OS (C Axis Aligned Crystalline This refers to oxide semiconductor films, etc.

[0185] Amorphous oxide semiconductor films have an irregular arrangement of atoms within the film and do not contain crystalline components. It is a crystalline semiconductor film. Even in minute regions, it does not have crystalline areas; the entire film has a completely amorphous structure. Oxide semiconductor films are a typical example.

[0186] Microcrystalline oxide semiconductor films are, for example, microcrystals (nanocrystals) with a size of 1 nm to less than 10 nm. It is also called. ) contains. Therefore, microcrystalline oxide semiconductor films are more fundamental than amorphous oxide semiconductor films. The arrangement of the microcrystalline elements is highly regular. Therefore, microcrystalline oxide semiconductor films are superior to amorphous oxide semiconductor films. It also has the characteristic of having a low defect level density.

[0187] CAAC-OS film is one of the oxide semiconductor films having multiple crystalline regions, and most of the bonds The crystal portion is small enough to fit within a cube with sides less than 100 nm. Therefore, CAAC-O The crystalline portion contained in the S film is within a cube with sides less than 10 nm, less than 5 nm, or less than 3 nm. This also includes cases where the size fits within the given space. CAAC-OS films have fewer defects than microcrystalline oxide semiconductor films. It is characterized by a low void density. A detailed explanation of the CAAC-OS membrane follows. .

[0188] CAAC-OS film is scanned using a transmission electron microscope (TEM). When observed with a microscope, clear boundaries between crystalline regions, i.e., bonds, can be seen. The grain boundaries (also called crystal grain boundaries) cannot be identified. Therefore, CA AC-OS films are less susceptible to the decrease in electron mobility caused by grain boundaries.

[0189] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). ) This confirms that metal atoms are arranged in layers in the crystalline region. Each layer has irregularities on the surface (also called the surface to be formed) or the upper surface that forms the CAAC-OS film. The shape reflects this, and the elements are arranged parallel to the surface or top surface of the CAAC-OS film.

[0190] On the other hand, the CAAC-OS film was observed by TEM from a direction roughly perpendicular to the sample surface (planar TEM). (M observation) In the crystalline region, metal atoms are arranged in a triangular or hexagonal shape. This can be confirmed. However, no regularity is observed in the arrangement of metal atoms between different crystalline regions. stomach.

[0191] Cross-sectional TEM observation and planar TEM observation revealed that the crystalline portion of the CAAC-OS film exhibits orientation. You can tell they are there.

[0192] X-ray diffraction (XRD) was applied to the CAAC-OS film. When structural analysis is performed using this method, for example, a CAAC-OS film having InGaZnO4 crystals is found. In the out-of-plane analysis, the diffraction angle (2θ) shows a peak near 31°. This peak may appear. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is generally aligned with the surface to be formed or the upper surface. It can be confirmed that it is facing in a nearly vertical direction.

[0193] On the other hand, in-pl X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis. In analysis using the ANE method, a peak may appear when 2θ is around 56°. This peak is It is attributed to the (110) plane of the InGaZnO4 crystal. Single crystal oxidation of InGaZnO4 For a solid semiconductor film, fix 2θ to around 56°, and use the normal vector of the sample surface as the axis (φ axis). When the analysis (φ scan) is performed while rotating the sample, the crystal plane equivalent to the (110) plane is found. Six attributed peaks are observed. In contrast, in the case of the CAAC-OS film, 2θ is set to 5 Even when fixed at approximately 6° and scanned using the φ scan function, no clear peak appears.

[0194] From the above, it can be concluded that in CAAC-OS films, the orientation of the a-axis and b-axis is inconsistent between different crystalline regions. It is a rule, but it has c-axis orientation and the c-axis is parallel to the normal vector of the surface to be formed or the upper surface. It can be seen that it is facing in a certain direction. Therefore, it is arranged in layers as confirmed by the aforementioned cross-sectional TEM observation. Each layer of arranged metal atoms is a plane parallel to the ab-plane of the crystal.

[0195] The crystalline portion is formed when the CAAC-OS film is deposited, or when crystallization treatment such as heat treatment is performed. It is formed when this occurs. As mentioned above, the c-axis of the crystal is the surface on which the CAAC-OS film is formed or It is oriented in a direction parallel to the normal vector of the upper surface. Therefore, for example, the shape of the CAAC-OS film When the shape is altered by etching or other means, the c-axis of the crystal becomes the surface on which the CAAC-OS film is formed. Alternatively, it may not be parallel to the normal vector of the top surface.

[0196] Furthermore, the degree of crystallinity in the CAAC-OS film does not need to be uniform. For example, the CAAC-OS film When the crystalline portion is formed by crystal growth from near the upper surface of the CAAC-OS film, the upper surface The nearby region may have a higher degree of crystallinity than the region near the surface being formed. Also, CAA When impurities are added to a C-OS film, the degree of crystallinity in the region where the impurities are added changes, and some areas Regions with different degrees of crystallinity may also be formed.

[0197] Furthermore, the out-of-plane method for CAAC-OS films containing InGaZnO4 crystals. Analysis revealed that in addition to a peak near 2θ = 31°, a peak also appeared near 2θ = 36°. In some cases, this may occur. Peaks near 36° 2θ indicate c-axis orientation in a portion of the CAAC-OS film. This indicates that it contains crystals that do not have [the specified characteristic]. The CAAC-OS film has 2θ near 31°. It is preferable that a peak is observed, and that no peak is observed near 36° for 2θ.

[0198] Transistors using CAAC-OS film exhibit changes in electrical properties due to irradiation with visible light and ultraviolet light. Its value is small. Therefore, this transistor is highly reliable.

[0199] Note that oxide semiconductor films include, for example, amorphous oxide semiconductor films, microcrystalline oxide semiconductor films, and CA The AC-OS film may be a multilayer film having two or more types.

[0200] CAAC-OS films are used, for example, for polycrystalline oxide semiconductor sputtering targets. The film is deposited using a sputtering method. Ions are directed onto the sputtering target. Upon collision, the crystalline region contained in the sputtering target cleaves from the ab plane, and a -The sputtering particles are exfoliated as flat or pellet-shaped sputtering particles having a surface parallel to the -b surface. In this case, the flat sputtering particles maintain their crystalline state and form a base By reaching the plate, the CAAC-OS film can be deposited.

[0201] Furthermore, it is preferable to apply the following conditions for forming the CAAC-OS film.

[0202] By reducing the inclusion of impurities during film formation, it is possible to suppress the disruption of the crystalline state due to impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, and nitrogen, etc.) present in the deposition chamber. It would be good to reduce it. Also, it would be good to reduce the impurity concentration in the film formation gas. Specifically, the dew point is A film-forming gas with a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0203] Furthermore, by increasing the substrate heating temperature during film deposition, the sputtering particles can be prevented from migrating after reaching the substrate. A reaction occurs. Specifically, the substrate heating temperature is preferably between 100°C and 740°C. The film is deposited at a temperature between 200°C and 500°C. By increasing the substrate heating temperature during film deposition, the flat When plate-shaped sputtering particles reach the substrate, migration occurs on the substrate. The flat surface of the sputtered particles adheres to the substrate.

[0204] Furthermore, by increasing the oxygen content in the deposition gas and optimizing the power, plasma damage during film deposition can be reduced. It is preferable to reduce this. The oxygen content in the film-forming gas is 30% by volume or more, preferably 100% by volume. Let the product be %.

[0205] As an example of a target for sputtering, an In-Ga-Zn oxide target is used. The following is shown.

[0206] InO X powder, GaO Y Powder and ZnO Z The powder is mixed in a predetermined number of moles and then subjected to pressure treatment. By heat treatment at temperatures between 1000°C and 1500°C, polycrystalline In-Ga - A Zn-based oxide target is used. X, Y, and Z are arbitrary positive numbers. Here, A given molar ratio is, for example, InO X powder, GaO Y Powder and ZnO Z The powder is 2: The ratios are 2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, or 3:1:2. Oh, the type of powder and the molar ratio in which they are mixed are important for the sputtering target being prepared. You can change it as needed depending on the situation.

[0207] Furthermore, semiconductor films are formed using metal oxide targets with different atomic ratios of metals. The multiple oxide semiconductor films may have a stacked structure. For example, The atomic ratio of the first oxide semiconductor film is In:Ga:Zn=1:1:1, and the second layer is acid The ionized semiconductor film may be formed such that In:Ga:Zn = 3:1:2. The atomic ratio of the GET is In:Ga:Zn=1:3:2 for the first oxide semiconductor film, and for the second layer... The first oxide semiconductor film is In:Ga:Zn=3:1:2, and the third oxide semiconductor film is In: It may also be formed such that Ga:Zn = 1:1:1.

[0208] Alternatively, the semiconductor film is formed using multiple metal oxide targets containing different metals. The oxide semiconductor film may have a stacked structure.

[0209] Furthermore, transistor 130t or transistor 133t can be amorphous, microcrystalline, polycrystalline, or It is a single crystal, a semiconductor film such as silicon or germanium having a channel-forming region. A transistor may be used, and like the transistor 131t, it may be made of silicon. In semiconductor films with a wide band gap and a lower intrinsic carrier density than silicon, channel-shaped A transistor having a specific region may be used. As for silicon, plasma CV Amorphous silicon, amorphous silicon produced by vapor phase growth methods such as Method D or by sputtering methods. Polycrystalline silicon and single-crystal silicon are produced by crystallizing silicon through processes such as laser annealing. This involves using single-crystal silicon, etc., obtained by implanting hydrogen ions, etc., into a wafer and then exfoliating the surface layer. can.

[0210] <Example of cell structure> Next, we will describe another configuration example of the switch circuit 120 shown in Figure 3. Figure 13(A An example of cell 140 in the switch circuit 120 is shown in Figure 13(A). 40 is the same as the cell 140 in the switch circuit 120 shown in Figure 9, and is a transistor 13 It has transistor 1t, transistor 130t, and transistor 133t. However, Figure 13( Cell 140 shown in A) has an inverter 180 and an inverter for maintaining the potential of node FD. The configuration differs from that of cell 140 shown in Figure 9 in that a converter 181 is provided.

[0211] Specifically, Figure 13(A) shows the input terminals of inverter 180 and the output terminals of inverter 181. The terminal is electrically connected to node FD, and the output terminal of inverter 180 and inverter It is electrically connected to the input terminal of TA181. In cell 140 shown in Figure 13(A), With the above configuration, the potential of node FD is maintained by inverters 180 and 181. It is possible to possess it.

[0212] Furthermore, the cell 140 shown in Figure 13(A) has a configuration in which two cells share wiring 123. An example is shown in Figure 13(B). Note that in Figure 13(B), two cells 140 are connected by wiring 123. Although the example illustrates a case where the wiring is shared, in one aspect of the present invention, the wiring 123 is shared among three or more multiple It's okay if the number 140 cells are shared.

[0213] Cell 140 shown in Figures 13(A) and 13(B) may contain transistors, etc., as needed. It further includes other circuit elements such as ions, resistive elements, capacitive elements, and inductors. You can.

[0214] Furthermore, in Figures 13(A) and 13(B), transistor 133t is transistor 13 The source and drain of 0t are electrically connected to the wiring 111. This illustrates a case. Transistor 133t has the same source and One of the drains may be electrically connected to the wiring 123.

[0215] <Regarding the prevention of through-current by latching> Furthermore, in a PLD according to one aspect of the present invention, the wiring 11 is electrically connected to the input terminal of the LE. 1. The latch may be electrically connected. Add to the switch 126 for initialization. Figure 14(A) shows how the latch 182 is electrically connected to the wiring 111. The latch 182 shown in Figure 14(A) is electrically connected to the wiring 111 at the input terminal of the LE. It has the function of maintaining the potential at either a high or low level.

[0216] Figure 14(B) shows an example of the configuration of latch 182. The inverter 2 has an inverter 183 and a p-channel type transistor 184. The input terminal of 183 is electrically connected to wiring 111, and the output terminal of inverter 183 is connected to the transistor It is electrically connected to the gate of transistor 184. The source and gate of transistor 184 Rain is electrically connected to wire 185, which is given a higher potential than wire 125. The other end is connected to wiring 111.

[0217] In one aspect of the present invention, the latch 182 having the above configuration is electrically connected to the wiring 111. By doing so, after power is supplied to the PLD, the potential of wiring 111 is set to either high or low level. Since it can be maintained on either side of the bell, an intermediate potential is applied to the wiring 111. Therefore, it is possible to prevent a through-current from occurring in the LE to which the input terminal is connected to wiring 111. Cut.

[0218] <Regarding the connection structure between I / O and logic elements> Next, we will explain the connection structure between I / O and logic elements in the PLD100. Figure 15 illustrates a part of the PLD100 according to one aspect of the present invention.

[0219] Figure 15 shows column 102 having multiple LE101s and column 151 having multiple IO150s. And are provided in PLD100. In Figure 15, from left to right in the drawing, row 1 This example illustrates the case where column 51 and column 102 are arranged in parallel.

[0220] Furthermore, in Figure 15, there are multiple wires 152, multiple wires 153, multiple wires 154, and multiple A single wire 155 and multiple wires 156 are provided on the PLD100.

[0221] Furthermore, each LE101 in row 102 has a first output terminal, which is connected to a plurality of wires 152 and a plurality Each is connected to wiring 156. The second output terminal of each LE101 in row 102 is Each of the multiple wires 153 is connected. The child is connected to multiple wires 155. Multiple wires 154 are shown in Figure 15. The first output of each of the multiple LE101 (not shown) located to the right of column 102 toward They are connected to the power terminals, respectively.

[0222] Note that the number of output terminals that each IO150 has is not necessarily one, and may be multiple. Good. However, even if there are multiple output terminals, one output terminal must always be connected to one wire. It shall be assumed that the number of IO150 in column 151 is Y (where Y is a natural number). If so, the PLD100 has Y wires 155 electrically connected to the above output terminal, Even if you don't have it, you possess it.

[0223] And multiple wires 152, multiple wires 154, multiple wires 155, and multiple wires 1 Number 56 is located between column 151 and column 102. Also, column 102 has multiple wiring 1 It is located between 52 and multiple wires 153.

[0224] Furthermore, in Figure 15, multiple wires 152, multiple wires 154, and multiple wires 155 are... The switch circuit 110 electrically supplies multiple input terminals of each LE101 in row 102. They are connected. Also, in Figure 15, multiple wires 156 are connected via switch 157 in a row. It is electrically connected to each IO150 input terminal of 151.

[0225] The switch 157 has one switch circuit 120 having the configuration described above. The switch circuit 120 of the switch 157 controls one of the multiple wires 156. Select according to the structuring data, and connect the selected wiring to each IO150 input. It has the function of connecting to the power terminal.

[0226] Note that in Figures 1(A) and 15, multiple wirings are provided between rows having LE101. The example shows the case where two LE101s belonging to the same column are connected. However, A wiring is provided in the PLD100 that directly connects two LE101 units belonging to the same row. That's good too.

[0227] <Example of LE configuration> Figure 16(A) illustrates one form of LE101. The LE101 shown in Figure 16(A) is L UT (Look-up Table) 160, Flip-flop 161, and Configure It has a configuration memory 162. The configuration memory 162 is a memory element It has the function of storing configuration data sent from the ment. LUT 160 is the configuration sent from the configuration memory 162 The logic circuit determined differs depending on the content of the data. Once the data is finalized, LUT160 will process the multiple input signals provided to input terminal 163. A single output value is determined for each input value. Then, LUT160 includes the above output value. A signal is output. Flip-flop 161 holds the signal output from LUT 160. The output signal corresponding to the clock signal CLK is sent to the first output terminal 164 in synchronization with the clock signal CLK. And it outputs from the second output terminal 165.

[0228] Furthermore, the LE101 also has a multiplexer circuit, and this multiplexer circuit This allows you to select whether or not the output signal from LUT160 passes through flip-flop 161. You can do that.

[0229] Furthermore, the type of flip-flop 161 can be defined by the configuration data. It is also possible to configure it in such a way. Specifically, the configuration data will flip Flop 161 is a D-type flip-flop, a T-type flip-flop, a JK-type flip-flop It may also have the functionality of either a flip-flop or an RS-type flip-flop.

[0230] Furthermore, Figure 16(B) illustrates another form of LE101. LE1 shown in Figure 16(B) 01 has a configuration in which an AND circuit 166 is added to LE101 shown in Figure 16(A). The AND gate 166 receives the signal from the flip-flop 161 as a positive logic input. Given, the signal INIT for initializing the potential of wiring 111 shown in Figure 3 is negative. It is given as the input to the circuit. With the above configuration, the power of wiring 111 according to the signal INIT When the position is initialized, the output signal from LE101 should be at the same potential as wiring 125. Therefore, as shown in Figure 3, multiple wires to which the output signal from LE101 is supplied 1 This prevents a large amount of current from flowing through 23 and wiring 111. This can prevent damage to the PLD.

[0231] Furthermore, Figure 16(C) illustrates another form of LE101. LE1 shown in Figure 16(C) 01 is the LE101 shown in Figure 16(A), with multiplexer 168 and configuration It has a configuration in which a 169 complication memory is added. In Figure 16(C), the multiple Lexa 168 receives the output signal from LUT 160 and the output signal from flip-flop 161. The number and are entered. And the multiplexer 168 has a configuration memo. According to the configuration data stored in Ri169, the two output signals above It has the function to select and output one of the following: Output signal from multiplexer 168 This is output from the first output terminal 164 and the second output terminal 165.

[0232] <Top view of the PLD> Figure 17 shows a top view of the PLD100 as an example.

[0233] In Figure 17, PLD100 is connected to logic array 170, IO150, and PLL(pha It has a (se lock loop) 172, RAM 173, and a multiplier 174. .

[0234] The logic array 170 includes multiple LE101s and wiring that controls the connections between the LE101s. It has wiring resources 175 that include a switch. PLL172 has a clock signal CL It has the function of generating K. RAM173 is a device that stores data used in logical operations. It has the capability. The multiplier 174 corresponds to a logic circuit dedicated to multiplication. If the program includes a multiplication function, the multiplier 174 does not necessarily need to be provided.

[0235] Note that in Figure 17, the configuration data that defines the logic circuit of each LE101 is This example illustrates the case where the data is stored in a memory element located outside the PLD100. However, the memory element may also be located on the PLD100.

[0236] <Example of LUT configuration> In this embodiment, an example configuration of the LUT160 included in LE101 will be described. The 160 can be configured using multiple multiplexers. Configuration data is input to either the input terminal or control terminal of the Lexus. This configuration can be achieved.

[0237] Figure 18(A) shows one embodiment of the LUT160 provided by LE101.

[0238] In Figure 18(A), LUT160 has seven 2-input multiplexers (multiplexers SA31, Multiplexer32, Multiplexer33, Multiplexer34, Multiplex It is composed of (S35, multiplexer36, multiplexer37). Each input terminal from the 31 to the 34 multiplexer connects to input terminals M1 to M8 of the 160. It corresponds to this.

[0239] Each control terminal of multiplexer 31 to multiplexer 34 is electrically connected, The control terminal corresponds to the input terminal IN3 of LUT160. The output terminal of multiplexer 31 The output terminals of the child and multiplexer 32 are connected to the two input terminals of multiplexer 35 and electrical They are connected in a manner, and the output terminals of multiplexer 33 and multiplexer 34 are, It is electrically connected to the two input terminals of the multiplexer 36. The control terminals of the multiplexer 36 are electrically connected, and the above control terminals are connected to the LUT This corresponds to the IN2 input terminal of the 160. The output terminal of the multiplexer 35, and the multiplexer The output terminal of unit 36 ​​is electrically connected to the two input terminals of unit 37 of the multiplexer. The control terminal of the multiplexer 37 corresponds to the input terminal IN1 of the LUT160. The output terminal of the Lexa 37 corresponds to the output terminal OUT of the LUT160.

[0240] Input terminals M1 through M8 receive the following information from the configuration memory: An output signal corresponding to the configuration data stored in the configuration memory is input. By doing so, you can define the type of logical operation performed by LUT160. ru.

[0241] For example, in LUT160 shown in Figure 18(A), input terminals M1 to M8 are connected to From the figuring memory, the digital values ​​are "0", "1", "0", "1", "0" The configuration stored in the configuration memory is "1", "1", "1". When output signals corresponding to the regulation data are input, the results are shown in Figure 18(C). This allows for the realization of the equivalent circuit's functionality.

[0242] Figure 18(B) shows another embodiment of the LUT160 that LE101 has.

[0243] In Figure 18(B), LUT160 has three 2-input multiplexers (multiplexer Using a 41 (saturator), a 42 (multiplexer), a 43 (multiplexer), and a 44 (two-input OR gate) It is composed of [this].

[0244] The output terminals of multiplexer 41 and multiplexer 42 are connected to the multiplexer It is electrically connected to the two input terminals of 43. The output terminal of the OR circuit 44 is a multiplexer. It is electrically connected to the control terminal of the Kusa 43. The output terminal of the multiplexer 43 is LUT This corresponds to the OUT output terminal of the 160.

[0245] Then, control terminal A1, input terminal A2 and input terminal A3 of the multiplexer 41, multiplexer Control terminal A6, input terminals A4 and A5 of Lexa 42, input terminal A of OR circuit 44 Either terminal 7 or input terminal A8 receives the configuration from the configuration memory. An output signal corresponding to the configuration data stored in the configuration memory is input. By doing so, you can define the type of logical operation performed by LUT160. ru.

[0246] For example, in LUT160 in Figure 18(B), input terminal A2, input terminal A4, input terminal Digital values ​​are sent from the configuration memory to terminals A5, control terminal A6, and input terminal A8. In the configuration memory where the values ​​are "0", "1", "0", "0", "0", When output signals corresponding to the stored configuration data are input, The equivalent circuit shown in Figure 18(C) can be realized. Note that in the above configuration, Terminal A1, input terminal A3, and input terminal A7 are input terminal IN1, input terminal IN2, respectively. This corresponds to input terminal IN3.

[0247] Note that in Figures 18(A) and 18(B), L is configured using a 2-input multiplexer. The example of UT160 was shown, but LUT1 can be configured using a multiplexer with more inputs. It's fine even if it's 60.

[0248] In addition, the LUT160 includes diodes, resistors, logic circuits (or It may further have one or all of the following: logic elements, switches, logic circuits (or Examples of logic elements include buffers, inverters, NAND gates, NOR gates, and three-stage switches. A clocked buffer, clocked inverter, etc. can be used as a switch, for example... Analog switches, transistors, etc., can be used.

[0249] Furthermore, using the LUT160 shown in Figures 18(A) and 18(B), as shown in Figure 18(C) The example shown is for a 3-input, 1-output logical operation, but it is not limited to this. LUT160 And by appropriately defining the configuration data to be input, more input This allows for the implementation of logical operations with many outputs.

[0250] <Example of cell cross-sectional structure> Figure 19 shows the transistors 130t and 13, which are present in cell 140 as shown in Figure 6. The cross-sectional structure of 1t and the capacitive element 132 are shown as an example.

[0251] Furthermore, in this embodiment, the transistor 13 has a channel formation region in the oxide semiconductor film. 1t and the capacitive element 132 are connected to a single-crystal silicon substrate having a channel formation region. This example illustrates the case where it is formed on a ZISTA 130t.

[0252] Note that the transistor 130t is made of amorphous, microcrystalline, polycrystalline, or monocrystalline silicon. Alternatively, a semiconductor film such as germanium can be used as the active layer. Or, a transistor 130t may use an oxide semiconductor as the active layer. All transistors use an oxide semiconductor. When a conductor is used as the active layer, transistor 131t is stacked on top of transistor 130t. It is not necessary for them to be on the same layer, and transistors 131t and 130t are on the same layer. It's okay if it's already formed.

[0253] When forming a transistor 130t using a thin silicon film, methods such as plasma CVD are used. Amorphous silicon produced by vapor phase growth or sputtering, amorphous silicon Polycrystalline silicon and single-crystal silicon wafers that have been crystallized by processes such as lighter annealing. Single-crystal silicon, etc., can be used, which has had its surface layer exfoliated by injecting hydrogen ions or the like.

[0254] The semiconductor substrate 400 on which the transistor 130t is formed is, for example, an n-type or p-type conductive material. Silicon substrates with a mold, germanium substrates, silicon-germanium substrates, compound semiconductors Substrates (GaAs substrates, InP substrates, GaN substrates, SiC substrates, GaP substrates, GaInAs P substrate, ZnSe substrate, etc. can be used. Figure 19 shows n-type conductive This example illustrates the case using a single-crystal silicon substrate.

[0255] Furthermore, transistor 130t is separated from other transistors by an insulating film 401 for element isolation. They are electrically isolated. The insulating film 401 for element isolation is formed by selective oxidation (LOCOS). (Local Oxidation of Silicon) method or trench separation method The following can be used.

[0256] Specifically, transistor 130t is formed on the semiconductor substrate 400, source region or Impurity region 402 and impurity region 403 function as drain regions, and gate electrode 40 4 and a gate insulating film 405 provided between the semiconductor substrate 400 and the gate electrode 404 are included. The gate electrode 404 is separated from the impurity region 402 by the gate insulating film 405. It overlaps with the channel-forming region formed between the material regions 403.

[0257] An insulating film 409 is provided on transistor 130t. The insulating film 409 has an opening. A structure is formed in the above-mentioned opening, and the impurity region 402 and impurity region 403 are The wirings 410 and 411 that are in contact with each other, and the wiring that is electrically connected to the gate electrode 404 Line 412 is formed.

[0258] The wiring 410 is electrically connected to the wiring 415 formed on the insulating film 409. Furthermore, the wiring 411 is electrically connected to the wiring 416 formed on the insulating film 409. Wiring 412 is electrically connected to wiring 417 formed on insulating film 409.

[0259] Insulating film 420 and insulating film 440 are stacked sequentially on wiring 415 to wiring 417. An opening is formed in the insulating film 420 and the insulating film 440, and the opening A wire 421 is formed in the section that is electrically connected to the wire 417.

[0260] In Figure 19, a transistor 131t and a capacitive element 132 are formed on the insulating film 440. It is being done.

[0261] The transistor 131t has a semiconductor film 430 containing an oxide semiconductor on an insulating film 440, and a semiconductor film 430 containing an oxide semiconductor. A conductive film 432 on the conductive film 430 that functions as a source electrode or drain electrode and a conductive film The film 433, the semiconductor film 430, the conductive film 432, and the gate insulating film 431 on the conductive film 433 , located on the gate insulating film 431, and between the conductive film 432 and the conductive film 433, the semiconductor film 4 It has a gate electrode 434 that overlaps with 30. The conductive film 433 is connected to wiring 421. It is electrically connected to it.

[0262] Furthermore, a conductive film 435 is provided on the gate insulating film 431 at a position overlapping with the conductive film 433. The conductive films 433 and 435 are superimposed with the gate insulating film 431 in between. The part that is present functions as a capacitive element 132.

[0263] In Figure 19, the capacitive element 132 is placed on the insulating film 440 together with the transistor 131t. The example shows the case where it is being removed, but the capacitive element 132, together with the transistor 130t, It may be located beneath the insulating film 440.

[0264] Then, insulating film 441 and insulating film 442 are placed on transistor 131t and capacitive element 132. They are arranged to be stacked in order. The insulating film 441 and insulating film 442 are provided with openings. The conductive film 443 that contacts the gate electrode 434 at the above-mentioned opening is an insulating film 441 It is located above.

[0265] In Figure 19, the transistor 131t has a gate electrode 434 on the semiconductor film 430. It is sufficient if at least one side has them, but a pair exists with the semiconductor film 430 in between. It may have a gate electrode.

[0266] The transistor 131t has a pair of gate electrodes that are located with a semiconductor film 430 in between. If so, one of the gate electrodes is given a signal to control whether it is in a conductive or non-conductive state. Furthermore, the other gate electrode may be in a state where its potential is supplied from another source. In addition, the same potential may be applied to the pair of gate electrodes, or the other gate electrode A fixed potential, such as ground potential, may be applied only to the other gate electrode. By controlling the height of the position, the threshold voltage of the transistor can be controlled.

[0267] Also, in Figure 19, transistor 131t corresponds to one gate electrode 434. This example illustrates a single-gate structure having a nel-forming region. However, ZISTA 131t has multiple electrically connected gate electrodes, which allows one active layer to It may also be a multi-gate structure having multiple channel-forming regions.

[0268] <Example of transistor configuration> Next, regarding an example of the structure of a transistor having a channel formation region in an oxide semiconductor film... I will explain.

[0269] The transistor 601 shown in Figure 20 has a conductive film 602, a conductive film 603, and It has a gate electrode 604. The gate electrode 604 is positioned between the conductive film 602 and the conductive film 603. It is placed. Also, the transistor 601 has a conductive film 602 provided on its insulating surface, conductive film It has an insulating film 605 located between 603 and the gate electrode 604.

[0270] Furthermore, transistor 601 has island-shaped insulating films on its gate electrode 604 and insulating film 605. It has 606 and island-shaped oxide semiconductor films 607 located on the insulating film 606. Transistor 601 has a source electrode 608 on the conductive film 602 and oxide semiconductor film 607. It comprises a conductive film 603 and a drain electrode 609 on an oxide semiconductor film 607.

[0271] Furthermore, transistor 601 has an oxide semiconductor film 607, a source electrode 608 and a drain electrode It has an insulating film 610 provided on the pole 609.

[0272] Furthermore, the source electrode 608 and the drain electrode 609 have progressively smaller film thicknesses at their ends. It is burning. Alternatively, the source electrode 608 and the drain electrode 609 have odor at their ends. The film thickness may decrease continuously. With the above configuration, the source electrode 608 and the drain The insulating film 610 provided on the in electrode 609, source electrode 608 and drain electrode 60 Coverage at the edges of 9 can be improved.

[0273] Furthermore, transistor 601 has a gate electrode 611 provided on the insulating film 610. The gate electrode 611 overlaps with the oxide semiconductor film 607 with the insulating film 610 in between. ru.

[0274] Note that in Figure 20, transistor 601 covers gate electrode 611 and insulating film 610. This example illustrates the case where an insulating film 612 is provided.

[0275] Figure 21 shows a transistor 630 having a channel formation region on a single-crystal silicon substrate. Figure 20 shows a cross-sectional view of how the transistors 601 shown are stacked.

[0276] As shown in Figure 21, the transistor 630 is formed on the semiconductor substrate 631. The substrate 631 is, for example, a single-crystal silicon substrate having an n-type or p-type conductivity, a compound semiconductor substrate, etc. Conductive substrates (GaAs substrates, InP substrates, GaN substrates, SiC substrates, GaP substrates, GaIn AsP substrate, ZnSe substrate, etc. can be used. Figure 21 shows n-type conductivity This example illustrates the case using a single-crystal silicon substrate.

[0277] Furthermore, the transistor 630 is separated from other transistors by the element isolation insulating film 632. The semiconductor element is electrically isolated. The formation of the element isolation insulating film 632 involves selective oxidation Law (LOCOS (Local Oxidation of Silicon) Law) or Trench separation methods and the like can be used.

[0278] The region where the n-channel transistor 630 is formed is given p-type conductivity. By selectively introducing impurity elements, p-well 633 is formed. When forming a p-channel type transistor using an electrically conductive semiconductor substrate, In the region where the Nell-type transistor is formed, an impurity element that imparts an n-type conductivity is selected. By introducing it precisely, a region called an n-well is formed.

[0279] Specifically, transistor 630 has a source region or dot formed on the semiconductor substrate 631. Impurity regions 634 and 635 function as rain regions, and semiconductor substrate 631 It has a gate insulating film 637 provided between it and the gate electrode 636. This is formed between the impurity region 634 and the impurity region 635, with the gate insulating film 637 in between. It overlaps with the channel formation region.

[0280] An insulating film 638 is provided on the transistor 630. The insulating film 638 has an opening. The opening is formed, and the opening has an impurity region 634, an impurity region 635, and a gate electrode. Wirings 639 and 640 are formed, each in contact with 636.

[0281] Furthermore, the wiring 639 is connected to the wiring 641 formed on the insulating film 638, 640 is connected to wiring 642 formed on insulating film 638.

[0282] An insulating film 643 is formed on wiring 641 and wiring 642.

[0283] In Figure 21, a transistor 601 is formed on the insulating film 643. Conductive film 6 03 is connected to the gate electrode of transistor 630.

[0284] Figure 22 shows the layer on which transistor 630 is formed and the layer on which transistor 601 is stacked. The cross-sectional view shows how another wiring layer is formed between existing layers.

[0285] In Figure 22, wiring 645 is formed on the insulating film 643. An insulating film 646 is formed on the wiring 645. An opening is formed in the insulating film 646. The opening is formed therein, and a wiring 647 connected to the wiring 645 is formed in the opening. On 646, a wiring 648 is formed that is connected to wiring 647. Also, insulating film 64 An insulating film 649 is formed on 6 and the wiring 648. An opening is formed in the insulating film 649. Insulation is provided, and wiring 650 connected to wiring 648 is formed in the above-mentioned opening. A transistor 601 is formed on the film 649, and the wiring 650 is in contact with the conductive film 603. It continues.

[0286] Figure 23 shows that another wiring layer is formed on top of the layer on which transistor 601 is formed. The situation is shown in a cross-sectional view.

[0287] In Figure 23, an insulating film 651 is formed on transistor 601. Wiring 652 is formed on the film 651, and the wiring 652 is made of insulating film 651, insulating film 61 0, and in the opening formed in the insulating film 612, connected to the drain electrode 609 An insulating film 653 is formed on the insulating film 651 and the wiring 652. Also, insulating film 6 Wiring 654 is formed on 53, and wiring 654 is formed in the opening formed in insulating film 653. In this section, it is connected to wiring 652. Insulating film 6 is on insulating film 653 and wiring 654. 55 is formed. Also, wiring 656 is formed on the insulating film 655, and wiring 6 56 is connected to the wiring 654 through an opening formed in the insulating film 655.

[0288] <Example of configuration memory configuration> Next, Figure 24 shows the circuit configuration of the memory cells of the configuration memory. Let me give you an example.

[0289] In one embodiment of the present invention, the memory cell 200 has switches 201 to 205. It may or may not have it. Also, as shown in Figure 24, the memory cell 200 has a capacitive element 206 and It may also have a capacitive element 207.

[0290] Note that Figure 24 illustrates the case where one transistor is used as a switch, Multiple transistors may be used as switches.

[0291] Switch 201 sends a configuration message to node FD1 in memory cell 200. It has the function of controlling the supply of the potential of the first signal, which includes the DATA. Specifically, switch 20 When 1 is in a conductive state (on), the configuration data given to wiring 210 The potential of the first signal, including the 'ta' signal, is supplied to node FD1. Also, switch 201 is non-conductive. When in the (off) state, the potential of node FD1 is maintained. Capacitive element 206 is at node F It is electrically connected to D1 and has the function of maintaining the potential of node FD1.

[0292] The selection of a conductive or non-conductive state in switch 201 is determined by the signal given to wiring 212. It is carried out according to the potential of the number.

[0293] Switch 202, according to the potential of node FD1, connects the electrical connections of wires 208 and 209. It has a function to control the connection. Specifically, when switch 202 is in a conductive state, wiring 2 08 and wiring 209 are electrically connected. Also, when switch 202 is in a non-conductive state As a result, wiring 208 and wiring 209 are electrically isolated.

[0294] Furthermore, the switch 203 provides configuration to node FD2 in the memory cell 200. It has a function to control the supply of the potential of the second signal, which includes the data. Specifically, the switch When circuit 203 is in a conductive state (on), the configuration given to wiring 211 The potential of the second signal, which includes the data, is supplied to node FD2. Also, switch 203 When in a non-conductive state (off), the potential of node FD2 is maintained. Capacitive element 207 is It is electrically connected to node FD2 and has the function of maintaining the potential of node FD2.

[0295] The selection of a conductive or non-conductive state in switch 203 is determined by the signal given to wiring 212. It is carried out according to the potential of the number.

[0296] Switch 204, according to the potential of node FD2, electrically connects wires 214 and 209. It has a function to control the connection. Specifically, when switch 204 is in a conductive state, wiring 2 14 and wiring 209 are electrically connected. Also, when switch 204 is in a non-conductive state As a result, wiring 214 and wiring 209 are electrically isolated.

[0297] Note that a high-level potential VDD is applied to wiring 208, and a low-level potential VDD is applied to wiring 214. Assume that the potential VSS is given. Then, the configuration data is stored in memory. When writing to the RU200, the potentials of the first signal and the second signal are reversed in polarity. Assume that the logic level is inverted. Therefore, switch 202 and S Switch 204 is a state where, when one side is conducting, the other side is not conducting. Which of the two, the 202 or the switch 204, is in a conductive state, and which is in a non-conductive state? This is determined by the potentials of the first and second signals, i.e., the configuration data. Therefore, the potential applied to wiring 209 is determined by the configuration data. This determines whether the potential is high-level VDD or low-level VSS.

[0298] Switch 205 has the function of controlling the electrical connection between wiring 209 and wiring 215. Specifically, when switch 205 is in a conductive state, wiring 209 and wiring 215 Electrically connected, the potential of wiring 209 is applied to wiring 215. Also, switch 20 When 5 is in a non-conductive state, wiring 209 and wiring 215 are electrically isolated.

[0299] Furthermore, in the configuration memory shown in Figure 24, switch 201 and switch The transistor used in Chi 203 maintains the potentials of nodes FD1 and FD2. Because it has a function, it is desirable to have a transistor with a very low off-current. Semiconductor films have a wider band gap than silicon and a lower intrinsic carrier density than silicon. A transistor characterized by the formation of a channel formation region has a significantly low off-current. Therefore, it is suitable for use in switches 201 and 203. As an example, oxide semiconductors have a band gap that is more than twice as large as that of silicon. Examples include silicon dioxide and gallium nitride. Transistors having the above semiconductors are typically silicon dioxide. Compared to transistors made of semiconductors such as cellulose or germanium, it has an extremely low off-current. Therefore, the transistor having the above configuration can be used as switch 201 and By using switch 203, the charges held at nodes FD1 and FD2 are It can prevent leaks.

[0300] In a configuration memory according to one aspect of the present invention, configuration data According to the instructions, either the low-level potential VSS or the high-level potential VDD is connected to wiring 215. Either one can be given. Therefore, the wiring to which the configuration data is output. The configuration data is read out depending on whether or not a potential of 1 is applied to 215. Unlike configuration memory, configuration data is stored in memory cell 2 Before reading from 00, you can accurately configure without pre-charging wiring 215. Configuration data can be read. Therefore, the configuration memory is driven. The circuit does not require a pre-charge circuit, and the programmable logic is The area of ​​the vise can be kept small.

[0301] Furthermore, after power is turned on to the PLD, the configuration data is lost, and node F Even if D1 and node FD2 are in an indeterminate state, the potential of the first signal and the potential of the second signal are... By setting both to a low potential, wiring 208 and wiring 214 become electrically connected. It can prevent this.

[0302] Furthermore, in Figure 24, switch 20 is activated in only one of the two memory cells 200. By making 5 conductive, the confidential data stored in each of the two memory cells 200 is transmitted. Read either one of the regulation data from a single wire 215, multicontext This illustrates the configuration of a configuration memory using the T method. However, one aspect of the present invention In the configuration memory related to this, the multiple memory cells 200 are stored in The configuration was such that the configuration data was read from different wirings 215. You can.

[0303] In addition to the above configuration, the potential of wiring 215 is set to either a high level or a low level. A latch 182, which has the function of keeping the wiring 215 in place, is provided to be electrically connected to the wiring 215. It is also acceptable to have it. In one aspect of the present invention, with the above configuration, after the power is turned on, the wiring 21 Since the potential of 5 can be kept at either a high or low level, the power is turned on. Afterward, a shoot-through current occurs in the circuit, such as the LUT or multiplexer connected to wiring 215. This can prevent it from happening.

[0304] Note that when the potential VDD of wiring 210 is supplied to node FD1 via switch 201 In reality, node FD1 has a potential equal to the threshold voltage of the transistor used in switch 201. The potential will be lower than VDD. Therefore, even if switch 205 is in a conductive state, wiring 21 It is difficult to raise the potential of point 5 to the same potential VDD as wiring 208. However, latch 1 By providing 82, the potential of wiring 215 can be raised to potential VDD, and wiring 2 This prevents 15 from becoming an intermediate potential between potential VSS and potential VDD. Also, wiring When a potential VSS of 210 is applied to node FD1 via switch 201, node F The potential of D1 drops by the threshold voltage of the transistor used in switch 201. There is no such thing. Similarly, the potential VSS of wiring 211 is supplied to node FD2 via switch 203. If available, the potential of node FD2 is the threshold voltage of the transistor used in switch 203. It will not drop by a certain amount of time. Therefore, switch 202 or switch 204, Since it can be made to a non-conductive state, via switch 202 or switch 204 No through-current will flow.

[0305] Furthermore, as mentioned above, when an n-channel transistor is used in switch 201 It is easy to set node FD1 to the potential VSS, but setting node FD1 to the potential VDD is easy. This is difficult considering the threshold voltage of the above transistor. Therefore, switch 202 If a p-channel transistor is used, switch 202 will be completely deconducted. This becomes difficult, and through-current flows more easily through switch 202. Therefore, If an n-channel transistor is used in switch 201, then switch 202 will have: Using an n-channel transistor is desirable to prevent shoot-through current. The same can be said for switch 203 and switch 204. That is, switch 203 has n switches When a channel-type transistor is used, switch 204 has an n-channel type transistor. Using a diaphragm is desirable to prevent through-current.

[0306] Furthermore, if a p-channel transistor is used in switch 201, node FD1 Setting the potential to VDD is easy, but setting node FD1 to the potential VSS is difficult as described above. Considering the threshold voltage of the transistor makes it difficult. Therefore, an n-channel type is used for switch 202. When a transistor is used, it is difficult to completely deconduct switch 202. This makes it easier for through-current to flow through switch 202. Therefore, switch 201 When a p-channel transistor is used, switch 202 has a p-channel transistor Using a transistor is desirable to prevent through-current. Switch 203 and switch The same can be said for switch 204. That is, switch 203 has a p-channel type transistor When a zista is used, a p-channel type transistor is used for switch 204. This is desirable in order to prevent through-current.

[0307] In addition to the above configuration, there is a wiring 216 to which a predetermined potential is applied, and a wiring 216 and a wiring A switch 217 for controlling the electrical connection with 215 may also be provided. In one embodiment, the above configuration initializes the potential of the wiring 215 to a predetermined height. Therefore, after the power to the programmable logic device is cut off, the wiring can be disconnected. Even if the potential of 215 becomes indeterminate, and furthermore, the configuration data is lost However, this prevents the LUTs and multiplexers within the LE from malfunctioning after the power is turned on. It is possible.

[0308] Furthermore, in the configuration memory, wiring 210 and wiring 211 are used for LE and S The rows of cells in the switch circuit are arranged in the direction in which wiring 212 and wiring 213 are positioned. When arranging in a direction intersecting the above direction, a multi-context method is used for one wiring 215. Even if the number of corresponding memory cells 200 increases, wiring 210 or wiring 211 and wiring 21 This prevents the distance between points 5, i.e., the distance between the switch circuit and the LE, from becoming too long. Therefore, in a multi-context system, multiple switch circuits and LEs are electrically connected. This can suppress the increase in load such as parasitic resistance and parasitic capacitance of the wiring, and the switch circuit This can prevent the size from increasing.

[0309] Next, the two memory cells 200 shown in Figure 24, the latch 182, and the switch 217 A configuration memory having multiple sets 220, each having a wiring 216, is given as an example. Figure 25 shows an example of the connection configuration of group 220 within the logic element.

[0310] The LE221 shown in Figure 25 is a configuration memory composed of multiple sets 220. 162, a configuration memory 169 composed of multiple sets 220, and logic It has a socket 225 and a latch 224.

[0311] Logic cell 225 contains LUTs, multiplexers, flip-flops, etc. The configuration memory 162 inputs the configuration to the LUT of the logic cell 225. Configuration data is stored. Configuration memory 169 is logic The configuration data to be input to the multiplexer in cell 225 is stored here.

[0312] Furthermore, the signal containing the data provided to wiring 223 is input to the LUT of logic cell 225. A latch 224 for holding data is connected to wiring 223.

[0313] Additionally, the INIT signal, which controls the switching of switch 217, is input to wiring 222. It can be done.

[0314] In one aspect of the present invention, by arranging the LE221 in a row, the configuration Memory 162 and configuration memory 169 are also, for example, the matrix shown in Figure 28 ( As shown in Mem), they are arranged in a matrix. Therefore, configuration memo The arrangement of the re 162 and the configuration memory 169 can be made dense, PLD This reduces the layout area required.

[0315] Next, an example of an I / O configuration in which multiple sets 220 described above are provided will be explained using Figure 26. The IO230 shown in Figure 26 consists of sets 220a to 220d, a latch 224, and Ex OR circuit 231a and ExOR circuit 231b, tristate buffer 232, and It has a converter 233, a buffer 234, and a terminal 236.

[0316] The output signal of set 220a, specifically the signal having a potential applied to wiring 215 in Figure 24, is This is input to the ExOR circuit 231a. Also, wiring 213a is connected to the ExOR circuit 231a. A signal containing data is input from there. The output signal of the ExOR circuit 231a contains data. This signal A is input to the tristate buffer 232.

[0317] Furthermore, the output signal of set 220b, specifically the potential applied to wiring 215 in Figure 24, The signal is input to ExOR circuit 231b. Also, wiring 2 is connected to ExOR circuit 231b. A signal containing data is input from 13b. The output signal of the ExOR circuit 231b is a tri As the signal EN that determines whether or not to set the state buffer 232 to high impedance, This is input to the live state buffer 232.

[0318] ExOR circuits 231a and 231b are stored in sets 220a and 220b. According to the configured configuration data, the signal poles of wiring 213a and wiring 213b It has a function to reverse the gender. In this way, according to the configuration data, ExOR circuits 231a and 231b, which reverse the polarity of the force signal, are provided at I / O. By doing so, the desired arithmetic circuit can be realized with a small number of LEs, thereby PLD It is possible to construct large-scale circuits as a whole. Furthermore, a desired arithmetic circuit can be constructed with a small number of LEs. Since this can be achieved, the power supply to the LEs that are not used in the calculation circuit is stopped, and the L Since the operation of E can be stopped, the power consumption of the PLD can also be reduced. Similarly, ExOR circuits 231a and E on the input side of LE are also used to invert the polarity of the input signal. An xOR circuit 231b may also be provided.

[0319] Furthermore, the output signal of set 220d, specifically the potential applied to wiring 215 in Figure 24, The signal is then reversed in polarity in inverter 233, and then the signal OD is tris It is input to the tate buffer 232. The output signal of pair 220d is tristate It has a function to control whether or not the output of buffer 232 is open-drain. When the potential of the output signal of set 220d is low, the tristate buffer 232 It operates as a normal tristate buffer. Also, the potential of the output signal of the 220d is The potential of signal A is low, and the potential of signal EN is high. When this is the case, the output terminal of the tristate buffer 232 is at a low potential. Furthermore, although the potential of the output signal of set 220d is high, the potentials of signal A and signal EN are When the combination is different from the above, that is, when the potential of signal A is low level, and Except when the potential of signal EN is high, the tristate buffer 232 is high This will result in impedance.

[0320] Furthermore, if a pull-up resistor is added to the outside of the tristate buffer 232, the tristate buffer will be able to perform the following actions. Even when the state buffer 232 is high impedance, the tristate buffer 23 The potential of the output signal from 2 can be raised to a high level. Tristate buffer 23 By using IO230, which has a configuration in which a pull-up resistor is added to the outside of 2, the power supply Semiconductor devices with different voltages can be electrically connected via IO230.

[0321] Figure 27 shows an example of the circuit configuration of the tristate buffer 232. The live state buffer 232 is a NAND gate into which signals OD, EN, and A are input. Circuit 501, inverter 502 to which the output signal of NAND circuit 501 is input, and The output signal of the data 502 is input to inverter 503, and the output signal of inverter 503 It has a p-channel transistor 508 that is input to it. It also has a tristate buffer. 232 is an inverter 504 into which the signal EN is input, and the output signal of the inverter 504, and A NOR gate 505 receives signal A, and the output signal of the NOR gate 505 receives signal A. Inverter 506, inverter 507 to which the output signal of inverter 506 is input, and It has an n-channel transistor 509 to which the output signal of the converter 507 is input.

[0322] The p-channel transistor 508 and the n-channel transistor 509 are mutually dependent. The terminal is connected, and the potential of the drain is used as the output signal Y in the tristate buffer 2. Output from 32.

[0323] Furthermore, the drains of the p-channel transistor 508 and the n-channel transistor 509 The output terminal of inverter 510 is connected to the input terminal of inverter 511. The input terminal of inverter 510 is connected to the output terminal of inverter 511. .

[0324] Inverters 502 and 503 function as buffers and do not necessarily try It is not necessary to provide it in the state buffer 232. Also, inverter 506 and inverter 5 07 functions as a buffer and does not necessarily need to be placed in the tristate buffer 232. It's not necessary.

[0325] The output signal of the tristate buffer 232 is supplied to terminal 236.

[0326] Furthermore, the signal input from terminal 236 to IO230 is switched via buffer 234. It is input to the circuit.

[0327] Figure 26 illustrates the case where set 220c is provided as a dummy on IO230. By providing set 220c, the functionality of set 220 can be added with only minor mask modifications. In addition, the layout of the mask of group 220 becomes possible compared to when group 220c is not provided. This can increase the periodicity in the mask. If the periodicity of the mask is low, the above mask can be used. In the photolithography process, interference from light emitted from the exposure device can cause problems. The width of conductive films, insulating films, semiconductor films, etc., formed by photolithography can be partially narrowed. Shape defects such as the above are prone to occur. However, in Figure 26, by providing set 220c This allows for increased periodicity in the layout of the 220 masks, thereby enabling the formation of the fo This prevents defects in the shape of conductive films, insulating films, and semiconductor films from occurring after the trisography process. It is possible.

[0328] <Explanation of PLD mask drawings> Next, Figure 28 shows a mask drawing of a PLD according to one aspect of the present invention. In Figure 28, the A row of logic elements (indicated by LE) is provided between rows of switch circuits (indicated by sw). Also, a switch is placed between the column of I / O elements (indicated as I / O) and the column of logic elements. A series of circuits is provided.

[0329] Furthermore, Figure 28 shows multiple configuration notes, as illustrated in Figure 16(C). A logic element having a 'ri' is used. And the above multiple configurations The memory is also arranged to form a matrix (represented by Mem). In one aspect of the present invention The logic elements, I / O elements, and switch circuits are arranged in rows. Because of this, the configuration memory included in the logic element is also matrix-like. It is easy to arrange them densely. Therefore, in one aspect of the present invention, as shown in Figure 28, The drive circuit (bd, wd) controls the operation of the switch circuit and configuration memory. (As shown) the area where logic elements, I / O elements, and switch circuits are provided. They can be grouped together around the periphery of the area. Configuration memory and switches If the circuit is considered as a memory cell array, then the region where the above memory cell array is located This can be considered to overlap with the region where the LE is located. Therefore, in one aspect of the present invention, The above configuration allows for a reduction in the layout area of ​​the PLD. Note that the PLD shown in Figure 28 In the mask diagram, Pad corresponds to a terminal, and cc represents the operation of drive circuits bd, wd, etc. It corresponds to a control controller.

[0330] Note that the configuration memory is not arranged in a matrix as shown in Figure 28. In this case, the wiring that electrically connects the drive circuit and the configuration memory The output becomes more complex. Also, multiple drives are required for each small area of ​​the configuration memory. A circuit can be provided, but in this case, the wiring for supplying control signals to each drive circuit is required. The process becomes complicated.

[0331] Also, Figure 29 shows the connection between LE101 and switch circuits 120a to 120c. An example of the structure is shown. Figure 29 shows the electrical connections between the output terminal and the input terminal of LE101. A switch circuit 120 that controls the connection is shown as switch circuit 120a. A switch circuit that controls the electrical connection between the output terminal (not shown) and the input terminal of the LE101. Circuit 120 is shown as switch circuit 120b. Also, the output terminals of LE101 and IO (not shown) A switch circuit 120 controls the electrical connection of the input terminals (without) This is shown as c.

[0332] Furthermore, as shown in Figure 29, in one aspect of the present invention, the output signal of each LE101 is provided. The wiring 195 and wiring 196 are arranged between the adjacent LE101. This allows the wiring length from each LE101 to the switch circuit 120 to be kept short. Therefore, the current supply capacity of the buffer on the output side of the LE101 can be small, and The size of the buffer can be kept small.

[0333] Furthermore, wiring is provided to supply output signals to adjacent LEs without going through a switch circuit. These wires are used when configuring shift registers, adders, subtractors, etc., with multiple LEs. This is effective. Furthermore, by adding a 1-bit half-adder and a full-adder to the LE, multiple Addition and subtraction circuits, which are composed of multiple LEs, can be constructed with just one LE, etc. The desired arithmetic circuit can be realized with an indefinite number of LEs.

[0334] Furthermore, the LEs are arranged in a row, and adjacent LEs are connected to each other without a switch circuit. If continued, in the case of PLD disclosed in U.S. Patent No. 4870302 Unlike other methods, this allows for shorter wiring between LEs.

[0335] <Cell Comparison> Next, a cell having a transistor using an OS film and a transistor using a silicon (Si) film This section explains the operational differences between a cell having an inverter and a cell having a pair of inverters.

[0336] Figure 30 shows a cell 140a having a transistor using an OS film, and a silicon (Si) film The circuit diagram of cell 140b, which has the transistors used and a pair of inverters, is shown. Figure 30 shows the timing of the potential of node FD in cell 140a and cell 140b. The power of the signal IN, which includes configuration data, is given to the cable and wiring 121. This shows the timing chart for each position.

[0337] In cells 140a and 140b, the transistor 131t is either in a conductive or non-conductive state. The potential of wiring 122 is controlled, and the configuration data supplied from wiring 121 is used. The node FD maintains a potential corresponding to the conduction state or non-conduction state of transistor 130t. This controls the n-channel. Note that the timing chart shown in Figure 30 shows that transistor 130t controls the n-channel. This example shows the case of a flannel-type filter.

[0338] In cell 140b, inverters 180 and 181 control the potential of node FD. It is retained. Meanwhile, in cell 140a, the OS film is used in transistor 131t. Due to the extremely small current, the potential of node FD is maintained. Therefore, cell 140a So, when transistor 131t is in a non-conductive state, node FD is connected to other electrodes and wiring. This results in a highly insulating floating electrode between them. Therefore, cell 1 is better than cell 140b. 40a allows the potential of node FD to be maintained with fewer transistors. ru.

[0339] Furthermore, in cell 140a, node FD floats when transistor 131t is in a non-conductive state. Since it enters a free state, the following boosting effect can be expected. That is, the cell In 140a, when node FD is floating, the potential of signal IN changes from low level to high level. As the bell changes, a capacitance is formed between the source and gate of transistor 130t. Cgs causes the potential of node FD to rise. The magnitude of this rise in node FD potential is The logic level of the configuration data input to the gate of transistor 130t It varies depending on the model. Specifically, the configuration data written to cell 140a When the value is "0", transistor 130t is in weak inversion mode, and therefore the potential of node FD is The capacitance Cgs that contributes to the increase depends on the potential of the gate electrode, i.e., the potential of node FD. It includes a capacitance cos that does not exist. Specifically, the capacitance cos consists of the gate electrode and the source region. The overlap capacitance formed in the superimposed region and the capacitance formed between the gate electrode and the source electrode This includes parasitic capacities, etc. On the other hand, the configuration written to cell 140a If the data is "1", transistor 130t is in strong inversion mode, so node FD In addition to the capacitance Cos mentioned above, the capacitance Cgs that contributes to the rise in potential includes the gate electrode and the do Capacitance Cod formed between the rain electrodes and between the channel formation region and the gate electrode This includes a portion of the capacity Cox. Therefore, the configuration data is "1 In this case, the capacitance Cgs of transistor 130t, which contributes to the rise in the potential of node FD, This is greater than the case where the configuration data is "0". Therefore, cell 14 In 0a, if the configuration data is "1", the configuration When the data is "0", the potential of node FD changes with the potential of signal IN, compared to when the data is "0". This provides a boosting effect that allows for a higher rise. As a result, the switch speed of cell 140a is set to "1" in the configuration data. In some cases, it improves, and if the configuration data is "0", transistor 130 t becomes a non-conductive state.

[0340] Switches included in typical PLD wiring resources are n to improve integration density. A channel-type transistor is used. However, in the above switch, due to the threshold voltage This occurs when the potential of the signal passing through the gate of an n-channel transistor drops. However, a problem is the decrease in switch speed. To improve the switch speed, an n-channel type A method using overdrive, which applies a high potential to the transistor gate, has also been proposed. However, in this case, the reliability of the n-channel transistor used in the switch is reduced. There is a risk of this happening. However, in one aspect of the present invention, due to the boosting effect described above, Even without using a Bird Drive, the switch speed of cell 140a can be configured Since it can be improved when the data is "1", the switch speed can be improved. Therefore, reliability does not need to be sacrificed.

[0341] Furthermore, even in the case of cell 140b, the potential of node FD increases due to the boosting effect. However, inverters 180 and 181 instantly return the potential of node FD to its original potential. Return to the previous state. Therefore, you can benefit from the improved switch speed due to the boosting effect. It's not possible.

[0342] Also, Reference 1 (KCChun, P.Jain, JHLee, and C. H.Kim,”A 3T Gain Cell Embedded DRAM Util izing Preferential Boosting for High Den sity and Low Power On-Die Caches”IEEE Jo urnal of Solid-State Circuits, vol.46, n o.6, pp.1495-1505, June. 2011), Reference 2 (F. Es lami and M. Sima,”Capacitive Boosting fo r FPGA Interconnection Networks” Int. Co nf. on Field Programmable Logic and Appl Unlike (Ications, 2011, pp. 453-458), cell 140 Further effects can be expected in case a.

[0343] Reference 1 assumes DRAM, so the number of memory cells is large, and the output of the memory cells The connected read bit line (RBL) will have high parasitic capacitance. On the other hand, in cell 140a, the signal OUT is supplied to the gate of the CMOS, so cell 140 The parasitic capacitance on the output side of a is smaller than in the case of reference 1. Therefore, transistor 130t As the potential of node FD increases due to the capacitance Cgs, further, a shape forms between the drain and gate. The resulting capacitance Cod has the secondary effect of increasing the potential of the signal OUT. A switching effect can also be obtained. That is, cell 140a is used as a switch circuit to control the connection between wires. When used in this way, the aforementioned secondary boosting effect results in even greater switching speeds. Improvements can be achieved. Also, in the case of cell 140a, fewer transistors are used compared to the case in reference 2. With a zista, it is possible to maintain the elevated potential of node FD.

[0344] To verify the boosting effect described above, a cell 140a or Two types of TEGs with 101 stages of ring oscillator (RO) circuits, each with a 140b cell. The circuit was created, and the delay time of cell 140a or cell 140b was evaluated from the oscillation frequency. n-channel transistors and p-channel transistors in the inverter that make up the TEG of the RO circuit The channel widths W of the inverters were set to 16 μm and 32 μm, respectively. Also, cell 140a and The channel width W of transistor 130t in cell 140b is 16 μm, and cell 140a The channel width W of transistor 131t in cell 140b is 4 μm, and the channel width W of transistor 131t in cell 140b is 4 μm The channel width W of the sta 131t was set to 8 μm. Also, the inverter 180 of cell 140b and The n-channel transistor and p-channel transistor in inverter 181 The channel widths W were set to 4 μm and 8 μm, respectively. Furthermore, an n-channel type using a silicon film was also tested. All transistors and p-channel transistors had a channel length L of 0.5 μm. Furthermore, transistor 131t of cell 140a contains CAA containing In-Ga-Zn oxide. A C-OS film was used, and its channel length L was set to 1 μm. Then, transistor 131t They were stacked on top of a transistor using a silicon film.

[0345] Next, the power supply voltage (VDD RO ) in the TEG of the RO circuit and the power supply voltage (VDD ) of the inverters 180 and 181 of cell 140b were used to calculate the overdrive voltage as the difference between them, and the delay time per stage of RO1 with respect to the overdrive voltage was measured. Note that the potential difference between the high-level potential and the low-level potential supplied to wiring 122 and wiring 121 corresponds to VDD MEM ).

[0346] MEM .

[0346] Figure 31 shows the measurement results of the delay time. In Figure 31, the horizontal axis represents the overdrive voltage (mV ), and the vertical axis represents the delay time per stage of RO1. Note that in Figure 31, the delay time on the vertical axis is shown as a relative value with respect to the measured value of the delay time when VDD RO is 2.00V and the overdrive voltage is 0V. Also, in Figure 31, the delay time when VDD RO is 2.00V is shown by a solid line, the delay time when it is 2.2 5V is shown by a dashed-dotted line, and the delay time when it is 2.50V is shown by a dotted line.

[0347] As shown in Figure 31, the RO circuit with cell 140a added has a shorter delay time than the RO circuit with cell 140b added, and it was confirmed that the delay time varies depending on the configurations of cells 140a and 140b.

[0348] RO RO

[0349]

[0350] <00026C0> <00026C1> <00026C2> <00026C3> また、図31に示すように、セル140bについては、オーバードライブ電圧を高めることによってスイッチ速度が向上するオーバードライブ効果が、VDDが低いほど顕著であることが示唆された。しかし、セル140bでは、VDDの0.2倍以上のオー <00026C4> <00026C5> <00026C6> <00026C7> <00026C8> <00026C9> <00026CA> <00026CB> <00026CC> <00026CD> <00026CE> <00026CF> <00026D0> <00026D1> <00026D2> <00026D3> <00026D4> <00026D5> <00026D6> <00026D7> <00026D8> <00026D9> <00026DA> <00026DB> <00026DC> <00026DD> <00026DE> <00026DF> <00026E0> <00026E1> <00026E2> <00026E3> <00026E4> <00D26E5> <00026E6> <00026E7> <00026E8> <00026E9> <00026EA> <00026EB> <00026EC> <00026ED> <00D26EE> <00026EF> <00026F0> <00026F1> [[ID=1I3]]<00026F2> <00026F3> <00026F4> <00026F5> <00026F6> <00026F7> <00026F8> <00026F9> <00026FA> <00026FB> <00026FC> <00026FD> <00026FE> <00026FF>

[0357]

[0358] [[ID=I49]]

[0359]

[0360] <00027C0> <00027C1> <00027C2> <00027C3> <00027C4> <00027C5> <00027C6> <00027C7> <00027C8> <00027C9> <00027CA> <00027CB> [[ID=I76]]<00027CC> <00027CD> <00027CE> <00027CF> <00027D0> <00027D1> <00027D2> <00027D3> <00027D4> <00027D5> <00027D6> <00027D7> <00027D8> <00027D9> <00027DA> <00027DB> <00027DC> <00027DD> [[IDEven with the Bird Drive voltage supplied, it was not fast enough to match the switching speed of cell 140a. In cell 140a, when configuration data is written, the transistor Because the threshold voltage of 131t causes a drop in the potential of node FD, the potential of node FD is V DD MEM It will be lower than that. Nevertheless, it does not supply overdrive voltage. In cell 140a, the switch speed is higher than that of cell 140b, which is supplied with an overdrive voltage. The fact that a high result was obtained is noteworthy.

[0349] Furthermore, when the overdrive voltage is the same, the RO circuit with the added cell 140a is better. It was confirmed that the power consumption was lower than that of the RO circuit with the addition of the 140b.

[0350] Furthermore, from the SPICE simulation corresponding to the TEG of the above RO circuit, cell 140 In an RO circuit with a component 'a' added, the potential of node FD increases with the potential of signal IN. We investigated this. In the calculation, VDD RO The voltage was set to 2.5V. The calculation results showed that the voltage at signal IN was... As the position increases, if the configuration data is "1", it is 0.75V, and if it is "0" In this case, it was confirmed that the potential of node FD increased by 0.07V.

[0351] Therefore, in a semiconductor device having cell 140a, without using an overdrive voltage, single Even when using a power supply voltage, high performance such as reduced power consumption and improved switching speed can be achieved. It was shown that this is possible.

[0352] Figure 32 shows a micrograph of the prototype PLD. Figure 32 shows the switch circuit and configuration. The drive circuit that controls the operation of the regulation memory (Bit Driver, Word D (river) and wiring resources including switch circuits and wiring (Routing Fabric) ic), IO element (User IO), and controller (Configurat ion Controller) and PLE (Programmable Logic For each element, the corresponding area is indicated by enclosing it in a rectangle.

[0353] The prototype PLD uses a CAAC-OS film containing an In-Ga-Zn oxide for transient The system has a configuration memory. Also, in the prototype PLD, the switch The circuit has cell 140a, and the transistor 131t in cell 140a has In-G A CAAC-OS film containing α-Zn oxide is used.

[0354] In the PLD shown in Figure 32, there are 20 PLEs, and the configuration memory has The PLE has 7520 memory cells and 20 I / O pins, and it has standard functions. It was installed. And the transistors that used the CAAC-OS film used a silicon film. n-channel transistors and p-channel transistors using silicon films stacked on top of transistors. All of the L-type transistors had a channel length L of 0.5 μm. Also, the In-Ga-Zn system... A transistor using a CAAC-OS film containing an oxide has a channel length L of 1 μm. Ta.

[0355] For comparison, SRAM was used for the configuration memory, and the switch circuit was... A PLD with cell 140b was also prototyped. A PLD using cell 140a was used as a comparison PLD. Compared to D, the layout area of ​​the switch circuit is 60%, the area of ​​the wiring resources is 52%, and PL We were able to reduce the overall area of ​​D by approximately 22%.

[0356] The PLD prototype, using cell 140a, includes a count-up / down circuit and a shift circuit. For various circuit configurations, for example, with a single power supply voltage of 2.5V and a frequency of 50MHz, It was confirmed that it was working correctly. Furthermore, in the PLD prototyped using cell 140a The system performs data retention operations, backs up necessary data to the storage device, and intermittently cuts off the power supply. We were also able to confirm the normally-off operation, which disconnects the system.

[0357] Figure 33 shows a prototype PLD using cell 140a, with 13 stages of PLE in each stage. This shows the change in oscillation frequency over time when a ring oscillator is configured. (At room temperature for 250 hours) No significant decrease in oscillation frequency was observed in the evaluation. Therefore, using cell 140a In the prototype PLD, the configuration memory has good data retention characteristics. This was suggested to be the case.

[0358] <Examples of electronic devices> A semiconductor device or programmable logic device according to one aspect of the present invention is a display device, Personal computers, image playback devices equipped with recording media (typically DVDs: Digi A digital display capable of playing recording media such as tal Versatile Discs and displaying their images. It can be used in devices having a display. In addition, semiconductors according to one aspect of the present invention As an electronic device that can use a body device or programmable logic device, Band telephones, game consoles including portable devices, personal digital assistants, e-books, video cameras, digital cameras Cameras such as flash cameras, goggle-type displays (head-mounted displays), navigation systems Audio systems, sound reproduction devices (car audio, digital audio players, etc.) , photocopiers, fax machines, printers, multifunction printers, ATMs (A Examples include electronic devices (TM), vending machines, etc. Specific examples of these electronic devices are shown in Figure 34.

[0359] Figure 34(A) shows a portable game console, comprising a casing 5001, casing 5002, display unit 5003, Display unit 5004, microphone 5005, speaker 5006, operation keys 5007, stand It has illustrations 5008, etc. Note that the portable game console shown in Figure 34(A) has two displays It has a section 5003 and a display section 5004, but the number of display sections a portable game console has is This is not limited to this.

[0360] Figure 34(B) shows a portable information terminal, consisting of a first housing 5601, a second housing 5602, and a first display unit. It includes 5603, a second display unit 5604, a connection unit 5605, an operation key 5606, etc. Table 1 The display unit 5603 is provided in the first housing 5601, and the second display unit 5604 is provided in the second housing 56 It is located at 02. And the first housing 5601 and the second housing 5602 are connected at the connection part 56 They are connected by 05, and the angle between the first housing 5601 and the second housing 5602 is the connection part It can be changed by 5605. The video in the first display unit 5603 is connected by the connection unit 5605 A configuration that switches according to the angle between the first housing 5601 and the second housing 5602 in It is also permissible to have at least one of the first display unit 5603 and the second display unit 5604, A display device with added functionality as a position input device may be used. The function as a force device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device involves a photoelectric conversion element, also known as a photosensor, as a display device. It can also be added by providing it in the pixel area.

[0361] Figure 34(C) shows a notebook personal computer, consisting of a casing 5401 and a display unit 5402. It includes a keyboard 5403, a pointing device 5404, and the like.

[0362] Figure 34(D) shows an electric refrigerator-freezer, consisting of a casing 5301, a refrigerator door 5302, and a freezer door. It has 5303, etc.

[0363] Figure 34(E) shows a video camera, consisting of a first housing 5801, a second housing 5802, and a display unit 58 03, it has an operation key 5804, a lens 5805, a connector 5806, etc. Operation key 580 4 and lens 5805 are provided in the first housing 5801, and the display unit 5803 is in the second housing It is located in 5802. And the first housing 5801 and the second housing 5802 are connected by a connection part. They are connected by 5806, and the angle between the first housing 5801 and the second housing 5802 is, The connection part 5806 can be modified. The video displayed in the display unit 5803 is connected to the connection part 5806. The configuration is such that it switches according to the angle between the first housing 5801 and the second housing 5802. You can.

[0364] Figure 34(F) is a regular passenger car, consisting of a body 5101, wheels 5102, and a dashboard 510 3. It has lights 5104, etc. [Explanation of symbols]

[0365] 31 Multiplexer 32 Multiplexer 33 Multiplexer 34 Multiplexer 35 Multiplexer 36 Multiplexer 37 Multiplexer 41 Multiplexer 42 Multiplexer 43 Multiplexer 44 OR circuits 100 PLD 101 LE 102 columns Column 102-1 Row 102-2 Row 102-3 103 Wiring 104 Wiring 104-1 Wiring 104-2 Wiring 104-3 Wiring 105 Wiring 105-1 Wiring 105-2 Wiring 105-3 Wiring 106 Wiring 106-1 Wiring 106-2 Wiring 106-3 Wiring 107 Wiring 108 Wiring 109 Wiring 110 Switch Circuit 111 Wiring 111-1 Wiring 111-2 Wiring 111-3 Wiring 120 Switch Circuits 120-1 Switch Circuit 120-2 Switch Circuit 120-3 Switch Circuit 120A switch circuit 120b Switch Circuit 120c switch circuit 121 Wiring 122 Wiring 122-1 Wiring 122-2 Wiring 122-3 Wiring 122-n wiring 123 Wiring 123-1 Wiring 123-n wiring 125 Wiring 126 switches 126t transistor 127 Wiring 128 Wiring 131 switches 131t transistor 130 switches 130t transistor 132 Capacitive elements 133t transistor 140 cells 140-1 cell 140-2 Cell 140-3 Cell 140-4 cell 140-n cell 150 IO Column 151 152 Wiring 153 Wiring 154 Wiring 155 Wiring 156 Wiring 157 switches 160 LUT 161 Flip-flops 162 Configuration Memory 163 Input terminals 164 output terminals 165 Output terminals 166 AND gate 168 Multiplexer 169 Configuration Memory 170 Logic Arrays 172 PLL 173 RAM 174 Multiplier 175 Wiring Resources 180 Inverter 181 Inverter 182 Latch 183 Inverter 184 transistors 185 Wiring 195 Wiring 196 Wiring 200 memory cells 201 Switch 202 Switch 203 Switch 204 Switch 205 Switch 206 Capacitive element 207 Capacitive elements 208 Wiring 209 Wiring 210 Wiring 211 Wiring 212 Wiring 213 Wiring 213a Wiring 213b Wiring 214 Wiring 215 Wiring 216 Wiring 217 switches 220 pairs 220a group 220b group 220c group 220d group 221 LE 222 Wiring 223 Wiring 224 Latch 225 logic cells 230 IO 231a ExOR circuit 231b ExOR circuit 232 Tristate buffer 233 Inverter 234 buffers 236 terminals 400 semiconductor substrates 401 Insulating film for element isolation 402 Impurity region 403 Impurity region 404 Gate 405 Gate Insulator 409 Insulating film 410 Wiring 411 Wiring 412 Wiring 415 Wiring 416 Wiring 417 Wiring 420 Insulating film 421 Wiring 430 Semiconductor film 431 Gate insulating film 432 Conductive film 433 Conductive film 434 gate 435 Conductive film 440 insulating film 441 Insulating film 442 Insulating film 443 Conductive film 501 NAND Circuit 502 Inverter 503 Inverter 504 Inverter 505 NOR circuit 506 Inverter 507 Inverter 508 p-channel transistor 509 n-channel transistors 510 Inverter 511 Inverter 601 Transistors 602 Conductive film 603 Conductive film 604 Gateway 605 Insulating film 606 Insulating film 607 Oxide semiconductor film 608 Source Electrode 609 Drain electrode 610 insulating film 611 Shuttle bus stop 612 Insulating film 630 transistors 631 Semiconductor substrate 632 Element isolation insulating film 633 p-well 634 Impurity region 635 Impurity region 636 Food Products 637 Gate insulating film 638 Insulating film 639 Wiring 640 Wiring 641 Wiring 642 Wiring 643 Insulating film 645 Wiring 646 Insulating film 647 Wiring 648 Wiring 649 Insulating film 650 Wiring 651 Insulating film 652 Wiring 653 Insulating film 654 Wiring 655 Insulating film 656 Wiring 5001 enclosure 5002 enclosure 5003 Display section 5004 Display section 5005 Microphone 5006 Speaker 5007 Operation Keys 5008 Stylus 5101 Car body 5102 Wheel 5103 Dashboard 5104 Light 5301 enclosure 5302 Refrigerator door 5303 Freezer door 5401 enclosure 5402 Display section 5403 Keyboard 5404 Pointing device 5601 enclosure 5602 enclosure 5603 Display section 5604 Display section 5605 Connection part 5606 Operation Keys 5801 enclosure 5802 enclosure 5803 Display section 5804 Operation Keys 5805 Lens 5806 Connection part

Claims

1. A first transistor containing silicon in the channel formation region, A second transistor having a channel formation region in an oxide semiconductor film, The channel formation region of the first transistor has a region located below the first insulating film, The oxide semiconductor film has a region located above the first insulating film, A semiconductor device in which either the source or drain of the second transistor is always in electrical contact with the gate of the first transistor, A first conductive film having a region positioned above the channel formation region of the first transistor and functioning as the gate of the first transistor, A second conductive film having a region located below the oxide semiconductor film, a region located above the first insulating film, and functioning as the first gate of the second transistor, A third conductive film having a region positioned above the first insulating film and always being electrically connected to the other of the source or drain of the second transistor, A fourth conductive film having a region positioned above the oxide semiconductor film and functioning as the second gate of the second transistor, A fifth conductive film having a region positioned above the oxide semiconductor film and always being electrically connected to either the source or the drain of the second transistor, A sixth conductive film having a region positioned above the oxide semiconductor film and always being in electrical contact with the other of the source or drain of the second transistor, The sixth conductive film has a region that is in contact with the upper surface of the third conductive film. The third conductive film is located in a layer below the oxide semiconductor film. Semiconductor equipment.

2. A first transistor containing silicon in the channel formation region, A second transistor having a channel formation region in an oxide semiconductor film, The channel formation region of the first transistor has a region located below the first insulating film, The oxide semiconductor film has a region located above the first insulating film, A semiconductor device in which either the source or drain of the second transistor is always in electrical contact with the gate of the first transistor, A first conductive film having a region positioned above the channel formation region of the first transistor and functioning as the gate of the first transistor, A second conductive film having a region located below the oxide semiconductor film, a region located above the first insulating film, and functioning as the first gate of the second transistor, A third conductive film having a region positioned above the first insulating film and always being electrically connected to the other of the source or drain of the second transistor, A fourth conductive film having a region positioned above the oxide semiconductor film and functioning as the second gate of the second transistor, A fifth conductive film having a region positioned above the oxide semiconductor film and always being electrically connected to either the source or the drain of the second transistor, A sixth conductive film having a region positioned above the oxide semiconductor film and always being in electrical contact with the other of the source or drain of the second transistor, The sixth conductive film has a region that is in contact with the upper surface of the third conductive film. The third conductive film is located in a layer below the oxide semiconductor film. The third conductive film does not overlap with the fourth conductive film in a cross-sectional view in the channel length direction of the second transistor. Semiconductor equipment.

3. A first transistor containing silicon in the channel formation region, A second transistor having a channel formation region in an oxide semiconductor film, The channel formation region of the first transistor has a region located below the first insulating film, The oxide semiconductor film has a region located above the first insulating film, A semiconductor device in which either the source or drain of the second transistor is always in electrical contact with the gate of the first transistor, A first conductive film having a region positioned above the channel formation region of the first transistor and functioning as the gate of the first transistor, A second conductive film having a region located below the oxide semiconductor film, a region located above the first insulating film, and functioning as the first gate of the second transistor, A third conductive film having a region positioned above the first insulating film and always being electrically connected to the other of the source or drain of the second transistor, A fourth conductive film having a region positioned above the oxide semiconductor film and functioning as the second gate of the second transistor, A fifth conductive film having a region positioned above the oxide semiconductor film and always being electrically connected to either the source or the drain of the second transistor, A sixth conductive film having a region positioned above the oxide semiconductor film and always being in electrical contact with the other of the source or drain of the second transistor, The sixth conductive film has a region that does not overlap with the oxide semiconductor film and is in contact with the upper surface of the third conductive film. The third conductive film is disposed in a layer below the oxide semiconductor film. Semiconductor equipment.

4. A first transistor containing silicon in the channel formation region, A second transistor having a channel formation region in an oxide semiconductor film, The channel formation region of the first transistor has a region located below the first insulating film, The oxide semiconductor film has a region located above the first insulating film, A semiconductor device in which either the source or drain of the second transistor is always in electrical contact with the gate of the first transistor, A first conductive film having a region positioned above the channel formation region of the first transistor and functioning as the gate of the first transistor, A second conductive film having a region located below the oxide semiconductor film, a region located above the first insulating film, and functioning as the first gate of the second transistor, A third conductive film having a region positioned above the first insulating film and always being electrically connected to the other of the source or drain of the second transistor, A fourth conductive film having a region positioned above the oxide semiconductor film and functioning as the second gate of the second transistor, A fifth conductive film having a region positioned above the oxide semiconductor film and always being electrically connected to either the source or the drain of the second transistor, A sixth conductive film having a region positioned above the oxide semiconductor film and always being in electrical contact with the other of the source or drain of the second transistor, The sixth conductive film has a region that does not overlap with the oxide semiconductor film and is in contact with the upper surface of the third conductive film. The third conductive film is located in a layer below the oxide semiconductor film. The third conductive film does not overlap with the fourth conductive film in a cross-sectional view in the channel length direction of the second transistor. Semiconductor equipment.

5. In any one of claims 1 to 4, The oxide semiconductor film contains indium oxide, Semiconductor equipment.

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