Memory circuit and memory processing method

Abstract

To further reduce the overall required power and area of a circuit for outputting pulse output signals for use in stochastic computing.SOLUTION: A stochastic memory which outputs pulse output signals with a probability p of HIGH state includes: a bistable circuit 2 configured to output the pulse output signals and feed back the signals to a translation circuit 1 on the basis of bistable characteristics including a first stable state, a second stable state and an unstable state; the translation circuit 1 connected to the bistable circuit 2, including a floating gate transistor, configured to receive the pulse output signals fed back from the bistable circuit 2, and translate the whole of the bistable characteristics in a state axis direction; and a voltage control circuit 3 which controls a floating gate voltage in accordance with the probability p to control the amount moved, or the like, in the translation of the bistable characteristics. The stochastic memory acquires random noise signals NZ which randomly change between HIGH state and LOW state, and superimposes the signals on the pulse output signals fed back to the translation circuit 1.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a memory circuit and Bime This falls under the technical field of memory processing methods. More specifically, it relates to memory circuits used in learning devices using artificial intelligence (so-called AI) and stochastic computing (hereinafter simply referred to as "SC"), and memory processing methods on said memory circuits. Law It belongs to the technical field. [Background technology]

[0002] In recent years, with the expansion of the so-called "Internet of Things," research and development on so-called edge computing, such as wearable devices worn by people, has become very active.

[0003] Meanwhile, alongside the aforementioned internet, research and development in artificial intelligence (AI) has also been actively pursued in recent years. However, in this AI research and development, the cost of multiply-accumulate operations (specifically, the high speed required for the processing unit and the amount of memory needed for processing) has increased dramatically. Therefore, when attempting to apply AI integrated circuits to edge computing, which has significant limitations on the area and power consumption of the integrated circuits themselves, the aforementioned cost becomes a very large barrier. Thus, when applying AI integrated circuits to edge computing, it is necessary to maximize the power efficiency of the circuit as much as possible.

[0004] Therefore, when considering the application of various architectures to edge computing from the above perspective, the inventors of the present invention focused on SC, which has a history of more than 50 years. SC is a computation method that significantly reduces circuit area by using probability. Originally, SC is characterized by the variability of the computation results due to the nature of probability, but in recent years it has been shown to have applicability in various applications such as image processing and deep learning, where "a certain degree of error" in the computation results is acceptable. And since the above-mentioned "certain degree of error" is also acceptable in the integrated circuit of AI in edge computing, it is expected that introducing SC into the edge computing will bring benefits such as smaller area and lower power consumption. Here, an example of elemental technology for realizing an integrated circuit of AI in edge computing using the above-mentioned SC is, for example, the true random number generator for digital circuits described in Patent Document 1 below. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Special Publication No. 2006-509286 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] However, prior art, including the technology described in Patent Document 1, often requires a decoder, encoder, and memory circuit in its configuration. In this case, there is a problem in that the low power consumption and small area required for a probabilistic computer compatible with SC are not sufficient.

[0007] Therefore, the present invention has been made in view of the above requirements and problems, and one example of the problems it addresses is a memory circuit that enables further reduction in power consumption and area of ​​the entire circuit for outputting pulse output signals used in the SC itself or the integrated circuit of an AI using the SC, and a memory processing method executed in said memory circuit. Law The purpose is to provide. [Means for solving the problem]

[0008] To solve the above problems, the invention described in claim 1 is a memory circuit such as a probabilistic memory that outputs a pulse output signal in which the state transitions between a HIGH state and a LOW state which is less than the HIGH state, and the probability that the state is the HIGH state is probability p, and has a bistable characteristic having a double well structure as a relationship between the state and the potential, and outputs the pulse output signal based on the bistable characteristic which includes a first stable state as the double well structure corresponding to the LOW state as an equilibrium state, a second stable state as the double well structure corresponding to the HIGH state, and an unstable state as the double well structure between the first stable state and the second stable state, and also parallel transfers the pulse output signal The system includes a bistable circuit that provides feedback to the dynamic circuit, a parallel movement circuit connected to the bistable circuit and including a floating gate transistor, the parallel movement circuit that receives feedback from the bistable circuit and parallel moves the entire bistable characteristic in the state axis direction in the double well structure, a voltage control circuit that controls the amount and direction of movement of the bistable characteristic in the parallel movement by controlling the floating gate voltage of the floating gate transistor in correspondence with the probability p, and a random signal acquisition unit such as a parallel movement circuit that acquires a random signal whose state changes randomly between a HIGH state and a LOW state and superimposes it on the pulse output signal that is fed back to the parallel movement circuit. 。

[0009] To solve the above problems, Claim 7The invention described herein is a memory circuit such as a probabilistic memory that outputs a pulse output signal in which the state transitions between a HIGH state and a LOW state which is less than the HIGH state, and the probability that the state is the HIGH state is probability p, and the memory processing method to be performed in a memory circuit comprising a bistable circuit, a parallel shift circuit connected to the bistable circuit including a floating gate transistor, a voltage control circuit, and a random signal acquisition unit, wherein the bistable characteristic has a double well structure as a relationship between the state and the potential, and the equilibrium states are a first stable state as the double well structure corresponding to the LOW state, a second stable state as the double well structure corresponding to the HIGH state, and an unstable state as the double well structure between the first stable state and the second stable state. The system includes: an output / feedback step of outputting the pulse output signal by the bistable circuit based on the bistable characteristics and feeding the pulse output signal back to the parallel movement circuit; a parallel movement step of parallel moving the entire bistable characteristics in the state axis direction in the double well structure by the parallel movement circuit to which the pulse output signal is fed back from the bistable circuit; a voltage control step of controlling the amount and direction of movement of the bistable characteristics in the parallel movement by controlling the floating gate voltage of the floating gate transistor with the voltage control circuit in correspondence with the probability p; and a random signal acquisition step of acquiring a random signal whose state changes randomly between a HIGH state and a LOW state by the random signal acquisition unit and superimposing it on the pulse output signal fed back to the parallel movement circuit.

[0010] Claim 1 prong Claim 7According to the invention described above, when outputting a pulse output signal in which the state transitions between a HIGH state and a LOW state and the probability of the state being in the HIGH state is probability p, the entire bistable characteristic of a bistable circuit that outputs a pulse output signal having a bistable characteristic including a first stable state, a second stable state and an unstable state is translated in the state axis direction by a translation circuit, and the amount and direction of the translation are controlled by controlling the floating gate voltage of the floating gate transistor of the translation circuit in correspondence with probability p. Then, a random signal is acquired and superimposed on the pulse output signal that is fed back to the translation circuit. As a result, since a pulse output signal in which the probability of being in the HIGH state is probability p can be generated using a small number of transistors, it becomes possible to reduce the power consumption and area of ​​the entire circuit for outputting the pulse output signal.

[0011] To solve the above problems, the invention described in claim 2 is a memory circuit described in claim 1, wherein the bistable circuit is composed of a plurality of transistors, and a second voltage control circuit, such as an intermediate circuit, which controls the gate voltage of the transistors included in the bistable circuit, is connected between the parallel shift circuit and the bistable circuit, such that the circuit coefficients of the bistable circuit become circuit coefficients based on potential coefficients corresponding to the bistable characteristics.

[0012] According to the invention described in claim 2, in addition to the effects of the invention described in claim 1, the gate voltage of the transistors included in the bistable circuit is controlled so that the circuit coefficients of the bistable circuit become circuit coefficients based on the potential coefficient corresponding to its bistable characteristics. Therefore, a bistable circuit with the required bistable characteristics can be realized without changing a predetermined potential coefficient.

[0013] To solve the above problems, the invention described in claim 3 is a memory circuit described in claim 1 or claim 2, wherein the bistable circuit and the translation circuit are composed of a plurality of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and the MOSFETs constituting the translation circuit and the bistable circuit are configured to be driven in a state in which each of the MOSFETs involved in the bistable characteristics exhibits subthreshold characteristics.

[0014] According to the invention described in claim 3, in addition to the effects of the invention described in claim 1 or claim 2, the bistable circuit and the parallel shift circuit are composed of a plurality of MOSFETs, and each of the MOSFETs constituting the parallel shift circuit and the MOSFETs involved in the bistable characteristics are driven in a state in which they exhibit subthreshold characteristics, thereby promoting low power consumption as a memory circuit.

[0015] To solve the above problems, the invention described in claim 4 is described in claim 1 or Claim 2 In the memory circuit described above, the random signal is configured to be a pseudo-random noise signal output from a linear feedback shift register.

[0016] According to the invention described in claim 4, claim 1 or Claim 2 In addition to the function of the invention described above, since the random signal is a pseudo-random noise signal output from a linear feedback shift register, by artificially generating the desired noise signal using a digital circuit, it is possible to accurately output a pulse output signal where the probability of being in the HIGH state is probability p.

[0017] To solve the above problems, the invention described in claim 5 is described in claim 1 or Claim 2The memory circuit described above further comprises an input unit such as a voltage control circuit, which is output from a learning device that performs artificial intelligence processing using the pulse output signal output from the bistable circuit and to which an increasing signal and a decreasing signal corresponding to the weighting in said processing are input, and the voltage control circuit is configured to control the floating gate voltage in accordance with the probability p based on the input increasing signal and decreasing signal.

[0018] According to the invention described in claim 5, claim 1 or Claim 2 In addition to the functions of the invention described above, the floating gate voltage is controlled in accordance with probability p based on increasing and decreasing signals output from a learning device that performs artificial intelligence processing using pulse output signals, and which correspond to the weighting in said processing. Therefore, when a pulse output signal with a probability of being in the HIGH state of probability p is used in the learning device, it becomes possible to reduce power consumption and reduce the area.

[0019] To solve the above problems, the invention described in claim 6 is described in claim 1 or Claim 2 In the memory circuit described above, the memory circuit is included in a probabilistic computer that has a processing unit that performs storage processing using the pulse output signal output from the bistable circuit, and the voltage control circuit is configured to control the floating gate voltage in correspondence with the probability p based on the stored value signal output from the processing unit.

[0020] According to the invention described in claim 6, claim 1 or Claim 2 In addition to the functions of the invention described above, the memory circuit is included in a probabilistic computer, and the floating gate voltage is controlled in accordance with probability p based on the memory value signal output from the processing unit of the probabilistic computer. Therefore, when a pulse output signal with a probability of being in the HIGH state of probability p is used in a probabilistic computer, it becomes possible to reduce power consumption and reduce the area. [Effects of the Invention]

[0021] According to the present invention, when outputting a pulse output signal in which the state transitions between a HIGH state and a LOW state and the probability of the state being the HIGH state is probability p, the entire bistable characteristic of a bistable circuit that outputs a pulse output signal having a bistable characteristic including a first stable state, a second stable state and an unstable state is translated in the state axis direction by a translation circuit, and the amount and direction of the translation are controlled by controlling the floating gate voltage of the floating gate transistor of the translation circuit in correspondence with probability p. Then, a random signal is acquired and superimposed on the pulse output signal that is fed back to the translation circuit.

[0022] Therefore, since a pulse output signal with a probability of being in the HIGH state of probability p can be generated using a small number of transistors, it becomes possible to reduce the power consumption and area of ​​the entire circuit for outputting the pulse output signal. [Brief explanation of the drawing]

[0023] [Figure 1] Figure (I) illustrates the principle of the present invention, where (a) is a waveform diagram showing an example of a pulse output signal in the present invention, and (b) is a diagram illustrating the bistable characteristics in the present invention. [Figure 2] Figure (II) illustrates the principle of the present invention, where (a) is Figure (i) showing the relationship between the bistable characteristics and the pulse output signal in the present invention, (b) is Figure (ii) showing the same relationship, and (c) is Figure (iii) showing the same relationship. [Figure 3] (a) is a block diagram showing the general configuration of the probabilistic memory of the embodiment, and (b) is a diagram showing the subthreshold characteristics of the embodiment. [Figure 4] This figure shows the relationship between the change in floating gate voltage and the change in bistable characteristics in the stochastic memory of the embodiment. [Figure 5] This is a circuit diagram showing the configuration of the translation circuit and bistable circuit that constitute the probabilistic memory of the embodiment. [Figure 6]It is a diagram showing the relationship between the change in the floating gate voltage in the probabilistic memory of the embodiment and the change in the probability in the pulse output signal. [Figure 7] It is a circuit diagram showing the configuration of a noise signal generation circuit corresponding to the probabilistic memory of the embodiment. [Figure 8] It is a diagram showing a random noise signal etc. used in the probabilistic memory of the embodiment. (a) is a waveform diagram showing the random noise signal, and (b) is a waveform diagram showing the change in the pulse output signal when the random noise signal is used. [Figure 9] It is a diagram etc. exemplifying the relationship between the probability and the floating gate voltage in the pulse output signal of the probabilistic memory of the embodiment. (a) is the diagram for exemplification, and (b) is the diagram explaining the resolution of the probability. [Figure 10] It is a flowchart showing a memory processing method by the probabilistic memory of the embodiment. [Figure 11] It is a circuit diagram showing the configuration of a translation circuit, a bistable circuit, etc. constituting the probabilistic memory of the modified form.

Embodiments for Carrying Out the Invention

[0024] Next, the principle of the present invention and the embodiments for carrying out the present invention using the principle will be described with reference to the drawings. Note that the embodiments of the present invention described below together with the principle are for the case where the present invention is applied to a probabilistic memory that outputs a pulse output signal in which the state transitions between a state x2 (specifically, for example, "1") and a state x1 smaller than the state x2 (specifically, for example, "0"), and the probability that the state is the state x2 is a probability p (0 < p < 1). At this time, in the probabilistic memory of the embodiment, the probability p in the pulse output signal is variably controllable according to the present invention. And the probabilistic memory of the embodiment corresponds to an example of the "memory circuit" of the present invention.

[0025] (I) The principle of the present invention First, before describing specific embodiments, the principle of the present invention will be explained using Figures 1 and 2. Figures 1 and 2 are diagrams illustrating the said principle, respectively.

[0026] As described above and as shown in Figure 1(a), the probabilistic memory of the embodiment is a pulse output signal V in which the state transitions between state x2 and state x1 (where state x2 > state x1), and the probability that the state is state x2 is "p". out It is a probabilistic memory that outputs the pulse output signal V. More specifically, first the pulse output signal V out Then, the state alternates between state x1 and state x2 randomly, for example, at a predetermined period (sampling period). And, for example, if state x2 occurred 500 times out of 1000 such periods, the pulse output signal V out The above probability p is 500 / 1000 = 0.5. Also, for example, if the above period is five times, and the state is x2 for two consecutive times and the remaining three times is state x1, then the above probability p in this case is 2 / 5 = 0.4.

[0027] Furthermore, in order to achieve low power consumption and small area in the probabilistic memory described above, the inventors of the present invention considered applying the bistable characteristics of a bistable circuit (for example, a so-called bistable multivibrator).

[0028] In this case, the bistable characteristic applied to the present invention is a bistable characteristic MV having a so-called "double well structure" as a relationship between state x and its corresponding potential, as shown in Figure 1(b), for example. In this bistable characteristic MV, as illustrated in Figure 1(b), state x and its corresponding potential are stable in states x1 and x2. In contrast, in state x0, state x and its corresponding potential are unstable.

[0029] As illustrated in Figure 2(a), when an external noise signal is applied to state x in the bistable characteristic MV while state x is in state x0, state x and the potential move from the unstable state x0 to either the stable state x1 or state x2 (i.e., state x transitions). If the application of such a noise signal is repeated multiple times, state x (and the corresponding potential) can be considered to change probabilistically between the two states x1 and x2, crossing state x0. This means that the pulse output signal V, which acts as a probabilistic memory corresponding to the noise signal, out However, this corresponds to a probabilistic transition between state x1 and state x2.

[0030] In the bistable characteristic MV described above, if the entire bistable characteristic MV (potential) is translated to the left along the state x-axis (in the direction in which state x becomes smaller), while maintaining its overall shape, as illustrated in Figure 2(b), then the probability that state x transitions (moves) when a noise signal is applied while state x0 is state x1 < state x2. This means that, as illustrated on the right in Figure 2(b), the pulse output signal V out This means that the probability p of this condition increases. In contrast, for example, as illustrated in Figure 2(c), if the entire bistable characteristic MV (potential) is translated to the right along the state x axis (in the direction in which state x increases) while maintaining its overall shape, the probability that state x transitions (moves) when a noise signal is applied while state x0 becomes state x1 > state x2. This means that, as illustrated on the right in Figure 2(c), the pulse output signal V out This means that the probability p of being [the desired outcome] becomes smaller.

[0031] As described above, if the direction and amount of movement when translating the bistable characteristic MV can be controlled, as illustrated in Figure 2, then the pulse output signal V as a probabilistic memory will be able to be controlled. outIt is found that the probability p can be freely controlled. This means that it becomes possible to "store the probability" as a probabilistic memory. Therefore, based on the principle described above, the inventors of the present invention studied a bistable circuit capable of translating the bistable characteristic MV in the direction of the state x-axis.

[0032] (II) Embodiment Next, embodiments of the present invention based on the above-described principle will be specifically described with reference to FIGS. 3 to 10. FIG. 3 is a block diagram showing the schematic configuration of the probabilistic memory of the embodiment, FIG. 4 is a diagram showing the relationship between the change in the floating gate voltage and the change in the bistable characteristic in the probabilistic memory, and FIG. 5 is a circuit diagram showing the configuration of the translation circuit and the bistable circuit constituting the probabilistic memory. Further, FIG. 6 is a diagram showing the relationship between the change in the floating gate voltage and the change in the probability in the pulse output signal in the probabilistic memory, FIG. 7 is a circuit diagram showing the configuration of the noise signal generation circuit corresponding to the probabilistic memory, and FIG. 8 is a diagram showing a random noise signal or the like used in the probabilistic memory. Furthermore, FIG. 9 is a diagram exemplifying the relationship between the probability and the floating gate voltage in the pulse output signal of the probabilistic memory, and FIG. 10 is a flowchart showing the memory processing method by the probabilistic memory.

[0033] As shown in FIG. 3(a), the probabilistic memory SM of the embodiment is composed of a translation circuit 1, a bistable circuit 2, a voltage control circuit 3, and a noise signal application circuit 4. In this configuration, the bistable circuit 2 is a bistable circuit having the above-described bistable characteristic MV to bistable characteristic MV2, and outputs the above-described pulse output signal V as the probabilistic memory SM, and feeds back the pulse output signal V to the translation circuit 1. At this time, the pulse output signal V fed back to the translation circuit 1 out and out is fed back to the translation circuit 1. outIn this configuration, a random noise signal NZ, as described above (see Figure 2), is superimposed from the noise signal application circuit 4 via capacitor C1. That is, the part of the parallel translation circuit 1 where the pulse output signal Vout is fed back corresponds to an example of the "random signal acquisition unit" of the present invention. Also, the voltage control unit 3 corresponds to an example of the "input unit" of the present invention.

[0034] On the other hand, the parallel translation circuit 1 receives a pulse output signal V that is superimposed with the random noise signal NZ mentioned above. out And the floating gate voltage V from the voltage control circuit 3 fg Based on this, the direction and amount of movement of the bistable characteristic MV in the state x-axis direction of the bistable circuit 2 are controlled (see Figure 2). At this time, the voltage control circuit 3 is configured to have a predetermined memory function, etc. (not shown), and based on the input signal IN received from the outside, the direction and amount of movement are set to the desired direction and amount (in other words, the pulse output signal V out The floating gate voltage V above (so that the probability p as is becomes the desired value) fg This generates and outputs to the parallel translation circuit 1. The specific configuration of this voltage control circuit 3 itself is basically the same as that of conventional voltage control circuits of the same type. As a result, when the random noise signal NZ is applied and the direction and amount of movement of the bistable characteristic MV are controlled by the parallel translation circuit 1, a pulse output signal V with the desired probability p is generated. out This is output from the bistable circuit 2 and fed back to the translation circuit 1.

[0035] Here, the parallel translation circuit 1 and the bistable circuit 2 are each composed of multiple MOSFETs connected together. In the following description, these MOSFETs will be simply referred to as "FETs". The FETs constituting the parallel translation circuit 1 and the bistable circuit 2 include both p-type and n-type FETs, as will be described in detail later. Furthermore, as one of the FETs constituting the parallel translation circuit 1, a floating-gate FET is used, as will be described later.

[0036] Furthermore, since each FET constituting the parallel transport circuit 1 and the bistable circuit 2 is required to be driven with low power (i.e., driven with low voltage and low current), they are driven in a region where so-called subthreshold characteristics are exhibited. In this case, the subthreshold characteristic is the characteristic in which a weak current flows through the FET when the gate voltage of the FET is below its threshold, as illustrated in Figure 3(b). The value of the saturation current corresponding to the subthreshold characteristic is given by the following equation (1), where the gate voltage V g It can be expressed as an exponential function of .

number

[0037] Next, in considering the circuit configurations of the parallel translation circuit 1 and the bistable circuit 2, the inventors of the present invention examined the characteristic equations corresponding to these circuit configurations. That is, in order for a circuit using a subthreshold characteristic expressed by an exponential function as shown in equation (1) above to have a bistable characteristic MV, first, the potential (potential function) of the bistable characteristic MV must be expressed by an exponential function. Therefore, the pulse output signal V output from the probabilistic memory SM of the embodiment out Potential H(V out ) is defined as shown in equation (2) below.

number

[0038] In the example shown in Figure 4, the pulse output signal V outFor it to have bistable characteristics MV, the pulse output signal V as the output voltage must out It must satisfy the differential equation (4) below.

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[0039] Next, the circuit configurations of the parallel translation circuit 1 and the bistable circuit 2, which were concretized through the above-mentioned considerations, will be explained using Figure 5.

[0040] First, the parallel translation circuit 1 of the embodiment is configured such that the floating gate FET 10 and FETs 11 to 14 shown in Figure 5 are connected as shown in Figure 5. The gate voltage of the floating gate FET 10 is the floating gate voltage V fg It is controlled by the voltage control circuit 3. At this time, the voltage control circuit 3 controls the floating gate voltage V corresponding to the input signal IN based on the memory control values ​​stored in the memory function. fg This is generated and output to the parallel translation circuit 1. Furthermore, the output voltage V' of the parallel translation circuit 1 in the circuit configuration shown in Figure 5 is given by the following equation (5), which corresponds to the above equation (3). According to this equation (5), the floating gate voltage V fg Based on this, it can be seen that the output voltage V' (differential voltage) changes.

number

[0041] On the other hand, the bistable circuit 2 of the embodiment is configured by connecting FETs 20 to FET 23, FETs 30 to FET 33, and capacitor C as shown in Figure 5. Of these, the p-type FETs 20 and FET 21 and the n-type FETs 22 and FET 23 are related to the potential as the bistable characteristic MV. These four FETs then control the current I shown in Figure 5 with reference to the output voltage V'. pa , current I pb , current I na and current I nb Each of these generates current I pa These currents flow to capacitor C via current mirror circuits composed of FET30 and FET31, and current mirror circuits composed of FET32 and FET33, and this flows into the pulse output signal V out It is output as follows. At this time, the pulse output signal V out The differential equation that must be satisfied is given by equation (6) below, which corresponds to equation (4) above.

number

[0042] More specifically, first the current I of FET22 na The current I of FET23 nb If it is greater than, "(current I na -Current I nb Since )>0, the pulse output signal V out The pulse output signal V increases, out Due to the increase in current I na The voltage also increases, and as a result, the pulse output signal V becomes stable until it reaches a stable voltage. out This will result in a change in the current I of FET20. pa The current I of FET21 pb If it is greater than, "(current I pb -Current I pa Since )<0, the pulse output signal V out The pulse output signal V decreases. out The decrease in current I paThe voltage increases, and as a result, the pulse output signal V becomes stable until it reaches a stable voltage. out This will change.

[0043] As described above, the parallel translation circuit 1 and bistable circuit 2 of the embodiment generate the pulse output signal V out A configuration for variably controlling the probability p in (a so-called bistable sense amplifier) ​​has been realized. Next, the inventors of the present invention have determined whether these operate as a probabilistic memory SM (i.e., the pulse output signal V as its output signal). out A simulation was conducted to determine whether the probability p can be variably controlled. The results of this simulation are described below.

[0044] First, before performing the necessary simulations, it is necessary to set the constant k and the value of the current I0 in the subthreshold characteristics of each FET (see equation (1) above).

[0045] First, the values ​​of the constant k and current I0 for the floating gate FETs 10 and 11 to 14 that constitute the parallel translation circuit 1, and for the FETs 30 to 33 that constitute the bistable circuit 2, are as described in the reference "Andreas G. Andreou, et al., "Current-Mode Subthreshold MOS Circuits for Analog VLSI Neural Systems", 1991" (k=0.7, I0=0.72×10). -18 The ampere was used. Furthermore, the subthreshold characteristic in this case is given by the following equation (7).

number

[0046] In contrast, the FETs 20 to 23 included in the bistable circuit 2 use values ​​corresponding to the constants a to d (see Figure 4) of the potential (potential function) because the value of their constant k and the value of the current I0 are related to the formation of the bistable characteristic MV. For FETs 20 and 22, the values ​​are k = 0.650 and I0 = 3.89 × 10⁻¹⁰. -18 Assuming amperes, k = 0.728 and I0 = 0.730 × 10 for FET21 and FET23. -18 These values ​​were set to be as close as possible to the parameters shown in the reference paper mentioned above.

[0047] And the pulse output signal V as the output voltage. out To confirm the time evolution of the power supply voltage, a so-called "transient analysis" was performed in the simulation, and the power supply voltage was set to V. DD = +0.25V, V SS = -0.25V. Under the above conditions, the floating gate voltage V as the memory holding voltage is fg The operation of the parallel translation circuit 1 and the bistable circuit 2 was simulated when the value was changed.

[0048] Here, if we do not consider the random noise signal NZ, when the potential as the bistable characteristic MV is shifted, the unstable state x0 is no longer in equilibrium, and it is thought that state x moves directly to state x1 or state x2 (see Figures 2(b) and 2(c)). Therefore, in the simulation of the operation of the shifted circuit 1 and the bistable circuit 2, as shown in Figure 6, the floating gate voltage V is initially set so that state x stabilizes in state x2. fg The value was set (see dashed line in Figure 6). Then, from this state, the floating gate voltage V fg As the value of increases, at a certain point state x stops at state x0, and furthermore, the floating gate voltage V fg As the value of was increased, state x stabilized in state x1 (see dashed and dotted lines in Figure 6). Thus, as shown in Figure 6, the floating gate voltage V fgAs the floating gate voltage V is changed in a certain direction, fg It was confirmed that the stable operation of the circuit as a bistable circuit 2 changes even without changing anything else.

[0049] Next, the inventors of the present invention performed a simulation in which a random noise signal NZ was input from the noise signal application circuit 4 of the embodiment in order to simulate the actual operation of the probabilistic memory SM.

[0050] First, the configuration of the noise signal application circuit 4 of the embodiment will be explained using Figure 7. Here, the noise signal application circuit 4 of the embodiment functions as a so-called transient noise source and is common to multiple probabilistic memory SMs. For example, the (one) noise signal application circuit 4 common to five probabilistic memory SMs is configured as a linear feedback shift register (LFSR) as shown in Figure 7, consisting of five flip-flop circuits 40 to 44 and a negative exclusive OR circuit 45 connected as shown in Figure 7. The flip-flop circuits 40 to 44 are driven based on a common clock signal CLK, and one of their outputs is used as a pseudo-random random noise signal NZ in the corresponding probabilistic memory SM. More specifically, as the random noise signal NZ, a random noise signal NZ with an amplitude of 0.1 volts and a period of 1 millisecond, as exemplified in Figure 8(a), was used. Then, with the capacitance of capacitor C1 (see Figure 3(a)) set to 1 femtofarad (fF), the pulse output signal V is fed back. out It was superimposed on it.

[0051] Here, if the potential as the bistable characteristic MV is not shifted, it is thought that when a random noise signal NZ is applied to the unstable state x0, the state will probabilistically transition (move) to two stable states (state x1 and state x2) (see Figure 2). Therefore, in the simulation by the inventors of this invention, the floating gate voltage (memory holding voltage) V is set so that the potential does not shift. fg With the element fixed, a random noise signal NZ was applied.

[0052] As a result, the time and pulse output signal V when the same random noise signal NZ is applied nine times out The relationship is shown in Figure 8(b). Note that in Figure 8(b), the time and pulse output signal V when the same random noise signal NZ is applied individually nine times are shown. out The relationship is shown as nine graphs for each application. In each of the nine graphs, the left vertical axis represents the pulse output signal V out The graph shows the value of V, with the horizontal axis representing the time (seconds) since the random noise signal NZ was applied, and the right vertical axis representing the state x (shown as a dashed line for each graph). As shown in each graph of Figure 8(b), when the random noise signal NZ is applied, the pulse output signal V, which was initially in state x0, out However, it was found that over time, the system transitions to a stable state (either state x1 or state x2), and further, that the transition to which stable state occurs is probabilistic.

[0053] As described above, the inventors of the present invention confirmed that the translation circuit 1 and bistable circuit 2 of the embodiment operate as a probabilistic memory SM, based on the results of two simulations shown in Figures 6 and 8(b).

[0054] Finally, the inventors of the present invention, while maintaining the conditions in each of the previous simulations, have determined the floating gate voltage (memory holding voltage) V fgWe performed a simulation considering the simultaneous input of changes in and a random noise signal NZ. More specifically, we repeated the stochastic stable operation (transition (movement) to a stable state x1 or state x2) that occurs when a random noise signal NZ is input 1,000 times, and then calculated the pulse output signal V from the number of times it remained stable in state x2. out The probability p as (see Figure 1) is calculated with respect to the floating gate voltage V fg The process was repeated with variations in the parameter. The results are shown in Figure 9(a).

[0055] As is clear from Figure 9(a), the floating gate voltage V fg By changing the pulse output signal V out It can be confirmed that the probability p as has changed, and furthermore, as shown in Figure 9(b), the floating gate voltage V fg By simply changing the voltage from 0.18 volts to 0.28 volts, the pulse output signal V out It was found that the change in probability p as can be obtained at the desired full scale. Note that the floating gate voltage V is illustrated in Figure 9(a). fg If we attempt to formulate a mathematical relationship between and probability P, we obtain a relationship like the following equation (8) (however, this is an approximation).

number

[0056] Here, the floating gate voltage V fg Pulse output signal V by variable control out When considering the storage of probability p as (probabilistic memory), if the resolution of the memory function constituting the voltage control circuit 3 is assumed to be 8 bits, then if the power supply voltage for the memory function is 0.5 volts, then the floating gate voltage V fg It can store values ​​in increments of 2 millivolts. In contrast, as shown in Figure 9(b), the floating gate voltage V required to obtain a sufficient probability p is fg Since the change in voltage is 0.1 volts, the resulting floating gate voltage Vfg The value will be divided by 50. Therefore, the above probability p will also be divided by 50, and it can be seen that the resolution of the probability p will be 6 bits. From the above, although the resolution will be slightly reduced, if the probabilistic memory SM of the embodiment including the voltage control circuit 3 using the above memory function is used, the pulse output signal V out As the probability of this becomes probability p, it became clear that, as a result, "storage of the said probability p" can be performed as a probabilistic memory SM.

[0057] Next, we will explain the operation of the probabilistic memory SM described above as a memory processing method, using Figure 10. Figure 10 is a flowchart showing the memory processing method using the probabilistic memory SM of the embodiment.

[0058] When the operation of the stochastic memory SM described above is viewed as a memory processing method, as shown in Figure 10, when a random noise signal NZ is applied (step S1), the pulse output signal V from the bistable circuit 2 out The output is fed back to the parallel translation circuit 1 (step S2). Then, the floating gate voltage V from the voltage control circuit 3 is applied. fg It is checked whether there is a change in the floating gate voltage V (step S3), and the floating gate voltage V fg If there is a change (Step S3: YES), the operation of the parallel shift circuit 1 based on the change causes a parallel shift in the x-axis direction of the bistable characteristic MV (Step S4), and then the process proceeds to Step S5, which will be described later. On the other hand, in the confirmation of Step S3 above, the floating gate voltage V fg If there are no changes (Step S4: NO), then it is determined whether to terminate the operation as a probabilistic memory SM, for example, because the power supply has been turned off (Step S5). If the operation is to be terminated (Step S5: YES), the operation is terminated. On the other hand, if the determination in Step S5 is to continue the operation (Step S5: NO), the process returns to Step S1 and the series of operations described above are repeated.

[0059] Note that, as an example of the input signal IN input to the voltage control circuit 3 to control the floating gate voltage V of the embodiment fg the following can be mentioned. (A) When the probabilistic memory SM of the embodiment is used for learning by AI such as online learning or batch learning, as the input signal IN, an increase signal and a decrease signal of the weight (w) output from a learning device using the AI are used. This is because, as an update of the weight W, an operation of "newly storing a value slightly increased or decreased from the stored value" such as "W(t + 1)=W(t)±ΔW" is required. (B) When the probabilistic memory SM of the embodiment is used as a storage device of a computer (including a processing unit such as a CPU) using the SC, the input signal IN is a storage value signal having a value of the probability p to be stored in the probabilistic memory SM (for example, a storage value signal output from the processing unit). This is because the computer needs to store the results of various calculations such as "A×B" and "C + D".

[0060] As described above respectively, according to the configuration of the probabilistic memory SM of the embodiment, when outputting a pulse output signal V in which the state x transitions between the state x2 and the state x1 and the probability that the state x is the state x2 is the probability p out when the bistable characteristic MV of the bistable circuit 2 having the bistable characteristic MV of the double well structure and outputting the pulse output signal V out is translated in the state x-axis direction by the translation circuit 1, the floating gate voltage V of the floating gate FET10 of the translation circuit 1 fg is controlled corresponding to the probability p, thereby controlling the movement amount and the movement direction in the translation. Then, a random noise signal NZ is acquired and superimposed on the pulse output signal V out fed back to the translation circuit 1. Therefore, since the pulse output signal V in which the probability of being in the state x2 is the probability p can be generated using a small number of FETs, the power consumption and the area of the entire circuit for outputting the pulse output signal V out can be reduced. out ​

[0061] In addition, as specific values of the above power reduction on the premise that a large number of probabilistic memories SM of the embodiment are used, the inventors of the present invention have confirmed that the power consumption per bit in the probabilistic memory SM of the embodiment is 22.2 femtojoules (fJ). The power consumption in this case is the sum of the power consumption per bit in each of one translation circuit 1, one bistable circuit 2, and one flip-flop circuit in a noise signal application circuit 4 that outputs one random noise signal NZ corresponding to these. On the other hand, when a conventional circuit is applied to a probabilistic memory, it has been confirmed by simulations by other researchers etc. that the power consumption per bit is, for example, 658.6 femtojoules. Thus, according to the configuration of the probabilistic memory SM of the embodiment, a probabilistic memory can be realized with a power consumption one digit lower than the conventional one.

[0062] Also, since the bistable circuit 2 and the translation circuit 1 are each composed of a plurality of FETs, and each of the FETs constituting the translation circuit 1 and the FETs related to the bistable characteristic MV are driven in a state where they exhibit subthreshold characteristics, power reduction as the probabilistic memory SM can be promoted.

[0063] Furthermore, since the random noise signal NZ is a noise signal of pseudo-random numbers output from the noise signal application circuit 4 which is a linear feedback shift register, by generating the desired noise signal pseudo-digitally by a digital circuit, a pulse output signal V whose probability of being in the state x2 is the probability p out can be accurately output.

[0064] Furthermore, when the floating gate voltage V out is controlled corresponding to the probability p based on an increase signal and a decrease signal output from a learning device that performs AI processing using the pulse output signal V fg and corresponding to the weighting in the processing, power reduction and area reduction are possible when the pulse output signal V out is used in the learning device.

[0065] Furthermore, a probabilistic memory SM is included in the probabilistic computer, and a floating gate voltage V is generated based on the memory value signal output from the processing unit of the probabilistic computer. fg When controlling it in accordance with probability p, the pulse output signal V has a probability of being in state x2 that corresponds to probability p. out This enables lower power consumption and smaller footprint when used in probabilistic computers.

[0066] (III) Transformation form Next, a modified version of the present invention will be described with reference to Figure 11. Figure 11 is a circuit diagram showing the configuration of a translation circuit and a bistable circuit, etc., that constitute a modified version of the probabilistic memory. In Figure 11, components similar to those in the translation circuit 1 and bistable circuit 2 of the embodiment are given the same component numbers, and detailed explanations are omitted.

[0067] In the probabilistic memory SM of the embodiments described above, the bistable characteristic MV was achieved by making the constant k arbitrary. In contrast, in the modified probabilistic memory described below, instead of changing the constant k, the same function as a probabilistic memory is achieved by changing the gate voltage Vg of the FET constituting the bistable circuit 2.

[0068] In other words, as shown in Figure 11, an intermediate circuit 50 is provided between the translation circuit 1 and the bistable circuit 2 that constitute the modified stochastic memory, with FETs 51 to 54 connected as shown in Figure 11. In this case, the intermediate circuit 50 corresponds to an example of the "second voltage control circuit" of the present invention. This intermediate circuit 50 utilizes the fact that the FETs in the off state have high resistance to suppress power consumption by reducing current, and also uses voltage division by resistance to produce the voltage V shown in Figure 11. a The goal is to generate the following. Then, the intermediate circuit 50 is used to generate the voltage V shown in Figure 11 so that the circuit coefficients of the bistable circuit 2 become circuit coefficients based on the potential coefficient corresponding to the bistable characteristic MV. a Voltage V bIt is configured to be smaller than this. And these voltages V a and voltage V b Therefore, the gate voltage V of FET20 to FET23 of the bistable circuit 2 contributes to the bistable characteristic MV. g This is controlled. As a result, the bistable characteristic MV of the bistable circuit 2 is achieved without changing the constant k.

[0069] As explained above, according to the modified form of probabilistic memory equipped with the intermediate circuit 50, the gate voltage V of the FET 20 etc. included in the bistable circuit 2 g Since this is controlled, a bistable circuit 2 with the required bistable characteristics MV can be realized without changing the constant k.

[0070] Furthermore, as other variations, the bistable circuit 2 of the embodiment may have the following alternative means: (i) to (iii). (i) Using a closed-loop operational amplifier with bistable characteristics as a substitute by feeding the output of the operational amplifier back into the input. (ii) Using static memory as an alternative, which forms bistable characteristics with a circuit configuration such as a "cross-linking" configuration using transistors or FETs. (iii) Using non-volatile memory as an alternative, which changes between two states in response to external input and maintains that state unless rewritten, thereby achieving bistable characteristics.

[0071] Furthermore, as other variations, the translation circuit 1 of the embodiment may have alternative means such as (iv) and (v) below. (iv) Use a source follower circuit (common-source amplifier circuit) as an alternative, which has the characteristic that the output voltage changes in accordance with the input voltage and is lower by the gate-source voltage. (v) Although the amplification factor changes depending on the resistance value of the circuit, a subtraction circuit that amplifies and outputs the difference between two voltages can be used as an alternative. [Industrial applicability]

[0072] As described above, the present invention can be used in the field of probabilistic memory, and particularly remarkable effects can be obtained when applied to probabilistic memory in order to achieve low power consumption and small area size. [Explanation of symbols]

[0073] 1. Parallel translation circuit 2 Bistable circuit 3. Voltage control circuit 4. Noise signal application circuit 10 Floating Gate FET 11, 12, 13, 14, 20, 21, 22, 23, 30, 31, 32, 33, 51, 52, 53, 54 FET 40, 41, 42, 43, 44 Flip-flop circuits 45 Negative exclusive OR circuit 50 intermediate circuit C, C1 Capacitor V' Output voltage V fg Floating gate voltage V out pulse output signal MV, MV1, MV2 bistable characteristics SM (Probabilistic Memory) NZ Random Noise Signal IN Input signal

Claims

1. A memory circuit that outputs a pulse output signal in which the state transitions between a HIGH state and a LOW state which is less than the HIGH state, and the probability that the state is the HIGH state is probability p. A bistable characteristic having a double well structure as a relationship between state and potential, wherein the equilibrium state includes a first stable state as the double well structure corresponding to the LOW state, a second stable state as the double well structure corresponding to the HIGH state, and an unstable state as the double well structure between the first and second stable states, and a bistable circuit that outputs the pulse output signal based on this bistable characteristic and feeds the pulse output signal back to a parallel translation circuit, A translation circuit connected to the bistable circuit, which includes a floating gate transistor, wherein the pulse output signal is fed back from the bistable circuit and the translation circuit moves the entire bistable characteristic in the direction of the state axis in the double well structure, By controlling the floating gate voltage of the floating gate transistor in accordance with the probability p, the amount and direction of movement in the parallel translation of the bistable characteristic can be controlled. A voltage control circuit to be controlled, A random signal acquisition unit acquires a random signal whose state changes randomly between a HIGH state and a LOW state, and superimposes it on the pulse output signal that is fed back to the parallel translation circuit. A memory circuit characterized by comprising the following features.

2. In the memory circuit described in claim 1, The aforementioned bistable circuit is composed of multiple transistors, A memory circuit characterized in that a second voltage control circuit, which controls the gate voltage of the transistor included in the bistable circuit, is connected between the parallel shift circuit and the bistable circuit, such that the circuit coefficients of the bistable circuit become circuit coefficients based on the potential coefficient corresponding to the bistable characteristics.

3. In the memory circuit according to claim 1 or claim 2, The bistable circuit and the parallel translation circuit are composed of a plurality of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). A memory circuit characterized in that the MOSFETs constituting the parallel translation circuit and the MOSFETs involved in the bistable circuit are driven in a state in which they exhibit subthreshold characteristics.

4. In the memory circuit according to claim 1 or claim 2, A memory circuit characterized in that the random signal is a pseudo-random noise signal output from a linear feedback shift register.

5. In the memory circuit according to claim 1 or claim 2, The system further comprises an input unit to which an increasing signal and a decreasing signal corresponding to the weighting in the process are input, which are output from a learning device that performs artificial intelligence processing using the pulse output signal output from the bistable circuit, The voltage control circuit is a memory circuit characterized by controlling the floating gate voltage in accordance with the probability p based on the input increasing and decreasing signals.

6. In the memory circuit according to claim 1 or claim 2, The memory circuit is included in a probabilistic computer that has a processing unit that performs storage processing using the pulse output signal output from the bistable circuit. The voltage control circuit is a memory circuit characterized by controlling the floating gate voltage in correspondence with the probability p based on the memory value signal output from the processing unit.

7. A memory circuit that outputs a pulse output signal in which the state transitions between a HIGH state and a LOW state which is less than the HIGH state, and the probability that the state is the HIGH state is probability p, and a memory processing method to be performed in a memory circuit comprising a bistable circuit, a parallel shift circuit connected to the bistable circuit including a floating gate transistor, a voltage control circuit, and a random signal acquisition unit, A bistable characteristic having a double well structure as a relationship between state and potential, wherein the bistable characteristic includes, as an equilibrium state, a first stable state as the double well structure corresponding to the LOW state, a second stable state as the double well structure corresponding to the HIGH state, and an unstable state as the double well structure between the first and second stable states, and outputs the pulse output signal by the bistable circuit based on this bistable characteristic, and also feeds back the pulse output signal to the parallel translation circuit, A parallel movement step is performed by the parallel movement circuit, which receives the pulse output signal from the bistable circuit, to parallel move the entire bistable characteristic in the state axis direction in the double well structure. A voltage control step in which the floating gate voltage of the floating gate transistor is controlled by the voltage control circuit in accordance with the probability p, thereby controlling the amount and direction of movement in the parallel movement of the bistable characteristic, A random signal acquisition step is to acquire a random signal whose state changes randomly between a HIGH state and a LOW state using the random signal acquisition unit, and superimpose it on the pulse output signal that is fed back to the parallel movement circuit. A memory processing method characterized by including the following.

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