Wiring board

Abstract

This wiring board includes an insulating layer made of a ceramic material, and a conductor layer extending in a plane direction inside the insulating layer. The conductor layer is composed of a sintered body of a plurality of crystallites containing metal as a main component, and has a layered structure in which a dense layer, a non-dense layer and a dense layer are layered in this order in the thickness direction.

Description

Technical Field

[0001] The disclosed embodiments relate to a wiring board.

Background Art

[0002] Conventionally, a wiring board having an insulating layer mainly composed of ceramics and a conductor layer mainly composed of metal has been known. Such a wiring board can be obtained, for example, by simultaneously firing a conductor material in which a metal oxide is added to copper powder and a glass ceramic as an insulating layer material (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Brief Description of the Drawings

[0005] [Figure 1] FIG. 1 is an enlarged cross-sectional view showing an example of the configuration of a wiring board according to an embodiment. [Figure 2] FIG. 2 is an enlarged view of region A shown in FIG. 1. [Figure 3] ]>FIG. 3 is an explanatory diagram showing a method for evaluating crystallites. [Figure 4] FIG. 4 is a diagram showing a SEM observation photograph of a conductor layer according to an example.

Modes for Carrying Out the Invention

[0006] The embodiments of the wiring board disclosed herein will be described below with reference to the attached drawings. However, the embodiments described below do not limit this disclosure. Furthermore, each embodiment can be combined as appropriate, provided that the processing content is not inconsistent. Also, the same parts are denoted by the same reference numerals in each of the embodiments below, and redundant descriptions are omitted.

[0007] Furthermore, in the embodiments described below, expressions such as "parallel" may be used, but these expressions do not require strict parallelism. In other words, the expressions described above allow for deviations such as manufacturing accuracy and installation accuracy.

[0008] Conventionally, wiring substrates having an insulating layer mainly composed of ceramics and a conductive layer mainly composed of metal are known. Such wiring substrates can be obtained, for example, by simultaneously firing a conductive material obtained by adding a metal oxide to copper powder and glass ceramics as the insulating layer material.

[0009] However, with conventional technology, there was a risk of delamination between the insulating layer and the conductor layer, for example, if the adhesion between the insulating layer and the conductor layer was insufficient. Therefore, there is a need for a technology that can overcome the above-mentioned problems and reduce delamination between the insulating layer and the conductor layer in a wiring board.

[0010] Figure 1 is an enlarged cross-sectional view showing an example of a wiring board 1 according to the embodiment, and Figure 2 is an enlarged view of region A shown in Figure 1. As shown in Figures 1 and 2, the wiring board 1 according to the embodiment comprises an insulating layer 10 and a conductor layer 20.

[0011] The insulating layer 10 can be made of, for example, a glass-ceramic sintered body. It may also contain ceramics such as aluminum oxide, aluminum nitride, silicon carbide, silicon nitride, or mullite as fillers.

[0012] The insulating layer 10 may be made of, for example, glass ceramics. This allows the wiring board 1 to be manufactured by simultaneously firing the green sheet, which is the raw material for the insulating layer 10, and the conductive paste, which is the raw material for the conductor layer 20. Therefore, according to this embodiment, the manufacturing cost of the wiring board 1 can be reduced.

[0013] The insulating layer 10 may have a first layer 11 and a second layer 12 facing each other with the conductor layer 20 in between. The first layer 11 and the second layer 12 are positioned, for example, to sandwich both sides of the conductor layer 20 in the thickness direction.

[0014] The conductive layer 20 is electrically conductive and extends in a planar direction (lateral direction in Figure 1) within the insulating layer 10. The conductive layer 20 is arranged in a predetermined pattern shape, for example, between the first layer 11 and the second layer 12. In this disclosure, the conductive layer 20 may be located exposed on the surface of the wiring board 1.

[0015] The conductive layer 20 is composed of a sintered body of multiple crystallites 24 (see Figure 4). These crystallites 24 are composed of metallic materials such as copper, silver, palladium, gold, platinum-tungsten, molybdenum, or manganese, or alloy materials or mixed materials mainly composed of these metallic materials.

[0016] In this embodiment, as shown in Figure 2, the conductive layer 20 has a layered structure in which a dense layer 21, a non-dense layer 22, and a dense layer 23 are stacked in this order in the thickness direction (vertical direction in Figure 2).

[0017] The non-compact layer 22 has multiple voids 25 (see Figure 4) and is less compact than the compact layers 21 and 23. On the other hand, the compact layers 21 and 23 have almost no voids 25 and are more compact than the non-compact layer 22.

[0018] Thus, even if stress is generated between the conductor layer 20 and the insulating layer 10 due to differences in their Young's moduli and coefficients of thermal expansion, stress relaxation can occur in the portion of the non-dense layer 22 because the apparent Young's modulus of the non-dense layer 22 is low (i.e., the apparent rigidity is low).

[0019] Therefore, according to the embodiment, peeling between the insulating layer 10 and the conductor layer 20 can be reduced.

[0020] Also, in the embodiment, when a specific range (for example, region A) of the conductor layer 20 is specified in a cross-sectional view, the straight-line length in the planar direction (the horizontal direction in FIG. 2) is L0, and the length of the contour 20a of the conductor layer 20 (i.e., the interface length between the conductor layer 20 and the insulating layer 10) is L1, L1 / L0 may be in the range of 1.04 to 1.14.

[0021] Thus, in the embodiment, by making the unevenness of the contour 20a of the conductor layer 20 relatively small, the interface conductivity of the conductor layer 20 can be increased.

[0022] Also, in the embodiment, the sintered body constituting the conductor layer 20 may contain nano-sized silica particles (not shown). And such silica particles may be located on the surface of the crystallites 24. In other words, in this wiring board 1, silica may exist on the surface of the conductor layer 20 in a particulate state.

[0023] Here, the "surface of the conductor layer 20" means, when the conductor layer 20 is formed on the surface of the insulating layer 10, the vicinity of the interface between the insulating layer 10 and the conductor layer 20. This "vicinity of the interface" includes a range with a slight width from the surface of the conductor layer 20 to the inside of the conductor layer 20. This "slight width" is, for example, within 1 μm from the surface of the conductor layer 20.

[0024] In this embodiment, the presence of nano-sized silica particles on the surface of the conductive layer 20 enhances the adhesion between the conductive layer 20 and the insulating layer 10. The silica particles may be present across the entire surface of the conductive layer 20 facing the insulating layer 10, or they may be present only on a portion of the surface of the conductive layer 20. If multiple silica particles are present on the surface of the conductive layer 20, these silica particles may exist in isolation from one another.

[0025] The reason why the presence of silica particles on the surface of the conductive layer 20, or near the interface between the insulating layer 10 and the conductive layer 20, increases the adhesion between the insulating layer 10 and the conductive layer 20 is thought to be partly because the shrinkage behavior of the metal material (for example, copper) used in the conductive layer 20 during firing is similar to that of the silica particles.

[0026] Furthermore, the reason why the shrinkage behavior of the metal material used in the conductive layer 20 during firing is similar to that of the silica particles is thought to be due to the minute size (nano-size) of the silica particles.

[0027] If silica particles larger than nanoscale are used, there will be an expansion of the particle size distribution based on size, and an increase in heat capacity due to size. These factors will then alter the sintering behavior and adhesion.

[0028] Furthermore, if composite oxide glass powder is used instead of nano-sized silica particles, the temperature range in which the glass powder melts will be wider than that of nano-sized silica particles, because the glass powder contains multiple components.

[0029] For example, glass powder may have a lower melting temperature compared to nano-sized silica particles. Also, glass powder often has a wide particle size distribution. When glass powder with these properties is used, aggregation and migration due to sintering are more likely to occur within the printed pattern that becomes the conductive layer 20 during firing.

[0030] As a result, when forming the conductive layer 20, metal particles tend to grow larger, and voids tend to form within the conductive layer 20. This is because the glass powder tends to diffuse from the printed pattern area to the area that becomes the insulating layer 10.

[0031] On the other hand, when nano-sized silica particles are used, the range of temperatures at which they melt is narrower than that of glass powder due to their single composition. As a result, the conductive layer 20 becomes denser, and gently shaped recesses tend to form on the surface along the insulating layer 10.

[0032] The particle size of the silica particles according to this embodiment is preferably such that the average particle size is 1 nm to 50 nm. Among these, silica particles with an average particle size of 20 nm are preferable. Furthermore, the silica particles should preferably have a cumulative amount of 70% or more between a lower limit of 10 nm and an upper limit of 30 nm.

[0033] As described later, the disclosed conductive layer 20 is formed by using a composite powder, which is a mixture of silica particles and composite oxide glass powder with metal powder, as the solid component of the conductive paste. In this case, silica particles tend to be present on the conductive layer 20 side near the interface between the conductive layer 20 and the insulating layer 10, but the composite oxide glass powder is not found in the conductive layer 20. It is thought that the composite oxide glass powder diffuses from the conductive layer 20 to the insulating layer 10 side during firing. Thus, the non-dense layer 22 in the conductive layer 20 is considered to be the part where the composite oxide glass powder originally existed.

[0034] The dense layers 21 and 23 have areas in the planar direction of the conductor layer 20 that do not have voids 25 in a band shape. In particular, voids 25 are hardly seen in the range of 2 μm or less from the interface with the insulating layer 10. The proportion of voids 25 is preferably 3% or less when the area of ​​one of the dense layers 21 or 23 over a predetermined length is taken as 100%. The structure consists of a dense layer 21 with a proportion of voids 25 of 3% or less and a dense layer 23 with a proportion of voids 25 of 3% or less, sandwiched between a non-dense layer 22.

[0035] The proportion of voids 25 in the non-dense layer 22 is preferably 5% or more and 40% or less when the area over a predetermined length is set to 100%. In this case, when the predetermined length is further divided and measurements are taken, the non-dense layer 22 may be distributed in the planar direction as follows: a portion with a void ratio of 5% or more and 10% or less, a portion with a void ratio of more than 10% and 30% or less, and a portion with a void ratio of more than 30% and 40% or less.

[0036] A good method for distinguishing between the dense layers 21 and 23 and the non-dense layer 22 in the conductor layer 20 is to use the difference in porosity of each part. In this case, a difference of porosity of 2% or more between the dense layers 21 and 23 and the non-dense layer 22 is a good guideline. The difference in porosity may be 5% or more, or even 10% or more. For example, the dense layers 21 and 23 have a porosity of 3% or less. On the other hand, the non-dense layer 22 is located in the center of the thickness direction of the conductor layer 20 and has a porosity of 5% or more.

[0037] When identifying the dense layer 21, dense layer 23, and non-dense layer 22 from the conductor layer 20, the conductor layer 20 may simply be divided into three equal parts in the thickness direction. Alternatively, a straight line parallel to the main surface of the insulating layer 10 may be applied to the conductor layer 20 at any position so as to be parallel to it, and the dense layers 21, 23 and the non-dense layer 22 may be identified visually. In this case, it is preferable that the thickness difference between the dense layers 21 and 23 located above and below the non-dense layer 22 be 1 μm or less.

[0038] Furthermore, in this embodiment, the crystallites 24 are composed mainly of copper, and a plurality of crystallites 24 may include polygonal crystallites 24 with linear edges, and these edges may be in contact with each other as grain boundaries. This makes it possible to increase the interfacial conductivity in the high-frequency range, and thus obtain a wiring substrate 1 that exhibits high interfacial conductivity in the high-frequency range.

[0039] Here, we will explain the method for evaluating the "linear edges" of the crystallite 24 using Figure 3. Figure 3 is an explanatory diagram showing the evaluation method of the crystallite 24. As shown in Figure 3, the crystallite 24 has a polygonal cross-section. As an example, the crystallite 24 shown in Figure 3 has an octagonal outline with edges S01 to S08.

[0040] For an image of the conductive layer 20 including such a cross-section, a scale (or ruler) 30 is prepared and positioned along the edge S01. The length of the portion of edge S01 that aligns with the scale (or ruler) 30 is the longest diameter d of the crystallite 24. MAX If it is 1 / 2 or more of the length, it is defined as a "straight edge".

[0041] Furthermore, the other edges S02 to S08 are each evaluated in the same way as edge S01 to determine whether they are "linear edges". In the example shown in Figure 3, edge S01 with length L01 and edge S07 with length L07 are evaluated as "linear edges". That is, the crystallite 24 shown in Figure 3 has two "linear edges". The longest diameter d of the crystallite 24 MAX The diameter should be between 1 μm and 10 μm.

[0042] For example, the evaluation described above is repeated for each side of each of the multiple crystallites 24 in the conductive layer 20 according to the embodiment. In this case, the multiple crystallites 24 may have 70% or more crystallites 24 with two or more straight sides in number proportion.

[0043] Thus, in a wiring substrate 1 having a conductive layer 20 in which crystallites 24 having two or more straight edges constitute 70% or more in number proportion, the decrease in interfacial conductivity in the high-frequency region (for example, 1 GHz to 49 GHz) can be reduced. Therefore, according to this embodiment, the interfacial conductivity of the conductive layer 20 in the high-frequency region can be increased. [Examples]

[0044] The embodiments of this disclosure will be described below in detail. In the embodiments described below, a wiring substrate having an insulating layer made of glass ceramics and a conductive layer mainly composed of copper will be shown, but this disclosure is not limited to the embodiments described below.

[0045] <Examples> First, a mixture of 40 wt% alumina particles and 60 wt% borosilicate glass was prepared as the material for the insulating layer. This mixture is a glass ceramic raw material with a firing temperature of 900°C to 1000°C.

[0046] Furthermore, as an organic binder, 20 parts by mass of isobutyl methacrylate resin and dibutyl phthalate were used per 100 parts by mass of glass ceramic raw material, and a green sheet with a thickness of 100 μm was produced by doctor blade molding.

[0047] Furthermore, as raw materials for the conductive layer, copper powder with an average particle size of 2 μm (purity 99.9 wt%), silica particles with an average particle size of 20 nm, and borosilicate glass powder with an average particle size of 2 μm were prepared. The silica particles had a cumulative amount of 70% or more between a lower limit of 10 nm and an upper limit of 30 nm.

[0048] The amount of silica particles added was 1 part by mass per 100 parts by mass of copper powder (i.e., a silica particle content of 1 wt%). Similarly, the amount of glass powder added was 1 part by mass per 100 parts by mass of copper powder (i.e., a glass powder content of 1 wt%).

[0049] Furthermore, an organic binder was used, consisting of isobutyl methacrylate resin and a mixed solvent of butyl carbitol acetate and dibutyl phthalate. Then, isobutyl methacrylate resin was added at a ratio of 5 parts by mass per 100 parts by mass of copper powder, and the mixed solvent of butyl carbitol acetate and dibutyl phthalate was further added to prepare a conductive paste containing copper powder, silica particles, and glass powder.

[0050] Next, conductive paste was printed onto both surfaces of the fabricated green sheet in a predetermined area and then fired. The firing was performed in a reducing atmosphere using a hydrogen-nitrogen mixed gas, with a maximum temperature of 930°C and a holding time of 2 hours. Multiple green sheets were stacked to a thickness of 500 μm. This obtained the wiring board 1 of the example.

[0051] <Reference example> Except for the composition of the conductive paste in the conductive paste manufacturing process, the reference example wiring board 1 was obtained using the same methods and conditions as in the above-described examples.

[0052] In the reference example, silica particles were not added during the manufacturing process of the conductive paste. Furthermore, the amount of glass powder added was 1 part by mass per 100 parts by mass of copper powder (i.e., a glass powder content of 1 wt%).

[0053] <Various evaluations> Next, the wiring board 1 of the embodiment and reference example obtained above was cut, the cut surface was mirror-polished, and the cross-section was observed with a scanning electron microscope (SEM). Figure 4 shows an SEM observation photograph of the conductor layer 20 according to the embodiment.

[0054] As shown in Figure 4, in the wiring board 1 of the embodiment, the conductive layer 20 is composed of a sintered body of multiple crystallites 24 mainly composed of metal. Furthermore, in the wiring board 1 of the embodiment, the conductive layer 20 has a layered structure in which a dense layer 21, a non-dense layer 22, and a dense layer 23 are stacked in layers.

[0055] When specifying the dense layer 21, non-dense layer 22, and dense layer 23 from the conductor layer 20, a straight line parallel to the main surface of the insulating layer 10 was drawn parallel to any position on the conductor layer 20, and the dense layers 21, 23 and non-dense layer 22 were identified by visual inspection. In this case, the difference in thickness between the dense layers 21 and 23 located above and below the non-dense layer 22 was 1 μm or less.

[0056] In the fabricated wiring board 1, as shown in Figure 4, the thickness of the conductor layer 20 varied along its longitudinal direction (the direction of the interface between the insulating layer 10 and the conductor layer 20 in Figure 4). Therefore, the conductor layer 20 was divided so that its thickness was 1 μm or less, and the dense layers 21, 23, and non-dense layer 22 were identified from these divided portions. The porosity of each layer was determined by image analysis of photographs taken with an electron microscope.

[0057] Although not shown in the diagram, in the reference example wiring board 1, the conductor layer 20 did not have a layered structure in which a dense layer 21, a non-dense layer 22, and a dense layer 23 were stacked.

[0058] In other words, in this disclosure, it is presumed that by adding both silica particles and glass powder to the conductive paste, the formation of voids 25 in the central part of the thickness direction of the conductive layer 20 is promoted.

[0059] Furthermore, using the SEM observation images obtained above, the ratio L1 / L0 of the length L1 of the contour 20a of the conductive layer 20 to the straight length L0 in the planar direction was measured in the example and the reference example, respectively.

[0060] Specifically, first, points A and B were marked at both ends of a contour 20a of the conductive layer 20 as seen in the cross-sectional photograph, and a straight line was drawn between points A and B, with the length of this straight line being defined as L0. Next, the length of the contour 20a from point A to point B was determined using an image processing device, and this length was defined as L1. Finally, the ratio of the two lengths, L1 / L0, was calculated.

[0061] Furthermore, using the SEM observation images obtained above, we evaluated the number of edges of multiple crystallites 24 in the example and confirmed that more than 70% of the crystallites 24 had two or more straight edges.

[0062] Furthermore, the interfacial conductivity of the wiring board 1 of the examples and reference examples obtained above was measured. The interfacial conductivity was measured using the dielectric cylindrical resonator method shown below. For the measurement, a sample with a diameter of 50 mm and a conductive layer 20 formed on almost the entire surface of both sides was used.

[0063] The dielectric cylinder resonator method is a method for measuring interfacial conductivity by forming a dielectric resonator by attaching an insulating layer with a conductor formed inside to one or both ends of a dielectric cylinder made of a dielectric material with known relative permittivity and dielectric loss, in a predetermined relationship, thereby measuring the conductivity at the interface between the conductor and the insulating layer, i.e., the conductor interface.

[0064] The principle of this measurement method is that when an electromagnetic field resonator is constructed by sandwiching a dielectric cylinder having a predetermined dimensional ratio (height h / diameter d) between two sufficiently large conducting plates (usually conducting plates with a diameter D about three times the diameter d of the dielectric cylinder) positioned parallel to each other, the high-frequency current flowing through the conducting plates due to the TEomn resonant mode (hereinafter referred to as the TEomn mode) is distributed only on the short-circuit surface, i.e., the surface facing the dielectric and the conductor.

[0065] In a dielectric resonator, the high-frequency current flowing through a conductor due to TEomn modes (m=1,2,3..., n=1,2,3...) is distributed only at the interface between the conductor and the dielectric substrate in contact with the dielectric cylinder. This allows for the calculation of the interface conductivity from the measured resonant frequencies f0 of the TEomn modes (m=1,2,3..., n=1,2,3...), and the unloaded Q and Qu. The interface conductivity was measured at a frequency of 10 GHz.

[0066] Furthermore, the adhesion between the insulating layer 10 and the conductor layer 20 in the wiring board 1 of the above-mentioned examples and reference examples was evaluated by a temperature cycling test. In this temperature cycling test, the maximum temperature was set to 125°C and the minimum temperature to -55°C. After leaving the sample at the maximum and minimum temperatures for 30 minutes each, the temperature was changed over a period of 30 seconds, and this condition was followed by 1000 cycles. After the temperature cycling test, the presence or absence of delamination between the insulating layer 10 and the conductor layer 20 was checked in the sample.

[0067] Here, Table 1 shows the silica particle and glass powder content in the conductive layer 20, the L1 / L0 value in the conductive layer 20, the area ratio of silica particles in the conductive layer 20, the measurement results of the interfacial conductivity at a frequency of 10 (GHz), and the adhesion evaluation results for the examples and reference examples. Note that the measurement results of the interfacial conductivity at a frequency of 10 (GHz) are relative values ​​when the interfacial conductivity at DC is set to 100 (%).

[0068] [Table 1]

[0069] The results are shown in Table 1. In the example shown in Table 1, the conductor layer 20 had a layered structure in which a dense layer 21, a non-dense layer 22, and a dense layer 23 were stacked in layers, while the conductor layer 20 of the reference example had a microstructure that was generally equivalent to dense layers 21 and 23. As shown in the example in Table 1, it can be seen that delamination between the insulating layer 10 and the conductor layer 20 can be reduced by making the conductor layer 20 a layered structure in which a dense layer 21, a non-dense layer 22, and a dense layer 23 are stacked in layers.

[0070] Furthermore, as shown in Table 1, it can be seen that the interfacial conductivity of the conductive layer 20 can be increased to 89% by setting the L1 / L0 value in the conductive layer 20 to the range of 1.04 to 1.14. The conductive layer 20 in the fabricated example contained silica particles. The conductive layer 20 also had a structure in which multiple crystallites 24 contained polygonal crystallites 24 with linear edges, and these edges were in contact with each other as grain boundaries. When the L1 / L0 value of the conductive layer 20 was evaluated by dividing it in the longitudinal direction, the average value was 1.05, as shown in Table 1, but individual parts had values ​​ranging from 1.04 to 1.14.

[0071] While embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments, and various modifications are possible without departing from its spirit. For example, the above embodiments show an example in which fine silica particle powder is added to the conductive paste, which is the raw material for the conductive layer 20, but the present disclosure is not limited to such examples.

[0072] For example, ceramic fine powders other than silica (such as alumina fine powder) may be added to the conductive paste. This will also provide the same effects as those in the above embodiment.

[0073] Further effects and other embodiments can be readily derived by those skilled in the art. Therefore, broader embodiments of this disclosure are not limited to the specific details and representative embodiments expressed and described above. Accordingly, various modifications are possible without departing from the spirit or scope of the overall concept of the invention as defined by the appended claims and their equivalents. [Explanation of Symbols]

[0074] 1 Wiring board 10 Insulating layer 20 Conductor layer 20a Contour 21 Compact layer 22 Non-dense layer 23 compact layer 24 crystallites 25 void

Claims

1. An insulating layer made of ceramics, A conductive layer extending in the planar direction within the insulating layer, Equipped with, The conductive layer is composed of a sintered body of multiple crystallites mainly composed of metal, and has a layered structure in which a dense layer, a non-dense layer, and a dense layer are stacked in this order in the thickness direction. The sintered body contains silica particles, The plurality of crystallites include polygonal crystallites with straight edges, The silica particles are located on the edges, The non-dense layer has a plurality of voids Wiring board.

2. The silica particles have a diameter of 1 nm to 50 nm. The wiring board according to claim 1.

3. The aforementioned crystallite is composed mainly of copper, Multiple crystallites are in contact with each other at the edges, which serve as grain boundaries. A wiring board according to claim 1 or 2.

4. The plurality of crystallites have 70% or more crystallites with two or more edges in number proportion. The wiring board according to claim 3.

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