Semiconductor equipment

Abstract

To provide a transistor using an oxide semiconductor layer and having electrical characteristics required for a particular application, and a semiconductor device including the transistor.SOLUTION: A transistor 440a includes a semiconductor layer, source or drain electrode layers 405a and 405b, a gate insulating film 402, and a gate electrode layer 401 stacked in this order over an oxide insulating film 436. The transistor 440a uses an oxide semiconductor stack including at least two oxide semiconductor layers 101 and 102 having different band gaps as the semiconductor layers. Oxygen or a dopant may be introduced into the oxide semiconductor stack.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method of manufacturing the same.

[0002] In the present specification, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

Background Art

[0003] Techniques for forming a transistor (also referred to as a thin film transistor (TFT)) using a semiconductor thin film have attracted attention. The transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (display device). As a semiconductor thin film applicable to the transistor, a silicon-based semiconductor material is widely known, but an oxide semiconductor has attracted attention as another material. ]]

[0004] [[ID=,32]]

[0005]

[0006]

Prior Art Documents

Patent Documents

[0006] ]]

Patent Document 1

Non-Patent Document

[0007]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] When the on characteristics of a transistor (e.g., on-current and field-effect mobility) are improved, high-speed response and high-speed driving with respect to an input signal become possible in a semiconductor device, and a higher-performance semiconductor device can be realized. On the other hand, for power consumption reduction of a semiconductor device, it is required that the off-current of the transistor be sufficiently low. Thus, the electrical characteristics required for a transistor vary according to the application and purpose, and it is beneficial to control the electrical characteristics more precisely. When the on characteristics of a transistor (e.g., on-current and field-effect mobility) are improved, high-speed response and high-speed driving with respect to an input signal become possible in a semiconductor device, and a higher-performance semiconductor device can be realized. On the other hand, for power consumption reduction of a semiconductor device, it is required that the off-current of the transistor be sufficiently low. Thus, the electrical characteristics required for a transistor vary according to the application and purpose, and it is beneficial to control the electrical characteristics more precisely. When the on characteristics of a transistor (e.g., on-current and field-effect mobility) are improved, high-speed response and high-speed driving with respect to an input signal become possible in a semiconductor device, and a higher-performance semiconductor device can be realized. On the other hand, for power consumption reduction of a semiconductor device, it is required that the off-current of the transistor be sufficiently low. Thus, the electrical characteristics required for a transistor vary according to the application and purpose, and it is beneficial to control the electrical characteristics more precisely. When the on characteristics of a transistor (e.g., on-current and field-effect mobility) are improved, high-speed response and high-speed driving with respect to an input signal become possible in a semiconductor device, and a higher-performance semiconductor device can be realized. On the other hand, for power consumption reduction of a semiconductor device, it is required that the off-current of the transistor be sufficiently low. Thus, the electrical characteristics required for a transistor vary according to the application and purpose, and it is beneficial to control the electrical characteristics more precisely. When the on characteristics of a transistor (e.g., on-current and field-effect mobility) are improved, high-speed response and high-speed driving with respect to an input signal become possible in a semiconductor device, and a higher-performance semiconductor device can be realized. On the other hand, for power consumption reduction of a semiconductor device, it is required that the off-current of the transistor be sufficiently low. Thus, the electrical characteristics required for a transistor vary according to the application and purpose, and it is beneficial to control the electrical characteristics more precisely.

[0009] It is an object to provide a transistor structure and a method of manufacturing the same that can set the threshold voltage of the electrical characteristics of a transistor using an oxide semiconductor in a channel formation region to a plus, and can realize a so-called normally-off switching element. It is an object to provide a transistor structure and a method of manufacturing the same that can set the threshold voltage of the electrical characteristics of a transistor using an oxide semiconductor in a channel formation region to a plus, and can realize a so-called normally-off switching element. It is an object to provide a transistor structure and a method of manufacturing the same that can set the threshold voltage of the electrical characteristics of a transistor using an oxide semiconductor in a channel formation region to a plus, and can realize a so-called normally-off switching element.

[0010] It is desirable that a channel of a transistor be formed at a positive threshold voltage as close as possible to 0V of the gate voltage. When the threshold voltage of a transistor is negative, the gate voltage is It is desirable that a channel of a transistor be formed at a positive threshold voltage as close as possible to 0V of the gate voltage. When the threshold voltage of a transistor is negative, the gate voltage is Even at 0V, current flows between the source and drain electrodes, making it prone to what is known as a normally-on state. In LSIs, CPUs, and memory, the electrical characteristics of the transistors that make up the circuit are important. These electrical characteristics affect the power consumption of semiconductor devices. In particular, the electrical characteristics of transistors Of these properties, the threshold voltage (Vth) is important. Even if the field-effect mobility is high, the threshold When the voltage is negative, it is difficult to control the circuit. Transistors, which form a drain and allow drain current to flow, are used in integrated circuits of semiconductor devices. It is unsuitable as a transistor.

[0011] Furthermore, depending on the materials and manufacturing conditions, the manufactured transistor may not normally turn off. Even in such cases, it is important to approximate the normally-off characteristics, and the threshold voltage is Even in an inusive state, or so-called normally-on state, the transistor threshold is brought closer to zero. One of the objectives is to provide a configuration and a method for manufacturing it.

[0012] Furthermore, in order to realize a higher-performance semiconductor device, the on-characteristics of the transistor (for example, on A configuration that improves current and field-effect mobility to achieve high-speed response and high-speed drive of semiconductor devices. Providing a method for producing the same is also one of the objectives.

[0013] As described above, using an oxide semiconductor layer with the electrical characteristics required for the application One of the objectives is to provide a transistor and a semiconductor device having the transistor. [Means for solving the problem]

[0014] A semiconductor layer, a source electrode layer and a drain electrode layer, a gate insulating film and a gate electrode layer are stacked in order. In a layered transistor, the semiconductor layer has at least one with different energy gaps. This also uses an oxide semiconductor stack containing two oxide semiconductor layers.

[0015] In a case where the oxide semiconductor stack is a stacked structure of a first oxide semiconductor layer and a second oxide semiconductor layer In total, the first oxide semiconductor layer and the second oxide semiconductor layer have their respective energy values The caps just need to be different, and the stacking order is not limited; the side in contact with the gate insulating film is energy It can be a layer with a large gap, or a layer with a small energy gap.

[0016] Specifically, in an oxide semiconductor stack, the energy gap of one of the oxide semiconductor layers is The energy gap of the other oxide semiconductor layer shall be 3 eV or greater, and the energy gap of the other oxide semiconductor layer shall be less than 3 eV. In this specification, the term "energy gap" is used in conjunction with "band gap" and " It is used with the same meaning as "prohibited belt width".

[0017] When an oxide semiconductor stack is made into a stacked structure of three or more layers, all oxide semiconductor layers are different from each other. It may be a structure having an energy gap, or it may have a structure with almost the same energy gap. Multiple oxide semiconductor layers may be used in a stacked oxide semiconductor structure.

[0018] For example, an oxide semiconductor stack consists of a first oxide semiconductor layer, a second oxide semiconductor layer, and a third In a stacked structure of oxide semiconductor layers, the energy gap of the second oxide semiconductor layer is set to the first The energy gap between the first oxide semiconductor layer and the third oxide semiconductor layer is made smaller. This relates to the electron affinity of the second oxide semiconductor layer to the first oxide semiconductor layer and the third oxide semiconductor layer. The electron affinity of the body layer is made greater than that of the body layer. In this case, the first oxide semiconductor layer and the third oxide The energy gap and electron affinity of a semiconductor layer can be considered equivalent. A second oxide semiconductor layer with a small energy gap is placed over the first oxide semiconductor layer with a large energy gap. By creating a structure sandwiched between a body layer and a third oxide semiconductor layer, the transistor can be further improved. This has the effect of reducing off-current (leakage current). Here, electron affinity is the vacuum level and This represents the energy difference between the conduction band and the energy band of an oxide semiconductor.

[0019] In a transistor using an oxide semiconductor layer, the energy gap of the oxide semiconductor layer This affects the electrical characteristics of the transistor. For example, a transistor using an oxide semiconductor layer In a stylus, if the energy gap of the oxide semiconductor layer is small, the ON characteristics (for example, O Current and field-effect mobility improve, while the energy gap of the oxide semiconductor layer becomes larger. This reduces the off-current.

[0020] In a single-layer oxide semiconductor layer, the size of the energy gap of the oxide semiconductor layer determines the transient Since the electrical characteristics of a transistor are largely determined, the goal is to impart the desired electrical characteristics to the transistor. That is difficult.

[0021] Using an oxide semiconductor stack with multiple oxide semiconductor layers having different energy gaps By doing so, the electrical characteristics of the transistor can be controlled with greater precision, and the desired This makes it possible to impart electrical characteristics to transistors.

[0022] Therefore, we provide semiconductor devices that meet various purposes, such as high functionality, high reliability, or low power consumption. It is possible.

[0023] One embodiment of the invention disclosed herein is a first oxide semiconductor with different energy gaps. An oxide semiconductor stack including a conductive layer and a second oxide semiconductor layer, and a saw on the oxide semiconductor stack. A source electrode layer and a drain electrode layer, and a gate insulating film on the source electrode layer and the drain electrode layer, This semiconductor device has a gate electrode layer that overlaps with an oxide semiconductor stack on a gate insulating film.

[0024] One embodiment of the invention disclosed herein is a first oxide semiconductor layer, a second oxide semiconductor An oxide semiconductor stack comprising, in order, a layer and a third oxide semiconductor layer, and a so A source electrode layer and a drain electrode layer, and a gate insulating film on the source electrode layer and drain electrode layer. The gate insulating film has a gate electrode layer that overlaps with an oxide semiconductor stack, and the second oxide semiconductor The body layer is smaller than the energy gap between the first oxide semiconductor layer and the third oxide semiconductor layer. This is a semiconductor device having a large energy gap.

[0025] In the above configuration, the oxide semiconductor stack is island-shaped, and the source electrode layer and drain electrode layer are It can be formed in contact with the side (edge) of the oxide semiconductor stack. The sides (edges) of the volume layer consist of a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide Since the side (edge) of the semiconductor layer is exposed, the first oxide semiconductor layer and the second oxide semiconductor layer The body layer and the third oxide semiconductor layer are configured to be in contact with the source electrode layer and the drain electrode layer.

[0026] One embodiment of the invention disclosed herein involves an oxide insulating film with different energy gaps. An oxide semiconductor stack is formed, which includes two oxide semiconductor layers, and a source is placed on the oxide semiconductor stack. An electrode layer and a drain electrode layer are formed, and a gate insulation covers the source electrode layer and the drain electrode layer. This is a method for fabricating a semiconductor device by forming a film and then forming a gate electrode layer on a gate insulating film.

[0027] One embodiment of the invention disclosed herein involves an oxide insulating film with different energy gaps. A stack of oxide semiconductor films is formed, a mask is formed on the stack of oxide semiconductor films, and the mask is used The oxide semiconductor layer is formed by etching the stack of oxide semiconductor films, and the oxide semiconductor layer A source electrode layer and a drain electrode layer are formed on a layer, and the source electrode layer and the drain electrode layer are covered. A method for fabricating a semiconductor device in which a gate insulating film is formed and a gate electrode layer is formed on the gate insulating film. It is the law.

[0028] Furthermore, by introducing a dopant into the oxide semiconductor stack using the gate electrode layer as a mask, self-alignment is achieved. The channel formation region is sandwiched between the channel formation region, and the resistance is lower than the channel formation region, and the low resistance contains a dopant. A region may be formed. The dopant is an impurity that changes the conductivity of the oxide semiconductor stack. Yes. Methods for introducing dopants include ion implantation, ion doping, and plasma injection. Methods such as Merjohn ion implantation can be used.

[0029] The oxide semiconductor stack includes a low-resistance region sandwiched between channel-forming regions in the channel length direction. As a result, the transistor has high on-characteristics (e.g., on-current and field-effect mobility). This enables high-speed operation and fast response.

[0030] Furthermore, a heat treatment (dehydration) is performed to release hydrogen or moisture from the oxide semiconductor layer (oxide semiconductor film). A water-based or dehydrogenation treatment may be performed. For example, in the above configuration, before forming the mask Next, a heat treatment is performed to release hydrogen or moisture contained in the stacked oxide semiconductor film. It is preferable to do so.

[0031] Furthermore, dehydration or dehydrogenation treatment removes oxygen, which is the main component material constituting oxide semiconductors. There is a risk that oxygen will be simultaneously desorbed and reduced. In oxide semiconductor films, oxygen is desorbed. In the affected area, an oxygen deficiency exists, which causes fluctuations in the transistor's electrical characteristics. This can result in a donor level being created.

[0032] Therefore, oxygen is added to the oxide semiconductor layer (oxide semiconductor film) that has undergone dehydration or dehydrogenation treatment. It is preferable to supply oxygen. By supplying oxygen to the oxide semiconductor layer (oxide semiconductor film) This allows for the replenishment of oxygen deficiencies in the membrane.

[0033] For example, an oxide insulating film containing a large amount (excess) of oxygen, which serves as an oxygen source, is used as an oxide semiconductor layer. By providing it in contact with the oxide semiconductor film, the oxide semiconductor layer (acid) is separated from the oxide insulating film. Oxygen can be supplied to the (hydrogenated semiconductor film). In the above configuration, dehydration or dehydrogenation As a process, heat treatment is performed on an oxide semiconductor layer (oxide semiconductor film) and an oxide insulating film, in small quantities. By performing heat treatment while at least a part of it is in contact, the oxide semiconductor layer (oxide semiconductor film) is created. Oxygen may be supplied to ).

[0034] Furthermore, in an oxide semiconductor layer (oxide semiconductor film) that has undergone dehydration or dehydrogenation treatment, oxygen (low Even if not present, an oxygen radical, oxygen atom, or oxygen ion is introduced into the membrane. Oxygen may be supplied. Methods for introducing oxygen include ion implantation and ion doping. Plasma immersion ion implantation and plasma treatment can be used. can.

[0035] Furthermore, preferably, the oxide semiconductor layer (oxide semiconductor film) provided in the transistor is acid In a crystalline semiconductor, there is a region where the oxygen content is excessive compared to the stoichiometric composition ratio in the crystalline state. It is best to consider it as a film that is embedded. In this case, the oxygen content is the stoichiometric composition of the oxide semiconductor. The ratio should be greater than the actual ratio. Alternatively, the oxygen content should be greater than the amount of oxygen in the case of a single crystal. Let it be in degrees. Oxygen may also be present between the lattice of oxide semiconductors.

[0036] Hydrogen or water is removed from the oxide semiconductor, and it is purified to the highest possible purity with as few impurities as possible. By supplying oxygen and compensating for the oxygen deficiency, a type I (intrinsic) oxide semiconductor is produced, or type I It is possible to create an oxide semiconductor that is very close to (intrinsic). By doing so, oxide To raise the Fermi level (Ef) of a semiconductor to the same level as the intrinsic Fermi level (Ei). Therefore, by using this oxide semiconductor film in a transistor, oxygen vacancies can be eliminated. Reduces the variation in the threshold voltage Vth of transistors and the threshold voltage shift ΔVth. It is possible.

[0037] One embodiment of the present invention has a transistor or a circuit comprising a transistor. This relates to semiconductor devices. For example, in an oxide semiconductor, a channel formation region is formed, This relates to a semiconductor device having a circuit that includes a star or transistor. LSIs, CPUs, power devices mounted in power supply circuits, memory, thyristors, Semiconductor integrated circuits including converters and image sensors, and electronic displays such as liquid crystal displays. This relates to electronic equipment that incorporates light-emitting display devices, such as gas-optical devices and light-emitting elements, as components. [Effects of the Invention]

[0038] Using an oxide semiconductor stack with multiple oxide semiconductor layers having different energy gaps By doing so, the electrical characteristics of the transistor can be controlled with greater precision, and the desired This makes it possible to impart electrical characteristics to transistors.

[0039] Therefore, we provide semiconductor devices that meet various purposes, such as high functionality, high reliability, or low power consumption. It is possible. [Brief explanation of the drawing]

[0040] [Figure 1] A diagram illustrating one form of semiconductor device. [Figure 2] A diagram illustrating one form of semiconductor device and a method for manufacturing such a device. [Figure 3] A diagram illustrating one form of semiconductor device. [Figure 4] A diagram and energy band diagram illustrating a form of semiconductor device. [Figure 5] A diagram illustrating one form of semiconductor device and a method for manufacturing such a device. [Figure 6] A diagram illustrating one form of semiconductor device and a method for manufacturing such a device. [Figure 7] A diagram illustrating one form of semiconductor device. [Figure 8] A diagram illustrating one form of semiconductor device. [Figure 9] A diagram illustrating one form of semiconductor device. [Figure 10] A diagram illustrating one form of semiconductor device. [Figure 11] A diagram showing electronic equipment. [Figure 12] A diagram showing the ionization potential. [Figure 13] A diagram showing the energy bands. [Figure 14] TEM image of a sample of the embodiment and its schematic diagram. [Modes for carrying out the invention]

[0041] Hereinafter, embodiments of the invention disclosed herein will be described in detail with reference to the drawings. However, the inventions disclosed herein are not limited to the following description, and their forms and details may vary. It will be readily apparent to those skilled in the art that this can be changed. This shall not be interpreted as being limited to the descriptions of the embodiments shown below. The ordinal number 2 is used for convenience only and does not indicate the order of processes or stacking. Furthermore, in this specification, a specific name is not used to identify the invention. do not have.

[0042] (Embodiment 1) In this embodiment, one form of semiconductor device and a method for manufacturing a semiconductor device is shown using Figures 1 and 3. Let me explain. In this embodiment, as an example of a semiconductor device, a transistor having an oxide semiconductor film is used. Show the indicator.

[0043] Even in a single-gate transistor structure where one channel formation region is formed, or where two are formed... It may be a double-gate structure or a triple-gate structure with three gates formed. It has two gate electrode layers arranged above and below the channel region with a gate insulating film in between. A dual-gate type would also be acceptable.

[0044] Transistors 440a and 440b shown in Figures 1(A) and 1(B) are top gate transistors. This is an example of a planar transistor with a structure.

[0045] As shown in Figures 1(A) and 1(B), transistors 440a and 440b are oxidized. A first oxide with a different energy gap is placed on a substrate 400 on which a material insulating film 436 is provided. Oxide semiconductor stack 403 including semiconductor layer 101 and second oxide semiconductor layer 102, source The electrode layer 405a, drain electrode layer 405b, gate insulating film 402, and gate electrode layer 401 An insulating film 407 is formed on transistors 440a and 440b. It is.

[0046] In Figure 1, the interface between the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102. The dotted line in the diagram is a schematic representation of the oxide semiconductor stack 403. Depending on the materials, film deposition conditions, and heat treatment, the first oxide semiconductor layer 101 and the second oxide semiconductor layer may be formed. The interface with body layer 102 may become unclear. If it becomes unclear, it may be composed of multiple different oxides. A mixed region or a region that can be called a mixed layer may also be formed in the semiconductor layer. The same applies to the other drawings in this specification.

[0047] In the oxide semiconductor stack 403, the first oxide semiconductor layer 101 and the second oxide semiconductor Each layer 102 only needs to have a different energy gap, and its stacking order is not limited. I can't.

[0048] Specifically, in the oxide semiconductor stack 403, the energy g of one of the oxide semiconductor layers The energy gap of one oxide semiconductor layer is set to 3 eV or more, and the energy gap of the other oxide semiconductor layer is set to less than 3 eV. .

[0049] The transistor 440a shown in Figure 1(A) is formed by the second oxide from the first oxide semiconductor layer 101. This is an example where the semiconductor layer 102 has a larger energy gap. In this embodiment, In the lampistor 440a, the first oxide semiconductor layer 101 is an In-Sn-Zn system oxide Solid film (energy gap 2.6eV~2.9eV, typically 2.8eV), second acid The oxide semiconductor layer 102 is an In-Ga-Zn oxide (also written as IGZO) film ( An energy gap of 3.0 eV to 3.4 eV (typically 3.2 eV) is used.

[0050] On the other hand, the transistor 440b shown in Figure 1(B) is located in the second region from the first oxide semiconductor layer 101. The oxide semiconductor layer 102 is an example where the energy gap is smaller. So, as the first oxide semiconductor layer 101 in transistor 440b, In-Ga-Z n-based oxide film (energy gap 3.2 eV), as the second oxide semiconductor layer 102 An In-Sn-Zn oxide film (energy gap 2.8 eV) is used.

[0051] Thus, in the oxide semiconductor stack 403, the first oxide semiconductor layer 101 and the second The oxide semiconductor layer 102 has a larger energy gap on the side in contact with the gate insulating film 402. It can be a layer, or it can be a layer with a small energy gap.

[0052] Figure 4(A) shows an oxide semiconductor stack 403 consisting of a first oxide semiconductor layer 101 and a second oxide semiconductor layer Transition using a stacked three-layer structure of semiconductor layer 102 and third oxide semiconductor layer 103 This indicates Ta480a.

[0053] Transistor 480a is provided on a substrate 400 on which an oxide insulating film 436 is attached, first oxide It includes a monocrystalline semiconductor layer 101, a second oxide semiconductor layer 102, and a third oxide semiconductor layer 103. A multilayer oxide semiconductor 403, a source electrode layer 405a, a drain electrode layer 405b, and a gate electrode layer. It has a border film 402 and a gate electrode layer 401. On the transistor 480a, there is an insulating film 407 It is formed.

[0054] In Figure 4, the boundary between the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102. The surface is shown with dotted lines, which schematically represent the oxide semiconductor stack 403. Depending on the materials, film formation conditions, and heat treatment, the first oxide semiconductor layer 101 and the second oxide In some cases, the interface with the semiconductor layer 102 may become unclear. If it becomes unclear, different multiple acids may be used. A mixed region or a region that can be called a mixed layer may also be formed in the ionized semiconductor layer. The same applies to the interface between the second oxide semiconductor layer 102 and the third oxide semiconductor layer 103.

[0055] In the oxide semiconductor stack 403 of transistor 480a, the first oxide semiconductor layer 101 Energy gap between the second oxide semiconductor layer 102 and the third oxide semiconductor layer 103 These are not all the same, and each contains at least two different energy gap values.

[0056] When the oxide semiconductor stack 403 has a stacked structure of three or more layers, all oxide semiconductor layers The structures may have different energy gaps, or they may have almost the same energy gap. Multiple oxide semiconductor layers having a rib may be used in the oxide semiconductor stack 403.

[0057] Oxide semiconductor stack 403 (first oxide semiconductor layer 101, second oxide semiconductor layer 102, The oxide semiconductor used in the third oxide semiconductor layer 103) is at least indium ( It is preferable to include in (In) or zinc (Zn). It is especially preferable to include both in and Zn. i. Also, stabilizers to reduce variations in the electrical characteristics of transistors using the oxide It is preferable to have gallium (Ga) in addition to those as a stabilizer. It is preferable to have tin (Sn) as the riser. Also, as the stabilizer, It is preferable to have nium(Hf). Also, aluminum(A) is preferred as a stabilizer. It is preferable to have l).

[0058] Also, other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce, praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Lu It may contain one or more types of tecium (Lu).

[0059] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and the oxide of binary metals. These are In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, and Zn-Mg oxides. Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metals Oxides include In-Ga-Zn oxides, In-Al-Zn oxides, and In-Sn-Zn oxides. Sn-Ga-Zn oxides, Al-Ga-Zn oxides, Sn-Al-Zn Oxides, In-Hf-Zn oxides, In-La-Zn oxides, In-Ce-Zn acids In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm-Zn oxides Materials, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides, In-Lu-Zn ​​oxides, four In-Sn-Ga-Zn oxides and In-Hf-Ga-Zn acids are oxides of the original metals. In-Al-Ga-Zn oxides, In-Sn-Al-Zn oxides, In-Sn -Hf-Zn oxides and In-Hf-Al-Zn oxides can be used.

[0060] For example, an In-Ga-Zn oxide is a material whose main components are In, Ga, and Zn. This means an oxide containing In, Ga, and Zn, and the ratio of In, Ga, and Zn is not specified. It is also acceptable for metal elements other than a and Zn to be present.

[0061] In addition, as an oxide semiconductor, InMO3(ZnO) m (m > 0, and m is not an integer) Materials represented by may also be used. Note that M is selected from Ga, Fe, Mn, and Co. It represents one or more metallic elements. Also, as an oxide semiconductor, In2SnO5 (ZnO) n Materials expressed as (n>0 and n is an integer) may also be used.

[0062] For example, In:Ga:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn system oxidation with atomic ratio a:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) Oxides with a similar composition to the substance can be used. Alternatively, In:Sn:Zn=1: 1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5 (=1 / 4:1 / 8:5 / 8) It is advisable to use In-Sn-Zn oxides with a specific ratio or oxides with a similar composition.

[0063] However, this is not limited to these, and depends on the required semiconductor characteristics (mobility, threshold, variability, etc.) A suitable composition should be used accordingly. Furthermore, in order to obtain the required semiconductor properties, Carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond distance, density It is preferable to make the following appropriate.

[0064] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. However, Furthermore, even with In-Ga-Zn oxides, mobility can be increased by lowering the bulk defect density. It is possible to do so.

[0065] For example, if the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of an oxide with c=1 is such that the atomic ratio is In:Ga:Zn=A:B:C(A+B+C The composition of the oxide in the vicinity of (aA) = 1) means that a, b, and c are in the vicinity of (aA) 2 +(bB) 2 + (cC) 2 ≤r 2 This means that the following conditions are met, and r can be set to, for example, 0.05. The same applies to monsters.

[0066] Oxide semiconductors can be single crystals or non-single crystals. In the latter case, they can be amorphous or polycrystalline. But that's fine too. Also, even if the structure contains crystalline parts within the amorphous material, it can be non-amorphous. But that's fine.

[0067] Amorphous oxide semiconductors can be made relatively easily to obtain a flat surface, This can reduce interfacial scattering when fabricating transistors, and it can be done relatively easily and relatively high You can obtain a high degree of mobility.

[0068] Furthermore, in crystalline oxide semiconductors, bulk defects can be reduced even further, and surface By improving the flatness, it is possible to obtain mobility higher than that of an amorphous oxide semiconductor. To improve surface flatness, it is preferable to form an oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, more preferably Alternatively, it is preferable to form it on a surface with a nm or smaller.

[0069] Ra is defined in JIS B 0601:2001 (ISO 4287:1997) This is an extension of the arithmetic mean roughness that can be applied to curved surfaces in three dimensions, and is called a "reference surface." It can be expressed as "the average of the absolute values ​​of the deviations from the specified surface," and is defined by formula (1).

[0070]

number

[0071] In the above, S0 is the measurement surface (coordinates (x1,y1)(x1,y2)(x2,y1 Z0 refers to the area of ​​the quadrilateral region represented by the four points (x2, y2), and Z0 is the average height of the measured surface. Ra refers to atomic force microscope (AFM). It can be evaluated using OPE.

[0072] The first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 of the oxide semiconductor stack 403, As the third oxide semiconductor layer 103, an oxide semiconductor layer containing crystals and having crystalline properties (crystals) A crystalline oxide semiconductor layer can be used. The crystals in the crystalline oxide semiconductor layer have a crystal axis. The orientation may be disordered or it may be in a state with a certain degree of orientation.

[0073] For example, as a crystalline oxide semiconductor layer, an acid containing crystals having a c-axis approximately perpendicular to the surface. A semiconductor layer can be used.

[0074] An oxide semiconductor layer containing crystals having a c-axis roughly perpendicular to the surface does not have a single-crystal structure. It is not an amorphous structure, but a crystalline oxide semiconductor with c-axis orientation (C Axis Aligned Crystalline Oxide Semiconductor; It is a membrane (also known as CAAC-OS).

[0075] CAAC-OS films are neither perfectly single crystals nor perfectly amorphous. This is an oxide semiconductor film having a crystalline-amorphous multiphase structure with crystalline and amorphous parts in an amorphous phase. Yes, it exists. Furthermore, the crystalline portion must be small enough to fit within a cube with sides less than 100 nm long. There are many. Also, transmission electron microscopes (TEM) In the image observed using a microscope, the amorphous region contained in the CAAC-OS film and The boundary with the crystalline portion is not clear. Also, TEM revealed grain boundaries in the CAAC-OS film. Also called inboundary. ) cannot be confirmed. Therefore, the CAAC-OS film has grain boundaries. The resulting decrease in electron mobility is suppressed.

[0076] The crystalline portion contained in the CAAC-OS film has a c-axis that is the normal vector to the surface on which the CAAC-OS film is formed. Aligned in a direction parallel to the normal vector of the plane or surface, and triangular when viewed from a direction perpendicular to the ab plane. Having a shape or hexagonal atomic arrangement, the metal atoms are layered or when viewed from a direction perpendicular to the c-axis. Metal atoms and oxygen atoms are arranged in layers. Furthermore, between different crystalline regions, the a-axis is... The orientation of the b-axis may be different. In this specification, when simply referred to as vertical, 8 The range of 5° to 95° is also included. Furthermore, when simply describing something as parallel, -5 This will include the range of 5° to 5°.

[0077] Furthermore, the distribution of crystalline regions in the CAAC-OS film does not need to be uniform. For example, CAA In the formation process of a C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the shape The proportion of crystalline material may be higher near the surface compared to near the surface of the material. Also, CA By adding impurities to the AC-OS film, the crystalline region in the impurity-added area becomes amorphous. It can also become qualitative.

[0078] The c-axis of the crystalline portion contained in the CAAC-OS film is the normal vector to the surface on which the CAAC-OS film is formed. Because they are aligned in a direction parallel to the normal vector of the surface or the material, the shape of the CAAC-OS film (formed Depending on the cross-sectional shape of the surface or face, they may face in different directions. Oh, the direction of the c-axis of the crystalline portion is the normal vector to the surface on which the CAAC-OS film was formed. The direction is parallel to the normal vector of the crystalline or surface. The crystalline portion is formed by deposition, and It is formed by performing crystallization treatments such as heat treatment after film formation.

[0079] Transistors using CAAC-OS film exhibit changes in electrical properties due to irradiation with visible light and ultraviolet light. It is possible to reduce this. Therefore, the transistor in question is highly reliable.

[0080] There are three methods for obtaining a CAAC-OS film. The first is to set the deposition temperature to 200°C. The oxide semiconductor layer is deposited at a temperature of 500°C or lower, and the c-axis is oriented roughly perpendicular to the surface. The first method involves forming a thin film and then performing a heat treatment at a temperature between 200°C and 700°C. This method involves aligning the c-axis approximately perpendicular to the surface. The third method involves depositing a thin first layer of film. After that, a heat treatment is performed at 200°C to 700°C to deposit the second layer, and the surface is roughly This method involves oriented the c-axis vertically.

[0081] First oxide semiconductor layer 101, second oxide semiconductor layer 102, third oxide semiconductor layer 10 The film thickness of 3 shall be 1 nm to 100 nm (preferably 5 nm to 30 nm), Puttering method, MBE (Molecular Beam Epitaxy), CVD Methods: pulsed laser deposition, ALD (Atomic Layer Deposition) It can be manufactured using appropriate methods, etc. Also, the first oxide semiconductor layer 101, the second acid The oxide semiconductor layer 102 and the third oxide semiconductor layer 103 are located on the sputtering target surface. In contrast, using a sputtering apparatus that performs film deposition with multiple substrate surfaces set up roughly vertically... A thin film may be formed.

[0082] In a transistor using an oxide semiconductor layer, the energy gap of the oxide semiconductor layer This affects the electrical characteristics of the transistor. For example, a transistor using an oxide semiconductor layer In a stylus, if the energy gap of the oxide semiconductor layer is small, the ON characteristics (for example, O Current and field-effect mobility improve, while the energy gap of the oxide semiconductor layer becomes larger. This reduces the off-current.

[0083] Oxide semiconductor stack 40 using multiple oxide semiconductor layers with different energy gaps By using 3, transistor 440a, transistor 440b, transistor The electrical characteristics of 480A can be controlled with greater precision, and the desired electrical characteristics can be achieved with a transistor. This makes it possible to apply it to transistors 440a, 440b, and 480a.

[0084] For example, in the oxide semiconductor stack 403 of transistor 480a shown in Figure 4(A), The energy gap of the second oxide semiconductor layer 102 is shared between the first oxide semiconductor layer 101 and the third oxide semiconductor layer 102. The energy gap of the oxide semiconductor layer 103 is made smaller. In this case, the first oxide The energy gaps of semiconductor layer 101 and the third oxide semiconductor layer 103 are assumed to be approximately the same. It is possible.

[0085] Figure 4(C) shows the energy band diagram in the film thickness direction (between E1 and E2) in Figure 4(A). For transistor 480a, the energy band diagram is as shown in Figure 4(C). Oxide semiconductor layer 101, second oxide semiconductor layer 102, and third oxide semiconductor layer 1 It is preferable to select material 03. However, if an embedded channel is formed in the conduction band Since sufficient effect can be obtained, it is not always necessary to have a concave shape in both the conduction band and the valence band as shown in Figure 4(C). The energy band diagram is not limited to those having a portion; for example, it may have a recess only in the conduction band. A configuration that can obtain an energy band diagram is also acceptable.

[0086] For example, as the first oxide semiconductor layer 101 in transistor 480a, In-Ga A Zn-based oxide film (energy gap 3.2 eV) is used as the second oxide semiconductor layer 102. This is an In-Sn-Zn oxide film (energy gap 2.8 eV), the third oxide semiconductor. An In-Ga-Zn oxide film (energy gap 3.2 eV) is used as layer 103. .

[0087] Furthermore, the three-layer stacked oxide semiconductor stack 403 is the first in transistor 480a The first oxide semiconductor layer 101 is an In-Ga-Zn based oxide film, and the second oxide semiconductor layer 10 2 is an In-Zn oxide film, and the third oxide semiconductor layer 103 is In-Ga-Zn Lamination of oxide films, Ga-Zn-based oxide film as the first oxide semiconductor layer 101, second acid The oxide semiconductor layer 102 is an In-Sn-Zn oxide film, and the third oxide semiconductor layer 103 The first oxide semiconductor layer 101 is made of Ga-Zn oxide film stacking, or Ga-Zn The first oxide film is an In-Zn-based oxide film, and the second oxide semiconductor layer 102 is an In-Zn-based oxide film, and the third oxide A stacked Ga-Zn oxide film can be used as the semiconductor layer 103.

[0088] A second oxide semiconductor layer 102 with a small energy gap, and a larger energy gap The structure is sandwiched between a first oxide semiconductor layer 101 and a third oxide semiconductor layer 103. This further reduces the off-current (leakage current) of transistor 480a. It can be done.

[0089] Figures 2(A) to (E) show an example of the fabrication method using transistor 440a.

[0090] First, an oxide insulating film 436 is formed on the substrate 400.

[0091] There are no major restrictions on the substrates that can be used for substrate 400, but at least the subsequent heat treatment It is necessary to have sufficient heat resistance to withstand the following. For example, barium borosilicate gas Glass substrates such as lath and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire A substrate such as an earpiece can be used. Also, single-crystal semiconductors such as silicon and silicon carbide can be used. Substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates, etc. These can also be applied, and a substrate 400 on which semiconductor elements are provided is a substrate 400 It may be used as such.

[0092] Furthermore, a flexible substrate may be used as the substrate 400 to fabricate a semiconductor device. To fabricate such a semiconductor device, a transient containing an oxide semiconductor laminate 403 is placed on a flexible substrate. The substrate 440a may be fabricated directly, or the oxide semiconductor laminate 403 may be included in another fabricated substrate. The lunger 440a may be fabricated, then peeled off and transferred to a flexible substrate. To peel and transfer the plate to a flexible substrate, the fabricated substrate and the oxide semiconductor laminate are used. It is preferable to provide a release layer between the sta 440a and the other component.

[0093] As the oxide insulating film 436, an oxide film is formed by plasma CVD or sputtering, etc. Ricon, silicon oxide nitride, aluminum oxide, aluminum oxide nitride, hafnium oxide It can be formed using gallium oxide, or a mixture thereof.

[0094] The oxide insulating film 436 may be a single layer or a multilayer. In this embodiment, the oxide insulating film 436 and A silicon oxide film formed using the sputtering method is used.

[0095] Alternatively, a nitride insulating film may be provided between the oxide insulating film 436 and the substrate 400. The edge film is made of silicon nitride, silicon nitride oxide, etc., by plasma CVD or sputtering. Formed using aluminum nitride, aluminum nitride oxide, or mixtures thereof. It is possible.

[0096] Next, a first oxide semiconductor film 191 and a second oxide semiconductor film 1 A stack of oxide semiconductor films consisting of 92 is formed (see Figure 2(A)).

[0097] The oxide insulating film 436 is in contact with the oxide semiconductor film stack 493 (oxide semiconductor stack 403). Therefore, the membrane (bulk) contains an amount of oxygen that exceeds at least the stoichiometric composition ratio. This is preferable. For example, when a silicon oxide film is used as the oxide insulating film 436. SiO 2+α (However, assume α > 0.) Use such an oxide insulating film 436. Therefore, oxygen can be supplied to the oxide semiconductor film stack 493 (oxide semiconductor stack 403). This allows for improved properties. Lamination of oxide semiconductor film 493 (Oxide semiconductor laminate 4 By supplying oxygen to (03), the oxygen deficiency in the membrane can be compensated for.

[0098] For example, an oxide insulating film 436 containing a large amount (excess) of oxygen, which serves as an oxygen source, is used in an oxide semiconductor By providing it in contact with the laminated body film 493 (oxide semiconductor laminated film 403), the oxide semiconductor Oxygen is supplied from the edge film 436 to the oxide semiconductor film stack 493 (oxide semiconductor stack 403). This is possible. Laminated oxide semiconductor film 493 (laminated oxide semiconductor film 403) and oxide semiconductor By performing heat treatment with at least a portion of the edge film 436 in contact, the oxide semiconductor film Oxygen may be supplied to the laminated 493 (oxide semiconductor laminated 403).

[0099] Lamination of oxide semiconductor films 493 (first oxide semiconductor film 191 and second oxide semiconductor film 1 In the formation process of 92), the oxide semiconductor film is stacked 493 (first oxide semiconductor film 191 And in order to ensure that hydrogen or water is contained in the second oxide semiconductor film 192) as little as possible. In addition, a lamination of oxide semiconductor films 493 (first oxide semiconductor film 191 and second oxide semiconductor film) As a pretreatment for film deposition of film 192), the oxide insulating film 43 is heated in the preheating chamber of the sputtering apparatus. The substrate on which 6 is formed is preheated, and hydrogen and moisture adsorbed on the substrate and oxide insulating film 436 are removed. It is preferable to remove and exhaust any impurities. The exhaust means provided in the preheating chamber is a clam. Iopumps are preferred.

[0100] In the oxide insulating film 436, the oxide semiconductor film stacking 493 (oxide semiconductor stacking 403) A planarization treatment may be performed on the region formed by contact. The planarization treatment is not particularly limited. However, polishing treatment (for example, chemical mechanical polishing) Polishing (CMP), dry etching, and plasma treatment are used. It is possible.

[0101] Plasma processing can be performed, for example, by introducing argon gas to generate plasma. Sputtering can be performed. Reverse sputtering is a process where RF is applied to the substrate side under an argon atmosphere. This method involves applying a voltage using a power supply to form plasma near the substrate and modify its surface. Note that nitrogen, helium, oxygen, etc. may be used instead of an argon atmosphere. (Reverse sputtering) When the process is performed, powdery substances (particles, dust) adhering to the surface of the oxide insulating film 436 are removed. It can remove (also known as).

[0102] For planarization, polishing, dry etching, and plasma treatment can be performed multiple times. Furthermore, these can be combined. Also, when combining them, the order of the steps is not particularly limited. It is not fixed and should be set appropriately according to the surface irregularities of the oxide insulating film 436.

[0103] Furthermore, the first oxide semiconductor film 191 and the second oxide semiconductor film 192 are formed when oxygen is present during film formation. Conditions that result in a high concentration of the substance (for example, by sputtering in a 100% oxygen atmosphere) The film is formed by (for example, by making a film) and contains a large amount of oxygen (preferably an oxide semiconductor in a crystalline state) (A membrane containing a region with an excess of oxygen relative to the stoichiometric composition ratio) preferable.

[0104] In this embodiment, the first oxide semiconductor film 191 is fabricated by sputtering. For example, a target for this purpose is a composition ratio of In:Sn:Zn in terms of atomic ratio. Oxide tars such as 1:2:2, 2:1:3, 1:1:1, or 20:45:35. An In-Sn-Zn-O film is deposited using a GET method.

[0105] In this embodiment, the second oxide semiconductor film 192 is fabricated by sputtering. For example, a target composition ratio could be In2O3:Ga2O3:Zn Using an oxide target with a molar ratio of O=1:1:2, an In-Ga-Zn oxide film was created. A film is formed. Furthermore, this is not limited to the target material and composition; for example, In2O3:G A metal oxide target with a molar ratio of a2O3:ZnO = 1:1:1 may also be used.

[0106] Furthermore, the filling rate of the metal oxide target is 90% to 100%, preferably 95% or more. It is 99.9% or less. By using a metal oxide target with a high packing efficiency, the film can be formed. The oxide semiconductor film can be made into a dense film.

[0107] The first oxide semiconductor film 191 and the second oxide semiconductor film 192 are formed using the S Puttering gas is a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed. It is preferable to use [this].

[0108] The substrate is held in a deposition chamber under reduced pressure. Then, any residual moisture in the deposition chamber is removed. Sputtered gas from which hydrogen and moisture have been removed is introduced, and the substrate 40 is cut using the target described above. 493 (a stack of oxide semiconductor films 191 and a second oxide semiconductor film) is laid on top of 0. A body film (192) is deposited. To remove residual moisture in the deposition chamber, an adsorption-type vacuum pump is used. For example, by using cryopumps, ion pumps, and titanium sublimation pumps. This is preferable. Furthermore, as an exhaust means, a turbomolecular pump with a cold trap added is preferable. It may also be the case that the deposition chamber, which has been evacuated using a cryopump, contains, for example, hydrogen atoms, water ( Compounds containing hydrogen atoms (more preferably compounds containing carbon atoms) such as H2O are exhausted. Therefore, the oxide semiconductor film deposited in the deposition chamber is stacked 493 (first oxide semiconductor film The concentration of impurities in the second oxide semiconductor film 191 and 192) can be reduced.

[0109] Furthermore, the oxide insulating film 436 and the oxide semiconductor film are stacked 493 (first oxide semiconductor film 191 It is preferable to continuously form the second oxide semiconductor film 192) without exposing it to the atmosphere. i. Lamination of oxide insulating film 436 and oxide semiconductor film 493 (first oxide semiconductor film 191 and When the second oxide semiconductor film (192) is formed continuously without exposure to the atmosphere, an oxide insulating film is formed. This prevents impurities such as hydrogen and moisture from being adsorbed onto the surface of the film 436.

[0110] CAAC-OS films are used, for example, for polycrystalline oxide semiconductor sputtering targets. The film is deposited using a sputtering method. Ions are directed onto the sputtering target. Upon collision, the crystalline region contained in the sputtering target cleaves from the ab plane, and a -The sputtering particles are exfoliated as flat or pellet-shaped sputtering particles having a surface parallel to the -b surface. In this case, the flat sputtering particles maintain their crystalline state and form a base By reaching the plate, the CAAC-OS film can be deposited.

[0111] Furthermore, it is preferable to apply the following conditions for forming the CAAC-OS film.

[0112] By reducing the inclusion of impurities during film formation, it is possible to suppress the disruption of the crystalline state due to impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, and nitrogen, etc.) present in the deposition chamber. It would be good to reduce it. Also, it would be good to reduce the impurity concentration in the film formation gas. Specifically, the dew point is A film-forming gas with a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0113] Furthermore, by increasing the substrate heating temperature during film deposition, the sputtering particles can be prevented from migrating after reaching the substrate. A reaction occurs. Specifically, the substrate heating temperature is preferably between 100°C and 740°C. The film is deposited at a temperature between 200°C and 500°C. By increasing the substrate heating temperature during film deposition, the flat When plate-shaped sputtering particles reach the substrate, migration occurs on the substrate. The flat surface of the sputtering particles adheres to the substrate.

[0114] Also, it is preferable to reduce the plasma damage during film formation by increasing the oxygen ratio in the film-forming gas and optimizing the power. The oxygen ratio in the film-forming gas is 30 vol% or more, preferably 100 vol%. %

[0115] As an example of the sputtering target, an In-Ga-Zn-O compound target is shown below.

[0116] InO X powder, GaO Y powder and ZnO Z powder are mixed at a predetermined molar ratio, and after pressure treatment heat treatment is performed at a temperature of 1000 °C or higher and 1500 °C or lower to obtain a polycrystalline In-G a-Zn-O compound target. Here, X, Y, and Z are arbitrary positive numbers. Here the predetermined molar ratio is, for example, InO X powder, GaO Y powder and ZnO Z powder are 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3 or 3:1:2 mo lar ratio. The type of powder and the mixing ratio thereof may be appropriately changed depending on the sputtering target to be produced.

[0117] The stack 493 of the oxide semiconductor films (the first oxide semiconductor film 191 and the second oxide semiconductor film 1 92) is processed into an island-shaped oxide semiconductor stack 403 (the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102) by a photolithography process (see Fig. 2(B)).

[0118] Also, a resist mask for forming the island-shaped oxide semiconductor stack 403 is formed by inkjet ​​It may be formed by a method. If the resist mask is formed by the inkjet method, a photomask can be used. Since it does not require any additional components, manufacturing costs can be reduced.

[0119] Note that etching of oxide semiconductor films can be done by either dry etching or wet etching. Both may be used. For example, the etching of oxide semiconductor films. As a quenching solution, a solution of phosphoric acid, acetic acid, and nitric acid can be used. O07N (manufactured by Kanto Chemical Co., Ltd.) may also be used.

[0120] In this embodiment, the first oxide semiconductor film 191 and the second oxide semiconductor film 192 are the same Since it is formed by etching with a mask, the first oxide semiconductor layer 101 and the second The oxide semiconductor layer 102 is an oxide semiconductor layer with the same shape and matching edges on the sides. In the conductive laminate 403, the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 The sides (ends) are exposed.

[0121] Furthermore, excess hydrogen (water or water) is present in the oxide semiconductor stack 403 (the oxide semiconductor film stack 493). Heat treatment may be performed to remove (dehydrate or dehydrogenate) acid groups. The processing temperature shall be between 300°C and 700°C, or below the strain point of the substrate. This can be carried out under reduced pressure or in a nitrogen atmosphere. For example, an electric heating device is one of the heating devices. A substrate is introduced into the furnace, and the oxide semiconductor stack 403 (oxide semiconductor film stack 493) The material is subjected to a heat treatment at 450°C for 1 hour under a nitrogen atmosphere.

[0122] Furthermore, the heat treatment device is not limited to electric furnaces, but also includes heat conduction or heat from heat-generating elements such as resistance heating elements. You may use a device that heats the object to be processed by radiation. For example, RTA (Rapid Thermal Anneal) devices such as GRTA (Gas Rapid Thermal Anneal) devices and LRTA (Lamp Rapid Thermal Anneal) devices can be used. A LRTA device is a device that heats the object to be processed by the radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. A GRTA device is a device that performs heat treatment using high-temperature gas. For the high-temperature gas, inert gases such as argon or non-reactive gases such as nitrogen that do not react with the object to be processed by heat treatment are used. For example, as the heat treatment, GRTA may be performed by placing the substrate in an inert gas heated to a high temperature of 650°C to 700°C, heating for several minutes, and then taking the substrate out of the inert gas. In heat treatment, it is preferable that nitrogen or inert gases such as helium, neon, and argon do not contain water, hydrogen, etc. Or, the purity of nitrogen or inert gases such as helium, neon, and argon introduced into the heat treatment device is preferably 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). After heating the oxide semiconductor layer 403 (stacked oxide semiconductor film 493) by heat treatment, high-purity oxygen gas, high-purity dinitrogen monoxide gas, or ultra-dry air (CRDS) is introduced into the same furnace. 被処理物を加熱する装置である。GRTA装置は、高温のガスを用いて加熱処理を行う装置である。高温のガスには、 アルゴンなどの希ガス、または窒素のような、加熱処理によって被処理物と反応しない不 活性気体が用いられる。

[0123] 例えば、加熱処理として、650℃~700℃の高温に加熱した不活性ガス中に基板を入 れ、数分間加熱した後、基板を不活性ガス中から出すGRTAを行ってもよい。

[0124] なお、加熱処理においては、窒素、またはヘリウム、ネオン、アルゴン等の希ガスに、水 、水素などが含まれないことが好ましい。または、熱処理装置に導入する窒素、またはヘ リウム、ネオン、アルゴン等の希ガスの純度を、6N(99.9999%)以上好ましく は7N(99.99999%)以上(即ち不純物濃度を1ppm以下、好ましくは0.1 ppm以下)とすることが好ましい。

[0125] また、加熱処理で酸化物半導体積層403(酸化物半導体膜の積層493)を加熱した後 、同じ炉に高純度の酸素ガス、高純度の一酸化二窒素ガス、又は超乾燥エア(CRDS( The amount of moisture measured using a dew point meter (cavity ring-down laser spectroscopy) 20 ppm or less (equivalent to a dew point of -55°C), preferably 1 ppm or less, more preferably 10 ppm Air (at ppb or less) may be introduced. Oxygen gas or nitrous oxide gas, water, hydrogen, etc. It is preferable that it does not contain oxygen gas or dioxide. Alternatively, oxygen gas or dioxide introduced into the heat treatment apparatus is preferable. The purity of nitrogen gas should be 6N or higher, preferably 7N or higher (i.e., oxygen gas or nitrous oxide gas) It is preferable that the impurity concentration in the syrup be 1 ppm or less, preferably 0.1 ppm or less. Impurities are removed by dehydration or dehydrogenation treatment using oxygen gas or nitrous oxide gas. The main component material constituting the oxide semiconductor, acid, which was simultaneously reduced by the removal process. By supplying the material, the oxide semiconductor stack 403 (oxide semiconductor film stack 493) It can be purified to a high degree and electrically converted to type I (intrinsic).

[0126] Furthermore, the heat treatment for dehydration or dehydrogenation is performed on the lamination of oxide semiconductor films 493 (first acid After the formation of the oxide semiconductor film 191 and the second oxide semiconductor film 192, before the formation of the insulating film 407 Therefore, it can be done at any point in the manufacturing process of transistor 440a. For example, stacking of oxide semiconductor films 493 (first oxide semiconductor film 191 and second oxide semiconductor film After the formation of the body film 192), or the island-shaped oxide semiconductor stack 403 (first oxide semiconductor layer 10 This can be done after the formation of the first and second oxide semiconductor layers 102).

[0127] Furthermore, the heat treatment for dehydration or dehydrogenation may be carried out multiple times, and may be combined with other heat treatments. It is also possible to do this. For example, after the formation of the first oxide semiconductor film 191 and the second oxide semiconductor film 19 2. Heat treatment may be performed twice after formation.

[0128] Heat treatment for dehydration or dehydrogenation is performed on the oxide semiconductor stack 403 (first oxide semiconductor Before being processed into island-like structures as layer 101 and the second oxide semiconductor layer 102, the oxide semiconductor film The stacked 493 (first oxide semiconductor film 191 and second oxide semiconductor film 192) is made of oxide When the procedure is carried out with the insulating film 436 covering the oxygen contained in the oxide insulating film 436 is affected by the heat treatment. This is preferable because it prevents the release of these substances.

[0129] Next, on the oxide semiconductor stack 403, a source electrode layer and a drain electrode layer (same layer) are placed. A conductive film is formed, which includes wiring formed by the same process. The conductive film is able to withstand subsequent heat treatment. The following materials are used. Examples of conductive films used for the source electrode layer and drain electrode layer include: A metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, W, or the above Metal nitride films containing the following elements (titanium nitride film, molybdenum nitride film, tungsten nitride film) A film (or similar material) can be used. Also, either the underside or the upper side of a metal film such as Al or Cu. Both sides have high melting point metal films such as Ti, Mo, and W, or metal nitride films of those metals (titanium nitride film). A configuration in which molybdenum nitride film and tungsten nitride film are laminated is also possible. The conductive film used for the drain electrode layer and the drain electrode layer is formed from a conductive metal oxide. These are also good. Examples of conductive metal oxides include indium oxide (In2O3) and tin oxide (SnO3). 2) Zinc oxide (ZnO), indium tin oxide (In2O3-SnO2), i Zinc oxide (In2O3-ZnO) or silicon oxide in these metal oxide materials A product containing this can be used.

[0130] A resist mask is formed on the conductive film by a photolithography process, and selective etching is performed to form the source electrode layer 405a and the drain electrode layer 405b, and then the resist mask is removed. In this embodiment, the source electrode layer 405a and the drain electrode layer 405b are formed as tungsten films with a film thickness of 10 nm. When the film thicknesses of the source electrode layer 405a and the drain electrode layer 405b are thin, the coverage of the gate insulating film 402 formed thereon is improved, and when introducing a dopant into the oxide semiconductor layer 403 to form a low-resistance region, the dopant can also be introduced into the oxide semiconductor layer 403 under the source electrode layer 405a and the drain electrode layer 405b through the source electrode layer 405a and the drain electrode layer 405b.

[0131] In the oxide semiconductor layer 403, since the side surfaces (ends) of the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 are exposed, the source electrode layer 405a and the drain electrode layer 4 05b are formed so as to contact a part of the side surfaces of the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102.

[0132] Next, a gate insulating film 402 covering the oxide semiconductor layer 403, the source electrode layer 405a, and the drain electrode layer 405b is formed (see FIG. 2(C)).

[0133] In addition, in order to improve the coverage of the gate insulating film 402, the above planarization treatment may also be performed on the surfaces of the oxide semiconductor layer 403, the source electrode layer 405a, and the drain electrode layer 405b. Especially when using an insulating film with a thin film thickness as the gate insulating film 402, the oxide semiconductor layer 40 ​​​3. The flatness of the surface of the source electrode layer 405a and the drain electrode layer 405b is good. It is preferable.

[0134] The thickness of the gate insulating film 402 shall be between 1 nm and 20 nm, and the method of sputtering or MBE shall be used. Methods such as CVD, pulsed laser deposition, and ALD can be used as appropriate. The insulating film 402 has multiple substrate surfaces arranged approximately perpendicular to the sputtering target surface. The film may also be deposited using a sputtering apparatus that performs film deposition while the film is in its assembled state.

[0135] The gate insulating film 402 can be a silicon oxide film, a gallium oxide film, or an aluminum oxide film. Silicon nitride film, silicon oxide nitride film, aluminum oxide nitride film, or silicon oxide nitride film It can be formed using a film. The gate insulating film 402 is made of an oxide semiconductor stack 403 and It is preferable that the contact portion contains oxygen. In particular, the gate insulating film 402 contains (ba It is preferable that at least an amount of oxygen exceeding the stoichiometric composition ratio is present in the luk. For example, when a silicon oxide film is used as the gate insulating film 402, SiO 2+α ( However, α > 0). In this embodiment, the gate insulating film 402 is SiO 2+α A silicon oxide film is used (where α > 0). This silicon oxide film is used as the gate insulating film. By using it as 402, oxygen can be supplied to the oxide semiconductor stack 403, and the characteristics This can improve performance. Furthermore, the gate insulating film 402 provides a good performance for the fabricated transistor. It is preferable to form the gate insulating film 402 with consideration for step coverage.

[0136] Furthermore, the gate insulating film 402 is made of hafnium oxide, yttrium oxide, and hafnium. Silicate (HfSi x O y x>0, y>0)), nitrogen-added hafnium silicate (HfSiO x N y (x>0, y>0), hafnium aluminate (HfAl x O y (x>0, y>0), by using high-k materials such as lanthanum oxide, gately The current can be reduced. Furthermore, the gate insulating film 402 may be a single layer structure or a multilayer structure. It can also be used as a construction tool.

[0137] Then, the gate electrode layer 401 is subjected to plasma CVD or sputtering, etc. It is formed on the insulating film 402. The gate electrode layer 401 is made of molybdenum, titanium, tantalum, and Metal materials such as sten, aluminum, copper, chromium, neodymium, scandium or It can be formed using alloy materials that have these as their main components. Also, gate electrode layer 401 Semiconductor films, such as polycrystalline silicon films doped with impurity elements like phosphorus, A silicide film such as ckel silicide may be used. The gate electrode layer 401 has a single-layer structure. Alternatively, it may be a laminated structure.

[0138] Furthermore, the material of the gate electrode layer 401 is indium tin oxide, tungsten oxide, and other indium oxides. Indium zinc oxide containing zinc oxide, tungsten oxide, and titanium oxide Indium oxide, titanium oxide-containing indium tin oxide, indium zinc oxide, silicon oxide Conductive materials such as indium tin oxide with added ions can also be applied. A laminated structure of an electrolytic material and the above-mentioned metallic material can also be used.

[0139] Furthermore, a nitrogen-containing metal acid is used as one layer of the gate electrode layer 401 that is in contact with the gate insulating film 402. These are phosphates, specifically In-Ga-Zn-O films containing nitrogen, and In-Sn-O films containing nitrogen. or nitrogen-containing In-Ga-O film, nitrogen-containing In-Zn-O film, nitrogen-containing Sn- O films, nitrogen-containing In-O films, and metal nitride films (InN, SnN, etc.) can be used. These films have a work function of 5 electron volts, preferably 5.5 electron volts or more. When used as a gate electrode layer, it increases the threshold voltage of the transistor's electrical characteristics. This makes it possible to realize a so-called normally-off switching element.

[0140] The transistor 440a of this embodiment is fabricated through the above process (see Figure 2(D)). Multiple oxide semiconductor layers having different energy gaps (first oxide semiconductor layer 101 By using an oxide semiconductor stack 403 with a second oxide semiconductor layer 102), This allows for more precise control of the electrical characteristics of transistors 440a and 440b. This makes it possible to impart the desired electrical characteristics to transistors 440a and 440b.

[0141] Next, oxide semiconductor multilayer 403, source electrode layer 405a, drain electrode layer 405b, An insulating film 402 and an insulating film 407 are formed on the gate electrode layer 401 (see Figure 2(E)). .

[0142] The insulating film 407 is deposited by plasma CVD, sputtering, or vapor deposition. This is possible. The insulating film 407 is typically a silicon oxide film, a silicon oxide nitride film, or a silicon oxide film. An aluminum oxide film or an inorganic insulating film such as a gallium oxide film can be used.

[0143] Furthermore, the insulating film 407 can be an aluminum oxide film, a hafnium oxide film, or magnesium oxide. Films, zirconium oxide films, lanthanum oxide films, barium oxide films, or metal nitride films (for example) Aluminum nitride film can also be used.

[0144] The insulating film 407 may be a single layer or a multilayer, for example, a silicon oxide film and an aluminum oxide film. Lamination can be used.

[0145] The insulating film 407 is made by methods such as sputtering, which introduces impurities such as water and hydrogen into the insulating film 407. It is preferable to form it using an appropriate method. Also, in the insulating film 407, the oxide semi If the insulating film in contact with the conductive laminate 403 is a film containing an excess of oxygen, then the oxide semiconductor laminate 40 It is preferable as it serves as a source of oxygen for 3.

[0146] In this embodiment, a silicon oxide film with a thickness of 100 nm is used as the insulating film 407, and sputtering The film is deposited using the sputtering method. The deposition of silicon oxide films by sputtering is performed using a rare gas (substitute). In general, under an argon atmosphere, an oxygen atmosphere, or a mixed atmosphere of a noble gas and oxygen... It can be done by doing so.

[0147] Similar to the deposition of oxide semiconductor films, in order to remove residual moisture in the deposition chamber of the insulating film 407 It is preferable to use an adsorption-type vacuum pump (such as a cryopump). The concentration of impurities in the insulating film 407 deposited in a deposition chamber that has been evacuated using a pump can be reduced. Furthermore, as an exhaust means for removing residual moisture in the deposition chamber of the insulating film 407, a turbo A molecular pump with a cold trap added may also be used.

[0148] The sputtering gas used when depositing the insulating film 407 is hydrogen, water, hydroxyl group, or hydrogen It is preferable to use a high-purity gas from which impurities such as monoxides have been removed.

[0149] Furthermore, as shown in Figure 3(B), an insulating film is provided on the transistor 440d as an interlayer insulating film. As a film, an insulating film 416 is formed between the transistor 440d and the insulating film 407, providing interlayer insulation. The films may be arranged in a layered structure. The insulating film 416 is made using the same materials and methods as the insulating film 407. It can be formed. For example, an aluminum oxide film is used as the insulating film 416, By using a silicon oxide film as 407, the insulating film provided on transistor 440d and Therefore, a lamination of an aluminum oxide film and a silicon oxide film can be used. The etcher 440d etches the gate insulating film 402 using the gate electrode layer 401 as a mask. The oxide semiconductor laminate 403 is subjected to a processing method to expose a portion of it, and a portion of the oxide semiconductor laminate 403 This is an example of providing the insulating film 416 in contact with the insulating film.

[0150] The insulating film 407 and insulating film 416 provided on the oxide semiconductor stack 403 are used. The resulting aluminum oxide film allows both hydrogen, water and other impurities, as well as oxygen, to pass through the film. It has a high blocking effect that prevents leakage.

[0151] Therefore, the aluminum oxide film is subject to fluctuations in hydrogen during and after the manufacturing process. The incorporation of impurities such as moisture into the oxide semiconductor stack 403, and the main components constituting the oxide semiconductor It functions as a protective film that prevents the release of oxygen, a component material, from the oxide semiconductor stack 403. .

[0152] Furthermore, a planarizing insulating film may be formed to reduce surface irregularities caused by transistors. Organic materials such as polyimide, acrylic, and benzocyclobutene resins can be used as tanning insulators. In addition to the above organic materials, low dielectric constant materials (low-k materials), etc. can be used. It can be used. Furthermore, by stacking multiple insulating films formed from these materials, A planar insulating film may be formed.

[0153] Furthermore, the insulating film 407 is formed to have openings that reach the source electrode layer 405a and the drain electrode layer 405b. The opening is formed, and the source electrode layer 405a and drain electrode layer 405b are electrically connected to the wiring layer. A wiring layer may be used to connect to other transistors and configure various circuits. It is possible.

[0154] The source electrode layer 405a and the drain electrode layer 405b are the source electrode layer 405a and the drain electrode During the etching process to form the openings reaching layer 405b, some over-etching occurs. This can happen. The source electrode layer and drain electrode layer are made into a laminated structure, and when the opening is formed... A conductive film that also functions as a ching stopper is provided as the source electrode layer and the drain electrode layer. It is possible.

[0155] As shown in Figure 3(A), transistor 440c has a source electrode layer and a drain electrode layer. This is an example of a layered structure, where the source electrode layers are source electrode layer 404a and source electrode layer 40 5a. Drain electrode layer 404b and drain electrode layer 405b are laminated as drain electrode layers. It is done. For example, transistor 440c has a gate insulating film 402, insulating film 407, and Source electrode layer 405a, drain electrode layer 405b, source electrode layer 404a, drain electrode An opening is formed that reaches layer 404b, and the source electrode layer 404a and drain electrode layer 404 are placed in the opening. Wiring layers 465a and 465b that are electrically connected to b may be formed.

[0156] In transistor 440c, the source electrode layer 404a and the drain electrode layer 404b are open. It also functions as an etching stopper during formation. Source electrode layer 404a, Dray The source electrode layer 405a can be a tungsten film or a tantalum nitride film, for example. For the drain electrode layer 405b, a copper film or an aluminum film can be used, respectively. It can be done. Source electrode layer 404a and source electrode layer 405a, drain electrode layer 404b and If the film thickness of the rain electrode layer 405b in the lamination is set to approximately 5 nm to 15 nm, The coating properties of the insulating film 402 can be improved.

[0157] Wiring layer 465a and wiring layer 465b are gate electrode layer 401, source electrode layer 405a, and drain It can be formed using the same materials and methods as the electrode layer 405b. For example, wiring layer 465a, wiring layer 465b is a laminate of tantalum nitride film and copper film, or tantalum nitride film and Lamination with a tungsten film can be used.

[0158] Furthermore, a sidewall insulating layer may be provided on the side surface of the gate electrode layer 401. The sidewall insulating layer is provided on the gate electrode After forming an insulating film covering the polar layer 401, this is subjected to RIE (Reactive Ion Etching). An insulating film is added by anisotropic etching using the ching (reactive ion etching) method. Therefore, a self-aligned sidewall insulating layer can be formed on the sidewall of the gate electrode layer 401. Here, There are no particular limitations on the insulating film, but for example, TEOS (Tetraethyl-Orthopropyl Reacting o-silicate or silane with oxygen or nitrous oxide, etc. A silicon oxide with good step coverage can be used. The insulating film can be made by thermal CVD, plastic Formed by methods such as Zuma CVD, atmospheric pressure CVD, biased ECRCVD, and sputtering. It is possible to perform low-temperature oxidation (LTO). Silicon oxide formed by the (dation) method may also be used.

[0159] The highly purified oxide semiconductor stack 403, with oxygen deficiencies filled, contains impurities such as hydrogen and water. The hydrogen has been sufficiently removed, and the hydrogen concentration in the oxide semiconductor stack 403 is 5 × 10 19 Atom s / cm 3 The following is preferably 5 × 10 18 atoms / cm 3 The following applies. Note that it is an oxide. The hydrogen concentration in semiconductor stack 403 was determined by secondary ion mass spectrometry (SIMS). This is measured using ion mass spectrometry.

[0160] Using this embodiment, an oxidation product was prepared that is highly purified and contains an excess of oxygen to compensate for oxygen deficiencies. The transistor 440a, which uses a multilayer semiconductor 403, has a current value in the off state (off current The current value is 100 zA / μm (1 zA (zeptoampere) per 1 μm channel width at room temperature. ) is 1 × 10 -21 A) Less than or equal to 10 zA / μm, preferably 1 zA / μm or less, more preferably 1 zA / The level can be reduced to μm or less, and more preferably to 100 yA / μm or less.

[0161] As described above, semiconductor devices are available to meet various purposes, such as high functionality, high reliability, or low power consumption. We can provide this.

[0162] (Embodiment 2) In this embodiment, another form of semiconductor device and method for manufacturing a semiconductor device is shown using Figure 5. Let me explain. The same parts as or having similar functions as those in the above embodiment, and the process, are as described above. This can be done in the same way as the method of application, so repeated explanations will be omitted. Also, detailed explanation of the same section The "Akira" part will be omitted.

[0163] In this embodiment, in the method for manufacturing a semiconductor device according to the disclosed invention, dehydration or dehydration In an oxide semiconductor stack that has undergone chemical treatment, oxygen (at least oxygen radicals, oxygen atoms, acid) This example shows how to supply oxygen into a membrane by introducing (containing any of the elementary ions).

[0164] Dehydration or dehydrogenation treatment simultaneously removes oxygen, which is a major component material of oxide semiconductors. There is a risk that oxygen will be desorbed and decrease in the oxide semiconductor stack. In this location, an oxygen deficiency exists, and this oxygen deficiency causes fluctuations in the electrical characteristics of the transistor. - A level is created.

[0165] Therefore, it is preferable to supply oxygen to oxide semiconductor stacks that have undergone dehydration or dehydrogenation treatment. It is possible to supply oxygen to oxide semiconductor stacks to compensate for oxygen deficiencies in the film. This can be achieved. By using this oxide semiconductor stack in a transistor, transistors caused by oxygen deficiency can be prevented. This reduces the variation in the threshold voltage Vth of the inverter and the threshold voltage shift ΔVth. This can be done. Additionally, the threshold voltage can be shifted positively to normally-off the transistor. It is also possible.

[0166] Figure 5(A) corresponds to Figure 2(C), and shows a substrate 400 on which an oxide insulating film 436 is provided. On top of that are a first oxide semiconductor layer 101 and a second oxide semiconductor with different energy gaps. Oxide semiconductor stack 403 including layer 102, source electrode layer 405a, drain electrode layer 405 b. A gate insulating film 402 is formed.

[0167] Next, oxygen 431 (at least oxygen radical, oxygen atom, acid) is added to the oxide semiconductor stack 403. By introducing (containing any of the elementary ions), the first oxide semiconductor layer 101 and the second oxide Oxygen-rich regions 111 and 112 are formed in the oxide semiconductor stack 403 containing the monocrystalline semiconductor layer 102. (See Figure 5(B)).

[0168] Furthermore, the oxygen-rich regions 111 and 112 represent the stoichiometric composition of the oxide semiconductor in its crystalline state. This refers to a region where, relative to the ratio, at least a portion of the region contains an excess of oxygen. The oxygen 431 supplied to the excess regions 111 and 112 causes the first oxide semiconductor layer 101 and oxygen vacancies present in the oxide semiconductor stack 403 including the second oxide semiconductor layer 102 It can be compensated for.

[0169] On an oxide semiconductor stack 403 having oxygen-rich regions 111 and 112, on a gate insulating film 402 A gate electrode layer 401 is formed to fabricate a transistor 430 (see Figure 5(C)).

[0170] Oxygen is introduced into the oxide semiconductor stack 403 that has undergone dehydration or dehydrogenation treatment, so that oxygen is present in the film. By supplying this, the oxide semiconductor multilayer 403 can be made highly pure and type I (intrinsic). This is possible. A transient having a highly purified, type I (intrinsic) oxide semiconductor stack 403 The Sta430 exhibits suppressed electrical characteristic fluctuations and is electrically stable.

[0171] Methods for introducing oxygen include ion implantation, ion doping, and plasma immersion. On-plantation methods, plasma treatment, and other similar techniques can be used.

[0172] The oxygen introduction process is performed when introducing oxygen into the oxide semiconductor stack 403, It can be introduced directly into 3, or through other films such as the gate insulating film 402 or insulating film 407. It may also be introduced into the oxide semiconductor stack 403. If oxygen is introduced by passing it through another film, On-injection method, ion doping method, plasma immersion ion implantation method While methods such as the above can be used, if oxygen is to be directly introduced into the exposed oxide semiconductor stack 403, Plasma treatment and other methods can also be used.

[0173] The introduction of oxygen into the oxide semiconductor stack 403 is possible after dehydration or dehydrogenation treatment. Often, it is not particularly limited. Furthermore, oxide semiconductor stacks subjected to the above-mentioned dehydration or dehydrogenation treatment. Oxygen can be introduced into unit 403 multiple times.

[0174] For example, in Embodiment 1, the introduction of oxygen into the oxide semiconductor stack 403 is an exposed acid A source electrode layer 405 is provided for the oxide semiconductor film stack 493 or oxide semiconductor stack 403. a. After the drain electrode layer 405b is formed, the gate insulating film 402 is formed, and then the gate electrode layer 401 is formed. This can be done after the formation of the insulating film 416, or after the formation of the insulating film 407.

[0175] Furthermore, in the oxygen-rich regions 111 and 112 within the oxide semiconductor stack 403, an oxygen introduction process is performed. The oxygen concentration introduced by the process is 1 × 10 18 atoms / cm 3 The above 5 x 10 21 at oms / cm 3 The following is preferable:

[0176] Furthermore, in oxide semiconductors, oxygen is one of the main component materials. The oxygen concentration in the conductive laminate 403 is measured using SIMS (Secondary Ion Mass Saturation). It is difficult to estimate accurately using methods such as pectrometry. In other words, It is difficult to determine whether or not oxygen was intentionally added to the oxide semiconductor stack 403. It can be said that...

[0177] By the way, oxygen contains 17 O or 18 Isotopes such as 0 exist, and their existence in nature It is known that their respective proportions are approximately 0.037% and 0.204% of the total oxygen atoms. In other words, if these isotopes are intentionally added to the oxide semiconductor stack 403, The concentrations of these isotopes can be estimated by methods such as SIMS, and these concentrations By taking measurements, it is possible to estimate the oxygen concentration in the oxide semiconductor stack 403 more accurately. This may be the case. Therefore, by measuring these concentrations, the oxide semiconductor stack 403 can be intended. It is also possible to determine whether or not oxygen has been added to the target.

[0178] Furthermore, it is preferable to introduce oxygen into the oxide semiconductor film and then perform a heat treatment.

[0179] As in the transistor 430 of this embodiment, oxygen is directly introduced into the oxide semiconductor stack 403. In this case, the oxide insulating film 436 and gate insulating film 402 are in contact with the oxide semiconductor stack 403. It is not necessarily required that the film contain a large amount of oxygen. The introduced oxygen is re-conducted into the oxide semiconductor product. To prevent desorption from layer 403, and to prevent hydrogen-containing impurities such as hydrogen and water from affecting the oxide semiconductor, To prevent re-incorporation into the 403 layer, shielding is provided against hydrogen-containing impurities such as oxygen, hydrogen, and water. It is preferable to provide a film with a high blocking effect as the insulating film 407. For example, Highly effective at blocking oxidation against both hydrogen, water and other impurities, as well as oxygen. Using an aluminum film or similar material would be beneficial.

[0180] Of course, the oxide insulating film 436 and gate insulating film 402 that are in contact with the oxide semiconductor film are oxygen-free. The film contains a large amount of oxygen, and oxygen is directly introduced into the oxide semiconductor stack 403, and multiple oxygen supply methods are used. You may use the law.

[0181] Furthermore, in this embodiment, the introduction of oxygen into the oxide semiconductor stack 403 is described as an example, but acid The element is introduced by the gate insulating film 402 and oxide insulating film 436 that are in contact with the oxide semiconductor stack 403. This may also be done in insulating film 416 or insulating film 407. Oxygen is introduced into the oxide insulating film 402, oxide insulating film 436, insulating film 416, and insulating film 407. By creating an oxygen surplus, oxygen can be supplied to the oxide semiconductor stack 403. Cut.

[0182] As described above, we provide a semiconductor device using an oxide semiconductor multilayer with stable electrical characteristics. This allows us to provide highly reliable semiconductor devices.

[0183] This embodiment can be implemented in appropriate combination with other embodiments.

[0184] (Embodiment 3) In this embodiment, another form of semiconductor device and method for manufacturing a semiconductor device is shown using Figure 6. Let me explain. The same parts as or having similar functions as those in the above embodiment, and the process, are as described above. This can be done in the same way as the method of application, so repeated explanations will be omitted. Also, detailed explanation of the same section The "Akira" part will be omitted.

[0185] In this embodiment, in the method for manufacturing a semiconductor device according to the disclosed invention, oxide semiconductor product This is an example of forming a low-resistance region in a layer. The low-resistance region changes the conductivity of the oxide semiconductor stack. It can be formed by introducing impurities (also called dopants).

[0186] Figure 6(A) corresponds to Figure 2(D), and shows a substrate 400 on which an oxide insulating film 436 is provided. On top of that are a first oxide semiconductor layer 101 and a second oxide semiconductor with different energy gaps. Oxide semiconductor stack 403 including layer 102, source electrode layer 405a, drain electrode layer 405 b, a gate insulating film 402 and a gate electrode layer 401 are formed.

[0187] Next, using the gate electrode layer 401 as a mask, the gate insulating film 4 is applied to the oxide semiconductor stack 403. 02, the dopant 421 passes through the source electrode layer 405a and the drain electrode layer 405b. By selectively introducing these elements, low-resistance regions 121a, 121b, 122a, and 122b are formed.

[0188] In this embodiment, the source electrode layer 405a and the drain electrode layer 405b are made into thin films. Therefore, in the oxide semiconductor stack 403 beneath the source electrode layer 405a and the drain electrode layer 405b Dopant 421 is also introduced, and the low-resistance regions 121a, 121b, 122a, and 122b are An example of what is formed is shown.

[0189] The film thickness of the source electrode layer 405a and the drain electrode layer 405b, and the introduction of the dopant 421. Depending on the conditions, the oxide semiconductor beneath the source electrode layer 405a and the drain electrode layer 405b may If dopant 421 is not introduced into stacked 403, even if it is introduced, the concentration will be low and the source power Regions with higher resistance compared to low-resistance regions other than those below the polar layer 405a or the drain electrode layer 405b. In some cases, this may occur. Also, depending on the conditions for introducing dopant 421, the first oxide semiconductor Dopant 421 is introduced only in layer 101 and only in the second oxide semiconductor layer 102, resulting in low resistance. When a region is formed, the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 In some cases, a dopant concentration distribution exists.

[0190] Dopant 421 is an impurity that alters the conductivity of the oxide semiconductor stack 403. Pant 421 includes Group 15 elements (typically phosphorus (P), arsenic (As), and ammonium compounds). Timon (Sb), Boron (B), Aluminum (Al), Nitrogen (N), Argon (Ar) ), helium (He), neon (Ne), indium (In), fluorine (F), chlorine (C) l) Use one or more selected from titanium (Ti) and zinc (Zn). It is possible.

[0191] Dopant 421 is injected by the injection method into insulating film 407, source electrode layer 405a, and drain It passes through the electrode layer 405b and is introduced into the oxide semiconductor stack 403. Dopant 421 Methods of introduction include ion implantation, ion doping, and plasma immersion ion implantation. Plantation methods can be used. In that case, dopant 421 alone It is preferable to use ions of fluoride or chloride.

[0192] The introduction process for dopant 421 involves injection conditions such as acceleration voltage and dose, as well as the process of passing through the saturation zone. The thickness of the edge film 407 can be appropriately set and controlled. In this embodiment, dopant 421 Boron is used as the dopant, and boron ions are implanted using the ion implantation method. The dose of 21 is 1 × 10⁻⁶. 13 ions / cm 2 The above 5 x 10 16 ions / cm 2 below That's all you need to do.

[0193] The concentration of dopant 421 in the low-resistance region is 5 × 10⁻⁶. 18 / cm 3 The above 1 x 10 22 / cm 3 The following is preferable:

[0194] When introducing dopant 421, the substrate 400 may be heated during the process.

[0195] Furthermore, the process of introducing the dopant 421 into the oxide semiconductor stack 403 may be performed multiple times. Furthermore, multiple types of Dopants may be used.

[0196] Furthermore, after the introduction of dopant 421, heat treatment may be performed. The heating conditions are as follows: 300°C to 700°C, preferably 300°C to 450°C for 1 hour in an oxygen atmosphere It is preferable to carry out the process under gaseous conditions. Alternatively, heating can be performed under a nitrogen atmosphere, under reduced pressure, or under atmospheric (ultra-dry) air. You may proceed with the processing.

[0197] When the oxide semiconductor stack 403 is a crystalline oxide semiconductor film, the introduction of the dopant 421 In some cases, partial amorphization may occur. In this case, heat treatment is performed after the introduction of dopant 421. By doing so, the crystallinity of the oxide semiconductor stack 403 can be restored.

[0198] Therefore, in the oxide semiconductor stack 403, a low-resistance region is formed between the channel formation region 121c. A first oxide semiconductor layer 101 having 121a and 121b, and a channel formation region 12 A second oxide semiconductor layer 102 has low-resistance regions 122a and 122b separated by 2c. A formation is created.

[0199] The transistor 420 of this embodiment is manufactured through the above process (see Figure 6(B)).

[0200] Furthermore, as with the transistor 440d shown in Embodiment 1, the gate insulating film 402 is The electrode layer 401 is used as a mask for etching, and the oxide semiconductor stack 403 is partially exposed. In the transistor that is brought into contact with the insulating film 416, a dopant is introduced to create a low-resistance region. The transistor 425 formed is shown in Figure 3(C).

[0201] Transistor 425 introduces a dopant using the gate electrode layer 401 as a mask, and channel With the resistance-forming regions 121c and 122c in between, the low-resistance regions 121a, 121b, 122a, It is fabricated by forming 22b. Also, the source electrode layer that passes through when introducing the dopant, In some cases, dopants are also introduced into the drain electrode layer. Transistor 425 is dopant The dopant is also introduced into the source electrode layer and the drain electrode layer, and the source electrode layer 4 containing the dopant 15a is an example of a drain electrode layer 415b containing a dopant.

[0202] Low-resistance regions 121a and 121b are provided in the channel length direction, flanking the channel-forming region 121c. The first oxide semiconductor layer 101 is separated from the channel formation region 122c, and a low-resistance region is separated from it. Oxide semiconductor stack including a second oxide semiconductor layer 102 having 122a and 122b By having 403, transistors 420 and 425 have on-characteristics (e.g.) For example, high on-current and field-effect mobility enable high-speed operation and fast response.

[0203] Furthermore, a dopant is introduced into the transistor 430 having an oxygen-rich region as shown in Embodiment 2. The transistor 423, which has been modified to form a low-resistance region, is shown in Figure 6(C).

[0204] Transistor 423, as shown in transistor 430 in Figure 5(C), enters the oxygen-rich region 111 A first oxide semiconductor layer 101 including a region, and a second oxide semiconductor including an oxygen-rich region 112 In a transistor provided with an oxide semiconductor stack having layer 102, gate electrode layer 4 A dopant is introduced using 01 as a mask, and the channel-forming region 121c, which contains an excess of oxygen, With 122c in between, there are low-resistance regions 121d, 121e, and 1 containing dopant and excess oxygen. 22d, 122e, and low-resistance regions including the dopant 121a, 121b, 122a, 12 It is manufactured by forming 2b.

[0205] Low-resistance regions 121d, 121e, and 1 are separated by the channel-forming region 121c in the channel length direction. A first oxide semiconductor layer 101 having 21a and 121b, and a channel formation region 122 A second oxidation is provided with low-resistance regions 122d, 122e, 122a, and 122b on either side of c. The transistor has an oxide semiconductor stack 403 including a monocrystalline semiconductor layer 102. The 423 has high on-characteristics (e.g., on-current and field-effect mobility), enabling fast operation and fast response. This becomes possible.

[0206] Furthermore, as shown in the first embodiment, the oxide semiconductor stack 403 is In a three-layer transistor, oxygen and a dopant are introduced to create an oxygen-rich region and a low-resistance region. The transistor 480b with the anti-region formed is shown in Figure 4(B).

[0207] Transistor 480b consists of a first oxide semiconductor layer 101, a second oxide semiconductor layer 102, And oxygen is introduced into the oxide semiconductor stack 403 including the third oxide semiconductor layer 103 to oxygenate After forming the excess region and the gate electrode layer 401 is formed, the gate electrode layer 401 is used as a mask for doping An element is introduced, and channel-forming regions 121c, 122c, and 123c containing an excess of oxygen are sandwiched between them. Therefore, the low resistance regions 121d, 121e, 122d, 122 contain dopants and excess oxygen. e, 123d, 123e, and low-resistance regions 121a, 121b, 122a containing the dopant. It is manufactured by forming 122b, 123a, and 123b.

[0208] Low-resistance regions 121d, 121e, and 1 are separated by the channel-forming region 121c in the channel length direction. A first oxide semiconductor layer 101 having 21a and 121b, and a channel formation region 122 A second oxidation is provided with low-resistance regions 122d, 122e, 122a, and 122b on either side of c. The monocrystalline semiconductor layer 102 and the low-resistance regions 123d and 123e are separated by the channel formation region 123c. an oxide semiconductor multilayer including a third oxide semiconductor layer 103 having 123a and 123b provided By having layer 403, the transistor 480b has on-characteristics (e.g., on-current and High field effect mobility enables high-speed operation and fast response.

[0209] Transistor 420, Transistor 423, Transistor 425, Transistor 480b In this region, the low-resistance regions 121a, 121b, 122a, and 122b are the source region, or DRE It can function as an input region. Low resistance regions 121a, 121b, 122a, 1 By providing 22b, the low resistance regions 121a, 121b, 122a, and 122b This allows the electric field applied to the channel formation regions 121c and 122c to be relaxed. Furthermore, in the low-resistance regions 121a, 121b, 122a, and 122b, the oxide semiconductor product... The layer 403 is electrically connected to the source electrode layer 405a and the drain electrode layer 405b. As a result, oxide semiconductor stack 403, source electrode layer 405a and drain electrode layer 405 The contact resistance with b can be reduced. Therefore, transistor 420, transistor 4 23 electrical characteristics can be improved.

[0210] This embodiment can be implemented in appropriate combination with other embodiments.

[0211] (Embodiment 4) A semiconductor having a display function using a transistor as an example shown in any of Embodiments 1 to 3. Conductor devices (also called display devices) can be manufactured. Furthermore, drivers including transistors can be used. A system-on-panel is formed by integrally forming part or all of the circuit on the same substrate as the pixel section. It is possible.

[0212] In Figure 7(A), the pixel portion 4002 provided on the first substrate 4001 is surrounded by A sealing material 4005 is provided and sealed by the second substrate 4006. Figure 7( In A), the region surrounded by the sealing material 4005 on the first substrate 4001 and These are formed in different regions on a separately prepared substrate using a single-crystal semiconductor film or a polycrystalline semiconductor film. A scan line drive circuit 4004 and a signal line drive circuit 4003 are implemented. The signal line drive circuit 4003 and the scan line drive circuit 4004 or the pixel unit 4002 are supplied The various signals and potentials are transmitted via FPC (Flexible Printed Circuit). ) Supplied from 4018a and 4018b.

[0213] In Figures 7(B) and 7(C), the pixel section 4002 provided on the first substrate 4001 and scanning A sealing material 4005 is provided so as to surround the line drive circuit 4004. A second substrate 4006 is provided on part 4002 and the scan line drive circuit 4004. The pixel section 4002 and the scan line driving circuit 4004 are connected to the first substrate 4001 and the sealing material 4 The display element is sealed together with 005 and the second substrate 4006. Figure 7(B) In C), the region surrounded by the sealing material 4005 on the first substrate 4001 and These are formed in different regions on a separately prepared substrate using a single-crystal semiconductor film or a polycrystalline semiconductor film. A signal line drive circuit 4003 is implemented. In Figures 7(B) and 7(C), separately formed... The signal line drive circuit 4003 and the scan line drive circuit 4004 or the pixel unit 4002 are supplied The various signals and potentials are supplied from the FPC4018.

[0214] Furthermore, in Figures 7(B) and 7(C), a signal line drive circuit 4003 is formed separately, and the first substrate 4 An example of implementation in 001 is shown, but the configuration is not limited to this. The scan line drive circuit is separate. It may be formed and implemented, or only a part of the signal line drive circuit or a part of the scan line drive circuit may be used. It may be formed and implemented separately.

[0215] Furthermore, the method of connecting the separately formed drive circuit is not particularly limited, and COG(Ch ip On Glass) method, wire bonding method, or TAB (Tape A Methods such as utmost bonding can be used. Figure 7(A) shows C This is an example of implementing the signal line drive circuit 4003 and the scan line drive circuit 4004 using the OG method. Figure 7(B) shows an example of implementing the signal line drive circuit 4003 using the COG method, and Figure 7(C) shows an example of implementing the signal line drive circuit 4003 using the COG method. This is an example of implementing the signal line drive circuit 4003 using the TAB method.

[0216] Furthermore, the display device includes a panel in which the display elements are sealed, and a controller on the panel. Includes modules with ICs and other components mounted on them.

[0217] In this specification, the term "display device" refers to an image display device, a display device, or an optical display device. This refers to the power source (including lighting equipment). It also refers to connectors, such as FPC or TAB tape. A module with TCP attached, a TAB tape, or a printed circuit board at the end of the TCP. An IC (integrated circuit) is directly mounted to the provided module or display element using the COG method. All modules that have been modified shall also be included in the display device.

[0218] Furthermore, the pixel section and scanning line driving circuit provided on the first substrate have multiple transistors. Therefore, the transistor shown as an example in any of Embodiments 1 to 3 can be applied. ru.

[0219] Display elements provided in a display device include liquid crystal elements (also called liquid crystal display elements) and light-emitting elements ( A light-emitting element (also called a light-emitting display element) can be used. The light-emitting element is activated by current or voltage. This category includes elements whose brightness is controlled, specifically inorganic EL (Electroluminescent) elements. This includes Luminescence, organic EL, etc. It also includes electronic inks and other electrically powered materials. Display media where the contrast changes depending on the application can also be used.

[0220] One form of semiconductor device will be explained using Figures 7 and 8. Figure 8 is M of Figure 7(B). - This corresponds to a cross-sectional view in N.

[0221] As shown in Figures 7 and 8, the semiconductor device has connection terminal electrodes 4015 and terminal electrodes 4016. It has, and the connecting terminal electrode 4015 and terminal electrode 4016 are terminals of FPC4018 It is electrically connected via an anisotropic conductive film 4019.

[0222] The connecting terminal electrode 4015 is formed from the same conductive film as the first electrode layer 4030, and the terminal electrode 4 016 is the same conductive material as the source electrode layer and drain electrode layer of transistors 4010 and 4011. It is formed of an electrochemical film.

[0223] Furthermore, the pixel section 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001 are, It has multiple transistors, and in Figures 7 and 8, the transistors included in the pixel section 4002 The transistor 4010 and the transistor 4011 included in the scan line drive circuit 4004 are shown as examples. In Figure 8(A), an insulating film 4020 is provided on transistors 4010 and 4011. Furthermore, in Figure 8(B), an insulating film 4021 is provided. Note that insulating film 4023 is It is an insulating film that functions as a base layer.

[0224] As transistors 4010 and 4011, any of embodiments 1 to 3. The transistor shown can be applied. In this embodiment, the transistor shown in Embodiment 1 An example of applying a transistor having a similar structure to transistor 440a is shown.

[0225] Transistors 4010 and 4011 have an energy gap as a semiconductor layer. A transistor having an oxide semiconductor stack comprising at least two different oxide semiconductor layers. This is an oxide semiconductor using multiple oxide semiconductor layers with different energy gaps. By using multilayer architecture, the electrical characteristics of transistors can be controlled with greater precision. This makes it possible to impart the desired electrical characteristics to transistors 4010 and 4011. It becomes Noh.

[0226] Therefore, the semiconductor device of this embodiment shown in Figures 7 and 8 is highly functional, highly reliable, or We can provide semiconductor devices that meet various purposes, such as low power consumption.

[0227] The transistor 4010 provided in the pixel section 4002 is electrically connected to the display element, and the display The panel is constructed using various display elements, as long as they can perform a display. You can use it.

[0228] Figure 8(A) shows an example of a liquid crystal display device using liquid crystal elements as display elements. The liquid crystal element 4013, which is a display element, has a first electrode layer 4030 and a second electrode layer 403 1, and a liquid crystal layer 4008 are included. An insulating film 4032, 4033 capable of performing the function is provided. The second electrode layer 4031 is on the second substrate Located on the 4006 side, the first electrode layer 4030 and the second electrode layer 4031 are connected to the liquid crystal layer 400. The configuration involves stacking components via 8.

[0229] Furthermore, 4035 is a columnar spacer obtained by selectively etching an insulating film. It is provided to control the film thickness (cell gap) of the liquid crystal layer 4008. You may use a pacer.

[0230] When using liquid crystal elements as display elements, thermotropic liquid crystals, low molecular weight liquid crystals, and polymer liquid crystals are used. Crystals, polymer-dispersed liquid crystals, ferroelectric liquid crystals, antiferroelectric liquid crystals, etc. can be used. The liquid crystal material (liquid crystal composition) can be divided into a cholesteric phase, a smectic phase, and a cue phase, depending on the conditions. It exhibits the Big phase, chiral nematic phase, isotropic phase, etc.

[0231] Furthermore, a liquid crystal composition that exhibits a blue phase without using an alignment film may be used for the liquid crystal layer 4008. The blue phase is one of the liquid crystal phases, and as the temperature of cholesteric liquid crystal is increased, the cholesteric phase This phase appears immediately before the transition from the blue phase to the isotropic phase. The blue phase consists of liquid crystals and chiral agents. It can be expressed using a liquid crystal composition that is a mixture of these. Also, the temperature at which the blue phase appears To broaden the range of degrees, polymerizable monomers and polymerization initiators are added to the liquid crystal composition that exhibits the blue phase. By adding substances such as blue and performing a polymer stabilization process, a liquid crystal layer can also be formed. The liquid crystal composition that exhibits this phase has a short response speed and is optically isotropic, so no orientation treatment is required. Yes, it has low viewing angle dependence. Also, since an alignment layer is not required, rubbing treatment is unnecessary. Therefore, electrostatic discharge damage caused by rubbing can be prevented, and the manufacturing process This can reduce defects and damage to liquid crystal displays during use. Therefore, the productivity of liquid crystal displays is reduced. This makes it possible to improve the performance. Transistors using oxide semiconductor films are affected by static electricity. This could cause the electrical characteristics of the transistor to fluctuate significantly, potentially exceeding the design range. This refers to a liquid crystal display device having a transistor that uses an oxide semiconductor film, which exhibits a blue phase. Using a crystalline composition is more effective.

[0232] Furthermore, the resistivity of the liquid crystal material is 1 × 10⁻⁶ 9 The value is Ω·cm or greater, preferably 1 × 10⁻⁶. 11 It is Ω·cm or greater, and more preferably 1 × 10⁻⁶ 12 It is greater than Ω·cm. Furthermore, this specification... The resistivity values ​​in this document shall be those measured at 20°C.

[0233] The size of the retention capacitance provided in a liquid crystal display device depends on the regeneration of the transistors arranged in the pixel area. The system is set to hold the charge for a predetermined period of time, taking into account the current and other factors. The size should be set considering the transistor's off-current, etc. The oxidation disclosed herein By using a transistor having a physical semiconductor film, the liquid crystal capacitance in each pixel is It is sufficient to provide a holding capacity having a size of 1 / 3 or less, preferably 1 / 5 or less of the capacity. ru.

[0234] The transistor using the oxide semiconductor film disclosed herein has an off-state current value ( The off-current value can be controlled to be low. Therefore, the holding time of electrical signals such as image signals can be controlled. It can be extended, and the writing interval can also be set to be longer when the power is on. Therefore, This reduces the frequency of the flashing operation, thus having the effect of suppressing power consumption.

[0235] Furthermore, transistors using oxide semiconductor films disclosed herein have high field-effect mobility. Because it can be controlled precisely, high-speed driving is possible. For example, high-speed driving like this is possible. By using a capable transistor in a liquid crystal display device, the switching transistor in the pixel section and This allows the driver transistors used in the drive circuit section to be formed on the same substrate. In other words, a semiconductor device formed from a silicon wafer or the like is used as a separate drive circuit. Since it is not necessary, the number of components in the semiconductor device can be reduced. Also, in the pixel area Furthermore, by using transistors capable of high-speed operation, it is possible to provide high-quality images. Therefore, high reliability can also be achieved as a semiconductor device.

[0236] LCD displays include TN (Twisted Nematic) mode and IPS (In-Place Printed Display). lane-Switching) mode, FFS (Fringe Field Switching) mode ching) mode, ASM(Axially Symmetric aligned) Micro-cell mode, OCB (Optical Compensated B) irefringence) mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq. You can use modes such as UID Crystal.

[0237] Furthermore, normally black type liquid crystal display devices, such as those employing vertical alignment (VA) mode, It may also be used as a transmissive liquid crystal display device. Several vertical orientation modes are possible, For example, MVA (Multi-Domain Vertical Alignment) Mode, PVA (Patterned Vertical Alignment) mode Features such as ASV (Advanced Super View) mode can be used. Furthermore, it can also be applied to VA-type liquid crystal display devices. VA-type liquid crystal display devices are... This is a type of method for controlling the arrangement of liquid crystal molecules in a liquid crystal display panel. VA-type liquid crystal display devices are... This method involves the liquid crystal molecules oriented perpendicular to the panel surface when no voltage is applied. Furthermore, a pixel is divided into several subpixel regions, each in a different direction. This is called multi-domainization or multi-domain design, which is a method of knocking down molecules. A method can be used.

[0238] Furthermore, in a display device, the black matrix (light-shielding layer), polarizing member, phase difference member, and reflector are used. Optical components (optical substrates) such as protective members are provided as appropriate. For example, polarizing substrates and phase difference substrates Circularly polarized light from a plate may be used. Also, backlights, sidelights, etc., may be used as light sources. It's okay to be there.

[0239] Furthermore, the display method used in the pixel area may be a progressive or interlaced method. It is possible. Also, when displaying in color, the color elements controlled by pixels are RGB (R is It is not limited to the three colors (red, green, and blue). For example, RGBW (where W represents white). Alternatively, some models use RGB with one or more additional colors such as yellow, cyan, or magenta. The size of the display area for each dot of the color element may differ. However, the disclosed invention This applies not only to color display devices, but also to monochrome display devices. It is also possible.

[0240] Furthermore, as a display element included in the display device, an electroluminescent light-emitting element is used. It can be applied to light-emitting devices that utilize electroluminescence, light-emitting material They are distinguished by whether they are organic or inorganic compounds, and generally the former are organic E The latter is called an L element, and the latter an inorganic EL element.

[0241] Organic EL elements emit electrons and holes from a pair of electrodes when a voltage is applied to the light-emitting element. Each of these is injected into a layer containing a luminescent organic compound, and an electric current flows through it. Then, these... The recombination of electrons and holes causes the luminescent organic compound to form an excited state. And when that excited state returns to the ground state, it emits light. From this mechanism, Such light-emitting devices are called current-excited light-emitting devices.

[0242] Inorganic electroluminescent (EL) elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements based on their element configuration. They are classified as such. Dispersive inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The luminescence mechanism utilizes donor and acceptor levels, and the donor-acceptor level is the key to this process. This is a receptor recombination type light emission. Thin-film inorganic EL elements sandwich the light-emitting layer between dielectric layers. Furthermore, it has a structure where it is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. This is a localized light emission. Here, we will explain using an organic EL element as the light-emitting element. ru.

[0243] A light-emitting element only needs to have at least one of its pair of electrodes that is translucent in order to extract light. Then, a transistor and a light-emitting element are formed on the substrate, and light is extracted from the side opposite to the substrate. This includes top-side emission, bottom-side emission which extracts light from the substrate side, and emission from both the substrate side and the opposite side of the substrate. There are light-emitting elements with a double-sided emission structure that extract light from both sides, and any light-emitting element with an emission structure is applicable. It is possible.

[0244] Figure 8(B) shows an example of a light-emitting device that uses a light-emitting element as a display element. Element 4513 is electrically connected to transistor 4010 provided in pixel section 4002. The configuration of the light-emitting element 4513 is as follows: first electrode layer 4030, electroluminescent layer 4511, The electrode layer 4031 has a stacked structure, but is not limited to the configuration shown. Light-emitting element 4513 The configuration of the light-emitting element 4513 can be appropriately changed to match the direction of the light extracted from it. ru.

[0245] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material, particularly a photosensitive resin. Using the material, an opening is formed on the first electrode layer 4030, and the side wall of the opening is a continuous curve It is preferable to form the surface in a way that creates an inclined surface with a certain ratio.

[0246] Even if the electroluminescent layer 4511 consists of a single layer, it is configured to be stacked with multiple layers. It doesn't matter whether it's done or not.

[0247] To prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting element 4513, the second electrode layer A protective film may be formed on 4031 and the partition wall 4510. The protective film may be silicon nitride. Films, silicon nitride films, DLC films, etc. can be formed. Also, the first substrate 400 1. The space sealed by the second substrate 4006 and the sealing material 4005 is filled with a filler material 45 14 is provided and sealed. In this way, it is highly airtight and does not expose to the outside air, and gas removal Protective films with minimal defects (laminated films, UV-curing resin films, etc.) and cover materials It is preferable to package (enclose) them in this way.

[0248] In addition to inert gases such as nitrogen and argon, filler material 4514 can also be UV-curing resin. Thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic, and poly Mid, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (E Tylene vinyl acetate can be used. For example, nitrogen can be used as a filler. stomach.

[0249] Furthermore, if necessary, a polarizing plate or circular polarizing plate (including elliptical polarizing plate) may be placed on the emission surface of the light-emitting element. You may also appropriately incorporate optical films such as phase difference plates (λ / 4 plate, λ / 2 plate) and color filters. Furthermore, an anti-reflective coating may be provided on the polarizing plate or circular polarizing plate. For example, by the surface irregularities An anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0250] Furthermore, it is also possible to provide electronic paper that drives electronic ink as a display device. Electronic paper is also called an electrophoretic display device, and it is similar to paper. It is possible to achieve the same readability, lower power consumption compared to other display devices, and a thin and light form factor. It has the advantage of being able to do so.

[0251] Electrophoresis display devices can take various forms, but one is a first particle with a positive charge and Multiple microcapsules containing a second particle having a negative charge are in the solvent or solute. It is a dispersed substance, and by applying an electric field to the microcapsules, the microcapsules Move the particles in the cell in opposite directions and display only the color of the particles that have gathered on one side. Furthermore, the first or second particle contains dye and moves in the absence of an electric field. It is immovable. Also, the color of the first particle and the color of the second particle are different (including colorless). )

[0252] Thus, electrophoretic devices can detect the movement of substances with high dielectric constants into high electric field regions. This display utilizes a mild dielectrophoretic effect.

[0253] When the above microcapsules are dispersed in a solvent, it is called an electronic ink. This electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Color display is also possible by using color filters or particles containing pigments.

[0254] Furthermore, the first and second particles in the microcapsules are made of conductive material, insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, electro A type of material selected from trochromic materials, magnetophoretic materials, or a composite material thereof Use it.

[0255] Furthermore, a display device using the twist ball display method can also be applied as electronic paper. Yes, it is possible. The twist ball display method uses spherical particles painted in white and black as display elements. It is placed between the first electrode layer and the second electrode layer, which are electrode layers, and the first electrode layer and the second This method of displaying information involves controlling the orientation of spherical particles by creating a potential difference in the electrode layer. be.

[0256] In Figures 7 and 8, the first substrate 4001 and the second substrate 4006 are made of glass. In addition to stainless steel substrates, flexible substrates can also be used, such as translucent plastics. A substrate such as a acrylic sheet can be used. As for plastics, FRP (Fiberglass Plastic) can be used. s-Reinforced Plastics) sheets, PVF (Polyvinyl Fluoride) Film, polyester film, or acrylic resin film can be used. If light transmission is not required, a metal substrate such as aluminum or stainless steel (metal film) can be used. ) may be used. For example, aluminum foil can be used with PVF film or polyester film. It is also possible to use a sheet with a structure sandwiched between layers of material.

[0257] In this embodiment, an aluminum oxide film is used as the insulating film 4020.

[0258] The aluminum oxide film provided as an insulating film 4020 on the oxide semiconductor film contains hydrogen and moisture. It has a high barrier effect (blocking effect) that prevents both impurities and oxygen from passing through the membrane. stomach.

[0259] Therefore, the aluminum oxide film is subject to fluctuations in hydrogen during and after the manufacturing process. The inclusion of impurities such as moisture into oxide semiconductor films, and the main component materials that make up the oxide semiconductors It functions as a protective film that prevents the release of certain oxygen atoms from the oxide semiconductor film.

[0260] Furthermore, the insulating film 4021, which functions as a planarizing insulating film, is made of acrylic, polyimide, and benzosine. Using heat-resistant organic materials such as chlorobutene resins, polyamides, and epoxy resins is possible. Yes, it is possible. In addition to the organic materials mentioned above, low-dielectric materials (low-k materials) and siloxane resins can also be used. PSG (phosphorus glass), BPSG (phosphorus boron glass), etc., can be used. Alternatively, an insulating film may be formed by stacking multiple insulating films made of these materials.

[0261] The method for forming the insulating film 4021 is not particularly limited and may be sputtering, S OG method, spin coating, dip coating, spray coating, droplet ejection method (inkjet method, etc.) Printing methods (screen printing, offset printing, etc.), doctor knife, roll coater, car Ten coaters, knife coaters, etc., can be used.

[0262] A display device displays images by transmitting light from a light source or display element. Therefore, the pixels through which light is transmitted. The thin films provided in the section, such as substrates, insulating films, and conductive films, are all sensitive to light in the visible light wavelength range. It should be translucent.

[0263] A first electrode layer and a second electrode layer (pixel electrode layer, common electrode layer, pair) that apply voltage to the display element. In the electrode layer (also called the direct electrode layer), the direction of the light to be extracted, the location where the electrode layer is provided, and Transmittance and reflectivity can be selected based on the pattern structure of the electrode layer.

[0264] The first electrode layer 4030 and the second electrode layer 4031 are made of indium acid containing tungsten oxide. Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide Indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide Indium tin oxide with added silicon dioxide, graphene, and other light-transmitting conductive materials You can use the fee.

[0265] Furthermore, the first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W) and molybdenum. (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (N) b) Tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium Metals such as titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag), Alternatively, it can be formed using one or more types of the alloy or metal nitride thereof. Cut.

[0266] Furthermore, the first electrode layer 4030 and the second electrode layer 4031 are made of conductive polymer (conductive polymer It can be formed using a conductive composition containing (also called mer). For example, so-called π-electron conjugated conductive polymers can be used. or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers or derivatives thereof consisting of two or more aniline, pyrrole, and thiophene. Examples include conductors.

[0267] Furthermore, transistors are susceptible to damage from static electricity, etc., so a protection circuit for the drive circuit is necessary. It is preferable to provide this. The protection circuit is preferably constructed using nonlinear elements.

[0268] As described above, by applying the transistor shown in any of Embodiments 1 to 3, We can provide semiconductor devices with various functions.

[0269] (Embodiment 5) Using a transistor as an example in any of Embodiments 1 to 3, information about the object can be read. A semiconductor device having an image sensor function can be fabricated.

[0270] Figure 9(A) shows an example of a semiconductor device having an image sensor function. This is the equivalent circuit of the photosensor, and Figure 9(B) is a cross-sectional view showing a part of the photosensor.

[0271] Photodiode 602 has one electrode connected to the photodiode reset signal line 658, and the other electrode connected to the photodiode reset signal line 658. One electrode is electrically connected to the gate of transistor 640. Transistor 640 In this case, either the source or the drain is connected to the photosensor reference signal line 672, and the source or drain The other end is electrically connected to either the source or the drain of transistor 656. The transistor 656 has its gate connected to the gate signal line 659, and the other of its source or drain connected to the gate signal line 659. It is electrically connected to the sensor output signal line 671.

[0272] Furthermore, in the circuit diagrams in this specification, transistors using oxide semiconductor films are clearly defined. To make it clear, the symbol for a transistor using an oxide semiconductor film is written as "OS". In Figure 9(A), transistors 640 and 656 are of Embodiment 1. The transistors shown in section 3 can be applied, and these transistors use oxide semiconductor films. In this embodiment, a transistor having a structure similar to the transistor 440a shown in Embodiment 1 is used. An example of applying the generator is shown.

[0273] Figure 9(B) shows the photodiode 602 and transistor 640 in the photosensor. This is a cross-sectional view showing a photodiode functioning as a sensor on substrate 601 (TFT substrate). A photodiode 602 and a transistor 640 are provided. A substrate 613 is provided on top of the Zista 640 using an adhesive layer 608.

[0274] On transistor 640 are insulating film 631, insulating film 632, interlayer insulating film 633, and interlayer insulating film. 634 is provided. The photodiode 602 is provided on the interlayer insulating film 633. An electrode layer 641 formed on the interlayer insulating film 633 and an electrode layer provided on the interlayer insulating film 634 Between 642 and the interlayer insulating film 633, in order from the interlayer insulating film 633 side, are the first semiconductor film 606a and the second semiconductor film 60 It has a structure in which 6b and a third semiconductor film 606c are stacked.

[0275] The electrode layer 641 is electrically connected to the conductive layer 643 formed in the interlayer insulating film 634, and the electrode layer 642 is electrically connected to the conductive layer 645 via the electrode layer 641. The conductive layer 645 is The photodiode 602 is electrically connected to the gate electrode layer of transistor 640. It is electrically connected to transistor 640.

[0276] Here, the first semiconductor film 606a is a semiconductor film having a p-type conductivity, and the second semiconductor film 606b is a high-resistance semiconductor film (Type I semiconductor film), and the third semiconductor film 606c is an n-type This example illustrates a pin-type photodiode in which conductive semiconductor films are stacked.

[0277] The first semiconductor film 606a is a p-type semiconductor film, and contains an amorphous impurity element that confers the p-type properties. It can be formed by a silicon film. The formation of the first semiconductor film 606a requires a group 13 silicon Using a semiconductor material gas containing impurity elements (e.g., boron (B)) in the plasma CVD method It is formed from this. Silane (SiH4) can be used as the semiconductor material gas. Alternatively, S i2H6, SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. may also be used. Furthermore, after forming an amorphous silicon film free of impurity elements, diffusion or ion implantation is performed. Impurity elements may be introduced into the amorphous silicon film using methods such as ion implantation. It is best to introduce impurity elements first, and then perform heating or other methods to diffuse them. In this case, methods for forming amorphous silicon films include LPCVD, vapor phase growth, Alternatively, sputtering or the like may be used. The thickness of the first semiconductor film 606a should be 10 nm or more. It is preferable to form it so that the size is 0 nm or less.

[0278] The second semiconductor film 606b is a type I semiconductor film (intrinsic semiconductor film) and is amorphous silicon. It is formed by a film. For the formation of the second semiconductor film 606b, a semiconductor material gas is used to form an amorphous film. A fast silicon film is formed by plasma CVD. Silane is used as the semiconductor material gas. (SiH4) can be used. Alternatively, Si2H6, SiH2Cl2, SiHCl3, S iCl4, SiF4, etc. may be used. The formation of the second semiconductor film 606b is performed by LPCVD. This can be carried out by vapor phase growth, sputtering, etc. The thickness of the second semiconductor film 606b is 2 It is preferable to form the surface to be between 00 nm and 1000 nm.

[0279] The third semiconductor film 606c is an n-type semiconductor film containing an impurity element that confers n-type properties. It is formed by a fast silicon film. The formation of the third semiconductor film 606c involves impurity elements from Group 15. A semiconductor material gas containing an element (e.g., phosphorus (P)) is used to form a material by plasma CVD. For the semiconductor material gas, silane (SiH4) can be used. Alternatively, Si2H6, SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. may also be used. Furthermore, impurities may be present. After forming an amorphous silicon film that does not contain elements, using diffusion or ion implantation methods Impurity elements may be introduced into the amorphous silicon film by ion implantation or the like. It is advisable to diffuse impurity elements by heating or performing other methods after introducing the elements. In this case, Methods for forming morphous silicon films include LPCVD, vapor phase growth, or spasticity. Taring or similar methods can be used. The thickness of the third semiconductor film 606c should be between 20 nm and 200 nm. It is preferable to form it so that it is at the bottom.

[0280] Furthermore, the first semiconductor film 606a, the second semiconductor film 606b, and the third semiconductor film 606c are A It may also be formed using a polycrystalline semiconductor instead of a morphous semiconductor, or a microcrystalline (semi-aluminum) semiconductor. Semi-Amorphous Semiconductor (SAS) ))It may also be formed using semiconductors.

[0281] Microcrystalline semiconductors, when considering Gibbs free energy, exhibit metastable properties intermediate between amorphous and single-crystal materials. It belongs to a state. That is, a semiconductor having a third state that is stable in terms of free energy. It is a body that has short-range order and lattice distortion. Columnar or acicular crystals are formed relative to the substrate surface. It grows in the direction of the normal. Microcrystalline silicon, a typical example of a microcrystalline semiconductor, has a Raman curve. The spectrum shows single-crystal silicon at 520 cm². -1 It is shifted to lower wavenumbers. That is, 520 cm², which represents single-crystal silicon. -1 and amorphous silicon 480cm - 1 There is a peak in the Raman spectrum of microcrystalline silicon between these points. Also, unbonded (dangly) To terminate the bonding bond, it contains at least 1 atom% or more of hydrogen or halogen. It is mixed with noble gas elements such as helium, argon, krypton, and neon. By further promoting lattice distortion, stability is increased and a good microcrystalline semiconductor film can be obtained. .

[0282] This microcrystalline semiconductor film is produced by high-frequency plasma CVD with frequencies ranging from tens of MHz to hundreds of MHz, Alternatively, it can be formed using a microwave plasma CVD apparatus with a frequency of 1 GHz or higher. Typical examples include SiH4, Si2H6, SiH2Cl2, SiHCl3, SiCl4, and S It can be formed by diluting silicon-containing compounds such as iF4 with hydrogen. In addition to compounds (e.g., silicon hydride) and hydrogen, helium, argon, krypton, and neopolymers are also present. Diluting with one or more noble gas elements selected from the list to form a microcrystalline semiconductor film. This can be done. The hydrogen flow rate ratio for silicon-containing compounds (e.g., silicon hydride) at these times 5 times or more and 200 times or less, preferably 50 times or more and 150 times or less, more preferably 100 times Furthermore, in a gas containing silicon, carbide gases such as CH4 and C2H6, and GeH 4. Germaniumized gases such as GeF4 and F2 may be added.

[0283] Furthermore, because the mobility of holes generated by the photoelectric effect is smaller than that of electrons, the pin-type Photodiodes exhibit better characteristics when the p-type semiconductor film side is the light-receiving surface. Here, p From the surface of the substrate 601 on which the in-type photodiode is formed, the photodiode 602 This example shows how to convert light received by a device into an electrical signal. It also shows the opposite conductivity to the semiconductor film side that acts as the light-receiving surface. Since light from the semiconductor film side with a specific pattern becomes ambient light, the electrode layer uses a conductive film with light-shielding properties. It would be good to have one. Also, the n-type semiconductor film side can be used as the light-receiving surface.

[0284] Insulating materials are used for insulating film 632, interlayer insulating film 633, and interlayer insulating film 634. Depending on the material, sputtering, plasma CVD, SOG, spin coating, and D Dropping, spray coating, droplet ejection (inkjet method, etc.), printing methods (screen printing, etc.) (Flush printing, etc.), doctor knife, roll coater, curtain coater, knife coater It can be formed using the following methods.

[0285] In this embodiment, an aluminum oxide film is used as the insulating film 631. The insulating film 631 is It can be formed by puttering or plasma CVD.

[0286] The aluminum oxide film provided as an insulating film 631 on the oxide semiconductor film is resistant to hydrogen and moisture. It has a high barrier effect (blocking effect) that prevents both impurities and oxygen from passing through the membrane. .

[0287] Therefore, the aluminum oxide film is subject to fluctuations in hydrogen during and after the manufacturing process. The inclusion of impurities such as moisture into oxide semiconductor films, and the main component materials that make up the oxide semiconductors It functions as a protective film that prevents the release of certain oxygen atoms from the oxide semiconductor film.

[0288] As insulating film 632, as an inorganic insulating material, silicon oxide layer, silicon oxide nitride layer, An oxide insulating film such as an aluminum oxide layer or an aluminum oxide nitride layer, or a silicon nitride layer. , nitrides such as silicon nitride layer, aluminum nitride layer, or aluminum nitride layer A single-layer or multi-layer insulating film can be used.

[0289] The interlayer insulating films 633 and 634 function as planar insulating films to reduce surface irregularities. An insulating film is preferred. Examples of interlayer insulating films 633 and 634 include polyimide and acrylic. Heat-resistant organic resins such as resins, benzocyclobutene resins, polyamides, and epoxy resins. Insulating materials can be used. In addition to the above organic insulating materials, low dielectric constant materials (low- k-materials), siloxane resins, PSG (phosphorus glass), BPSG (phosphorus boron glass), etc. A single layer or a laminate can be used.

[0290] By detecting the light incident on the photodiode 602, information about the detected object can be read. This is possible. Furthermore, when reading information about the detected object, a light source such as a backlight is used. It is possible.

[0291] As described above, multiple oxide semiconductor layers having different energy gaps serve as semiconductor layers. By using oxide semiconductor stacking with this technology, the electrical characteristics of the transistor can be improved with greater precision. This allows for precise control and enables the application of desired electrical characteristics to the transistor. By using this transistor, various features such as high functionality, high reliability, and low power consumption can be achieved. We can provide semiconductor devices tailored to specific purposes.

[0292] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0293] (Embodiment 6) A transistor shown as an example in any of Embodiments 1 to 3 is formed by integrating multiple transistors. It can be suitably used in semiconductor devices having layered integrated circuits. In this embodiment, As an example of a conductive device, an example of a storage medium (memory element) is shown.

[0294] In this embodiment, the first transistor is fabricated on a single-crystal semiconductor substrate. A second semiconductor film fabricated above transistor 140 via an insulating film is A semiconductor device including a transistor, transistor 162, is fabricated. Embodiments 1 to A transistor shown as an example in any of the three is suitable for use in transistor 162. Yes, it is possible. In this embodiment, the transistor 162 is the same as the transistor shown in Embodiment 1. An example using a transistor with a structure similar to that of the Ta440a is shown.

[0295] The semiconductor materials and structures of the stacked transistors 140 and 162 are the same, but It is fine, or it may be different. This embodiment is suitable for the circuit of a storage medium (memory element). These are examples using transistors of different materials and structures, respectively.

[0296] Figure 10 shows an example of the configuration of a semiconductor device. Figure 10(A) shows a cross-section of the semiconductor device. Figure 10(B) shows the planes of the semiconductor device. Here, Figure 10(A) is the same as Figure 10 This corresponds to the cross-sections at C1-C2 and D1-D2 in (B). Also, Figure 10(C) shows An example of a circuit diagram when the above semiconductor device is used as a memory element is shown in Figure 10(A). The semiconductor device shown in Figure 10(B) has a transistor using the first semiconductor material at the bottom. It has a 140 and a transistor 162 made of a second semiconductor material on top. In this configuration, the first semiconductor material is a semiconductor material other than an oxide semiconductor, and the second semiconductor material This is an oxide semiconductor. Other semiconductor materials include, for example, silicon and glycerides. Using luminium, silicon germanium, silicon carbide, or gallium arsenide, etc. This can be achieved, and it is preferable to use a single-crystal semiconductor. Alternatively, organic semiconductor materials may also be used. Transistors using such semiconductor materials can easily operate at high speeds. On the other hand, oxidation Transistors, which use solid semiconductors, can retain charge for extended periods due to their properties.

[0297] The semiconductor device shown in Figure 10 will be explained using Figures 10(A) to (C).

[0298] The transistor 140 is provided on a substrate 185 containing a semiconductor material (for example, silicon). A channel-forming region 116 and an impurity formed so as to sandwich the channel-forming region 116 Region 120, metal compound region 124 adjacent to impurity region 120, and channel formation region 1 A gate insulating film 108 provided on 16, and a gate electric It has pole 110.

[0299] The substrate 185 containing semiconductor materials is a single-crystal semiconductor substrate such as silicon or silicon carbide, and multi-layered Crystal semiconductor substrates, compound semiconductor substrates such as silicon germanium, and SOI substrates are used. It is possible. Generally, an "SOI substrate" has a silicon semiconductor film provided on its insulating surface. This refers to a substrate having a configured structure, but in this specification, etc., a material other than silicon on the insulating surface This also includes substrates having a semiconductor film provided thereon. In other words, the semiconductor film that the "SOI substrate" has The film is not limited to silicon semiconductor films. Furthermore, the SOI substrate can be an insulating material such as a glass substrate. This includes configurations in which a semiconductor film is provided on a substrate via an insulating film.

[0300] The method for fabricating SOI substrates involves implanting oxygen ions into a mirror-polished wafer, followed by high-temperature heating. This process forms an oxide layer to a certain depth from the surface, and also creates defects in the surface layer. Methods that eliminate depressions, and methods that involve heat treatment of microvoids formed by hydrogen ion irradiation. Methods for cleaving semiconductor substrates using their length, or for growing single-crystal semiconductor films on insulating surfaces. Methods for forming [the material] can be used.

[0301] For example, by adding ions from one side of a single-crystal semiconductor substrate, one side of the single-crystal semiconductor substrate A weakening layer is formed to a certain depth from the surface, on one surface of a single-crystal semiconductor substrate, or on the device substrate. An insulating film is formed on one of the two. The single crystal semiconductor substrate and the device substrate are placed with the insulating film in between. While the materials are bonded together, cracks are induced in the weakening layer, separating the single-crystal semiconductor substrate at the weakening layer. After heat treatment, a single-crystal semiconductor film is formed on the device substrate from a single-crystal semiconductor substrate as a semiconductor film. SOI substrates prepared using the above method can also be suitably used.

[0302] An element isolation insulating layer 106 is provided on the substrate 185 so as to surround the transistor 140. Furthermore, in order to achieve high integration, the transistor 140 is as shown in Figure 10. It is desirable to have a configuration that does not have a side wall insulating layer that forms a wall. On the other hand, Transis When prioritizing the characteristics of the 140, the side of the gate electrode 110 will be the side wall. A wall insulating layer may be provided, and an impurity region 120 may be provided that includes regions with different impurity concentrations.

[0303] The transistor 140, which uses a single-crystal semiconductor substrate, is capable of high-speed operation. Therefore, By using this transistor as a readout transistor, information can be read out at high speed. This can be done by forming two insulating films to cover the transistor 140. As a pre-formation treatment for the star 162 and capacitive element 164, the two insulating film layers are subjected to CMP treatment. Then, the flattened insulating film 128 and insulating film 130 are formed, and at the same time, the upper surface of the gate electrode 110 To expose.

[0304] Insulating film 128 and insulating film 130 are typically silicon oxide film, silicon oxide nitride film, and oxide Aluminum film, aluminum oxide nitride film, silicon nitride film, aluminum nitride film, nitride Inorganic insulating films such as silicon oxide films and aluminum nitride films can be used. The film 128 and insulating film 130 are formed using plasma CVD or sputtering. It is possible.

[0305] Furthermore, organic materials such as polyimide, acrylic resin, and benzocyclobutene resin can be used. This can be done. In addition to the above organic materials, low dielectric constant materials (low-k materials) can also be used. This can be done. When using organic materials, an insulating film can be made using wet methods such as spin coating or printing. 128. An insulating film 130 may be formed.

[0306] In addition, in the insulating film 130, a silicon oxide film is used as the film in contact with the semiconductor film.

[0307] In this embodiment, the insulating film 128 is an oxide nitride with a thickness of 50 nm, obtained by sputtering. A silicon film is formed, and as an insulating film 130, it is oxidized to a thickness of 550 nm by sputtering. It forms a silicon film.

[0308] A dielectric film 130 that has been sufficiently planarized by CMP treatment is laid on an oxide semiconductor with different energy gaps. A conductive film is laminated. In this embodiment, the oxide semiconductor film is laminated using the sputtering method. Therefore, In-Sn-Zn oxide and In-Ga-Zn oxide layers are sequentially placed on the insulating film 130. It is stacked on top of each other.

[0309] Next, the oxide semiconductor film stack is selectively etched to form island-shaped oxide semiconductor stacks 144. To accomplish this, a source electrode or drain electrode 142a is placed on the oxide semiconductor stack 144, and the source electrode Forms an electrode or drain electrode 142b.

[0310] A gate insulating film 146 and a gate electrode layer 148 are formed on an oxide semiconductor film. 148 is formed by selectively etching the conductive layer after it has been formed. It is possible.

[0311] As the gate insulating film 146, an oxide film is formed using a plasma CVD method or a sputtering method. Silicon nitride film, silicon nitride film, silicon oxide nitride film, silicon oxide film, aluminum oxide film Aluminum film, aluminum nitride film, aluminum oxide nitride film, aluminum oxide nitride film, aluminum oxide film A phnium film, or a gallium oxide film, or an aluminum oxide film can be formed.

[0312] Electrode layer 148, source electrode or drain electrode 142a, source electrode or drain The conductive layer that can be used for electrode 142b is PVD, including sputtering. It can be formed using methods such as plasma CVD. The materials include elements selected from Al, Cr, Cu, Ta, Ti, Mo, and W, as well as the aforementioned Alloys containing elements can be used. Mn, Mg, Zr, Be, Nd, Sc Any of these materials, or a combination of several of them, may be used.

[0313] The conductive layer may be a single layer or a laminated structure of two or more layers. For example, titanium Single-layer structures of silicon films and titanium nitride films, single-layer structures of silicon-containing aluminum films, aluminum A two-layer structure in which a titanium film is laminated on a titanium film, and a two-layer structure in which a titanium film is laminated on a titanium nitride film. Examples include a three-layer structure in which a titanium film, an aluminum film, and another titanium film are laminated. Oh, when the conductive layer is a single-layer structure of titanium film or titanium nitride film, it has a tapered shape. Source electrode or drain electrode 142a, and source electrode or drain electrode 142 One advantage is that it is easy to process into form b.

[0314] Next, on the oxide semiconductor stack 144, gate insulating film 146, and gate electrode layer 148, Form 150. In this embodiment, an aluminum oxide film is formed as the insulating film 150. ru.

[0315] The aluminum oxide film provided as an insulating film 150 on the oxide semiconductor stack 144 contains hydrogen , a barrier effect that prevents both moisture and other impurities, as well as oxygen, from passing through the membrane (blocking effect) ) is high.

[0316] Therefore, the aluminum oxide film is subject to fluctuations in hydrogen during and after the manufacturing process. The incorporation of impurities such as moisture into the oxide semiconductor stack 144, and the main components constituting the oxide semiconductor It functions as a protective film that prevents the release of oxygen, a component material, from the oxide semiconductor stack 144. .

[0317] Alternatively, a separate insulating film may be formed by laminating it onto the insulating film 150.

[0318] As an insulating film, a silicon oxide film is formed using methods such as plasma CVD or sputtering. Silicon nitride film, silicon oxide nitride film, silicon nitride oxide film, aluminum nitride film, oxide Aluminum film, aluminum oxide nitride film, aluminum nitride oxide film, hafnium oxide film Alternatively, a gallium oxide film can be used.

[0319] On the insulating film 150, an electrode is placed in a region that overlaps with the source electrode or drain electrode 142a. Forms layer 153.

[0320] Next, an insulating film 152 is formed on the transistor 162 and the electrode layer 153. 2 can be formed using sputtering or CVD methods. Also, silica oxide Inorganic silicon nitride, silicon oxide, hafnium oxide, aluminum oxide, etc. It can be formed using materials that include edge material. Also, polyimide, acrylic, benzo Organic materials such as cyclobutene resins can be used, and the above organic materials can be coated or printed. Wet methods such as the inkjet method can be used.

[0321] Next, the gate insulating film 146, insulating film 150, and insulating film 152 are coated with a source electrode or drain. An opening is formed that reaches the in electrode 142b. The formation of this opening is done using a mask or the like. This is done by selective etching.

[0322] Subsequently, a wiring 156 is formed in the opening, which is in contact with the source electrode or drain electrode 142b. Figure 10(A) shows the connection between the source electrode or drain electrode 142b and the wiring 156. The continuation is not shown in the illustration.

[0323] Wiring 156 is used for PVD methods such as sputtering and plasma CVD. The conductive layer is formed by first forming it using the VD method, and then etching the conductive layer. Furthermore, the conductive layer material can be selected from Al, Cr, Cu, Ta, Ti, Mo, and W. The elements listed above, or alloys containing the aforementioned elements, can be used. Mn, Mg, Z You may use any one of the following materials: r, Be, Nd, Sc, or a combination of these. The details are the same as for the source electrode or drain electrode 142a, etc.

[0324] The transistor 162 and the capacitive element 164 are formed through the above process. In this embodiment, Transistor 162 comprises at least two oxide semiconductor layers with different energy gaps. This is a transistor having an oxide semiconductor stack 144. Different energy is used for the semiconductor layer. By using an oxide semiconductor stack 144 that has multiple oxide semiconductor layers having a G-gap, This allows for more precise control of the electrical characteristics of transistor 162, and the desired It becomes possible to impart electrical characteristics to transistor 162. Also, in this embodiment Therefore, the oxide semiconductor stack 144 is purified to an oxide containing an excess of oxygen to compensate for the oxygen deficiency. A multilayer semiconductor structure is used. Therefore, the off-current of transistor 162 is reduced, and the electrical characteristics are changed. Dynamics are suppressed and it is electrically stable. Capacitive element 164 is a source electrode or drain Electrode 142a, oxide semiconductor stack 144, gate insulating film 146, and electrode layer 153, It is composed of.

[0325] In addition, in the capacitive element 164 of Figure 10, the gate insulating film 146 and the insulating film 150 are stacked. This ensures sufficient insulation between the source electrode or drain electrode 142a and the electrode layer 153. It can be secured in minutes. Of course, to ensure sufficient capacity, an insulating film 150 is provided. A capacitive element 164 without such a configuration may also be used. 64 may be used. Furthermore, if capacitance is not required, a configuration without the capacitive element 164 is also possible. It is also possible to do so.

[0326] Figure 10(C) shows an example of a circuit diagram when the above semiconductor device is used as a memory element. In Figure 10(C), one of the source electrode or drain electrode of transistor 162 and One electrode of the capacitive element 164 and the gate electrode of the transistor 140 are electrically connected. It is done. Also, the first line (also called the source line) and the transistor The 140 source electrodes are electrically connected to the second line (bit wire). The (also called) and the drain electrode of transistor 140 are electrically connected. The third wire (also called the first signal line) and the source of transistor 162 The other electrode or drain electrode is electrically connected to the fourth line. The second signal line (also called the second signal line) and the gate electrode of transistor 162 are electrically connected. And, the fifth line (also called the word line) and the capacitive element 16 The other end of electrode 4 is electrically connected.

[0327] The oxide semiconductor transistor 162 has the characteristic of having an extremely low off-current. Therefore, by turning off transistor 162, the source of transistor 162 One of the electrodes or the drain electrode, one of the electrodes of the capacitive element 164, and the transistor 140 The potential of the node (hereinafter referred to as node FG) to which the gate electrode is electrically connected for an extremely long period of time It is possible to hold over a certain distance. And by having the capacitive element 164, The charge applied to the FG becomes easier to retain, and the retained information is easier to read out. It will become.

[0328] When storing information in a semiconductor device (writing), first, the potential of the fourth wire is set to the transistor. The potential is set so that transistor 162 is turned on, and transistor 162 is turned on. As a result, the potential of the third wiring is supplied to node FG, and a predetermined amount of charge is accumulated at node FG. Here, a charge that gives two different potential levels (hereinafter referred to as the low level) is used. Assume that either electric charge or high-level charge is given. The potential of the fourth wire is set to the potential at which transistor 162 is in the OFF state, and the transistor By turning off 162, node FG enters a floating state, and therefore node FG has The predetermined charge remains maintained. As described above, a predetermined amount of charge is applied to node FG. By accumulating and retaining data, information can be stored in memory cells.

[0329] The off-current of transistor 162 is controlled to be extremely small, so it is supplied to node FG. The charged charge is retained for a long time. Therefore, a refresh operation may become unnecessary. Alternatively, it becomes possible to significantly reduce the frequency of refresh operations, thus saving power. It can be reduced to this extent. Also, even in the absence of power supply, long-term memory can be stored. It is possible to retain the content.

[0330] When reading stored information (readout), a predetermined potential (constant potential) is applied to the first wiring. In this state, when an appropriate potential (readout potential) is applied to the fifth wiring, it is held at node FG. Depending on the amount of charge applied, transistor 140 takes on different states. Generally, transistor 1 If 40 is an n-channel type, then when a high-level charge is held at node FG Apparent threshold V of transistor 140 th_H Low-level charge at node FG Apparent threshold V of transistor 140 when held th_L It will become lower Here, the apparent threshold is the threshold that makes transistor 140 "on". This refers to the potential of the fifth wiring that is necessary for this purpose. Therefore, the potential of the fifth wiring is V th _H and V th_L By setting the potential V0 to the intermediate potential, the charge held at node FG can be determined. They can be separated. For example, in the case of writing, if a high-level charge is given, The potential of the fifth wire is V0 (>V th_H ) In that case, transistor 140 is in the "on state". This is the result. If a low-level charge is given, the potential of the fifth wiring is V0( <V t h_L Even in this case, transistor 140 remains in the "off state". Therefore, the fifth The potential of the wiring is controlled to read the ON or OFF state of transistor 140 ( The stored information can be retrieved by reading the potential of the wiring in step 2.

[0331] Furthermore, when rewriting stored information, the above writing process consumes a predetermined amount of electricity. By supplying a new potential to node FG, which is holding a load, new information is associated with node FG. To maintain the charge. Specifically, the potential of the fourth wire is set when transistor 162 is ON. The potential is set to this value, and transistor 162 is turned on. This turns on the power of the third wiring. A potential (related to new information) is supplied to node FG, and a predetermined amount of charge is stored in node FG. The charges are then added. After that, the potential of the fourth wire is set to the potential at which transistor 162 is in the off state. By turning off transistor 162, node FG receives new information related to The charge is retained. That is, a predetermined amount of charge is stored in node FG by the first write. By performing an operation similar to the first write (second write) while the charge is retained, It is possible to overwrite the stored information.

[0332] The transistor 162 shown in this embodiment has at least two layers with different energy gaps. It has an oxide semiconductor stack including an oxide semiconductor layer, and is controlled so that the off current is sufficiently low. This is a transistor. By using such a transistor, it is possible to extend the lifespan of the transistor over an extremely long period of time. A semiconductor device capable of retaining stored data can be obtained.

[0333] As described above, an oxide using multiple oxide semiconductor layers with different energy gaps By using semiconductor stacking, the electrical characteristics of transistors can be controlled with greater precision. This makes it possible to impart the desired electrical characteristics to the transistor. Therefore, high functionality, We can provide semiconductor devices that meet various purposes, such as high reliability or low power consumption. .

[0334] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0335] (Embodiment 7) The semiconductor devices disclosed herein are applicable to a variety of electronic devices (including amusement machines). This is possible. As an electronic device, for example, a television set (television, or television Receivers (also called receivers), computer monitors, digital cameras, digital video cameras Cameras such as LA, digital photo frames, and mobile phones (also called mobile phones or mobile phone devices). ), portable game consoles, personal digital assistants, sound playback devices, large game machines such as pachinko machines, etc. Examples include the semiconductor device described in the above embodiment. To clarify, by incorporating the semiconductor device described in the above embodiment, high functionality and high reliability can be achieved. To provide electronic devices that possess qualities tailored to various purposes, such as performance or low power consumption. It is possible.

[0336] Figure 11(A) shows a notebook-type personal computer, consisting of a main unit 3001 and a casing 300 2. It consists of a display unit 3003, a keyboard 3004, etc. Embodiment 1 By applying the semiconductor device shown in any of items 1 through 6 to the display unit 3003, high performance and It can be made into a highly reliable notebook-type personal computer.

[0337] Figure 11(B) shows a personal digital assistant (PDA), and the main unit 3021 has a display unit 3023, An external interface 3025 and operation buttons 3024, etc. are provided. A stylus 3022 is included as an accessory. The semiconductor shown in any of Embodiments 1 to 6 By applying the device to the display unit 3023, a more high-performance and highly reliable portable information terminal can be created. It can be called (PDA).

[0338] Figure 11(C) shows an example of an e-book. For example, an e-book is housed in a casing 2701 and It consists of two enclosures, enclosure 2701 and enclosure 2703. Enclosures 2701 and 2703 are shafts It is integrated with part 2711, and can open and close using the shaft part 2711 as an axis. This configuration allows it to function like a physical book.

[0339] The display unit 2705 is incorporated into the housing 2701, and the display unit 2707 is incorporated into the housing 2703. It is included. Display units 2705 and 2707 are configured to display a continuation screen. Alternatively, a configuration that displays different screens is also acceptable. For example, text is displayed on the right-hand display unit (display unit 2705 in Figure 11(C)), and on the left-hand side An image can be displayed on the display unit (display unit 2707 in Figure 11(C)). Embodiment The semiconductor device shown in any of 1 to 6 is applied to the display unit 2705 and the display unit 2707. This makes it possible to produce high-performance and highly reliable ebooks. The display unit 2705 is half When using transmissive or reflective liquid crystal display devices, use in relatively bright conditions is also anticipated. Therefore, solar panels are installed to enable power generation by solar panels and charging by batteries. This is also acceptable. Furthermore, using a lithium-ion battery allows for miniaturization. It has advantages such as [mentioning specific advantages].

[0340] Furthermore, Figure 11(C) shows an example in which the housing 2701 is equipped with an operating section, etc. For example, The enclosure 2701 is equipped with a power supply 2721, operation keys 2723, speaker 2725, etc. The page can be turned using operation key 2723. Note that it is on the same surface as the display unit of the casing. It may also be configured to include a keyboard and pointing device. External connection terminals (earphone jack, USB terminal, etc.), recording media insertion slot, etc. are located on the front or sides. It may also be configured to include the following features. Furthermore, the e-book may be configured to have the functionality of an electronic dictionary. You may do so.

[0341] Furthermore, e-books may be configured to transmit and receive information wirelessly. It is also possible to configure the system to allow users to purchase and download desired book data from a server. be.

[0342] Figure 11(D) shows a mobile phone, which consists of two housings, housing 2800 and housing 2801. The enclosure 2801 contains a display panel 2802, a speaker 2803, and a microphone. 2804, pointing device 2806, camera lens 2807, external connection terminal It is equipped with 2808, etc. Also, the 2800 housing has a solar cell for charging mobile phones. It features a 2810 chip, an external memory slot 2811, and other components. The antenna is located on the casing 28. 01 Built inside. Display the semiconductor device shown in any of Embodiments 1 to 6. By applying it to NEL 2802, a high-performance and highly reliable mobile phone can be created. .

[0343] Furthermore, the display panel 2802 is equipped with a touch panel, and an image is displayed in Figure 11(D). Multiple operation keys 2805 are shown with dotted lines. Note that the output is from solar cell 2810. A boost circuit is also implemented to increase the voltage to the voltage required for each circuit.

[0344] The display panel 2802 changes its display orientation as appropriate depending on the usage mode. Since the camera lens 2807 is located on the same plane as the 2802, video calls are possible. Speaker 2803 and microphone 2804 are not limited to voice calls, but also video calls. Recording and playback are possible. Furthermore, the casings 2800 and 2801 slide apart, as shown in the diagram. As shown in 11(D), it can be changed from an unfolded state to an overlapping state, making it suitable for carrying around. Further miniaturization is possible.

[0345] External connection terminal 2808 can be connected to various cables such as AC adapters and USB cables. It is capable of charging and data communication with personal computers, etc. By inserting a recording medium into memory slot 2811, it becomes possible to store and move larger amounts of data. ru.

[0346] Furthermore, even if it has infrared communication capabilities, television reception capabilities, etc. in addition to the above functions good.

[0347] Figure 11(E) shows a digital video camera, consisting of a main unit 3051, a display unit (A) 3057, Eyepiece 3053, operation switch 3054, display unit (B) 3055, battery 3056 It is composed of the following. The semiconductor device shown in any of Embodiments 1 to 6 is a display unit By applying (A)3057 and the display unit (B)3055, high performance and high reliability are achieved. It can be used as a digital video camera.

[0348] Figure 11(F) shows an example of a television system. The television system has a housing 96 The display unit 9603 is incorporated into 01. The display unit 9603 displays video. This is possible. Also, here we have a configuration in which the chassis 9601 is supported by the stand 9605. This is shown. Applicable to the display unit 9603 of the semiconductor device shown in any of Embodiments 1 to 6. This makes it possible to create a high-performance and highly reliable television system.

[0349] The television equipment is operated using the control switches on the 9601 housing or a separate remote control. This can be done by the machine. In addition, the remote control unit will output from the said remote control unit. The configuration may also include a display unit for displaying information.

[0350] The television system shall consist of a receiver, modem, etc. It can receive television broadcasts, and also communicate via wired or wireless connection through a modem. By connecting to a network, one-way (sender to receiver) or two-way (sender to receiver) communication is possible. It is also possible to communicate information between recipients, or between recipients themselves.

[0351] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case. [Examples]

[0352] In this embodiment, the energy gap of the first oxide semiconductor layer is formed on the first oxide semiconductor layer. A second oxide semiconductor layer smaller than the first is formed, and a third acid is further formed on the second oxide semiconductor layer. Samples were prepared with a semiconductor layer formed on them, and the ionization potential of these samples was measured. The following was performed, and an energy band diagram was calculated based on the results. In this specification, ionization The potential value is the sum of the band gap and electron affinity, and the band gap The value used is obtained by measuring a single-layer ellipsograph of the material.

[0353] The sample consists of a 5nm thick IGZO film and a 5nm thick In-Sn film on a single-crystal silicon substrate. - A Zn-based oxide film and an IGZO film with a thickness of 5 nm were layered and deposited. The deposition conditions for each film were as follows: The film was deposited using the puttering method at a substrate temperature of 300°C under an oxygen atmosphere (100% oxygen). The target used was an oxide target with an atomic ratio of In:Ga:Zn = 1:1:1. Next, an IGZO film is formed. Also, the In-Sn-Zn oxide film is In:Sn:Zn= A 2:1:3 [atomic ratio] oxide target is used.

[0354] Furthermore, a cross-section of a sample obtained by laminating a quartz substrate under the same deposition conditions was taken. The resulting TEM image is shown in Figure 14(A). A schematic diagram is shown in Figure 14(B). In B), the interface of the oxide semiconductor layer is shown with a dotted line, but this is a schematic representation. Depending on the materials, film deposition conditions, and heat treatment, the interface with each oxide semiconductor layer may become unclear. There are also cases where this occurs. The sample photographed in Figure 14(A) is a quartz substrate 1000 with a first film thickness of 5 nm. IGZO film 1001, thickness 5nm In-Sn-Zn oxide film 1002, thickness 5nm The second IGZO film 1003 is laminated and formed with an In-Sn-Zn oxide film. The interface of the IGZO film can be seen. Also, in Figure 14(A), the second IGZO film 1003 and The In-Sn-Zn oxide film 1002 contains crystals and has a c-axis orientation. It can be confirmed that it is an oxide semiconductor (CAAC). Also, in Figure 14(A), the first The IGZO film 1001 has an amorphous structure. Note that in Figure 14(A), two of the three layers are The oxide semiconductor film has a crystalline structure, but is not particularly limited to the second IGZO film. Only layer 1003 may have a crystalline structure, or all three layers may have a crystalline structure, or all three layers They may all be amorphous structures.

[0355] Ultraviolet photoelectron spectroscopy (UPS) analysis while sputtering from the surface of the sample. Ionization by violet photoelectron spectroscopy The results of the potential measurement are shown in Figure 12.

[0356] In Figure 12, the horizontal axis represents the sputtering time from the sample surface, and the vertical axis represents the ionization. This represents the potential. Note that sputtering of IGZO film and In-Sn-Zn oxide film is also shown. The sample boundaries are shown assuming equal rates. From Figure 12, the IGZO film is sandwiched between the two layers. It can be seen that the ionization potential decreases in the In-Sn-Zn oxide film. Oh, the ionization potential represents the energy difference from the vacuum level to the valence band.

[0357] By subtracting the band gap measured by an ellipsograph from the ionization potential value, the conduction band can be calculated. The energy was calculated and the band structure of this multilayer film was created. However, the IGZO film and In- The band gaps of the Sn-Zn oxide films were set to 3.2 eV and 2.8 eV, respectively. The result is shown in Figure 13. Figure 13 is filled in as shown in the energy band diagram in Figure 4(C). It can be seen that a crowded channel has been formed.

[0358] In this embodiment, IGZO films are used as the first oxide semiconductor layer and the third oxide semiconductor layer. , with a larger ionization potential than the first oxide semiconductor layer and the third oxide semiconductor layer In-Sn is used as the second oxide semiconductor layer, which has a small energy gap. -Stacking using Zn-based oxide films is shown in the energy band diagram in Figure 13 or Figure 4(C). It was confirmed that it can be represented by the first oxide semiconductor layer, the second oxide semiconductor layer, and The combination of materials for the third oxide semiconductor layer is not particularly limited, as shown in Figure 13 or Figure 4(C). Consider the energy gap of the materials used by the implementer so that the energy band diagram shown is obtained. The materials should be selected and combined appropriately, for example, a first oxide semiconductor layer and a third An IGZO film is used as the first oxide semiconductor layer, and indium zinc is used as the second oxide semiconductor layer. Lamination using oxide films may also be used. [Explanation of Symbols]

[0359] 101 Oxide semiconductor layer 102 Oxide semiconductor layer 103 Oxide semiconductor layer 106 Element isolation insulating layer 108 gate insulating film 110 Guard Station 111 Oxygen excess region 112. Oxygen excess region 116 Channel formation region 120 Impurity region 121a Low resistance area 121b Low resistance region 121c Channel formation region 121d Low resistance region 121e Low resistance region 122a Low resistance area 122b Low resistance region 122c Channel formation region 122d Low resistance region 122e low resistance area 123a Low resistance region 123b Low resistance region 123c Channel formation region 123d low resistance region 123e Low resistance region 124 Metal compound area 128 Insulating film 130 Insulating Film 140 transistors 142a Drain electrode 142b Drain electrode 144 Oxide semiconductor stack 146 Gate insulating film 148 Guard Layer 150 insulating film 152 Insulating film 153 Electrode layer 156 Wiring 162 transistors 164 Capacitive elements 185 circuit boards 191 Oxide semiconductor film 192 Oxide semiconductor film 400 circuit boards 401 Guard Layer 402 Gate Insulator 403 Oxide Semiconductor Layer 404a Source electrode layer 404b Drain electrode layer 405a Source electrode layer 405b Drain electrode layer 407 Insulating film 415a Source electrode layer 415b Drain electrode layer 416 Insulating film 420 transistors 421 Dopant 423 Transistors 425 transistors 430 transistors 431 Oxygen 436 Oxide insulating film 440a transistor 440b transistor 440c transistor 440d transistor 465a Wiring layer 465b Wiring layer 480a Transistor 480b transistor 493 Layers 601 circuit board 602 Photodiode 606a Semiconductor film 606b Semiconductor film 606c semiconductor film 608 Adhesive layer 613 circuit board 631 Insulating film 632 Insulating film 633 Interlayer insulating film 634 Interlayer insulating film 640 transistors 641 Electrode layer 642 Electrode layer 643 Conductive layer 645 Conductive layer 656 transistors 658 Photodiode reset signal line 659 Gate signal line 671 Photosensor output signal line 672 Photosensor Reference Signal Line 1000 quartz substrate 1001 IGZO membrane 1002 In-Sn-Zn oxide film 1003 IGZO membrane 2701 enclosure 2703 Casing 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation Keys 2725 Speaker 2800 cabinets 2801 enclosure 2802 Display Panel 2803 Speaker 2804 Microphone 2805 Operation Keys 2806 Pointing device 2807 Camera Lens 2808 External connection terminal 2810 solar cells 2811 External memory slot 3001 Main Unit 3002 enclosure 3003 Display section 3004 Keyboard 3021 Main Unit 3022 Stylus 3023 Display section 3024 Operation Buttons 3025 External Interface 3051 Main Unit 3053 Eyepiece 3054 Operation switch 3056 Battery 4001 circuit board 4002 pixel section 4003 Signal Line Drive Circuit 4004 Scan Line Drive Circuit 4005 Sealant 4006 circuit board 4008 Liquid Crystal Layer 4010 Transistor 4011 Transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Insulating film 4021 Insulating film 4023 Insulating film 4030 Electrode layer 4031 Electrode layer 4032 Insulating film 4033 Insulating film 4510 Bulkhead 4511 Electroluminescent layer 4513 Light-emitting element 4514 Filling material 9601 enclosure 9603 Display section 9605 Stand

Claims

1. A first transistor having silicon in the channel formation region, A second transistor having an oxide semiconductor in the channel formation region, It has a capacitive element, A semiconductor device in which the gate electrode of the first transistor, one of the source electrode and drain electrode of the second transistor, and one electrode of the capacitive element are electrically connected, A first conductive layer having a region located above the channel formation region of the first transistor and functioning as the gate electrode of the first transistor, A first insulating layer having a region in contact with the side surface of the first conductive layer, A second insulating layer having a region located above the first insulating layer, An oxide semiconductor layer having a region in contact with the upper surface of the second insulating layer and having a channel formation region for the second transistor, A second conductive layer having a region in contact with the upper surface of the oxide semiconductor layer and a region in contact with the upper surface of the first conductive layer, and having the function of one of the source electrode and drain electrode of the second transistor, A third insulating layer having a region in contact with the upper surface of the oxide semiconductor layer, A third conductive layer having a region located above the oxide semiconductor layer via the third insulating layer and functioning as the gate electrode of the second transistor, A fourth insulating layer having a region in contact with the upper surface of the third conductive layer, The fourth conductive layer has a region that overlaps with the second conductive layer via the fourth insulating layer and the third insulating layer, and functions as the other electrode of the capacitive element, A semiconductor device in which, in a plan view, the channel formation region of the first transistor and the channel formation region of the second transistor do not overlap.

2. A first transistor having silicon in the channel formation region, A second transistor having an oxide semiconductor in the channel formation region, It has a capacitive element, A semiconductor device in which the gate electrode of the first transistor, one of the source electrode and drain electrode of the second transistor, and one electrode of the capacitive element are electrically connected, A first conductive layer having a region located above the channel formation region of the first transistor and functioning as the gate electrode of the first transistor, A first insulating layer having a region in contact with the side surface of the first conductive layer, A second insulating layer having a region located above the first insulating layer, An oxide semiconductor layer having a region in contact with the upper surface of the second insulating layer and having a channel formation region for the second transistor, A second conductive layer having a region in contact with the upper surface of the oxide semiconductor layer and a region in contact with the upper surface of the first conductive layer, and having the function of one of the source electrode and drain electrode of the second transistor, A third insulating layer having a region in contact with the upper surface of the oxide semiconductor layer, A third conductive layer having a region located above the oxide semiconductor layer via the third insulating layer and functioning as the gate electrode of the second transistor, A fourth insulating layer having a region in contact with the upper surface of the third conductive layer, The fourth conductive layer has a region that overlaps with the second conductive layer via the fourth insulating layer and the third insulating layer, and functions as the other electrode of the capacitive element, The first insulating layer comprises nitrogen and silicon, The second insulating layer comprises oxygen and silicon, The third insulating layer comprises oxygen and silicon, A semiconductor device in which, in a plan view, the channel formation region of the first transistor and the channel formation region of the second transistor do not overlap.

3. A first transistor having silicon in the channel formation region, A second transistor having an oxide semiconductor in the channel formation region, It has a capacitive element, A semiconductor device in which the gate electrode of the first transistor, one of the source electrode and drain electrode of the second transistor, and one electrode of the capacitive element are electrically connected, A first conductive layer having a region located above the channel formation region of the first transistor and functioning as the gate electrode of the first transistor, A first insulating layer having a region in contact with the side surface of the first conductive layer, A second insulating layer having a region located above the first insulating layer, An oxide semiconductor layer having a region in contact with the upper surface of the second insulating layer and having a channel formation region for the second transistor, A second conductive layer having a region in contact with the upper surface of the oxide semiconductor layer and a region in contact with the upper surface of the first conductive layer, and having the function of one of the source electrode and drain electrode of the second transistor, A third insulating layer having a region in contact with the upper surface of the oxide semiconductor layer, A third conductive layer having a region located above the oxide semiconductor layer via the third insulating layer and functioning as the gate electrode of the second transistor, A fourth insulating layer having a region in contact with the upper surface of the third conductive layer, A fifth insulating layer having a region in contact with the upper surface of the fourth insulating layer, The fourth conductive layer has a region that overlaps with the second conductive layer via the fourth insulating layer and the third insulating layer, and functions as the other electrode of the capacitive element, In a plan view, the channel formation region of the first transistor and the channel formation region of the second transistor do not overlap. The fifth insulating layer is made of an organic material, wherein the semiconductor device is an organic material.

4. A first transistor having silicon in the channel formation region, A second transistor having an oxide semiconductor in the channel formation region, It has a capacitive element, A semiconductor device in which the gate electrode of the first transistor, one of the source electrode and drain electrode of the second transistor, and one electrode of the capacitive element are electrically connected, A first conductive layer having a region located above the channel formation region of the first transistor and functioning as the gate electrode of the first transistor, A first insulating layer having a region in contact with the side surface of the first conductive layer, A second insulating layer having a region located above the first insulating layer, An oxide semiconductor layer having a region in contact with the upper surface of the second insulating layer and having a channel formation region for the second transistor, A second conductive layer having a region in contact with the upper surface of the oxide semiconductor layer and a region in contact with the upper surface of the first conductive layer, and having the function of one of the source electrode and drain electrode of the second transistor, A third insulating layer having a region in contact with the upper surface of the oxide semiconductor layer, A third conductive layer having a region located above the oxide semiconductor layer via the third insulating layer and functioning as the gate electrode of the second transistor, A fourth insulating layer having a region in contact with the upper surface of the third conductive layer, A fifth insulating layer having a region in contact with the upper surface of the fourth insulating layer, The fourth conductive layer has a region that overlaps with the second conductive layer via the fourth insulating layer and the third insulating layer, and functions as the other electrode of the capacitive element, The first insulating layer comprises nitrogen and silicon, The second insulating layer comprises oxygen and silicon, The third insulating layer comprises oxygen and silicon, In a plan view, the channel formation region of the first transistor and the channel formation region of the second transistor do not overlap. The fifth insulating layer is made of an organic material, wherein the semiconductor device is an organic material.

5. In any one of claims 1 to 4, A semiconductor device wherein at least one of the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer has a laminated structure.

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