Indication device

Abstract

Improve the transmittance of the display device. [Solution] An embodiment of the present disclosure relates to a display device, and more specifically, to a display device including a substrate, a first metal pattern disposed in a non-transparent region and including a transparent material, a first data line disposed on the substrate and arranged across the non-transparent region and at least one transparent region among a plurality of transparent regions, and a first active layer disposed on the first metal pattern and overlapping the first metal pattern, thereby improving the transmittance of the optical region.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display device.

Background Art

[0002] As the information society develops, the requirements for display devices for displaying images are increasing in various forms. In recent years, various display devices such as liquid crystal display devices and organic light-emitting display devices have been utilized.

[0003] The display area is an area where an image is displayed. The display area can include a general display area and an optical area. The display device can include an optical device disposed in the optical area. The higher the transmittance of the optical area, the more the sensing ability of the optical device can be improved.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present disclosure can improve the transmittance of the optical area through a display panel including a transparent metal.

[0005] Embodiments of the present disclosure can improve the transmittance of the non-transmissive area through a display panel including a transparent metal.

[0006] Embodiments of the present disclosure can improve the transmittance of the transmissive area through a display panel including a transparent metal.

[0007] Embodiments of the present disclosure can provide a display device capable of low power as the transmittance of the optical area is improved.

Means for Solving the Problems

[0008] Embodiments of the present disclosure provide a display device that includes a display area on which an image is displayed, the display area including an optical area including a general area and a plurality of transparent areas, the optical area further including a non-transparent area which is the outer boundary of the plurality of transparent areas, a first metal pattern disposed on the substrate and in the non-transparent area and including a transparent material, a first data line disposed on the substrate and extending across the non-transparent area and at least one of the plurality of transparent areas, and a first active layer disposed on the first metal pattern and superimposed on the first metal pattern.

[0009] Embodiments of the present disclosure can provide a display device that includes a display area on which an image is displayed, the display area includes an optical area including a general area and a plurality of transparent areas, the optical area further including a non-transparent area which is the outer boundary of the plurality of transparent areas, a first subpixel located on the substrate and positioned in the non-transparent area and including a first transistor, a second subpixel located on the substrate and positioned in the non-transparent area and including a second transistor, a first data line connected to the first subpixel and positioned across the non-transparent area and at least one of the plurality of transparent areas, a second data line connected to the second subpixel and positioned across the non-transparent area and at least one of the plurality of transparent areas, and a first metal pattern located in the non-transparent area, positioned below the first and second transistors, superimposed on at least a portion of both the first and second transistors, and having a line shape. [Effects of the Invention]

[0010] According to embodiments of this disclosure, the transmittance of the optical region can be improved through a display panel containing transparent metal.

[0011] According to embodiments of this disclosure, the transmittance of an opaque region can be improved through a display panel containing transparent metal.

[0012] According to embodiments of this disclosure, the transmittance of a transparent area can be improved through a display panel containing transparent metal.

[0013] According to embodiments of this disclosure, a display device that can operate at low power as the transmittance of the optical region is improved can be provided. [Brief explanation of the drawing]

[0014] [Figure 1a] This disclosure shows a display device according to an embodiment of this disclosure. [Figure 1b] This disclosure shows a display device according to an embodiment of this disclosure. [Figure 1c] This disclosure shows a display device according to an embodiment of this disclosure. [Figure 2] This is a system configuration diagram of a display device according to an embodiment of the present disclosure. [Figure 3] A display panel according to an embodiment of this disclosure is shown. [Figure 4] The signal lines arranged on the display panel according to an embodiment of this disclosure are shown. [Figure 5] In the display panel according to the embodiment of this disclosure, a general area, a first optical area, and a second optical area are shown. [Figure 6] Figure 5 shows a cross-sectional view of the AB region of the general area. [Figure 7] This figure shows the pixel array layer and the lower metal layer according to an embodiment of the present disclosure. [Figure 8] This is a plan view of several regions of an optical region where a metal pattern according to an embodiment of the present disclosure is arranged. [Figure 9] Figure 8 is a cross-sectional view of the CD region. [Figure 10] Figure 8 shows a cross-sectional view of the EF region. [Figure 11] Figure 8 is a cross-sectional view of the GH region. [Figure 12] This is a plan view of several regions of an optical region where a metal pattern according to an embodiment of the present disclosure is arranged. [Figure 13] Figure 12 is a cross-sectional view of the IJ region. [Figure 14] It is a cross-sectional view of the K-L region shown in FIG. 12. [Figure 15] It is a plan view of an optical region where a metal pattern according to an embodiment of the present disclosure is disposed. [Figure 16] It is a plan view of an optical region where a metal pattern according to an embodiment of the present disclosure is disposed. [Figure 17] It is a plan view of an optical region where a metal pattern according to an embodiment of the present disclosure is disposed.

Embodiments for Carrying Out the Invention

[0015] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to exemplary drawings. When adding reference numerals to the components of each drawing, for the same components, even if they are shown on other drawings, the same numerals can be attached as much as possible. In describing the present disclosure, when it is determined that a specific description of related known configurations or functions may obscure the gist of the present disclosure, the detailed description thereof will be omitted. When terms such as "including", "having", "consisting of", etc. mentioned in this specification are used, other parts may be added unless "only" is used. When a component is expressed in the singular, it can include the case where a plurality are included unless there is a particularly explicit description.

[0016] Also, when describing the components of the present disclosure, terms such as first, second, A, B, (a), (b), etc. can be used. These terms are only for distinguishing the components from other components, and the essence, order, sequence, number, etc. of the components are not limited by these terms.

[0017] In descriptions of the positional relationships of components, when it is stated that two or more components are “linked,” “joined,” or “connected,” it should be understood that while two or more components can be directly “linked,” “joined,” or “connected,” it is also possible for two or more components to be further “interposed” with other components before being “linked,” “joined,” or “connected.” Here, the other components may be included in one or more of the two or more components that are “linked,” “joined,” or “connected” to each other.

[0018] In descriptions of temporal relationships concerning constituent elements, operating methods, or manufacturing methods, when temporal order or sequential relationships are described using phrases such as "after," "following," "next," or "before," unless "immediately" or "directly" is used, this can include cases that are not continuous.

[0019] On the other hand, if numerical values ​​or corresponding information (e.g., levels) relating to components are mentioned, even without further explicit mention, these numerical values ​​or corresponding information may be interpreted as including a range of errors that can occur due to various factors (e.g., process factors, internal or external shocks, noise, etc.).

[0020] Various embodiments of this disclosure will be described in detail below with reference to the attached drawings.

[0021] Figures 1a, 1b, and 1c show a display device 100 according to an embodiment of the present disclosure.

[0022] Referring to Figures 1a, 1b, and 1c, the display device 100 according to the embodiment of the present disclosure may include a display panel 110 for displaying images and one or more optical electronic devices 11, 12.

[0023] The display panel 110 may include a display area DA on which an image is displayed and a non-display area NDA on which no image is displayed. Multiple subpixels and various signal lines for driving the multiple subpixels may be arranged in the display area DA. The non-display area NDA may be an area outside the display area DA. Various signal lines may be arranged in the non-display area NDA, and various drive circuits may be connected to the non-display area NDA. The non-display area NDA may be bent so that it is not visible from the front, or it may be covered by a case (not shown). The non-display area NDA is also called a bezel or bezel area.

[0024] The display device 100 according to the embodiments of this disclosure may include one or more electronic devices 11, 12 located below the display panel 110 (on the opposite side of the viewing surface). Here, one or more electronic devices 11, 12 may be provided separately from the display panel 110.

[0025] One or more optical electronic devices 11, 12 may be devices that receive light transmitted through the display panel 110 and perform predetermined operations using the received light.

[0026] For example, one or more optical electronic devices 11, 12 may include one or more imaging devices such as cameras (image sensors), proximity sensors, illuminance sensors, and so on. Here, for example, the sensing sensor may be an infrared sensor.

[0027] Light necessary for the operation of one or more electronic devices 11, 12 can enter the front (viewing surface) of the display panel 110, pass through the display panel 110, and be transmitted to one or more electronic devices 11, 12 located at the bottom of the display panel 110 (opposite the viewing surface). For example, the light necessary for the operation of one or more electronic devices 11, 12 and that passes through the display panel 110 may include one or more of the following: visible light, infrared rays, ultraviolet rays, etc.

[0028] Referring to Figures 1a, 1b, and 1c, in the display panel 110 according to an embodiment of the present disclosure, the display area DA may include a general area NA and one or more optical areas OA1, OA2. The one or more optical areas OA1, OA2 may be areas that overlap with one or more electronic devices 11, 12.

[0029] As illustrated in Figure 1a, the display area DA may include a general area NA and a first optical area OA1. Here, at least a portion of the first optical area OA1 can be superimposed on the first electronic device 11.

[0030] As illustrated in Figure 1b, the display area DA may include a general area NA, a first optical area OA1, and a second optical area OA2. In the example of Figure 1b, a general area NA may exist between the first optical area OA1 and the second optical area OA2. Here, at least a portion of the first optical area OA1 may overlap with the first electronic device 11, and at least a portion of the second optical area OA2 may overlap with the second electronic device 12.

[0031] As illustrated in Figure 1c, the display area DA may include a general area NA, a first optical area OA1, and a second optical area OA2. In the example in Figure 1c, there is no general area NA between the first optical area OA1 and the second optical area OA2. That is, the first optical area OA1 and the second optical area OA2 are in contact with each other. Here, at least a portion of the first optical area OA1 may overlap with the first electronic device 11, and at least a portion of the second optical area OA2 may overlap with the second electronic device 12.

[0032] One or more optical regions OA1, OA2 must have both an image display structure and a light transmission structure. That is, since one or more optical regions OA1, OA2 are part of the display region DA, one or more optical regions OA1, OA2 must have light-emitting regions for subpixels for image display. Furthermore, one or more optical regions OA1, OA2 must have a light transmission structure for transmitting light to one or more electronic devices 11, 12.

[0033] One or more electronic devices 11, 12 are located behind (below, opposite the viewing surface) the display panel 110 and receive light that has passed through the display panel 110.

[0034] One or more electronic devices 11, 12 are not exposed on the front (viewing surface) of the display panel 110. Therefore, when the user looks at the front of the display device 110, the electronic devices 11, 12 are not visible to the user.

[0035] For example, the first electronic device 11 may be a camera that receives light in the visible light wavelength range (visible light), and the second electronic device 12 may be a sensing sensor such as a proximity sensor or an illuminance sensor. For example, the sensing sensor may be an infrared sensor that senses light in the infrared wavelength range (infrared light). Conversely, the first electronic device 11 may be a sensing sensor, and the second electronic device 12 may be a camera.

[0036] For the sake of explanation, the following explanation will use the example that the first electronic device 11 is a camera and the second electronic device 12 is an infrared-based sensing sensor. Here, the camera may be a camera lens or an image sensor.

[0037] If the first electronic device 11 is a camera, this camera is located behind (below) the display panel 110, but it may also be a front camera that photographs the front of the display panel 110. Therefore, the user can take a picture (selfie) while looking at the viewing surface of the display panel 110, via a camera that is not visible on the viewing surface.

[0038] The general area NA and one or more optical areas OA1, OA2 included in the display area DA may be areas on which images can be displayed. However, the general area NA is an area that does not need to form a light-transmitting structure, while one or more optical areas OA1, OA2 may be areas on which a light-transmitting structure should be formed.

[0039] Therefore, one or more optical regions OA1, OA2 should have a transmittance above a certain level, while the general region NA may have no light transmittance or a low transmittance below a certain level.

[0040] For example, one or more optical regions OA1, OA2 and the general region NA may differ from each other in terms of resolution, subpixel arrangement structure, number of subpixels per unit area, electrode structure, line structure, electrode arrangement structure, or line arrangement structure.

[0041] For example, the number of subpixels per unit area in one or more optical regions OA1, OA2 may be smaller than the number of subpixels per unit area in the general region NA. That is, the resolution of one or more optical regions OA1, OA2 may be lower than the resolution of the general region NA. Here, the number of subpixels per unit area may be synonymous with resolution, pixel density, or pixel integration. For example, the unit of the number of subpixels per unit area may be PPI (Pixels Per Inch), which means the number of pixels in one inch.

[0042] For example, the number of subpixels per unit area in the first optical region OA1 may be less than the number of subpixels per unit area in the general region NA. The number of subpixels per unit area in the second optical region OA2 may be greater than or equal to the number of subpixels per unit area in the first optical region OA1, and less than the number of subpixels per unit area in the general region NA.

[0043] On the other hand, as one method for increasing the transmittance of at least one of the first optical region OA1 and the second optical region OA2, the pixel density difference design method can be applied as described above. According to the pixel density difference design method, the display panel 110 can be designed such that the number of subpixels per unit area of ​​at least one of the first optical region OA1 and the second optical region OA2 is less than the number of subpixels per unit area of ​​the general region NA.

[0044] However, in some cases, a different approach can be taken to increase the transmittance of at least one of the first optical region OA1 and the second optical region OA2, by applying a pixel size difference design method. According to the pixel size difference design method, the display panel 110 can be designed such that the number of subpixels per unit area of ​​at least one of the first optical region OA1 and the second optical region OA2 is the same as or similar to the number of subpixels per unit area of ​​the general region NA, but the size of each subpixel SP (i.e., the light-emitting region size) located in at least one of the first optical region OA1 and the second optical region OA2 is smaller than the size of each subpixel SP (i.e., the light-emitting region size) located in the general region NA.

[0045] In the following explanation, for the sake of clarity, we will assume that the pixel density difference design method, one of two methods (pixel density difference design method and pixel size difference design method) for increasing the transmittance of at least one of the first optical region OA1 and the second optical region OA2, is applied. Therefore, in the following, a small number of subpixels per unit area may correspond to a small subpixel size, and a large number of subpixels per unit area may correspond to a large subpixel size.

[0046] The first optical region OA1 can have various shapes, such as a circle, ellipse, square, hexagon, or octagon. The second optical region OA2 can have various shapes, such as a circle, ellipse, square, hexagon, or octagon. The first optical region OA1 and the second optical region OA2 may have the same shape or different shapes.

[0047] Referring to Figure 1c, when the first optical region OA1 and the second optical region OA2 are in contact, the entire optical region including the first optical region OA1 and the second optical region OA2 can have various shapes such as circular, elliptical, square, hexagonal, or octagonal. For the sake of explanation, we will assume that the first optical region OA1 and the second optical region OA2 are both circular.

[0048] In the display device 100 according to the embodiment of this disclosure, if the first electronic device 11, which is not exposed to the outside and is hidden at the bottom of the display panel 100, is a camera, then the display device 100 according to the embodiment of this disclosure can be said to be a display to which UDC (Under Display Camera) technology is applied.

[0049] According to this, in the case of the display device 100 according to the embodiment of the present disclosure, a notch or camera hole for camera exposure does not need to be formed in the display panel 110, so there is no reduction in the area of ​​the display area DA. As a result, a notch or camera hole for camera exposure does not need to be formed in the display panel 110, so the size of the bezel area can be reduced, eliminating design constraints and potentially increasing the degree of freedom in design.

[0050] In the display device 100 according to the embodiment of the present disclosure, one or more electronic devices 11, 12 are arranged hidden behind the display panel 110, yet one or more electronic devices 11, 12 can receive light normally and perform predetermined functions normally.

[0051] Furthermore, in the display device 100 according to the embodiment of this disclosure, even though one or more electronic devices 11, 12 are arranged hidden behind the display panel 110 and overlap with the display area DA, normal image display is possible in one or more optical areas OA1, OA2 that overlap with the one or more electronic devices 11, 12 within the display area DA.

[0052] Since the first optical region OA1 described above is designed to be a transparent region, the image display characteristics in the first optical region OA1 may differ from those in the general region NA.

[0053] Furthermore, if the design of the first optical region OA1 is modified to improve the image display characteristics, the transmittance of the first optical region OA1 may decrease.

[0054] Accordingly, embodiments of this disclosure present a structure for a first optical region OA1 that can prevent variations in image quality between the first optical region OA1 and the general region NA, and can improve transmittance in the first optical region OA1.

[0055] Furthermore, the embodiments of this disclosure present a structure for a second optical region OA2 that can improve image quality and transmittance in the second optical region OA2, not only for the first optical region OA1 but also for the second optical region OA2.

[0056] Furthermore, in the display device 100 according to the embodiment of this disclosure, the first optical region OA1 and the second optical region OA2 are similar in that they are light-transmitting regions, but their applications may differ.

[0057] Therefore, in the display device 100 according to the embodiment of the present disclosure, the structure of the first optical region OA1 and the structure of the second optical region OA2 are basically similar or identical, but the resolution, subpixel arrangement structure, number of subpixels per unit area, electrode structure, line structure, electrode arrangement structure, or line arrangement structure may differ from each other.

[0058] Figure 2 is a system configuration diagram of the display device 100 according to an embodiment of the present disclosure.

[0059] Referring to Figure 2, the display device 100 is a component for displaying images and may include a display panel 110 and a display driving circuit. The display driving circuit is a circuit for driving the display panel 110 and may include a data driving circuit 220, a gate driving circuit 230, and a display controller 240, etc.

[0060] The display panel 110 may include a display area DA on which an image is displayed and a non-display area NDA on which no image is displayed. The non-display area NDA may be the outer area of ​​the display area DA, or it may also be called the bezel area. All or part of the non-display area NDA may be an area visible from the front of the display device 100, or an area that is bent and not visible from the front of the display device 100.

[0061] The display panel 110 may include a substrate 210 and a plurality of subpixels SP arranged on the substrate 210. Furthermore, the display panel 110 may further include various types of signal lines for driving the plurality of subpixels SP.

[0062] The display device 100 according to the embodiments of this disclosure may be a liquid crystal display device or the like, or it may be a self-emissive display device in which the display panel 110 emits light itself. When the display device 100 according to the embodiments of this disclosure is a self-emissive display device, each of the plurality of subpixels SP may include an element-emitting element. For example, the display device 100 according to the embodiments of this disclosure may be an organic light-emitting display device in which the element-emitting element is realized by an organic light-emitting diode (OLED). As another example, the display device 100 according to the embodiments of this disclosure may be an inorganic light-emitting display device in which the element-emitting element is realized by an inorganic-based light-emitting diode. As yet another example, the display device 100 according to the embodiments of this disclosure may be a quantum dot display device in which the element-emitting element is realized by a quantum dot, which is a semiconductor crystal that emits light itself.

[0063] The structure of each of the multiple subpixels SP may vary depending on the type of display device 100. For example, if the display device 100 is a self-emissive display device that emits light from the subpixels SP itself, each subpixel SP may include a light-emitting element that emits light itself, one or more transistors, and one or more capacitors.

[0064] For example, some types of signal lines may include multiple data lines (DL) that transmit data signals (also called data voltages or video signals) and multiple gate lines GL that transmit gate signals (also called scan signals).

[0065] Multiple data lines DL and multiple gate lines GL can intersect each other. Each of the multiple data lines DL can be arranged extending in a first direction. Each of the multiple gate lines GL can be arranged extending in a second direction. Here, the first direction may be the column direction and the second direction may be the row direction. Alternatively, the first direction may be the row direction and the second direction may be the column direction. For the sake of explanation, the following example will assume that each of the multiple data lines DL is arranged in the column direction and each of the multiple gate lines GL is arranged in the row direction.

[0066] The data drive circuit 220 is a circuit for driving multiple data lines DL and can output data signals to multiple data lines DL. The gate drive circuit 230 is a circuit for driving multiple gate lines GL and can output gate signals to multiple gate lines GL.

[0067] The display controller 240 is a device for controlling the data drive circuit 220 and the gate drive circuit 230, and can control the drive timing for multiple data lines DL and the drive timing for multiple gate lines GL.

[0068] The display controller 240 can supply a data drive control signal DCS to the data drive circuit 220 to control the data drive circuit 220, and can supply a gate drive control signal GCS to the gate drive circuit 230 to control the gate drive circuit 230.

[0069] The display controller 240 can receive input video data from the host system 250 and supply video data (Data) to the data drive circuit 220 based on the input video data.

[0070] The data drive circuit 220 receives digital video data (Data) from the display controller 240, converts the received video data (Data) into analog data signals, and outputs them to multiple data lines DL.

[0071] The gate drive circuit 230 is supplied with various gate drive control signals GCS, a first gate voltage corresponding to the turn-on level voltage, and a second gate voltage corresponding to the turn-off level voltage, and generates a gate signal, which can then be supplied to multiple gate lines GL.

[0072] On the other hand, at least one of the data drive circuit 220 and gate drive circuit 230 may be placed in the display area DA of the display panel 110. For example, at least one of the data drive circuit 220 and gate drive circuit 230 may be placed so as not to overlap with the subpixel SP, or it may be placed so as to partially or completely overlap with the subpixel SP.

[0073] The data drive circuit 220 may be connected to one side of the display panel 110 (for example, the top or bottom). Depending on the drive method, panel design method, etc., the data drive circuit 220 may be connected to both sides of the display panel 110 (for example, the top and bottom), or to two or more of the four sides of the display panel 110.

[0074] The gate drive circuit 230 may be connected to one side of the display panel 110 (for example, the left or right side). Depending on the drive method, panel design method, etc., the gate drive circuit 230 may be connected to both sides of the display panel 110 (for example, the left and right sides), or to two or more of the four sides of the display panel 110.

[0075] The display controller 240 may be implemented as a separate component from the data drive circuit 220, or it may be integrated with the data drive circuit 220 and implemented as an integrated circuit.

[0076] The display controller 240 may be a timing controller used in conventional display technology, a control device that can also perform other control functions including timing control, a control device different from a timing controller, or a control device internal circuit.

[0077] The display controller 240 can be mounted on a printed circuit board, a flexible printed circuit board, etc., and can be electrically connected to the data drive circuit 220 and the gate drive circuit 230 via the printed circuit board, flexible printed circuit board, etc.

[0078] The display device 100 according to the embodiments of this disclosure may include, in addition to a video display function, a touch sensor and a touch sensing circuit that senses the touch sensor to detect whether a touch has occurred by a touch object such as a finger or pen, and to detect the touch position, in order to further provide a touch sensing function.

[0079] The touch sensing circuit may include a touch drive circuit 260 that drives and senses a touch sensor and generates and outputs touch sensing data, and a touch controller 270 that can use the touch sensing data to detect touch occurrences and determine the touch position.

[0080] The touch sensor may include multiple touch electrodes. The touch sensor may further include multiple touch lines for electrically connecting the multiple touch electrodes to the touch drive circuit 260.

[0081] The touch sensor may be located outside the display panel 110 in the form of a touch panel, or it may be located inside the display panel 110. When the touch sensor is located outside the display panel 110 in the form of a touch panel, the touch sensor is called an external type. When the touch sensor is an external type, the touch panel and the display panel 110 can be manufactured separately and joined together during the assembly process. An external type touch panel may include a touch panel substrate and multiple touch electrodes on the touch panel substrate.

[0082] If the touch sensor is located inside the display panel 110, the touch sensor may be formed on the substrate 210 during the manufacturing process of the display panel 110, along with signal lines and electrodes related to display driving.

[0083] The touch drive circuit 260 can supply a touch drive signal to at least one of the multiple touch electrodes, sense at least one of the multiple touch electrodes, and generate touch sensing data.

[0084] The touch sensing circuit can perform touch sensing using either a self-capacitance sensing method or a mutual-capacitance sensing method.

[0085] The touch driving circuit 260 and the touch controller 270 included in the touch sensing circuit may be implemented in separate devices or in a single device. Furthermore, the touch driving circuit 260 and the data driving circuit 220 may be implemented in separate devices or in a single device.

[0086] The display device 100 may further include a power supply circuit that supplies various power sources to the display driving circuit and / or touch sensing circuit.

[0087] As described above, the display area DA in the display panel 110 may include a general area NA and one or more optical areas OA1, OA2. The general area NA and one or more optical areas OA1, OA2 are areas on which video can be displayed. However, the general area NA is an area on which a light-transmitting structure does not need to be formed, while the one or more optical areas OA1, OA2 are areas on which a light-transmitting structure should be formed.

[0088] As mentioned above, in the display panel 110, the display area DA may include one or more optical areas OA1 and OA2 along with the general area NA. However, for the sake of explanation, we will assume that the display area DA includes both the first optical area OA1 and the second optical area OA2 (Figures 1b and 1c).

[0089] Figure 3 shows a display panel 110 according to an embodiment of the present disclosure.

[0090] Referring to Figure 3, the display area DA of the display panel 110 may contain multiple subpixels SP. These multiple subpixels SP may be located in the general area NA, the first optical area OA1, and the second optical area OA2, which are included in the display area DA.

[0091] Referring to Figure 3, each of the multiple subpixels SP may include a light-emitting element ED and a subpixel circuit SPC configured to drive the light-emitting element ED.

[0092] Referring to Figure 3, the subpixel circuit SPC may include a drive transistor DT for driving the light-emitting element ED, a scan transistor ST for transmitting a data voltage Vdata to the drive transistor DT, and a storage capacitor Cst for maintaining a constant voltage for one frame.

[0093] The drive transistor DT may include a first node N1, a second node N2, and a third node N3.

[0094] The first node N1 can be electrically connected to the light-emitting element ED. The second node N2 may be connected to the scan transistor ST. The third node N3 can be connected to the drive voltage line VDDL.

[0095] The first node N1 may be electrically connected to the pixel electrode PE of the light-emitting element ED. A data voltage VDATA can be applied to the second node N2. A drive voltage VDD can be applied to the third node N3.

[0096] The first node N1 is either a source node or a drain node, the second node N2 is a gate node, and the third node N3 can be either a drain node or a source node. For the sake of explanation, the following example will be given where, in a drive transistor DT, the first node N1 is a source node, the second node N2 is a gate node, and the third node N3 is a drain node.

[0097] The light-emitting element ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE.

[0098] The pixel electrode PE may be an electrode placed on each subpixel SP. For example, the pixel electrode PE can be electrically connected directly or indirectly (via another transistor) to the first node N1 of the driving transistor DT of each subpixel SP.

[0099] The common electrode CE may be an electrode commonly placed across multiple subpixels SP. For example, the common electrode CE can be electrically connected to a base voltage line VSSL. A base voltage VSS, which is a type of common drive voltage, can be applied to the common electrode CE via the base voltage line VSSL.

[0100] For example, the pixel electrode PE could be the anode electrode and the common electrode CE could be the cathode electrode. Conversely, the pixel electrode PE could be the cathode electrode and the common electrode CE could be the anode electrode. For the sake of explanation, we will assume below that the pixel electrode PE is the anode electrode and the common electrode CE is the cathode electrode.

[0101] The intermediate layer EL may include the light-emitting layer EML and the common intermediate layer EL_COM.

[0102] The light-emitting layer (EML) may, for example, be placed in each of several subpixels (SP), or, for example, be placed in common across several subpixels (SP). The common intermediate layer (EL_COM) can be placed in common across several subpixels (SP).

[0103] The emissive layer EML can be placed in each emissive region EA, and the common intermediate layer EL_COM can be placed in common across multiple emissive regions EA and non-emissive regions.

[0104] The common intermediate layer EL_COM may include a first common intermediate layer COM1 and a second common intermediate layer COM2. The first common intermediate layer COM1 is located between the pixel electrode PE and the light-emitting layer EML and may include at least one layer (e.g., an organic layer). The second common intermediate layer COM2 is located between the light-emitting layer EML and the common electrode CE and may include at least one layer (e.g., an organic layer).

[0105] For example, the first common intermediate layer COM1 may include a hole injection layer (HIL) and a hole transfer layer (HTL). The second common intermediate layer COM2 may include an electron transfer layer (ETL) and an electron injection layer (EIL).

[0106] The hole injection layer injects holes from the pixel electrode PE into the hole transport layer, the hole transport layer transports the holes to the light-emitting layer EML, and the electron injection layer injects electrons into the electron transport layer using the common electrode CE, and the electron transport layer transports the electrons to the light-emitting layer EML.

[0107] Each light-emitting element ED can be composed of the overlapping portion of the pixel electrode PE, the light-emitting layer EML within the intermediate layer EL, and the common electrode CE. Each light-emitting element ED can form a predetermined light-emitting region EA. For example, the light-emitting region EA can be defined as the region where the pixel electrode PE, the light-emitting layer EML of the intermediate layer EL, and the common electrode CE overlap.

[0108] For example, the light-emitting element ED may be an organic-based organic light-emitting diode (OLED), an inorganic-based inorganic light-emitting diode, or a quantum dot light-emitting element. If the light-emitting element ED is an organic light-emitting diode, the light-emitting layer EL in the light-emitting element ED may include an organic layer containing organic material.

[0109] The scan transistor SCT is controlled on / off by a scan signal SC, which is a type of gate signal applied via a scan signal line GL, which is a type of gate line GL, and can be electrically connected between the second node N2 of the drive transistor DT and the data line DL.

[0110] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the drive transistor DT.

[0111] The subpixel circuit SPC may have a 2T (Transistor) 1C (Capacitor) structure including two transistors DT and ST and one capacitor Cst, as shown in Figure 3, and may optionally include one or more transistors or one or more capacitors.

[0112] The storage capacitor Cst may be an intentionally designed external capacitor located outside the drive transistor DT, rather than a parasitic capacitor that may exist between the first node N1 and the second node N2 of the drive transistor DT. Both the drive transistor DT and the scan transistor ST may be either n-type or p-type transistors.

[0113] Since the circuit elements within each subpixel SP (especially the light-emitting elements ED, which are realized using organic light-emitting diodes (OLEDs) containing organic materials) are vulnerable to external moisture and oxygen, a sealing layer 310 can be placed on the display panel 110 to prevent external moisture and oxygen from penetrating the circuit elements (especially the light-emitting elements ED). The sealing layer 310 can be placed so as to cover the light-emitting elements ED.

[0114] Referring to Figure 3, the display device 100 according to the embodiment of the present disclosure may include a touch sensor layer 320 including a plurality of sensor electrodes for sensing a user's touch, a touch driving circuit 260 configured to sense the plurality of sensor electrodes, and a touch controller 270 configured to determine whether a touch is present or the touch coordinates using the sensing results (touch sensing data) of the touch driving circuit 260.

[0115] The touch sensor layer 320 may be embedded within the display panel 110. For example, the touch sensor layer 320 can be placed on the sealing layer 310 within the display panel 110.

[0116] The display panel 110 may further include a plurality of touchpads TP to which the touch driving circuit 260 is electrically connected, and a plurality of touch routing wires for electrically connecting a plurality of sensor electrodes included in the touch sensor layer 320 to the plurality of touchpads TP to which the touch driving circuit 260 is connected.

[0117] Figure 4 shows the signal line SL arranged on the display panel 110 according to an embodiment of the present disclosure.

[0118] Referring to Figure 4, the display panel 110 according to an embodiment of the present disclosure may include a plurality of subpixels SP and a plurality of signal lines 410, 450 for driving the plurality of subpixels SP.

[0119] Referring to Figure 4, each of the multiple subpixels SP may include a light-emitting element ED and a subpixel circuit SPC for driving it. The light-emitting element ED can form a light-emitting region EA.

[0120] Referring to Figure 4, the multiple signal lines 410 and 450 can supply various drive signals necessary to drive the multiple subpixels SP to the multiple subpixels SP.

[0121] For example, the various drive signals may include a data signal Vdata for driving the data line DL and a scan signal SC for driving the gate line GL. The various drive signals may further include a drive voltage for driving the drive voltage line and a base voltage for driving the common base voltage line.

[0122] Therefore, the multiple signal lines may include multiple data lines DL for supplying data signals Vdata and multiple gate lines GL for supplying gate signals such as scan signals SC. The multiple signal lines may further include drive voltage lines and base voltage lines.

[0123] Referring to Figure 4, the display area DA may include a general area NA, a first optical area OA1, and a second optical area OA2.

[0124] Referring to Figure 4, each of the general region NA, the first optical region OA1, and the second optical region OA2 may contain multiple light-emitting regions EA. Each of the general region NA, the first optical region OA1, and the second optical region OA2 may have multiple light-emitting elements ED and multiple subpixel circuits SPC arranged within them.

[0125] Referring to Figure 4, the multiple signal lines 410, 450 may include multiple general signal lines 450 and multiple specific signal lines 410.

[0126] Multiple general signal lines 450 may be signal lines that are located only in the general region NA without passing through the first optical region OA1 and the second optical region OA2.

[0127] The multiple specific signal lines 410 may be signal lines that pass through at least one of the first optical region OA1 and the second optical region OA2.

[0128] For example, the multiple general signal lines 450 may include multiple data lines 470 and multiple gate lines 460 that do not pass through the first optical region OA1 and the second optical region OA2.

[0129] For example, a plurality of specific signal lines 410 may include a plurality of data lines 430, 440 passing through at least one of the first optical region OA1 and the second optical region OA2, and a plurality of gate lines 420.

[0130] Figure 5 shows a display panel 110 according to an embodiment of the present disclosure, including a general area NA, a first optical area OA1, and a second optical area OA2.

[0131] Referring to Figure 5, the display panel 110 according to the embodiment of the present disclosure may include a display area DA on which an image is displayed and a non-display area NDA on which an image is not displayed. The display area DA may include a first optical area OA1, a second optical area OA2, and a general area NA.

[0132] The first optical region OA1, the second optical region OA2, and the general region NA are included in the display region DA and can therefore have a display structure. For example, the first optical region OA1, the second optical region OA2, and the general region NA can each contain multiple light-emitting regions.

[0133] Furthermore, the first optical region OA1 and the second optical region OA2 are regions through which light can be transmitted, while the general region NA may be a region through which light cannot be transmitted or through which light can be transmitted to a very small extent. The general region NA can mean the region through which light cannot be transmitted, excluding the first optical region OA1 and the second optical region OA2. Here, light transmission may mean that light passes between the front and back surfaces of the display panel 110.

[0134] The first optical region OA1 may overlap with the first electronic device 11. The second optical region OA2 may overlap with the second electronic device 12.

[0135] The first optical region OA1 and the second optical region OA2 may each have a light-transmitting structure. However, the first optical region OA1 and the second optical region OA2 may have different structural characteristics. For example, the transmittance of the first optical region OA1 may be higher than that of the second optical region OA2. The resolution or the number of subpixels per unit area of ​​the first optical region OA1 may be less than that of the second optical region OA2.

[0136] The first electronic device 11 can perform a predetermined operation using light in a first wavelength band from among the light transmitted through the first optical region OA1. The second electronic device 12 can perform a predetermined operation using light in a second wavelength band different from the first wavelength band from among the light transmitted through the second optical region OA2.

[0137] The first wavelength band may include one or more of the visible light wavelength band, the infrared wavelength band, and the ultraviolet wavelength band. The second wavelength band may include one or more of the visible light wavelength band, the infrared wavelength band, and the ultraviolet wavelength band, but may be different from the first wavelength band.

[0138] For example, the first electronic device 11 may be a camera, and the second electronic device 12 may be a sensing sensor. The first electronic device 11 can perform camera operations using light in the visible light wavelength band corresponding to a first wavelength band among the light transmitted through the first optical region OA1. The second electronic device 12 can perform sensing operations using light in the infrared wavelength band corresponding to a second wavelength band among the light transmitted through the second optical region OA2.

[0139] Referring to Figure 5, the first optical region OA1 and the second optical region OA2 may each be circular or octagonal, etc. However, they are not limited to these, and the first optical region OA1 and the second optical region OA2 may each have various shapes such as elliptical, polygonal, or irregular shapes.

[0140] The first optical region OA1 and the second optical region OA2 may have the same shape. Alternatively, the first optical region OA1 and the second optical region OA2 may have different shapes.

[0141] Referring to Figure 5, the display area DA can include multiple light-emitting areas EA. Since the general area NA, the first optical area OA1, and the second optical area OA2 are areas included in the display area DA, the general area NA, the first optical area OA1, and the second optical area OA2 can each include multiple light-emitting areas EA.

[0142] Multiple light-emitting regions EA may include light-emitting regions that emit three or more colors of light. For example, multiple light-emitting regions EA may include a first-color light-emitting region that emits a first color of light, a second-color light-emitting region that emits a second color of light, and a third-color light-emitting region that emits a third color of light.

[0143] For example, if the first color of light is red, the second color of light is green, and the third color of light is blue, the first color light emission region is sometimes called the red light emission region EA_R, the second color light emission region is sometimes called the green light emission region EA_G, and the third color light emission region is sometimes called the blue light emission region EA_B.

[0144] The red light-emitting region EA_R, the green light-emitting region EA_G, and the blue light-emitting region EA_B may have the same size (light-emitting area size). Alternatively, at least one of the red light-emitting region EA_R, the green light-emitting region EA_G, and the blue light-emitting region EA_B may have a different size (light-emitting area size) from the rest.

[0145] As mentioned above, the first, second, and third colors may be various different colors, for example, the first, second, and third colors may include red, green, and blue. For the sake of explanation, the following example will use the case where the first color is red, the second color is green, and the third color is blue. However, it is not limited to this.

[0146] If the first color is red, the second color is green, and the third color is blue, then the size of the blue emission region EA_B (luminescence area size) may be the largest among the sizes of the red emission region EA_R, the green emission region EA_G, and the blue emission region EA_B (luminescence area size).

[0147] A light-emitting element ED located in the red light-emitting region EA_R may include a light-emitting layer EML that emits red light. A light-emitting element ED located in the green light-emitting region EA_G may include a light-emitting layer EML that emits green light. A light-emitting element ED located in the blue light-emitting region EA_B may include a light-emitting layer EML that emits blue light.

[0148] Of the light-emitting layers (EML) that emit red light, green light, and blue light, the organic material contained in the blue light-emitting layer (EML) is sometimes the most susceptible to material degradation. As a result, designing the blue light-emitting region (EA_B) to be the largest may result in the lowest current density supplied to the light-emitting element (ED) located in the blue light-emitting region (EA_B). Consequently, the degree of degradation of the light-emitting element (ED) located in the blue light-emitting region (EA_B) may be similar to that of the light-emitting element (ED) located in the red light-emitting region (EA_R) and the light-emitting element (ED) located in the green light-emitting region (EA_G).

[0149] Therefore, variations in degradation between the light-emitting elements ED located in the red light-emitting region EA_R, the green light-emitting region EA_G, and the blue light-emitting region EA_B are eliminated or reduced, thereby improving image quality.

[0150] Referring to Figure 5, each of the multiple first transmission regions TA1 contained in the first optical region OA1 can have various shapes, such as circular, elliptical, polygonal, or irregular. Each of the multiple second transmission regions TA2 contained in the second optical region OA2 can have various shapes, such as circular, elliptical, polygonal, or irregular.

[0151] The transparent regions TA1 and TA2 may have relatively higher transmittance than the non-transparent region NTA. For this reason, the common electrode CE corresponding to the transparent regions TA1 and TA2 can be removed by etching. Furthermore, the metal for the transistor shown in Figure 3 does not need to be placed in the transparent regions TA1 and TA2. Therefore, the transparent regions TA1 and TA2 may be regions from which the common electrode CE has been etched away, and may be the same as, for example, the transparent regions TA1 and TA2 and the non-transparent region NTA shown in Figure 5. Also, the transparent regions TA1 and TA2 may be regions from which no metal for the transistor is placed, and may be the same as, for example, the transparent region TA and the non-transparent region NTA shown in Figure 7.

[0152] Multiple first transparent regions TA1 may have the same shape. In contrast, some of the multiple first transparent regions TA1 may have a different shape from the rest. Multiple second transparent regions TA2 may have the same shape. Alternatively, some of the multiple second transparent regions TA2 may have a different shape from the rest.

[0153] The first transparent region TA1 and the second transparent region TA2 can have the same shape. Alternatively, the first transparent region TA1 and the second transparent region TA2 can have different shapes.

[0154] Referring to Figure 5, all general regions NA can correspond to opaque regions. That is, a general region NA can include opaque regions NTA that contain multiple luminescent regions EA. In other words, the entire general region NA can be an opaque region NTA, and a general region NA does not necessarily have to include a transmissive region TA.

[0155] The first optical region OA1 may further include a non-transmitting region NTA containing a plurality of light-emitting regions EA, and a plurality of first transmitting regions TA1. The non-transmitting regions NTA included in the first optical region OA1 may be regions through which no light is transmitted at all, or they may be regions through which light is transmitted with a lower transmittance than that of the first transmitting regions TA1.

[0156] The second optical region OA2 may further include a non-transmitting region NTA containing a plurality of light-emitting regions EA, and a plurality of second transmitting regions TA2. The non-transmitting regions NTA included in the second optical region OA2 may be regions through which no light is transmitted at all, or they may be regions through which light is transmitted with a lower transmittance than that of the second transmitting regions TA2.

[0157] On the other hand, the common electrode CE may include a plurality of common electrode holes CH1, CH2 corresponding to a plurality of openings. The plurality of common electrode holes CH1, CH2 may be formed in the first optical region OA1 and the second optical region OA2. That is, the positions in which the plurality of common electrode holes CH1, CH2 are formed may be in the first optical region OA1 and the second optical region OA2.

[0158] Referring to Figure 5, in the common electrode CE, the positions where multiple common electrode holes CH1 and CH2 are formed can correspond to multiple first transmission regions TA1 included in the first optical region OA1. Furthermore, the positions where multiple common electrode holes CH1 and CH2 are formed in the common electrode CE can correspond to multiple second transmission regions TA2 included in the second optical region OA2. This makes it possible to improve the transmittance of both the first optical region OA1 and the second optical region OA2.

[0159] Referring to Figure 5, the AB region is shown within the general region NA. The following describes the cross-sectional view of the AB region.

[0160] Figure 6 is a cross-sectional view of the AB region of the general region NA shown in Figure 5.

[0161] Referring to Figure 6, the display panel 110 according to the embodiment of the present disclosure may include a transistor section, a light-emitting section, and a sealing section, but the embodiment of the present disclosure is not limited thereto.

[0162] The substrate 210 may be single-layer or multilayer. If the substrate 210 is multilayer, it may include a first substrate 601, an intermediate layer 602, and a second substrate 603. The intermediate layer 602 may be located between the first substrate 601 and the second substrate 603. For example, each of the first substrate 601 and the second substrate 603 may be a polyimide (PI) layer, but embodiments of the present disclosure are not limited thereto. The intermediate layer 602 may also be an inorganic insulating layer, but embodiments of the present disclosure are not limited thereto. The intermediate layer 602 can block the charge from affecting a transistor located on the second substrate 603 via the polyimide layer of the second substrate 603 when the first substrate 601, which is a polyimide layer, is charged.

[0163] Furthermore, the intermediate layer 602 can block moisture components from penetrating the first substrate 601 and permeating to the top. For example, the intermediate layer 602 may consist of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), or it may be formed from a bilayer of silicon dioxide (SiO2) and silicon nitride (SiNx), but is not limited to these.

[0164] The transistor section may include a substrate 210, insulating layers 610, 611, 612, 613, 614, 615, and 616 on the substrate 210, thin-film transistors TFT1 and TFT2, a storage capacitor Cst, and various electrodes or signal wiring.

[0165] The thin-film transistors TFT1 and TFT2 included in the transistor section may include a first thin-film transistor TFT1 and a second thin-film transistor TFT2.

[0166] The first thin-film transistor TFT1 may include a first active layer ACT1, a first electrode E1a, a second electrode E1b, and a third electrode E1c. The first active layer ACT1 may be a first semiconductor layer, and embodiments of the disclosure are not limited thereto. For example, the first active layer ACT1 may be composed of an oxide semiconductor, amorphous silicon, polysilicon, or low-temperature polysilicon (LTPS), but embodiments of the disclosure are not limited thereto. The first thin-film transistor TFT1 may be implemented as a p-channel transistor or an n-channel transistor, but embodiments of the disclosure are not limited thereto.

[0167] The first electrode E1a is a gate electrode, the second electrode E1b is a source electrode or drain electrode, and the third electrode E1c may be a drain electrode or source electrode. For the sake of explanation, the first electrode E1a may be the first gate electrode E1a, the second electrode E1b may be the first source electrode E1b, and the third electrode E1c may be the first drain electrode E1c. However, embodiments of the present disclosure are not limited thereto.

[0168] The second thin-film transistor TFT2 may include a second active layer ACT2, a fourth electrode E2a, a fifth electrode E2b, and a sixth electrode E2c. The second active layer ACT2 may be a second semiconductor layer, and embodiments of the disclosure are not limited thereto. For example, the second active layer ACT2 may be composed of an oxide semiconductor, amorphous silicon, polysilicon, or low-temperature polysilicon (LTPS), but embodiments of the disclosure are not limited thereto. The second thin-film transistor TFT2 may be implemented as a p-channel transistor or an n-channel transistor, but embodiments of the disclosure are not limited thereto.

[0169] For example, one of the first thin-film transistor TFT1 and the second thin-film transistor TFT2 can be configured with an oxide semiconductor as the active layer. In another example, one of the first thin-film transistor TFT1 and the second thin-film transistor TFT2 can be configured with low-temperature polysilicon as the active layer. In yet another example, the first thin-film transistor TFT1 and the second thin-film transistor TFT2 can be configured with an oxide semiconductor as the active layer. In yet another example, the first thin-film transistor TFT1 and the second thin-film transistor TFT2 can be configured with low-temperature polysilicon as the active layer. In yet another example, among the first thin-film transistor TFT1 and the second thin-film transistor TFT2, the driving transistor DT can be configured with an oxide semiconductor as the active layer, and the scanning transistor ST can be configured with low-temperature polysilicon as the active layer. In yet another example, among the first thin-film transistor TFT1 and the second thin-film transistor TFT2, the driving transistor DT can be configured with low-temperature polysilicon as the active layer, and the scanning transistor ST can be configured with an oxide semiconductor as the active layer. In yet another example, the transistors included in the gate-in-panel (GIP) type gate drive circuit 140 can be configured with an oxide semiconductor or low-temperature polysilicon as the active layer. In yet another example, all transistors configured on the substrate 210 and the transistors included in the gate-in-panel (GIP) type gate drive circuit 130 can be configured with an oxide semiconductor as the active layer.

[0170] The fourth electrode E2a is a gate electrode, the fifth electrode E2b is a source electrode or drain electrode, and the sixth electrode E2c may be a drain electrode or source electrode. For the sake of explanation, the fourth electrode E2a may be the second gate electrode E2a, the fifth electrode E2b may be the second source electrode E2b, and the sixth electrode E2c may be the second drain electrode E2c. However, embodiments of the present disclosure are not limited thereto.

[0171] The second active layer ACT2 of the second thin-film transistor TFT2 may be positioned higher from the substrate 210 than the first active layer ACT1 of the first thin-film transistor TFT1.

[0172] A first buffer layer 611 may be placed beneath the first active layer ACT1 of the first thin-film transistor TFT1, and a second buffer layer 614 may be placed beneath the second active layer ACT2 of the second thin-film transistor TFT2. For example, the first active layer ACT1 of the first thin-film transistor TFT1 may be located on the first buffer layer 611, and the second active layer ACT2 of the second thin-film transistor TFT2 may be located on the second buffer layer 614. The second buffer layer 614 may be placed higher than the first buffer layer 611.

[0173] The storage capacitor Cst can be placed within various metal layers in the display panel 110. For example, the storage capacitor Cst may include a first capacitor electrode CAPE1 and a second capacitor CAPE2.

[0174] The optical element portion may include a plurality of light-emitting elements ED arranged on at least one planarization layer 621, 622, 623. Each of the plurality of light-emitting elements ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE.

[0175] The capping layer 640 can be placed on the common electrode CE. The capping layer 640 can further enhance the luminous efficiency of the display panel 110 by utilizing the microcavity effect.

[0176] The sealing portion may include sealing layers 310 on a plurality of light-emitting elements ED. The sealing layers 310 may be single-layer or multi-layer, but embodiments of this disclosure are not limited thereto.

[0177] The structure or vertical structure of the display panel 110 according to the embodiments of this disclosure will be described in more detail below with reference to Figure 6.

[0178] Referring to Figure 6, the second buffer layer 611 can be placed on the substrate 210. The first buffer layer 611 may be single-layer or multi-layer, but embodiments of this disclosure are not limited thereto. If the first buffer layer 611 is multi-layer, it may include an upper buffer layer 611a and a lower buffer layer 611b.

[0179] The first active layer ACT1 of the first thin-film transistor TFT1 may be located on the first buffer layer 611. The first active layer ACT1 may include a channel region where a channel is formed, a source connection region on one side of the channel region, and a drain connection region on the other side of the channel region.

[0180] The first insulating layer 612 can be placed on the first active layer ACT1 of the first thin-film transistor TFT1. The first gate electrode E1a of the first thin-film transistor TFT1 can be placed on the first insulating layer 612. The second insulating layer 613 may be placed on the first gate electrode E1a of the first thin-film transistor TFT1. The first insulating layer 612 may be a gate insulating layer, but embodiments of the present disclosure are not limited thereto. The second insulating layer 613 may be an interlayer insulating layer, but embodiments of the present disclosure are not limited thereto.

[0181] A second buffer layer 614 can be placed on the second insulating layer 613.

[0182] The second active layer ACT2 of the second thin-film transistor TFT2 can be placed on the second buffer layer 614. The second active layer ACT2 may include a channel region where a channel is formed, a source connection region on one side of the channel region, and a drain connection region on the other side of the channel region.

[0183] The third insulating film 615 may be located on the second active layer ACT2 of the second thin-film transistor TFT2. The second gate electrode E2a of the second thin-film transistor TFT2 may be located on the fourth insulating layer 616. The fourth insulating layer 616 may be located on the second gate electrode E2a of the second thin-film transistor TFT2. The third insulating layer 615 may be a gate insulating layer, but embodiments of the present disclosure are not limited thereto. The fourth insulating layer 616 may be an interlayer insulating layer, but embodiments of the present disclosure are not limited thereto.

[0184] The first source electrode E1b and first drain electrode E1c of the first thin-film transistor TFT1, and the second source electrode E2b and second drain electrode E2c of the second thin-film transistor TFT2 may be arranged on the fourth insulating layer 616.

[0185] The first source electrode E1b and the first drain electrode E1c of the first thin-film transistor TFT1 can be connected to the source connection region and drain connection region of the first active layer ACT1, respectively, through holes in the fourth insulating layer 616, the third insulating layer 615, the second buffer layer 614, the second insulating layer 613, and the first insulating layer 612.

[0186] The second source electrode E2b and the second drain electrode E2c of the second thin-film transistor TFT2 may be connected to the source connection region and the drain connection region of the second active layer ACT2, respectively, through holes in the fourth insulating layer 616 and the third insulating layer 615.

[0187] The first source electrode E1b and first drain electrode E1c of the first thin-film transistor TFT1, and the second source electrode E2b and second drain electrode E2c of the second thin-film transistor TFT2, may include a first metal and be disposed within a first metal layer. Here, the first metal and the first metal layer are sometimes referred to as the first source-drain metal and the first source-drain metal layer.

[0188] Referring to Figure 6, as an example, the storage capacitor Cst can be formed by a first capacitor electrode CAPE1 and a second capacitor electrode CAPE2. In some cases, the storage capacitor Cst may be formed by three or more capacitor electrodes, or by two or more capacitors connected in parallel.

[0189] The first capacitor electrode CAPE1 and the second capacitor electrode CAPE2 may each be placed on various metal layers arranged within the display panel 110.

[0190] For example, the first capacitor electrode CAPE1 may include the same first gate metal as the first gate electrode E1a of the first thin-film transistor TFT1 on the first insulating layer 612 and be located within the first gate metal layer, but embodiments of the present disclosure are not limited thereto.

[0191] For example, a second capacitor electrode CAPE2 can be placed on the second insulating layer 613.

[0192] The second source electrode E2b of the second thin-film transistor TFT2 may be electrically connected to the second capacitor electrode CAPE2 through holes in the fourth insulating layer 616, the third insulating layer 615, and the second buffer layer 614.

[0193] For example, the first thin-film transistor TFT1 may be the scan transistor ST in Figure 2, and the second thin-film transistor TFT2 may be the drive transistor DT in Figure 2.

[0194] Referring to Figure 6, the transistor section may further include a first shielding metal 651 disposed on the substrate 210. The first shielding metal 651 may be superimposed on the first active layer ACT1 of the first thin-film transistor TFT1. The first shielding metal 651 may be placed beneath the first active layer ACT1 of the first thin-film transistor TFT1. For example, the first shielding metal 651 may be placed between the substrate 210 and the first buffer layer 611, or between the upper buffer layer 611a and the lower buffer layer 611b.

[0195] The transistor section may further include a second shielding metal 652 disposed on the substrate 210. The second shielding metal 652 may be superimposed on the second active layer ACT2 of the second thin-film transistor TFT2. The second shielding metal 652 may be placed beneath the second active layer ACT2 of the second thin-film transistor TFT2.

[0196] For example, the second shielding metal 652 may be located within the metal layer between the second insulating layer 613 and the second buffer layer 614. The second shielding metal 652 may be located within the same metal layer as the second capacitor CAPE2, but embodiments of the present disclosure are not limited thereto.

[0197] As another example, the second shield metal 652 may be located within the same first gate metal layer as the first gate electrode E1a of the first thin-film transistor TFT1.

[0198] At least one planarization layer can be placed on the first thin-film transistor TFT1 and the second thin-film transistor TFT2. An example in Figure 6 shows a case where three planarization layers 621, 622, and 623 are placed on the first thin-film transistor TFT1 and the second thin-film transistor TFT2. In some cases, two planarization layers may be placed on the first thin-film transistor TFT1 and the second thin-film transistor TFT2, but embodiments of this disclosure are not limited thereto.

[0199] Referring to Figure 6, the first planarization layer 621 can be placed on the first source electrode E1b and first drain electrode E1c of the first thin-film transistor TFT1, and on the second source electrode E2b and second drain electrode E2c of the second thin-film transistor TFT2. For example, the first planarization layer 621 may be placed on both the first thin-film transistor TFT1 and the second thin-film transistor TFT2. For example, the first planarization layer 621 can be placed so as to cover both the first thin-film transistor TFT1 and the second thin-film transistor TFT2.

[0200] Referring to Figure 6, the relay electrode RE can be placed on the first planarization layer 621. The relay electrode RE can electrically connect the second source electrode E2b and the pixel electrode PE of the second thin-film transistor TFT2.

[0201] The relay electrode RE can be electrically connected to the second source electrode E2b of the second thin-film transistor TFT2 via a hole in the first planarization layer 621. The second source electrode E2b of the second thin-film transistor TFT2 may be electrically connected to the second capacitor electrode CAPE2 of the storage capacitor Cst.

[0202] The relay electrode RE can be placed within a second metal layer on the first planarization layer 621 and may include a second metal. The second metal and the second metal layer may be referred to as the second source-drain metal and the second source-drain metal layer.

[0203] The second planarization layer 622 may be placed on the first planarization layer 621. The second planarization layer 622 can be placed on the relay electrode RE.

[0204] Referring to Figure 6, the light-emitting element can be placed on the second planarization layer 622. The light-emitting element ED can be formed on the second planarization layer 622. The light-emitting element ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE. The light-emitting region of the light-emitting element ED can be formed in the region where the pixel electrode PE, the intermediate layer EL, and the common electrode CE are superimposed and in contact.

[0205] The pixel electrode PE can be placed on the second planarization layer 622. The pixel electrode PE can be electrically connected to the relay electrode RE through holes in the second planarization layer 622.

[0206] Bank 631 can be placed on the second planarization layer 622. The opening of bank 631 can expose a portion of the pixel electrode PE to form a light-emitting region. For example, the opening of bank 631 may overlap a portion of the pixel electrode PE. Bank 631 can be made of a material containing a black pigment, or an organic material such as benzocyclobutene resin, polyimide resin, acrylic resin, or photosensitive polymer, but embodiments of this disclosure are not limited thereto.

[0207] The spacer 632 can be placed on the bank 631. The spacer 632 can prevent damage to the micrometal mask used in the process by contact. The spacer 632 may be made of a material containing a black pigment, or an organic material such as benzocyclobutene resin, polyimide resin, acrylic resin, or photosensitive polymer, but embodiments of the present disclosure are not limited thereto.

[0208] The intermediate layer EL of the light-emitting element ED can be placed on a portion of the pixel electrode PE and on the spacer 632. The common electrode CE can be placed on the intermediate layer EL.

[0209] Referring to Figure 6, the sealing portion can be arranged on the light-emitting portion and located on the common electrode CE. The sealing portion may include a sealing layer 310 formed on the common electrode CE.

[0210] The sealing layer 310 can prevent moisture and oxygen from penetrating the light-emitting element ED. For example, the sealing layer 310 can prevent moisture and oxygen from penetrating the organic matter contained in the intermediate layer EL of the light-emitting element ED. The sealing layer 310 may be composed of a single layer or a multilayer, but the embodiments of this disclosure are not limited thereto.

[0211] Referring to Figure 6, for example, the sealing layer 310 may include a first inorganic sealing layer 311, a first organic sealing layer 312, and a second inorganic sealing layer 313, but embodiments of the present disclosure are not limited thereto. For example, the first inorganic sealing layer 311 and the second inorganic sealing layer 313 may include inorganic layers, and the first organic sealing layer 312 may include organic layers, but embodiments of the present disclosure are not limited thereto.

[0212] The display panel 110 according to the embodiments of this disclosure may incorporate a touch sensor. In this case, the display panel 110 according to the embodiments of this disclosure may include a touch sensor layer 320 formed on the sealing layer 310. The touch sensor layer 320 may be a touch portion.

[0213] Referring to Figure 6, the touch sensor layer 320 may include a plurality of touch electrodes TE, and may include a first touch metal TM1 and a second touch metal TM2 to form the plurality of touch electrodes TE. In embodiments of this disclosure, the layer on which the second touch metal TM2 is located may be called the sensor metal layer, and the layer on which the first touch metal TM1 is located may be called the bridge metal layer.

[0214] The touch sensor layer 320 may further include insulating layers such as a touch buffer layer 321 on the sealing layer 310 and an inter-touch layer insulating layer 322 on the touch buffer layer 321. Here, the touch buffer layer 321 may be omitted.

[0215] The first touch metal TM1 may be placed between the touch buffer layer 321 and the intertouch insulating layer 322. The second touch metal TM2 may be placed between the intertouch insulating layer 322 and the protective layer 653.

[0216] Each of the multiple touch electrodes TE may be composed of a second touch metal TM2. Each of the multiple touch electrodes TE may be a mesh-type electrode having multiple openings, but embodiments of the present disclosure are not limited thereto.

[0217] Multiple touch electrodes TE may include a first touch electrode TE1 and a second touch electrode TE2. The second touch metal TM2 included in the first touch electrode TE1 may be electrically connected via the first touch metal TM1. For example, two second touch metals TM2 that are spaced apart from each other can be electrically connected by the first touch metal TM1 to constitute a single first touch electrode TE1.

[0218] The first touch metal TM1 can be placed on the touch buffer layer 321. The inter-touch insulating layer 322 can be placed on the first touch metal TM1. The second touch metal TM2 can be placed on the inter-touch insulating layer 322. A portion of the second touch metal TM2 may be connected to the corresponding first touch metal TM1 through holes in the inter-touch insulating layer 322.

[0219] Referring to Figure 6, the first touch metal TM1 and the second touch metal TM2 can be arranged so as not to overlap with the light-emitting element ED. The first touch metal TM1 and the second touch metal TM2 may overlap with bank 631.

[0220] Multiple second touch metals TM2 can constitute a single touch electrode TE. The multiple second touch metals TM2 may be arranged in a mesh and electrically connected. Some of the second touch metals TM2 and other parts of the second touch metals TM2 can be electrically connected via a first touch metal TM1 to constitute a single touch electrode TE.

[0221] The configurations placed in the general region NA will be described below, and the configurations placed in the optical regions OA1 and OA2 will be described below.

[0222] Figure 7 is a diagram relating to the pixel array layer 720 and the lower metal layer 710 according to an embodiment of the present disclosure.

[0223] Referring to Figure 7, we can see the pixel array layer 720 and the lower metal layer 710 located in the second optical region OA2.

[0224] The lower metal layer 710 can be placed on the substrate. The lower metal layer 710 may contain a metallic material. The lower metal layer 710 may be an opaque metal or a transparent metal.

[0225] The lower metal layer 710 may include a plurality of metal patterns 711, 712, and 713. The plurality of metal patterns 711, 712, and 713 may be the same as the metal patterns shown in Figures 8 to 17. The plurality of metal patterns 711, 712, and 713 may be in the shape of lines. The plurality of metal patterns 711, 712, and 713 may be in the shape of lines but may include fracture points. A specific description of the plurality of metal patterns 711, 712, and 713 will be given later.

[0226] The pixel array layer 720 can be placed on the lower metal layer 710.

[0227] The pixel array layer 720 is a layer in which multiple subpixels SP are arranged. Referring to Figure 7, the pixel array layer 720 may include multiple light-emitting regions EA. Referring to Figure 7, the multiple light-emitting regions EA may include a first light-emitting region (EA of SP1) and a second light-emitting region (EA of SP2).

[0228] Referring to Figure 7, the pixel array layer 720 can be placed on the lower metal layer 710. The lower part of the pixel array layer 720 may be protected by the lower metal layer 710. For example, it is possible to prevent charge from accumulating in the configuration placed below the lower metal layer 710 and the corresponding charge from affecting the pixel array layer 720.

[0229] In the following section, with reference to Figure 8, we will describe the plan view of the first region 500 shown in Figure 5.

[0230] Figure 8 is a plan view of a portion 500 of the optical region OA2 in which metal patterns 810 and 820 according to an embodiment of the present disclosure are arranged.

[0231] Referring to Figure 8, the opaque region NTA2 can be used to place the components for the transistor, and the area where the components for the transistor can be placed is indicated by a rectangle within the opaque region NTA2.

[0232] Referring to Figure 8, the transmission region TA2 can be seen. Multiple transmission regions TA2 can be defined by a common electrode CE. The common electrode CE can contain multiple common electrode holes CH2. Each of the regions where multiple common electrode holes CH2 are located may also be a transmission region TA2.

[0233] Multiple light-emitting regions EA can be arranged so as not to overlap with multiple transmission regions TA2. Referring to Figure 8, multiple light-emitting regions EA can be placed outside the transmission regions TA2.

[0234] Referring to Figure 8, multiple data lines DL can be observed. Multiple data lines DL may extend from the opaque region NTA2 to the transparent region TA2. Multiple data lines DL may extend in the second direction DR2.

[0235] The second data line 432 can be positioned closer to the first data line 431 than the third data line 433. The fourth data line 434 can be positioned closer to the third data line 433 than the fifth data line 435. The sixth data line 436 can be positioned closer to the fifth data line 435 than the seventh data line 437.

[0236] The first data line 431, the second data line 432, the third data line 433, and the fourth data line 434 may extend from the fourth transparent region TA2d to the first transparent region TA2a. The first data line 431, the second data line 432, the third data line 433, and the fourth data line 434 may be located in the first transparent region TA2a and the fourth transparent region TA2d.

[0237] The second data line 435, the sixth data line 436, the seventh data line 437, and the eighth data line 438 may extend from the third transparent region TA2c to the second transparent region TA2b. The fifth data line 435, the sixth data line 436, the seventh data line 437, and the eighth data line 438 may be located in the second transparent region TA2b and the third transparent region TA2c.

[0238] In other words, referring to Figure 8, each of the multiple data lines DL can be placed in the opaque region NTA2, and the multiple data lines DL can be placed in at least one of the multiple transparent regions TA2. The multiple data lines DL may be placed across the opaque region NTA2 and at least one transparent region TA2.

[0239] Multiple data lines DL may extend from an opaque region NTA2 to a transparent region TA2. Each of the multiple data lines DL may include multiple layers of metal wiring. In this case, the portion of the data line located in the transparent region TA2 may include a transparent material. In this case, the transmittance of the transparent region TA2 can be further improved. The portion of the data line located in the opaque region NTA2 may include a transparent material or an opaque material. If the portion of the data line located in the opaque region NTA2 includes a transparent material, the transmittance of the opaque region NTA2 can be further improved.

[0240] Referring to Figure 8, multiple data lines DL can be arranged to intersect with metal patterns 810 and 820.

[0241] Referring to Figure 8, the first metal pattern 810 and the second metal pattern 820 may be placed in the opaque region NTA2.

[0242] The first metal pattern 810 and the second metal pattern 820 shown in Figure 8 may be included in the lower metal layer 710 shown in Figure 7.

[0243] Referring to Figure 8, the first metal pattern 810 and the second metal pattern 820 may extend in the first direction DR1.

[0244] Referring to Figure 8, the first metal pattern 810 may be positioned at a distance from the second metal pattern 820. The first metal pattern 810 may be positioned at a distance from the second metal pattern 820, with the fourth transparent region TA2d in between. The first metal pattern 810 may be positioned at a distance from the second metal pattern 820, with the third transparent region TA2c in between.

[0245] Referring to Figure 8, the second metal pattern 820 may be positioned between the first transparent region TA2a and the fourth transparent region TA2d. Alternatively, the first metal pattern 810 may be positioned between the second transparent region TA2b and the third transparent region TA2c. That is, the second metal pattern 820 may extend in the first direction DR1 between the transparent regions TA2.

[0246] Referring to Figure 8, the metal patterns 810 and 820 may overlap with multiple data lines DL.

[0247] Referring to Figure 8, the second metal pattern 820 may overlap with the fifth data line 435 and the sixth data line 436 in the first intersection region 831.

[0248] Referring to Figure 8, the second metal pattern 820 may overlap with the seventh data line 437 and the eighth data line 438 in the second intersection region 832.

[0249] Referring to Figure 8, the first metal pattern 810 and the second metal pattern 820 may have a line shape. The first metal pattern 810 and the second metal pattern 820 may have a bent line shape.

[0250] Referring to Figure 8, the first metal pattern 810 and the second metal pattern 820 may extend in the first direction DR1 with a predetermined pattern being repeated. The first metal pattern 810 and the second metal pattern 820 may be line shapes without fracture points.

[0251] Referring to Figure 8, the second metal pattern 820 can include a first pattern portion 820a, a second pattern portion 820b, and a third pattern portion 820c.

[0252] The first pattern portion 820a may be positioned closer to the third transparent region TA2c than the second pattern portion 820b. The first pattern portion 820a may extend in the first direction DR1, and the first pattern portion 820a may overlap with the fifth data line 435. The first pattern portion 820a may also overlap with the sixth data line 436.

[0253] The second pattern portion 820b may be positioned closer to the second transparent region TA2b than the first pattern portion 820a. The second pattern portion 820b may be "U" shaped. The second pattern portion 820b may be a portion that connects with the first pattern portion 820a and the third pattern portion 820c.

[0254] The third pattern portion 820c may be positioned closer to the third transparent region TA2c than the second pattern portion 820b. The third pattern portion 820c may extend in the first direction DR1, and the third pattern portion 820c may overlap with the seventh data line 437. The third pattern portion 820c may also overlap with the eighth data line 438.

[0255] Referring to Figure 8, the CD area shown in the plan view of the display panel 110 can be seen. The CD area is the region that crosses the second metal pattern 820, the blue light-emitting area EA_B, the second data line 432, and the first data line 431. Referring to Figure 9, a cross-sectional view of the display panel 110 including the metal patterns 810 and 820 will be explained.

[0256] Referring to Figure 8, the EF and GH regions shown in the plan view of the display panel 110 can be seen. The EF region is the area that crosses the second metal pattern 820, the third data line 433, and the fourth data line 434. The GH region is the area that crosses the second metal pattern 820 and the third data line 433. Referring to Figures 10 and 11, the cross-sectional view of the area where the metal pattern and data line DL overlap will be explained. Further explanation will follow below.

[0257] Figure 9 is a cross-sectional view of the CD region shown in Figure 8.

[0258] Referring to Figure 9, the substrate 210, multiple insulating layers 610, planarization layer 620, sealing layer 310, and touch sensor layer 320 are shown, which are the same as those shown in Figure 6. The explanation of the components in Figure 9 that are the same as those in Figure 6 can be omitted.

[0259] The following explanation will primarily focus on the cross-sectional view shown in Figure 9, but Figure 8 will also be referenced as needed.

[0260] Referring to Figure 9, the substrate 210 can be positioned in contact with the first buffer layer 611.

[0261] Charge can be accumulated in the area where the substrate 210 and the first buffer layer 611 are in contact.

[0262] If an electric charge accumulates in the area where the substrate 210 and the first buffer layer 611 are in contact, this charge may affect the first active layer ACT1 and the second active layer ACT2.

[0263] Referring to Figure 9, the second metal pattern 820 may be placed between the first buffer layer 611 and the substrate 210.

[0264] As the second metal pattern 820 is positioned between the first buffer layer 611 and the substrate 210, it is possible to prevent the charge from affecting the first active layer ACT1.

[0265] The second metal pattern 820 can prevent the charge from affecting the first active layer ACT1, so the charge on the upper side of the second metal pattern 820 may be smaller than the charge on the lower side of the second metal pattern 820.

[0266] The second metal pattern 820 can be placed below the first active layer ACT1.

[0267] A portion of the second metal pattern 820 can be positioned to completely overlap the first active layer ACT1. That is, as a portion of the second metal pattern 820 completely overlaps the first active layer ACT1, the second metal pattern 820 can more effectively block the charge from affecting the first active layer ACT1.

[0268] The area of ​​the first active layer ACT1 may be larger than the area of ​​the second active layer ACT2. In this case, the influence of charge on the first active layer ACT1 may be greater than the influence of charge on the second active layer ACT2. That is, when the second metal pattern 820 is placed below the first active layer ACT1, the subpixel SP including the first active layer ACT1 can be driven more stably. In this case, the first active layer ACT1 can be made of low-temperature polysilicon, and the second active layer ACT2 can be made of oxide semiconductor, but the first active layer ACT1 and the second active layer ACT2 are not limited to these.

[0269] On the other hand, the second metal pattern 820 can be placed in the non-transparent region NTA2. The non-transparent region NTA2 may have a lower transmittance than the transparent region TA2. The optical device is placed in the optical regions OA1 and OA2, and the higher the transmittance of the optical regions OA1 and OA2, the better the sensing performance of the optical device may be. Therefore, it is necessary to increase the transmittance of the transparent region TA2, and also to increase the transmittance of the non-transparent region NTA2.

[0270] The second metal pattern 820 may be made of an opaque metal, but if the second metal pattern 820 is made of a transparent metal, the transmittance of the opaque region NTA2 can be further improved.

[0271] Referring to Figures 8 and 9, the second metal pattern 820 may have a line shape including a zigzag pattern. In this case, the second metal pattern 820 may overlap with the first active layer ACT1 contained in each of the multiple subpixels. That is, the second metal pattern 820 may extend in the first direction DR1 while having a line shape including a zigzag pattern, and in this case, the second metal pattern 820 may be positioned to pass under the first active layer ACT1.

[0272] Referring to Figure 8, the second metal pattern 820 may have a linear shape and extend in the first direction DR1. In this case, the second metal pattern 820 may extend in the first direction DR1 to the general region NA shown in Figure 6. In this case, the first shield metal 651 shown in Figure 6 may be a part of the second metal pattern 820, and the first shield metal 651 may be a transparent metal. However, in contrast to this, the second metal pattern 820 can be placed only in the optical regions OA1 and OA2, separated from the first shield metal 651 shown in Figure 6. In this case, the second metal pattern 820 shown in Figure 9 may be a transparent metal, and the first shield metal 651 shown in Figure 6, although placed in the same layer as the second metal pattern 820, may be an opaque metal.

[0273] On the other hand, referring to Figure 9, the second metal pattern 820 may be placed in the same layer as the layer on which part of the data line DL is placed. Referring to Figure 9, the second metal pattern 820 may be placed in the same layer as part of the first data line 431 and part of the second data line 432.

[0274] Referring to Figure 9, the first data line 431 may be located in the transparent region TA2. In this case, the first data line 431 may include a transparent material. If the first data line 431 includes a transparent material, the transmittance of the transparent region TA2 can be further improved.

[0275] The first data line 431 is located in the transmission region TA2, and the common electrode CE does not necessarily have to be located in the transmission region TA2. Therefore, a portion of the first data line 431 does not have to overlap with the common electrode CE.

[0276] Referring to Figure 9, the second data line 432 may be located in the opaque region NTA2. In this case, the second data line 432 may be made of an opaque metal or a transparent metal. If the second data line 432 is made of a transparent metal, the transmittance of the opaque region NTA2 can be further improved.

[0277] Figure 10 is a cross-sectional view of the EF region shown in Figure 8.

[0278] Referring to Figure 8, the EF region is the area that separates the second metal pattern 820, the third data line 433, and the fourth data line 434. A cross-sectional view of the EF region is shown in Figure 10.

[0279] Referring to Figure 10, the second metal pattern 820 can be placed on the substrate 210.

[0280] Referring to Figure 10, the second metal pattern 820 can be positioned in the EF region, separated from the data lines.

[0281] Referring to Figure 10, the data lines can be placed on the second planarization layer 622.

[0282] Referring to FIG. 8, since the second metal pattern 820 extends in the first direction DR1 and the data line DL extends in the second direction DR2, the second metal pattern 820 and the data line DL can intersect. When the second metal pattern 820 and the data line DL intersect, the second metal pattern 820 can overlap the data line DL. If the second metal pattern 820 is arranged only in a specific layer, the data line DL may be arranged to overlap the second metal pattern 820 via metal wirings arranged in a plurality of layers. Also, if a plurality of data lines DL are arranged only in a specific layer, the second metal pattern 820 may be arranged to overlap the data line DL via metal wirings arranged in a plurality of layers.

[0283] Hereinafter, a structure in which the data line DL includes a metal wiring portion arranged in a plurality of layers and the data line DL overlaps the second metal pattern 820 will be described.

[0284] FIG. 11 is a cross-sectional view of the G-H region shown in FIG. 8.

[0285] Referring to FIG. 8, the G-H region is a region that separates the third data line 433 and the second metal pattern 820. FIG. 11 shows a cross-sectional view of the G-H region.

[0286] Referring to FIG. 11, the third data line 433 can include a first wiring portion 433a, a second wiring portion 433b, a third wiring portion 433c, a fourth wiring portion 433d, and a fifth wiring portion 433e. The third data line 433 can include a plurality of wiring portions, and this can be called a jumping wiring structure.

[0287] The first wiring portion 433a can be arranged on the substrate 210. The first wiring portion 433a may be arranged in the same layer as the layer where the second metal pattern 820 is arranged. The first wiring portion 433a may be a transparent metal or an opaque metal.

[0288] A portion of the second wiring section 433b can be placed on the first planarization layer 621. A portion of the second wiring section 433b can be electrically connected to the first wiring section 433a through contact holes formed in the plurality of insulating layers 610. The second wiring section 433b may be made of an opaque metal. The first wiring section 433a may include the first source-drain metal shown in Figure 6. The second wiring section 433b can be superimposed on the first wiring section 433a and the third wiring section 433c.

[0289] A portion of the third wiring section 433c may be positioned on the second planarization layer 622. A portion of the third wiring section 433c may be electrically connected to the second wiring section 433b through contact holes formed on the second planarization layer 622. The third wiring section 433c may be made of an opaque metal. The third wiring section 433c may include the second source-drain metal shown in Figure 6. A portion of the third wiring section 433c may be positioned to overlap the second metal pattern 820. The third wiring section 433c may extend from the portion connected to the second wiring section 433b to the portion connected to the fourth wiring section 433d, and the extending third wiring section 433c may be positioned to overlap the second metal pattern 820.

[0290] A portion of the fourth wiring section 433d may be placed on the first planarization layer 621. A portion of the fourth wiring section 433d may be electrically connected to the third wiring section 433c through contact holes formed in the plurality of insulating layers 610. The fourth wiring section 433d may be made of an opaque metal. The first wiring section 433a may include the first source-drain metal shown in Figure 6. The fourth wiring section 433d may overlap with the third wiring section 433c and the fifth wiring section 433e.

[0291] The fifth wiring section 433e can be placed on the substrate 210. The fifth wiring section 433e may be placed on the same layer as the second metal pattern 820. The fifth wiring section 433e may be made of transparent metal or opaque metal.

[0292] The first wiring section 433a and the fifth wiring section 433e may be made of transparent metal or opaque metal. The first wiring section 433a and the fifth wiring section 433e are arranged in the opaque region NTA2, and the first wiring section 433a and the fifth wiring section 433e may be made of transparent metal. In this case, the transmittance of the opaque region NTA2 can be further improved.

[0293] The characteristics of the third data line 433 described above are applicable to all data lines DL included in multiple data lines DL. The third data line 433 was explained as including the first wiring section 433a to the fifth wiring section 433e.

[0294] However, the third data line 433 does not have to include the third wiring section 433c and the fourth wiring section 433d. In this case, the second wiring section 433b can be arranged in the same manner as the third wiring section 433c, and the second wiring section 433b is arranged on the first planarization layer 621, electrically connected to the first wiring section 433a and the fifth wiring section 433e, and may overlap with the second metal pattern 820.

[0295] Furthermore, if an additional planarization layer is placed on the second planarization layer 622, the third data line 433 may further include additional wiring sections in addition to the fifth wiring section 433e.

[0296] Figure 12 is a plan view of a portion 500 of the optical region OA2 in which metal patterns 1210 and 1220 according to an embodiment of the present disclosure are arranged.

[0297] Figure 13 is a cross-sectional view of the IJ region shown in Figure 12.

[0298] Unlike the metal patterns 1210 and 1220 shown in Figure 8, the metal patterns 1210 and 1220 shown in Figure 12 may include at least one fracture point.

[0299] Referring to Figure 12, the first metal pattern 1210 may include multiple island metals 1211, 1212, 1213, 1214, and 1215. For example, the first metal pattern 1210 may include the first island metal 1211, the second island metal 1212, the third island metal 1213, the fourth island metal 1214, and the fifth island metal 1215. The second metal pattern 1220 may include the sixth island metal 1221, the seventh island metal 1222, the eighth island metal 1223, the ninth island metal 1224, and the tenth island metal 1225.

[0300] At least one data line DL can be placed between island metals. Referring to Figure 12, two data lines DL can be placed between island metals.

[0301] Referring to Figure 12, the first data line 431 and the second data line 432 may be positioned between the first island metal 1211 and the second island metal 1212. The second data line 432 and the third data line 433 may be positioned between the second island metal 1212 and the third island metal 1213.

[0302] Referring to Figure 12, the first data line 431 and the second data line 432 may be located between the fifth island metal 1215 and the sixth island metal 1221. The second data line 432 and the third data line 433 may be located between the sixth island metal 1221 and the seventh island metal 1222. A repetition of this explanation is omitted.

[0303] Referring to FIG. 12, the I-J region can be confirmed. A cross-sectional view of the I-J region is shown in FIG. 13. The configuration shown in FIG. 13 may be the same as the configuration shown in FIG. 9. Regarding the same configuration as that shown in FIG. 9 among the configurations shown in FIG. 13, the description can be omitted. Referring to FIG. 13, similar to the second metal pattern 1220 in FIG. 9, the second metal pattern 1220 in FIG. 13 can also be disposed below the first active layer ACT1. At this time, the second metal pattern 1220 can be disposed in the non-transmissive region NTA2. The second metal pattern 1220 may be a transparent metal. When the second metal pattern 1220 is a transparent metal, the transmittance of the non-transmissive region NTA2 can be further improved.

[0304] Referring to FIG. 12, the K-L region can be confirmed. The K-L region is a region that separates the sixth island metal 1221, the first data line 431, the second data line 432, and the seventh island metal 1222. A cross-sectional view of the K-L region is shown in FIG. 1 | 4.

[0305] FIG. 14 is a cross-sectional view of the K-L region shown in FIG. 12.

[0306] Referring to FIG. 14, the sixth island metal 1221 can be disposed in the same layer as the first data line 431 and the second data line | 432. Based on the horizontal direction, the sixth island metal 1221 may be disposed at a distance from the first data line 4 | 31 and the second data line 432.

[0307] Referring to FIG. 14, the seventh island metal 1222 can be disposed in the same layer as the first data line 431 and the second data line 432. Based on the horizontal direction, the seventh island metal 1222 may be disposed at a distance from the first data line 431 and the second data line 432.

[0308] Referring to Figures 12 and 14, the metal patterns 1210 and 1220 can include multiple fracture points. Thus, the first metal pattern 1210 can include multiple island metals 1211, 1212, 1213, 1214, and 1215, and the second metal pattern 1220 can also include multiple island metals 1221, 1222, 1223, 1224, and 1225.

[0309] When a metal pattern is positioned as an Irish metal, the metal pattern does not necessarily have to overlap with the data line DL. The metal pattern may extend in a first direction DR1, and the data line DL may extend in a second direction DR2, and at least a portion of the metal pattern may include a fractured shape at the point where the metal pattern and the data line DL intersect. This allows the data line DL to be positioned in the same layer as the metal pattern.

[0310] In other words, the metal pattern placed in the opaque region NTA2 may be made of transparent metal, thereby improving the transmittance of the opaque region NTA2. Furthermore, the data line DL placed in the opaque region NTA2 may also be made of transparent metal, in which case the transmittance of the opaque region NTA2 can be further improved.

[0311] However, the data line DL may be designed so that only a portion is made of transparent metal, while the other portion includes opaque metal. This is illustrated with reference to Figure 15.

[0312] Figure 15 is a plan view of an optical region in which a metal pattern according to an embodiment of the present disclosure is arranged.

[0313] Referring to Figure 15, the metal patterns 1210 and 1220 shown in Figure 15 are the same as the metal patterns shown in Figure 13.

[0314] Referring to Figure 15, multiple data lines DL can include transparent wiring sections 431b, 432b and opaque wiring sections 431a, 431c, 432a, 432c.

[0315] The transparent wiring sections 431b and 432b may be placed in the transparent region TA2. The transparent wiring sections 431b and 432b can be placed in the same layer as the metal patterns 1210 and 1220.

[0316] The opaque wiring sections 431a, 431c, 432a, and 432c may be placed in the opaque region NTA2. The opaque wiring sections 431a, 431c, 432a, and 432c may be placed in a layer higher than the layer on which the metal patterns 1210 and 1220 are placed. The opaque wiring sections 431a, 431c, 432a, and 432c can be connected to the transparent wiring sections 431b and 432b, but the opaque wiring sections 431a, 431c, 432a, and 432c can be connected to the transparent wiring sections 431b and 432b via the jumping wiring structure shown in Figure 11.

[0317] For example, the transparent wiring sections 431b and 432b may be located in the transparent region TA2 and in the same layer as the metal patterns 1210 and 1220. The opaque wiring sections 431a, 431c, 432a, and 432c may be located in a higher layer than the transparent wiring sections 431b and 432b. For example, the opaque wiring sections 431a, 431c, 432a, and 432c may be located on the first planarization layer 621 or the second planarization layer 622. The opaque wiring sections 431a, 431c, 432a, and 432c may include the first source-drain metal or the second source-drain metal.

[0318] The opaque wiring sections 431a, 431c, 432a, and 432c are arranged on the first planarization layer 621 or the second planarization layer 622 and may extend from the opaque region NTA2 to the transparent region TA2. In this case, the opaque wiring sections 431a, 431c, 432a, and 432c can be connected to the transparent wiring sections 431b and 432b via contact holes formed in the insulating layer, and the transparent wiring sections 431b and 432b may extend into the transparent region TA2.

[0319] Referring to Figure 15, the opaque wiring sections 431a, 431c, 432a, and 432c can be placed only in the opaque region NTA2. The transparent wiring sections 431b and 432b can be placed in the transparent region TA2 and can be extended into a part of the opaque region NTA2. If the opaque wiring sections 431a, 431c, 432a, and 432c extend into a part of the transparent region TA2, the transmittance of the transparent region TA2 may decrease. To prevent this, the transparent wiring sections 431b and 432b can extend from the transparent region TA2 to a part of the opaque region NTA2.

[0320] Figures 16 and 17 are plan views of an optical region in which a metal pattern according to an embodiment of the present disclosure is arranged.

[0321] Referring to Figure 16, the first optical region OA1 can include a plurality of transmission regions TA2 and non-transmission regions NTA1.

[0322] Referring to Figure 16, the multiple transmission regions TA1 can include a first transmission region TA1a, a second transmission region TA1b, a third transmission region TA1c, and a fourth transmission region TA1d.

[0323] Multiple transmission regions TA1 can correspond to common electrode holes CH1. Common electrode holes CH1 are regions where a portion of the common electrode CE has been removed.

[0324] The second transparent region TA1b may be arranged in a line with the first transparent region TA1a in the first direction DR1.

[0325] The third transparent region TA1c may be arranged in a line with the fourth transparent region TA1d in the second direction DR2. The third transparent region TA1c can be located at the upper right end of the first transparent region TA1a. The third transparent region TA1c can be located at the upper left end of the second transparent region TA1b.

[0326] The fourth transmission region TA1d can be located at the lower right end of the first transmission region TA1a. The fourth transmission region TA1d can be located at the lower left end of the second transmission region TA1b.

[0327] The light-emitting region EA can be located in the non-transparent region NTA1. The light-emitting region EA may also be positioned between the transmissive regions TA2.

[0328] The light-emitting region EA can be located between the transmission regions TA2 arranged in a line in the first direction DR1.

[0329] The light-emitting region EA can be located between the transmission regions TA2 arranged in a line in the second direction DR2.

[0330] Metal patterns 1611, 1612, and 1613 can be placed in the opaque region NTA1.

[0331] Metal patterns 1611, 1612, and 1613 may extend in the first direction DR1.

[0332] The metal patterns 1611, 1612, and 1613 do not necessarily have to be placed in the transparent region TA1.

[0333] The metal patterns 1611, 1612, and 1613 may have a curved line shape.

[0334] For example, the upper end of the first transparent region TA1a may be positioned relatively above the lower end of the third transparent region TA1c. In this case, the first metal pattern 1611 may extend above the first transparent region TA1a. The first metal pattern 1611 can extend in the first direction DR1, and the first metal pattern 1611 can extend below the third transparent region TA1c. Referring to Figure 16, it can be seen that the first metal pattern 1611 has a bent line shape.

[0335] Multiple data lines DL may extend from the opaque region NTA1 to the transparent region TA1.

[0336] Multiple data lines DL may extend in a second direction DR2.

[0337] The first data line group 441 can be positioned to pass through the first transparent region TA1a. The first data line group 441 may contain four data lines.

[0338] The second data line group 442 may be arranged to pass through the third transparent region TA1c and the fourth transparent region TA1d. The second data line group 442 may include four data lines.

[0339] The third data line group 443 can be positioned to pass through the second transparent region TA1b. The third data line group 443 may contain four data lines.

[0340] The fourth data line group 444 can be positioned to pass through the transparent region TA2. The fourth data line group 444 can contain four data lines.

[0341] Referring to Figure 16, metal patterns 1611, 1612, and 1613 can extend in the first direction DR1, and multiple data lines DL can extend in the second direction DR2. Therefore, metal patterns 1611, 1612, and 1613 can overlap with multiple data lines DL. Alternatively, metal patterns 1611, 1612, and 1613 can intersect with multiple data lines DL. Data lines DL can have the jumping wiring structure shown in Figure 11. In areas where data lines DL overlap with metal patterns, a portion of the data lines can be placed on the metal patterns.

[0342] The metal patterns 1611, 1612, and 1613 may be made of transparent metal. In this case, the transmittance of the opaque region NTA1 can be further improved.

[0343] Multiple data lines DL may include transparent metal. When multiple data lines DL include transparent metal, the transmittance of the transparent region TA1 and the non-transparent region NTA1 can be improved.

[0344] Referring to Figure 17, the metal patterns 1711, 1712, 1713, and 1714 may be arranged extending in the second direction DR2.

[0345] Referring to Figure 17, the first metal pattern 1711 can be positioned between the first data line group 441 and the second data line group 442.

[0346] Referring to Figure 17, the second metal pattern 1712 can be positioned between the second data line group 442 and the third data line group 443.

[0347] Referring to Figure 17, the third metal pattern 1713 can be positioned between the third data line group 443 and the fourth data line group 444.

[0348] Referring to Figure 17, the fourth metal pattern 1714 can be positioned to the right of the fourth data line group 444.

[0349] Multiple data lines DL may extend in a second direction DR2.

[0350] Multiple data lines DL can be positioned at a distance from metal patterns 1611, 1612, and 1613.

[0351] The metal patterns 1611, 1612, and 1613 may include transparent materials. In this case, the transmittance of the opaque region NTA1 can be improved.

[0352] Multiple data lines DL may include transparent materials. In this case, the transmittance of the opaque region NTA1 and the transparent region TA1 can be improved.

[0353] The metal patterns 1611, 1612, and 1613 shown in Figures 16 and 17 can be placed between the substrate 210 and the first buffer layer 611 shown in Figure 9.

[0354] Some of the data lines DL shown in Figure 16 can be placed between the substrate 210 and the first buffer layer 611 shown in Figure 9.

[0355] The multiple data lines DL shown in Figure 17 can be placed between the substrate 210 and the first buffer layer 611 shown in Figure 9.

[0356] The embodiments of this disclosure described above can be briefly described as follows.

[0357] Embodiments of the present disclosure can provide a display device that includes a display area on which an image is displayed, the display area including an optical area including a general area and a plurality of transparent areas, the optical area further including a non-transparent area which is the outer boundary of the plurality of transparent areas, a first metal pattern disposed on the substrate and disposed in the non-transparent area and including a transparent material, a first data line disposed on the substrate and distributed across the non-transparent area and at least one of the plurality of transparent areas, and a first active layer disposed on the first metal pattern and overlapping with the first metal pattern.

[0358] The first data line extends from a first transparent region included in the plurality of transparent regions to the opaque region, and a portion of the first data line located in the first transparent region includes a transparent material, and a portion of the first data line located in the opaque region may include the transparent material or an opaque material different from the transparent material.

[0359] The first data line may further include a first wiring section, which is arranged on the same layer as the first metal pattern and extends from a first transparent region to the opaque region, which is included in the plurality of transparent regions, and contains the transparent material; a second wiring section, which is arranged on the first metal pattern and electrically connected to the first wiring section, and contains the opaque material; and a third wiring section, which is arranged on the same layer as the first metal pattern and extends from the opaque region to the second transparent region, which is electrically connected to the second wiring section, and contains the transparent material.

[0360] The present invention further includes an optical device disposed below the substrate, with at least a portion of it located in the first transparent region, wherein the first wiring portion and the third wiring portion may overlap with the optical device.

[0361] The present invention further includes an optical device disposed below the substrate, with at least a portion of it located in the opaque region, wherein the first metal pattern may overlap with the optical device.

[0362] The first metal pattern may include a first island metal located in the same layer as the first data line, and a second island metal located in the same layer as the first data line but separated from the first island metal, with the first data line in between.

[0363] The first data line is arranged to extend from the opaque region to the first transparent region, but to pass through the region between the first island metal and the second island metal, and may include the transparent material.

[0364] The first data line is arranged to pass through the region between the first island metal and the second island metal, and may include a transparent wiring section containing the transparent material, located in the first transparent region which is included in the plurality of transparent regions, and an opaque wiring section containing an opaque material, located in the non-transparent region which is electrically connected to the transparent wiring section.

[0365] The first metal pattern and the first data line may be spaced apart from each other, and they may extend in the same direction from each other.

[0366] The amount of charge below the first metal pattern may be greater than the amount of charge on the first metal pattern.

[0367] The system further includes a second active layer containing a material different from the material contained in the first active layer, and the area of ​​the first active layer may be larger than the area of ​​the second active layer.

[0368] Embodiments of the present disclosure can provide a display device that includes a display area on which an image is displayed, the display area includes an optical area including a general area and a plurality of transparent areas, the optical area further including a non-transparent area which is the outer boundary of the plurality of transparent areas, a first subpixel located on the substrate and positioned in the non-transparent area and including a first transistor, a second subpixel located on the substrate and positioned in the non-transparent area and including a second transistor, a first data line connected to the first subpixel and positioned across the non-transparent area and at least one of the plurality of transparent areas, a second data line connected to the second subpixel and positioned across the non-transparent area and at least one of the plurality of transparent areas, and a first metallic pattern located in the non-transparent area, positioned below the first transistor and the second transistor, superimposed on at least a portion of the first transistor and at least a portion of the second transistor, and having a line shape.

[0369] The first metal pattern may include a transparent material.

[0370] The first metal pattern may extend over the general area.

[0371] The present invention may further include a second metal pattern, which is located in the same layer as the first metal pattern, is located in the general area, and contains an opaque material.

[0372] The first metal pattern may have a bent line shape.

[0373] The first metal pattern may have a line shape without fracture points.

[0374] The first metal pattern may have a line shape having at least one fracture point.

[0375] The first data line and the second data line may include the same transparent material as the first metal pattern.

[0376] The first metal pattern intersects the first data line and the second data line in a first region and a second region, respectively, the first data line includes a first opaque line portion located in the first region and a first transparent line portion located in a region different from the first region, the first opaque line portion and the first transparent line portion are electrically connected via a first contact hole in an insulating layer located between the first opaque line portion and the first transparent line portion, the second data line includes a second opaque line portion located in the second region and a second transparent line portion located in a region different from the second region, the second opaque line portion and the second transparent line portion may be electrically connected via a second contact hole in the insulating layer located between the second opaque line portion and the second transparent line portion.

[0377] The above description is merely illustrative of the technical concept of this disclosure, and any person with ordinary skill in the art to which this disclosure belongs could make various modifications and variations without departing from the essential characteristics of this disclosure. Furthermore, the embodiments shown in this disclosure are for illustrative purposes only and not to limit the technical concept of this disclosure, and therefore the scope of the technical concept of this disclosure is not limited by these embodiments. [Explanation of Symbols]

[0378] 100 display device 110 Display Panel 220 Data-driven circuit 230 Gate drive circuit 240 controllers

Claims

1. A substrate including a display area on which an image is displayed, wherein the display area includes a general area and an optical area including a plurality of transparent areas, and the optical area further includes a non-transparent area which is the outer boundary of the plurality of transparent areas, A first metal pattern, which is placed on the substrate and in the non-transparent region and includes a transparent material, A first data line is disposed on the substrate and is arranged across the non-transparent region and at least one transparent region among the plurality of transparent regions, A display device comprising a first active layer disposed on and overlapping the first metal pattern.

2. The first data line extends from the first transparent region included in the plurality of transparent regions to the non-transparent region, Of the portion of the first data line, the portion located in the first transparent region includes a transparent material. The display device according to claim 1, wherein a portion of the first data line located in the non-transparent region includes the transparent material or an opaque material different from the transparent material.

3. The first data line is, Displaced in the same layer as the first metal pattern, extending from the first transparent region included in the plurality of transparent regions to the non-transparent region, and comprising the first wiring portion including the transparent material, A second wiring portion is arranged on the first metal pattern, electrically connected to the first wiring portion, and includes an opaque material. The display device according to claim 1, further comprising a third wiring portion which includes the transparent material, disposed in the same layer as the first metal pattern, extending from the opaque region to the second transparent region, and electrically connected to the second wiring portion.

4. The optical device is located below the substrate and at least a portion of it is located in the first transparent region, The display device according to claim 3, wherein the first wiring section and the third wiring section are superimposed on the optical device.

5. The optical device is located below the substrate and at least a portion of it is located in the non-transparent region, The display device according to claim 1, wherein the first metal pattern is superimposed on the optical device.

6. The first metal pattern is, A first island metal arranged in the same layer as the first data line, The display device according to claim 1, further comprising a second island metal arranged on the same layer as the first data line, but separated from the first island metal with the first data line in between.

7. The display device according to claim 6, wherein the first data line is arranged to extend from the non-transparent region to the transparent region and to pass through the region between the first island metal and the second island metal, and includes the transparent material.

8. The first data line is, Distributed to pass through the region between the first island metal and the second island metal, and located in the first transparent region included in the plurality of transparent regions, the transparent wiring portion includes the transparent material, The display device according to claim 6, further comprising an opaque wiring portion disposed in the non-transparent region, electrically connected to the transparent wiring portion, and containing an opaque material.

9. The first metal pattern and the first data line are arranged spaced apart from each other. The display device according to claim 1, wherein the first metal pattern and the first data line are arranged to extend in the same direction from one another.

10. The display device according to claim 1, wherein the amount of charge below the first metal pattern is greater than the amount of charge on the first metal pattern.

11. The invention further includes a second active layer containing a material different from the material contained in the first active layer, The display device according to claim 1, wherein the area of ​​the first active layer is larger than the area of ​​the second active layer.

12. A substrate including a display area on which an image is displayed, wherein the display area includes a general area and an optical area including a plurality of transparent areas, and the optical area further includes a non-transparent area which is the outer boundary of the plurality of transparent areas, Displaced on the substrate and in the non-transparent region, a first subpixel including a first transistor, Displaced on the substrate and in the non-transparent region, a second subpixel including a second transistor, A first data line connected to the first subpixel and arranged across the opaque region and at least one transparent region among the plurality of transparent regions, A second data line connected to the second subpixel and positioned across the opaque region and at least one transparent region among the plurality of transparent regions, The first metal pattern, which is arranged in the opaque region, is located beneath the first transistor and the second transistor, superimposed on at least a portion of the first transistor and at least a portion of the second transistor, and includes a line-shaped first metal pattern, The first metal pattern includes a transparent material. Display device.

13. The display device according to claim 12, wherein the first metal pattern extends over the general area.

14. The display device according to claim 12, further comprising a second metal pattern disposed in the same layer as the first metal pattern, disposed in the general region, and comprising an opaque material.

15. The display device according to claim 12, wherein the first metal pattern has a bent line shape.

16. The display device according to claim 12, wherein the first metal pattern has a line shape without fracture points.

17. The display device according to claim 12, wherein the first metal pattern has a line shape having at least one fracture point.

18. A substrate including a display area on which an image is displayed, wherein the display area includes a general area and an optical area including a plurality of transparent areas, and the optical area further includes a non-transparent area which is the outer boundary of the plurality of transparent areas, Displaced on the substrate and in the non-transparent region, a first subpixel including a first transistor, Displaced on the substrate and in the non-transparent region, a second subpixel including a second transistor, A first data line connected to the first subpixel and arranged across the opaque region and at least one transparent region among the plurality of transparent regions, A second data line connected to the second subpixel and positioned across the opaque region and at least one transparent region among the plurality of transparent regions, Displaced in the opaque region, located beneath the first transistor and the second transistor, superimposed on at least a portion of both the first transistor and at least a portion of the second transistor, and having a line shape, a first metal pattern and Includes, The first data line and the second data line include the same transparent material as the first metal pattern. Display device.

19. The first metal pattern intersects the first data line and the second data line in the first region and the second region, respectively. The first data line includes a first opaque line portion located in the first region and a first transparent line portion located in a region different from the first region, and the first opaque line portion and the first transparent line portion are electrically connected via a first contact hole in an insulating layer located between the first opaque line portion and the first transparent line portion. The display device according to claim 18, wherein the second data line includes a second opaque line portion located in the second region and a second transparent line portion located in a region different from the second region, and the second opaque line portion and the second transparent line portion are electrically connected via a second contact hole in the insulating layer located between the second opaque line portion and the second transparent line portion.

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