Electronic circuits and semiconductor devices

Abstract

We provide electronic circuits that incorporate an ECC self-test function. [Solution] The electronic circuit of the present invention comprises an encoder unit 220 that encodes data for error detection and correction, a decoder unit 230 that decodes the encoded data, and a test means for testing the encoder unit 220 and the decoder unit 230. The test means includes a memory 200 that stores basic data including at least information bits and expected values, an ATPG 210 that generates a test pattern by performing ExOR processing or shift processing on the basic data provided from the memory 200, and a comparison unit 240 that compares the result of the encoder unit 220 processing the test pattern with the expected value, or the result of the decoder unit 230 processing the test pattern with the expected value.

Description

[Technical Field]

[0001] This invention relates to error detection and correction (ECC) testing, and more particularly to built-in self testing (BIST) for ECC. [Background technology]

[0002] In NAND flash memory, repeated programming and erasing of data can lead to deterioration of the tunnel insulating film, resulting in reduced charge retention characteristics, or threshold fluctuations due to trapped charges in the tunnel insulating film, which can cause bit errors. To counter such bit errors, ECC circuits are used in flash memory (for example, Patent Documents 1 and 2). [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 6744950 [Patent Document 2] Patent No. 6744951 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] While Hamming code is used when an ECC circuit performs single-bit error detection and correction, recent NAND flash memory requires multi-bit (e.g., 2-bit, 4-bit, 8-bit) error detection and correction capabilities due to cell miniaturization, increased rewrite cycles, and expanded applications in automotive equipment.

[0005] While BCH codes are commonly used for multi-bit error detection and correction, processing BCH codes is more complex than processing Hamming codes. This also complicates testing for ECC circuit failures, and testing ECC circuits, especially using external testers, can result in significant overhead and costs.

[0006] The present invention aims to solve these conventional problems and provide an electronic circuit and semiconductor device that incorporate an ECC self-test diagnostic function. [Means for solving the problem]

[0007] The electronic circuit according to the present invention comprises encoding means for encoding data for error detection and correction, decoding means for decoding the encoded data, and testing means for testing the encoding means and the decoding means, wherein the testing means includes storage means for storing basic data and expected values, which include at least multiple bit sequences; generation means for generating a test pattern by performing ExOR processing on the basic data provided from the storage means; and verification means for comparing the result of the encoding means or the decoding means processing the test pattern with the expected value and verifying whether or not there is a failure in the encoding means or the decoding means.

[0008] Furthermore, the electronic device according to the present invention includes encoding means for encoding data for error detection and correction, decoding means for decoding the encoded data, and testing means for testing the encoding means and the decoding unit, wherein the testing means includes storage means for storing basic data and expected values, which include at least multiple bit sequences; generation means for shifting the basic data provided from the storage means to generate a test pattern; and verification means for comparing the result of the encoding means or the decoding means processing the test pattern with the expected value to verify whether or not there is a malfunction in the encoding means or the decoding means. [Effects of the Invention]

[0009] According to the present invention, by implementing test means for encoding means and decoding means in an electronic circuit, it is possible to facilitate the test for the presence or absence of a failure in the ECC circuit, and reduce the load and cost of an external tester.

Brief Description of the Drawings

[0010] [Figure 1] It is a diagram showing a schematic configuration of a NAND type flash memory according to an embodiment of the present invention. [Figure 2] It is a block diagram showing an internal configuration of an ECC processing unit according to an embodiment of the present invention. [Figure 3] It is a block diagram showing an internal configuration of the ATPG shown in FIG. 2. [Figure 4] It is a diagram showing an internal configuration of the comparison unit shown in FIG. 2. [Figure 5] It is a diagram for explaining a method of generating a test pattern by ExOR processing according to a first embodiment of the present invention. [Figure 6] It is a diagram showing an example of generating a test pattern without errors according to the first embodiment. [Figure 7] It is a diagram showing an example of generating a test pattern with errors according to the first embodiment. [Figure 8] It is a diagram for explaining a method of generating a test pattern by shift processing according to a second embodiment of the present invention. [Figure 9] It is a diagram showing an example of generating a test pattern without errors by left shift processing in the second embodiment. [Figure 10] It is a diagram showing an example of generating a test pattern without errors by right shift processing in the second embodiment. [Figure 11] It is a diagram showing an example of generating a test pattern with errors by left shift processing in the second embodiment. [Figure 12] It is a diagram showing an example of generating a test pattern with errors by right shift processing in the second embodiment.

Modes for Carrying Out the Invention

[0011] Next, embodiments of the present invention will be described. The present invention relates to self-diagnosis of ECC incorporated in a semiconductor device, that is, BIST of an ECC circuit. The semiconductor device in which the ECC circuit is mounted is not particularly limited, and examples thereof include processors such as NAND flash memories, microprocessors, microcontrollers, logics, ASICs, and DSPs. In the following description, a NAND flash memory incorporating BIST of ECC will be exemplified.

Example

[0012] Next, examples of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing the internal configuration of a NAND flash memory according to an example of the present invention. The flash memory 100 includes a memory array 110 in which a plurality of memory cells are arranged in a matrix, an input / output circuit 120 connected to external input / output terminals and outputting read data to the outside or capturing data input from the outside, an ECC processing unit 130 incorporating a self-test function, an address register 140 receiving address data via the input / output circuit 120, a controller 150 controlling each unit based on a command (command) received via the input / output circuit 120 or a control signal applied to a control terminal, a word line selection circuit 160 performing block selection, word line selection, etc. based on the decoding result of the row address information Ax from the address register 140, a page buffer / sense circuit 170 holding data read from a selected page of the memory cell array 110 or holding data to be programmed to the selected page, and a column selection circuit 180 performing column selection, etc. based on the decoding result of the column address information Ay from the address register 140. Although not shown here, the flash memory 100 includes an internal voltage generation circuit that generates voltages (program voltage Vpgm, pass voltage Vpass, read voltage Vread, erase voltage Vers, etc.) necessary for data reading, programming (writing), and erasing.

[0013] The memory array 110 includes multiple blocks BLK(0), BLK(1), ..., BLK(m-1), and multiple NAND strings are formed in each block. The NAND strings may be formed two-dimensionally or three-dimensionally on the substrate surface. The memory cells may be of the SLC type that stores 1 bit (binary data) or of the type that stores multiple bits.

[0014] The controller 150 includes a microcontroller or state machine, and controls the overall operation of the flash memory 100, such as reading, programming, erasing, and testing the ECC processing unit, based on commands and control signals received from an external source.

[0015] The ECC processing unit 130 includes a function for detecting and correcting multi-bit errors, for example, using BCH code or Reed-Solomon code. During program operation, data input from the input / output circuit 120 is held in the page buffer / sense circuit 170, and the held data is transferred to the ECC processing unit 130. The ECC processing unit 130 performs ECC calculations on the transferred data, generates an error correction code (for example, a parity bit), and writes the generated error correction code back to the spare area of ​​the page buffer / sense circuit 170. Subsequently, the input data and error correction code are programmed into a selected page of the memory cell array 110.

[0016] During a read operation, data read from a selected page of the memory cell array 110 is transferred to the page buffer / sense circuit 170. The data held in the page buffer / sense circuit 170 is transferred to the ECC processing unit 130, which detects the presence or absence of errors based on error correction codes, and corrects any errors detected. Error correction is performed, for example, by rewriting the data held in the page buffer / sense circuit 170. Subsequently, the data held in the page buffer / sense circuit 170 is output to the outside via the input / output circuit 120.

[0017] Next, the ECC processing unit 130 will be described. The ECC processing unit 130 in this embodiment incorporates a self-test (diagnostic) function. Figure 2 is a block diagram showing the internal configuration of the ECC processing unit 130, illustrating the configuration of ECC using BCH codes. As shown in the figure, the ECC processing unit 130 consists of a memory 200, an automatic pattern generation unit (ATPG) 210, an encoder unit 220, a decoder unit 230, and a comparison unit 240. The controller 150 controls the operation of each part of the ECC processing unit 130 when executing the self-test function.

[0018] Memory 200 is a non-volatile memory, such as ROM, and stores data necessary for testing the ECC processing unit 130, such as basic data and basic parity for generating test patterns, and expected values ​​for verifying test results. When the ECC processing unit 130 is tested, the basic data and basic parity read from memory 200 are provided to the APTG 210, and the expected values ​​read from memory 200 are provided to the comparison unit 240. The controller 150 controls the reading from memory 200 so that the expected values ​​corresponding to the test patterns generated by the ATPG 210 are read.

[0019] The ATPG210 generates a test pattern based on the basic data / basic parity read from the memory 200. The test pattern is data including information bits; the test pattern provided to the encoder unit 220 is information bits without parity; and the test pattern provided to the decoder unit 230 is a codeword including both information bits and parity.

[0020] The ATPG210 can generate various types of test patterns, including error-free test patterns and test patterns containing errors. For example, the APTG210 can generate more than 100 test patterns, and the more types of test patterns there are, the higher the probability of detecting failures in the encoder unit 220 and decoder unit 230, thereby improving the reliability of the test.

[0021] A distinctive feature of this embodiment is that the ATPG210 generates test patterns by addition, multiplication, or a combination of addition and multiplication of linear codes or cyclic codes, and does not generate test patterns using an LFSR (Linear Feedback Shift Register). Addition is performed, for example, by ExOR (exclusive OR) of the data, and multiplication is performed by shifting the data. Addition and multiplication may be performed in software or hardware.

[0022] The encoder unit 220 includes a parity generation unit that generates parity bits for BCH encoding of the information bits received from the ATPG 210. That is, when a self-test is performed, the encoder unit 220 generates parity by BCH encoding the test pattern received from the ATPG 210.

[0023] The decoder unit 230 decodes the BCH-encoded test pattern (codeword) containing information bits and parity received from the ATPG 210. The decoder unit 230 includes a syndrome calculation unit 232 that evaluates the syndrome of the test pattern, a Euclidean algorithm calculation unit 234 that calculates an error location polynomial (ELP), and an error location search unit 236 that calculates the root of the error location polynomial and searches for the error location. In other words, when a self-test is performed, the decoder unit 230 decodes the test pattern received from the ATPG 210 and generates error information. The error information represents the location of the error bits.

[0024] When diagnosing the encoder unit 220, the comparison unit 240 compares the parity generated by the encoder unit 220 with the expected value received from the memory 200. If the generated parity and the expected value match, it determines that the encoder unit 220 is functioning normally; if the parity and the expected value do not match, it determines that the encoder unit 220 is abnormal or malfunctioning.

[0025] Furthermore, when diagnosing the decoder unit 230, the comparison unit 240 compares the error information generated by the decoder unit 230 with the expected value received from the memory 200. If the generated error information and the expected value match, it is determined that the decoder unit 230 is functioning normally; if the error information and the expected value do not match, it is determined that the decoder unit 230 is abnormal or malfunctioning.

[0026] The comparison unit 240 sets the determination result in a status register or the like when it determines that the encoder unit 220 or decoder unit 230 is faulty. The ECC processing unit 130 is tested, for example, during the flash memory power-up sequence or when a test command is received from the host device, and the host device can find out about the ECC processing unit 130's failure by reading the status register.

[0027] Figure 3 is a block diagram showing the internal configuration of the ATPG210. The ATPG210 includes a basic data input unit 300 that receives basic data read from memory 200, a basic data holding unit 310 that holds the basic data, an ExOR processing unit 320 that generates a test pattern by ExOR processing using the basic data, a shift processing unit 330 that generates a test pattern by shift processing using the basic data, a test pattern holding unit 340 that holds the generated test pattern, a bit inversion unit 350 that inverts one or more arbitrary bits, and a test pattern output unit 360 that outputs the test pattern to an encoder unit 220 or a decoder unit 230. These configurations are implemented by software and / or hardware.

[0028] Figure 4 is a block diagram showing the internal configuration of the comparison unit 240. The comparison unit 240 includes an expected value holding / updating unit 242 that holds or updates expected values ​​received from memory 200, a parity holding unit 244 that holds parity generated when the encoder unit 220 encodes a test pattern, an error information holding unit 246 that holds error information generated when the decoder unit 230 decodes a test pattern, and a verification unit 248 that verifies whether there is a failure or malfunction in the encoder unit 220 or the decoder unit 230 based on the comparison result between the expected value and the parity / error information. The expected value holding / updating unit 242 accumulates or updates the expected value loaded from memory 200 in accordance with the loading of basic data from the basic data input unit 310. These configurations are implemented by software and / or hardware.

[0029] Next, the method for generating test patterns by ExOR processing according to the first embodiment will be described. The generation of test patterns in this embodiment utilizes the properties of BCH codes / Reed-Solomon codes as linear codes. Linear codes have the property that the sum of any two codewords is again a codeword in the same set. For example, when x and y belong to set C, then x+y also belongs to set C. Expressed mathematically, when x∈C and y∈C, then x+y∈C (∈ means belonging to the set on the right).

[0030] By preparing a large number of error-free codes (codewords) and performing a bitwise ExOR operation on each code, a new error-free code can be obtained. Figure 5(A) illustrates the result of ExOR using the properties of linear codes. Code-A is an A without errors. n-1 X n-1 +A n-2 X n-2 This represents the data of the polynomial +...+A1X+A0. Code-B is a B without errors. n-1 X n-1 +B n-2 X n-2 This represents the data of the polynomial +...+B1X+B0. Code-C is the result of performing a bitwise ExOR (exclusive OR) operation on Code-A and Code-B, and Code-C represents error-free polynomial data.

[0031] Figure 5(B) shows an example of generating a code that contains errors. Code-A contains errors in An-1 and An-3, and Code-B contains errors in Bn-2 and Bn-3 (error bits are indicated by diagonal lines). Performing a bitwise ExOR operation on Code-A and Code-B results in Code-C containing errors in Cn-1 and Cn-2, and not containing an error in Cn-3.

[0032] The basic data input unit 310 receives basic data read from the memory 200 and transfers the data to the test pattern holding unit 340 or the ExOR processing unit 320. The ExOR processing unit 320 performs ExOR processing on the data stored in the test pattern holding unit 340 and the basic data received from the basic data input unit 310 to generate a test pattern. In one embodiment, the ExOR processing unit 320 performs bitwise ExOR processing on the first basic data having a first pattern and the second basic data having a second pattern received from the basic data input unit 310 to generate a test pattern having a third pattern. In another embodiment, the ExOR processing unit 320 performs bitwise ExOR processing on the test pattern held in the test pattern holding unit 340 and the basic data received from the basic data input unit 310 to generate a test pattern. Furthermore, in another embodiment, the bit inversion unit 350 inverts any bit of the basic data received from the basic data input unit 310 or the test pattern held in the test pattern holding unit 340, and the ExOR processing unit 320 performs ExOR processing using the bit-inverted basic data or test pattern to generate a test pattern. Bit inversion means changing from no error to error, or from error to no error.

[0033] The test pattern output unit 360 outputs the test pattern generated by the ExOR processing unit 320 to the encoder unit 220 or the decoder unit 230. The test pattern output to the encoder unit 220 is data of information bits without parity, and the test pattern output to the decoder unit 230 is data of information bits including parity. When the encoder unit 220 and the decoder unit 230 are tested simultaneously, the test pattern output unit 350 outputs the test pattern to both the encoder unit 220 and the decoder unit 230 simultaneously.

[0034] Next, the test operation of the ECC processing unit 130 in this embodiment will be described. The controller 150 controls the ECC processing unit 130 to perform a test, for example, when the flash memory is powered on.

[0035] Testing the encoder section The controller 150 controls the reading of memory 200, causes the ATPG 210 to output the basic data read from memory 200, and also causes the comparison unit 240 to output the parity corresponding to this basic data. The ATPG 210 generates a test pattern based on the basic data read from memory 200 and outputs the test pattern to the encoder unit 220. The encoder unit 220 outputs the parity generated when encoding the test pattern to the comparison unit 240. The comparison unit 240 compares the expected value read from memory 200 with the parity from the encoder unit 220, and if the two do not match, it sets a failure in the encoder unit 220 in the status register, for example. The user can find out about the failure of the encoder unit 220 by reading the status register.

[0036] Decoder section test The controller 150 controls the reading of the memory 200, causes the ATPG 210 to output the basic data read from the memory 200, and also causes the comparison unit 240 to output the expected value corresponding to the test pattern generated by the ATPG 210. The ATPG 210 generates a test pattern based on the basic data read from the memory 200 and outputs it to the decoder unit 230.

[0037] Figure 6 shows an example of generating a test pattern that does not contain errors. In step 1, the basic data Code-A loaded from memory 200 is stored as a test pattern in the test pattern holding unit 340. In other words, Code-A is the test pattern, and this is output to the decoder unit 230. In step 2, the ExOR processing unit 320 performs a bitwise ExOR operation on Code-A, which is held in the test pattern holding unit 340, and Code-B, which is loaded from memory 200, and stores the resulting data as a test pattern in the test pattern holding unit 340. In other words, Code-C, which is the ExOR result of the two basic data, is the test pattern. In step 3, the ExOR process of Code-C held in the test pattern holding unit 340 and Code-D loaded from memory 200 may be repeatedly executed to generate a test pattern. In other words, Code-E, which is the ExOR result of the three basic data, is the test pattern. Similarly, the ExOR result of four or more basic data can be used as a test pattern. In step 4, if a code with errors is required, the bit inversion unit 350 may be used to invert, for example, any bit of the test pattern Code-E. In this case, CodeE' is the test pattern.

[0038] When the test pattern generated in step 1 is used, memory 200 provides the comparison unit 240 with the expected value corresponding to that test pattern. Since the test pattern does not contain errors, the expected value is error-free information. The comparison unit 240 compares the expected value with the error information from the decoder unit 230 and verifies whether they match. In steps 2 and 3 as well, the test pattern does not contain errors, so the expected value is error-free information. In step 4, since the bit at bit position n-1 is inverted, bit position n-1 becomes the sign of an error. The expected value from memory 200 is information indicating the corrected bit position n-1. If the decoder unit 230 operates normally, the decoder unit 230 outputs error information indicating that bit position n-1 is an error.

[0039] Figure 7 shows an example of generating a test pattern containing errors. In step 1, Code-A contains an error in An-1 (shaded). The basic data Code-A loaded from memory 200 is stored in the test pattern holding unit 340 and used as the test pattern. Code-A is the test pattern, and this is output to the decoder unit 230. In step 2, the ExOR processing unit 320 performs a bitwise ExOR operation on Code-A held in the test pattern holding unit 340 and Code-B loaded from memory 200, and stores the resulting data as a test pattern in the test pattern holding unit 340. Code-B has an error in Bn-2. Code-C is a test pattern, and Cn-1 and Cn-2 have errors. In step 3, the ExOR process of Code-C held in the test pattern holding unit 340 and Code-D loaded from memory 200 may be repeated to generate a test pattern. Code-E is the test pattern, and En-1, En-2, and En-3 contain errors.

[0040] When the test pattern generated in step 1 is used, the memory 200 provides the comparison unit 240 with an expected value corresponding to that test pattern. The expected value is information representing the error bit position (n - 1). The comparison unit 240 compares the expected value with the error information from the decoder unit 230 and verifies whether they match. In steps 2 and 3, as the ExOR processing unit 320 loads the basic data from the memory 200, the comparison unit 240 also loads the expected value from the memory 200. Since the error bit positions of Code - A, Code - B, and Code - C are different, the error information accumulates. In the cases of steps 2 and 3 as well, since the test pattern contains errors, the expected value in step 2 is information representing the error bit positions (n - 1, n - 2), and the expected value in step 3 is information representing the error bit positions (n - 1, n - 2, n - 3). Similar to step 1, the comparison unit 240 compares the expected value with the error information from the decoder unit 230 and verifies whether they match.

[0041] Next, a method for generating a test pattern by shift processing according to the second embodiment will be described. The generation of the test pattern in this embodiment utilizes the property of the cyclic code of the BCH code / Reed - Solomon code. A cyclic code has the property that a cyclic permutation of a codeword results in the same set of codewords again. Expressed in a mathematical formula, when (A0, A1... An - 1, An) ∈ C, then (An, A0, A1... An - 1) ∈ C (in the case of a right shift), (A1... An - 1, An, A0) ∈ C (in the case of a left shift). However, since the code actually used is a shortened code that omits 0 data, there is a constraint that the MSB and LSB must not be 0.

[0042] Prepare a large number of codes (codewords) that do not contain errors and whose MSB is "0", and by shifting the bits of the code to the left, new codes that do not contain errors can be obtained. Figure 8(A) is an example of the generation of a code that does not contain errors. Code - A is A without error n-1 X n-1 +An-2 X n-2 This represents the data of the polynomial +...+A1X+A0, where A n-1 and A n-2 This value is 0. By shifting Code-A one bit to the left, we obtain Code-A', which does not contain errors. Although not illustrated here, Code-A may be shifted to the left, in which case the LSB, i.e., A0, must be 0.

[0043] Figure 8(B) shows an example of code generation that includes errors. Code-A contains an error in An-3. By shifting Code-A one bit to the left, we obtain Code-A' which also contains an error. At this time, the position of the error bit is also shifted one bit to the left.

[0044] In the second embodiment, the shift processing unit 330 shown in Figure 3 shifts the basic data received from the basic data input unit 310 and the test patterns held in the test pattern holding unit 340 to the left or right to generate a new test pattern. When shifting to the left, the shift processing unit 330 sets the MSB of the code to 0, and when shifting to the right, it sets the LSB of the code to 0. In addition, the bit inversion unit 350 can invert any bit, as in the first embodiment.

[0045] Figure 9 shows an example of generating a test pattern that does not contain errors (in the case of left shift). In step 1, the basic data Code-A loaded from memory 200 is stored as a test pattern in the test pattern holding unit 340. In other words, Code-A is the test pattern, and this is output to the decoder unit 230. In step 2, the shift processing unit 330 stores Code-A', which is obtained by left-shifting Code-A held in the test pattern holding unit 340, as a test pattern in the test pattern holding unit 340. In step 3, Code-A'', obtained by left-shifting Code-A' held in the test pattern holding unit 340, may be used as the test pattern. Test patterns may also be generated by repeating this left-shifting process. In step 4, if a code with errors is required, the bit inversion unit 350 may be used to obtain, for example, Code-A'' with An-5 inverted, as the test pattern.

[0046] When the test pattern generated in step 1 is used, memory 200 provides the comparison unit 240 with the expected value corresponding to that test pattern. Since the test pattern does not contain errors, the expected value is error-free information. The comparison unit 240 compares the expected value with the error information from the decoder unit 230 and verifies whether they match. In steps 2 and 3 as well, the test pattern does not contain errors, so the expected value is error-free information. In step 4, since the bit at bit position n-3 is inverted, bit position n-3 becomes the sign of an error. The expected value from memory 200 is information indicating the corrected bit position n-3. If the decoder unit 230 operates normally, the decoder unit 230 outputs error information indicating that bit position n-3 is an error.

[0047] Figure 10 shows an example of generating a test pattern without errors (in the case of a right shift). In the case of a right shift, the LSB is set to 0. The rest of the operation is the same as the left shift shown in Figure 9.

[0048] Figure 11 shows an example of generating a test pattern containing errors (in the case of left shift). In step 1, Code-A contains an error in An-3 (shaded). The basic data Code-A loaded from memory 200 is stored in the test pattern holding unit 340 and used as the test pattern. Code-A is the test pattern, and this is output to the decoder unit 230. In step 2, the shift processing unit 330 stores Code-A', obtained by left-shifting Code-A held in the test pattern holding unit 340, as a test pattern in the test pattern holding unit 340. An-3, which is shifted to bit position n-2 of Code-A', is an error. In step 3, Code-A'', obtained by left-shifting Code-A' held in the test pattern holder 340, may be used as the test pattern. An-3, which is shifted to bit position n-1 of Code-A'', is an error.

[0049] When the test pattern generated in step 1 is used, memory 200 provides the comparison unit 240 with an expected value corresponding to that test pattern. The expected value is information representing the error bit position (n-3). The comparison unit 240 compares the expected value with the error information from the decoder unit 230 and verifies whether they match. In steps 2 and 3, the error bit positions stored in the comparison unit 240 are also shifted in accordance with the shift processing unit 330 shifting the test pattern. In step 2, the expected value is information representing the error bit position (n-2), and in step 3, the expected value is information representing the error bit position (n-1). The comparison unit 240 compares the expected value with the error information from the decoder unit 230 and verifies whether they match, as in step 1.

[0050] Figure 12 shows an example of generating a test pattern that includes an error (in the case of a right shift). In the case of a right shift, the LSB is set to 0, but the other behavior is the same as the left shift shown in Figure 11.

[0051] The test pattern generation examples shown in Figures 6, 7, and 9-12 above are just examples, and the present invention is not limited thereto. The combination of basic data and generated test patterns used for ExOR processing is arbitrary. Furthermore, although the present invention has described an example in which the ExOR processing according to the first embodiment and the shift processing according to the second embodiment are performed individually, the present invention may also generate test patterns by combining ExOR processing and shift processing. For example, a new test pattern may be generated by left-shifting or right-shifting the test pattern generated by ExOR processing, or a new test pattern may be generated by ExOR processing the shifted test pattern with other basic data or generated test patterns.

[0052] While preferred embodiments of the present invention have been described in detail, the present invention is not limited to any particular embodiment, and various modifications and changes are possible within the scope of the gist of the invention as described in the claims. [Explanation of Symbols]

[0053] 100: Flash memory 130: ECC processing unit 200: Memory 210: ATPG 220: Encoder section 230: Decoder section 240: Comparison section 310: Basic data input section 320: ExOR processing unit 330: Shift processing unit 340: Test pattern holding unit 350: Bit inversion unit 360: Test pattern output section

Claims

1. An encoding means for encoding data for error detection and correction, A decoding means for decoding encoded data, The system includes a test means for testing the encoding means and the decoding means, The test means includes a storage means for storing basic data and expected values, which include at least multiple bit sequences. A generation means that generates a test pattern by performing at least ExOR processing on the basic data provided from the storage means, The system includes verification means that compares the result of the encoding means or the decoding means processing a test pattern with the expected value and verifies whether or not there is a malfunction in the encoding means or the decoding means, The verification means is an electronic circuit that updates the expected value provided by the storage means in accordance with the generation of the test pattern, and verifies the presence or absence of a fault using the updated expected value.

2. An encoding means for encoding data for error detection and correction, A decoding means for decoding encoded data, The system includes a test means for testing the encoding means and the decoding means, The test means includes a storage means for storing basic data and expected values, which include at least multiple bit sequences. A generation means that generates a test pattern by at least shifting the basic data provided from the storage means, The system includes verification means that compares the result of the encoding means or the decoding means processing a test pattern with the expected value and verifies whether or not there is a malfunction in the encoding means or the decoding means, The verification means is an electronic circuit that updates the expected value provided by the storage means in accordance with the generation of the test pattern, and verifies the presence or absence of a fault using the updated expected value.

3. The electronic circuit according to claim 1 or 2, wherein the generating means generates a test pattern by addition, multiplication, or a combination of addition and multiplication of linear codes or cyclic codes.

4. The electronic circuit according to claim 1, wherein the generation means generates a test pattern by performing bitwise ExOR processing on first basic data having a first pattern and second basic data having a second pattern.

5. The electronic circuit according to claim 4, wherein the verification means updates the expected value corresponding to the test pattern by accumulating a first expected value corresponding to the first basic data and a second expected value corresponding to the second basic data.

6. Encoding means for encoding data for error detection and correction, A decoding means for decoding encoded data, The system includes a test means for testing the encoding means and the decoding means, The test means includes a storage means for storing basic data and expected values, which include at least multiple bit sequences. A generation means that generates a test pattern by performing at least ExOR processing on the basic data provided from the storage means, The system includes verification means that compares the result of the encoding means or the decoding means processing a test pattern with the expected value and verifies whether or not there is a malfunction in the encoding means or the decoding means, The generation means is an electronic circuit that generates a test pattern by performing an ExOR operation on each bit of the generated test pattern and basic data.

7. Encoding means for encoding data for error detection and correction, A decoding means for decoding encoded data, The system includes a test means for testing the encoding means and the decoding means, The test means includes a storage means for storing basic data and expected values, which include at least multiple bit sequences. A generation means that generates a test pattern by performing at least ExOR processing on the basic data provided from the storage means, The system includes verification means that compares the result of the encoding means or the decoding means processing a test pattern with the expected value and verifies whether or not there is a malfunction in the encoding means or the decoding means, The generation means includes an inversion means for inverting bits, The generation means is an electronic circuit that generates a test pattern by performing an ExOR operation on data including bits that have been inverted by the inversion means.

8. The electronic circuit according to claim 1, wherein the test pattern has the properties of a linear code of a BCH code or a Reed-Solomon code.

9. The electronic circuit according to claim 2, wherein the generation means generates a test pattern by right-shifting or left-shifting the basic data.

10. Encoding means for encoding data for error detection and correction, A decoding means for decoding encoded data, The system includes a test means for testing the encoding means and the decoding means, The test means includes a storage means for storing basic data and expected values, which include at least multiple bit sequences. A generation means that generates a test pattern by at least shifting the basic data provided from the storage means, The system includes verification means that compares the result of the encoding means or the decoding means processing a test pattern with the expected value and verifies whether or not there is a malfunction in the encoding means or the decoding means, The generation means is an electronic circuit that generates test patterns by shifting already generated test patterns.

11. The electronic circuit according to claim 9, wherein the generating means sets the MSB to 0 when a left shift is performed and sets the LSB to 0 when a right shift is performed.

12. Encoding means for encoding data for error detection and correction, A decoding means for decoding encoded data, The system includes a test means for testing the encoding means and the decoding means, The test means includes a storage means for storing basic data and expected values, which include at least multiple bit sequences. A generation means that generates a test pattern by at least shifting the basic data provided from the storage means, The system includes verification means that compares the result of the encoding means or the decoding means processing a test pattern with the expected value and verifies whether or not there is a malfunction in the encoding means or the decoding means, The aforementioned test pattern is an electronic circuit having the properties of a cyclic code, such as a BCH code or a Reed-Solomon code.

13. A semiconductor device incorporating the electronic circuit described in claim 1 or 2.

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