Methods for manufacturing semiconductor substrates and semiconductor devices

Abstract

A method for manufacturing a semiconductor device that can improve the handling of the semiconductor device is provided. [Solution] A method for manufacturing a semiconductor device includes the steps of preparing a main substrate, a base semiconductor portion formed above the main substrate, and a compound semiconductor portion formed on the base semiconductor portion, and separating the base semiconductor portion and the compound semiconductor portion so as to form a resonator surface in at least the compound semiconductor portion, and separating the base semiconductor portion and the compound semiconductor portion into a plurality of element portions.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor substrate and the like.

Background Art

[0002] When miniaturizing a semiconductor device such as a semiconductor laser element, handling (handling) of the semiconductor device becomes difficult. Patent Document 1 describes a technique related to the handling property of a semiconductor laser element.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] A method for manufacturing a semiconductor device according to an aspect of the present disclosure includes a step of preparing a main substrate, a base semiconductor part formed above the main substrate, and a compound semiconductor part formed on the base semiconductor part, and separating the base semiconductor part and the compound semiconductor part so as to form a resonator surface at least in the compound semiconductor part, and separating the base semiconductor part and the compound semiconductor part into a plurality of element parts; and a step of separating the base semiconductor part and the compound semiconductor part to form a plurality of optical resonators each including a resonator surface. In the step of forming the plurality of optical resonators, the main substrate is not divided, or the main substrate is divided into a number less than that of the plurality of optical resonators.

[0005]

[0006] ​Furthermore, a template substrate in one aspect of the present disclosure comprises a main substrate, a seed portion, and a mask. The mask includes a longitudinally shaped opening and a mask portion, the opening having a notch.

[0007] Furthermore, a semiconductor device in one aspect of the present disclosure comprises a base semiconductor portion and a compound semiconductor portion located above the base semiconductor portion and having an optical resonator including a pair of resonator surfaces. The base semiconductor portion and the compound semiconductor portion include a GaN-based semiconductor. The base semiconductor portion includes an m-plane cleavage surface of the GaN-based semiconductor. [Brief explanation of the drawing]

[0008] [Figure 1] This is a perspective view illustrating the structure of a semiconductor laser element in one embodiment of the present disclosure. [Figure 2] This is a perspective view illustrating the optical resonator of a semiconductor laser element. [Figure 3] This flowchart shows an example of a method for manufacturing a semiconductor laser element in one embodiment of the present disclosure. [Figure 4] These are a plan view and a cross-sectional view showing the configuration of a template substrate in one embodiment of the present disclosure. [Figure 5] This is a cross-sectional view illustrating a semiconductor substrate in one embodiment of the present disclosure. [Figure 6A] This is a plan view illustrating an example of the element isolation process. [Figure 6B] This is a cross-sectional view taken along the line B-VI shown in Figure 6A. [Figure 7] This flowchart shows an example of the mounting stage of a semiconductor laser element manufacturing method in one embodiment of the present disclosure. [Figure 8] This is a block diagram showing an example of manufacturing equipment. [Figure 9] This is a flowchart showing an example of a method for manufacturing a semiconductor laser element in Example 1. [Figure 10]It is a cross-sectional view showing the configuration of the template substrate in Example 1. [Figure 11A] It is an enlarged view of the main part of FIG. 10. [Figure 11B] It is a plan view showing an example of the starting point inducing portion in Example 1. [Figure 11C] It is a plan view showing another example of the starting point inducing portion in Example 1. [Figure 11D] It is a plan view showing another example of the starting point inducing portion in Example 1. [Figure 11E] It is a plan view showing another example of the starting point inducing portion in Example 1. [[ID=1*]] [Figure 12] It is a cross-sectional view showing an example of the lateral growth of the base semiconductor layer in Example 1. [Figure 13] It is a plan view for explaining the base semiconductor layer in Example 1. [Figure 14] It is an enlarged view for explaining the growth state of the base semiconductor layer around the starting point inducing portion in Example 1. [Figure 15] It is a cross-sectional view showing the configuration of the compound semiconductor layer in Example 1. [Figure 16] It is a plan view for explaining the compound semiconductor layer in Example 1. [Figure 17] It is a plan view for explaining an example of the element isolation process in Example 1. [Figure 18] It is an exploded perspective view for explaining the configuration of the semi-element portion in Example 1. [Figure 19] It is a perspective view for explaining the configuration of the element portion in Example 1. [Figure 20] It is a cross-sectional view showing the configuration of the element portion in Example 1. [Figure 21] It is a cross-sectional view schematically showing the process of separating the element portion from the template substrate in the manufacturing method of the semiconductor laser element of Example 1. [Figure 22] It is a perspective view schematically showing the state where the element portion is joined to the support substrate. [Figure 23]It is a cross-sectional view schematically showing a state in which an element portion DS is joined to a support substrate SK. [Figure 24] It is a cross-sectional view schematically showing a process of forming a reflective film on a resonator surface in a method for manufacturing a semiconductor laser element of Example 1. [Figure 25] It is a plan view showing a configuration of a compound semiconductor layer after forming a mirror film. [Figure 26] It is a cross-sectional view schematically showing a process of dividing a support substrate in a method for manufacturing a semiconductor laser element of Example 1. [Figure 27] It is a plan view for explaining another example of a base semiconductor layer in Example 1. [Figure 28] It is an exploded perspective view for explaining another configuration example of a semi-element portion in Example 1. [Figure 29] It is a cross-sectional view showing a configuration of a semiconductor laser element in Example 2. [Figure 30] It is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor laser element in Example 2. [Figure 31] It is a flowchart showing an example of a method for manufacturing a semiconductor laser element in Example 3. [Figure 32] It is a plan view showing a configuration of a semiconductor substrate on which a base semiconductor layer is formed in Example 3. [Figure 33] It is a plan view showing a configuration of a semiconductor substrate on which an element structure is formed in Example 3. [Figure 34] It is a cross-sectional view showing a configuration of the semiconductor substrate of FIG. 33. [Figure 35] It is a plan view showing an example of element isolation in Example 4. [Figure 36] It is a schematic diagram showing a configuration of an electronic device in Example 5.

Embodiments for Carrying Out the Invention

[0009] Embodiments of this disclosure will be described below with reference to the drawings. The following description is intended to help you better understand the intent of this disclosure and does not limit this disclosure unless otherwise specified. Unless otherwise specified in this specification, "A to B" representing a numerical range means "A or greater and B or less". In addition, the shapes and dimensions (length, width, etc.) of the configurations shown in each drawing in this application do not necessarily reflect the actual shapes and dimensions and have been modified as appropriate for clarity and simplification of the drawings.

[0010] In the embodiments of this disclosure, a semiconductor laser (laser diode; LD) element is described as an example of a semiconductor device, but the semiconductor devices of this disclosure are not necessarily limited to this. The semiconductor devices of this disclosure may be, for example, a sensor having an optical resonator or a sensor having a resonator surface formed thereon.

[0011] In the following description, first, the structure of the semiconductor laser element in one embodiment of the present disclosure will be described in general terms, and then the method for manufacturing the semiconductor laser element in one embodiment of the present disclosure will be described in detail.

[0012] [Semiconductor laser element] A semiconductor laser element 20 in one embodiment of this disclosure will be described below with reference to Figures 1 and 2. Figure 1 is a perspective view illustrating the structure of the semiconductor laser element 20. Figure 2 is a perspective view illustrating the optical resonator LK of the semiconductor laser element 20. Note that Figure 1 is illustrative, and the semiconductor laser element 20 may have a shape in which the depth direction in the perspective view shown in Figure 1 is the longitudinal direction.

[0013] In one embodiment of this disclosure, the semiconductor laser element 20 has a structure having electrodes on the upper and lower sides (hereinafter referred to as a "double-sided electrode structure"), but is not limited thereto. For example, it may have a structure having two electrodes (anode and cathode) on the upper side (hereinafter referred to as a "single-sided two-electrode structure"). The semiconductor laser element 20 may also be mounted on a support substrate (also referred to as a submount), and in Figure 1, the support substrate is omitted from the illustration.

[0014] As shown in Figures 1 and 2, the semiconductor laser element (semiconductor device) 20 in this embodiment comprises a base semiconductor portion 8, a compound semiconductor portion 9 located above the base semiconductor portion 8 and including an optical resonator LK, a first electrode E1, a second electrode E2, and an insulating film DF. In the optical resonator LK, the surface from which the laser is emitted is defined as the emission surface F1, and the surface opposite the emission surface F1 is defined as the opposing surface F2. The emission surface F1 and the opposing surface F2 are a pair of resonator surfaces in the optical resonator LK. The specific form (element structure) of the optical resonator LK is not particularly limited.

[0015] The base semiconductor portion 8 and the compound semiconductor portion 9 are typically layered. Therefore, the base semiconductor portion 8 can also be called the base semiconductor layer 8, and the compound semiconductor portion 9 can also be called the compound semiconductor layer 9. In the following explanation, we will refer to them as the base semiconductor layer 8 and the compound semiconductor layer 9, but the base semiconductor layer 8 and the compound semiconductor layer 9 are not necessarily limited to being layered.

[0016] The base semiconductor layer 8 may include, for example, a nitride semiconductor. Nitride semiconductors can be represented as AlxGayInzN (0≦x≦1;0≦y≦1;0≦z≦1;x+y+z=1), and specific examples include gallium nitride (GaN) semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). GaN semiconductors are semiconductors containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN. The base semiconductor layer 8 may be a doped layer (e.g., an n-type layer containing a donor) or an undoped layer.

[0017] Furthermore, the compound semiconductor layer 9 may include, for example, the above-mentioned nitride semiconductor. Generally, it is difficult to reduce the defect density of nitride semiconductors. If the surface defects of the base semiconductor layer 8 are few, the number of dislocations (defects) transferred from the base semiconductor layer 8 to the compound semiconductor layer 9 will be fewer. This can reduce the defect density of the compound semiconductor layer 9. The semiconductor laser element 20 in this embodiment may have a semiconductor layer formed by the ELO (Epitaxial Lateral Overgrowth) method (hereinafter sometimes referred to as the ELO semiconductor layer) as the base semiconductor layer 8. Note that the base semiconductor layer 8 is not limited to the ELO semiconductor layer, as it is not limited to any layer that can reduce the defect density of the optical resonator LK of the compound semiconductor layer 9.

[0018] The method for manufacturing the base semiconductor layer 8 is not particularly limited; for example, the base semiconductor layer 8 may be a general semiconductor layer containing a nitride semiconductor. This "general semiconductor layer" refers to a semiconductor layer that has been epitaxially grown in the longitudinal direction on a growth substrate. In this specification, such a general semiconductor layer may be referred to as a "GE semiconductor layer" for convenience of explanation. Since the GE semiconductor layer can be formed by known methods, a detailed explanation is omitted.

[0019] Furthermore, in this specification, a substrate used to grow various semiconductor layers of a semiconductor laser element may be referred to as a "growth substrate."

[0020] In this embodiment, a semiconductor laser element 20 in which the base semiconductor layer 8 is an ELO semiconductor layer will be described, as shown in Figure 1. The manufacturing method of the base semiconductor layer 8 using the ELO method will be described later.

[0021] The base semiconductor layer 8, which is an ELO semiconductor layer, includes a first part (first section) B1, and a second part (second section) B2 and a third part (third section) B3, the second and third sections having a density of through-dislocations KD extending in the thickness direction (Z direction) that is smaller than that of the first part (B1). The second part (B2), the first part (B1), and the third part (B3) are arranged in this order in the X direction, with the first part (B1) located between the second part (B2) and the third part (B3). A through-dislocation KD is a dislocation (defect) that extends along the thickness direction of the base semiconductor layer 8 from the bottom surface or interior of the base semiconductor layer 8 to its surface or surface layer. The through-dislocation density of the second part (B2) and the third part (B3) is less than or equal to 1 / 5 of the through-dislocation density of the first part (e.g., 5 × 10⁻¹⁰). 6 / cm 2 The following may be the case.

[0022] In the semiconductor laser element 20, compound semiconductor layers 9, which include multiple layers, are stacked on a base semiconductor layer 8, and this stacking direction can be referred to as the "upward direction." Hereafter, the positive Z-axis side of the XYZ coordinate axes shown in Figure 1 will be referred to as the "upper side," and the negative Z-axis side will be referred to as the "lower side." Also, the face of each component on the positive Z-axis side will be referred to as the "upper surface," and the face of each component on the negative Z-axis side will be referred to as the "lower surface." For substrate-like or nearly substrate-like objects such as the semiconductor laser element 20, viewing the object from a line of sight parallel to the normal direction of the upper surface can be referred to as a "planar view." Although not explained repeatedly below, in other figures as well, the up and down directions will be defined, and the expression "in a planar view" will be used.

[0023] The compound semiconductor layer 9 contains, in order from the base semiconductor layer 8 upwards, an n-type semiconductor portion (first-type semiconductor portion) 9N, an active portion 9K, and a p-type semiconductor portion (second-type semiconductor portion) 9P. The n-type semiconductor portion 9N, the active portion 9K, and the p-type semiconductor portion 9P are typically layered. Therefore, the n-type semiconductor portion 9N can also be called an n-type semiconductor layer 9N. The active portion 9K can also be called an active layer 9K. The p-type semiconductor portion 9P can also be called a p-type semiconductor layer 9P. In the following explanation, we will refer to them as the n-type semiconductor layer 9N, the active layer 9K, and the p-type semiconductor layer 9P, but the n-type semiconductor layer 9N, the active layer 9K, and the p-type semiconductor layer 9P are not necessarily limited to being layered.

[0024] The p-type semiconductor layer 9P may have a ridge portion RJ. The n-type semiconductor layer 9N, the active layer 9K, and the p-type semiconductor layer 9P may contain the nitride semiconductor described above. The various layers included in the compound semiconductor layer 9 will be described in detail later. The compound semiconductor layer 9 may have a higher threading dislocation density above the first part B1 due to the influence of the first part B1 of the base semiconductor layer 8.

[0025] The compound semiconductor layer 9 has an optical resonator LK at a position that overlaps with the second part B2 in a plan view. The optical resonator LK includes a waveguide that extends between the exit surface F1 and the opposing surface F2, which constitute a pair of resonator surfaces. The distance between the exit surface F1 and the opposing surface F2 can be defined as the resonator length (resonance length) L1 of the optical resonator LK. The end faces of the active layer 9K included in the exit surface F1 and the end faces of the active layer 9K included in the opposing surface F2 may each be coated with a reflective film (e.g., a dielectric film).

[0026] The semiconductor laser element 20 may have at least one of its output surface F1 and opposing surface F2 be the m-plane or c-plane of the compound semiconductor layer 9 containing a nitride semiconductor. In Figure 1 and other figures, the positive X-axis direction can be the [11-20] direction of the nitride semiconductor, the positive Y-axis direction can be the [-1100] direction of the nitride semiconductor, and the positive Z-axis direction (thickness direction) can be the

[0001] direction of the nitride semiconductor. The m-plane that at least one of the output surface F1 and opposing surface F2 may have is a plane parallel to the (1-100) plane (or (-1100) plane) of the nitride semiconductor. The c-plane that at least one of the output surface F1 and opposing surface F2 may have is a plane parallel to the (0001) plane of the nitride semiconductor.

[0027] The semiconductor laser element 20 may have at least one of its output surface F1 and opposing surface F2 included in the cleavage plane of the compound semiconductor layer 9. Alternatively, each of the output surface F1 and opposing surface F2 may be included in the cleavage plane of the compound semiconductor layer 9. The semiconductor laser element 20 may also have a resonator length L1 of 200 [μm] or less.

[0028] The semiconductor laser element 20 is provided with a first electrode E1 and a second electrode E2 for supplying current to the optical resonator LK. The first electrode E1 can be positioned so as to overlap with the optical resonator LK in a plan view in the thickness direction of the base semiconductor layer 8. In a plan view, "two components overlap" means that at least a part of one component overlaps with the other component in a plan view (including a perspective plan view) in the thickness direction of each component, and these components may or may not be in contact with each other.

[0029] The first electrode E1 is located above the compound semiconductor layer 9, overlaps with at least a portion of the ridge RJ in a plan view, and may have a shape that extends along the longitudinal direction of the optical resonator LK. The first electrode E1 is electrically connected to the ridge RJ in the p-type semiconductor layer 9P and functions as an anode. The first electrode E1 and the ridge RJ may be in contact with each other or connected via another layer.

[0030] The second electrode E2 may be located below the compound semiconductor layer 9, for example, on the underside of the base semiconductor layer 8. In a plan view, the second electrode E2 may have a shape that overlaps with at least a portion of the first electrode E1. The second electrode E2 is electrically connected to the base semiconductor layer 8 and functions as a cathode. The second electrode E2 and the base semiconductor layer 8 may be in contact with each other or connected via another layer. The second electrode E2 may be in contact with the compound semiconductor portion 9 (for example, the n-type semiconductor layer 9N).

[0031] The insulating film DF is located above the compound semiconductor layer 9. The insulating film DF may cover the upper surface of the p-type semiconductor layer 9P, except for the contact portion between the first electrode E1 and the ridge portion RJ.

[0032] [Manufacturing of semiconductor laser devices] Semiconductor lasers are sometimes manufactured from a laminate containing multiple semiconductor layers (referred to as the conventional CT method). In the conventional CT method, multiple semiconductor lasers are formed on a growth substrate, and these multiple semiconductor lasers are separated along with the growth substrate.

[0033] The inventors diligently studied methods different from conventional CT methods and conceived the semiconductor laser element manufacturing method of this disclosure. The semiconductor laser element 20 in this embodiment is manufactured by a method that includes the step of forming an optical resonator on a growth substrate (forming a resonator surface on at least the compound semiconductor layer 9).

[0034] The following describes a method for manufacturing a semiconductor laser element (a semiconductor laser element in which the base semiconductor layer 8 is an ELO semiconductor layer) according to one embodiment of this disclosure. Figure 3 is a flowchart showing an example of a method for manufacturing a semiconductor laser element according to this embodiment. Figure 4 is a plan view and a cross-sectional view showing the configuration of a template substrate according to this embodiment.

[0035] (Preparing the template board) As shown in Figure 3, in a method for manufacturing a semiconductor laser element according to one embodiment of the present disclosure, a template substrate is first prepared. As shown in Figure 4, the template substrate 7 in this embodiment has a main substrate 1, a base portion 4 located above the main substrate 1, and a mask 6 located above the main substrate 1 and having an opening KS and a mask portion 5. Hereinafter, the main substrate 1 and the base portion 4 together may be referred to as the base substrate UK. This base substrate UK and template substrate 7 are examples of the growth substrates described above.

[0036] The base layer 4 and the mask layer 6 are typically layered. Therefore, the base layer 4 can also be called the base layer 4, and the mask layer 6 can also be called the mask layer 6. In the following explanation, we will refer to them as the base layer 4 and the mask layer 6, but the base layer 4 and the mask layer 6 are not necessarily limited to being layered. The mask layer 6 may be a mask pattern that includes a mask portion 5 and an opening KS. The opening KS is a region where the mask portion 5 does not exist, and the opening KS does not necessarily have to be surrounded by the mask portion 5.

[0037] The main substrate 1 can be a heterogeneous substrate having a different lattice constant from the nitride semiconductor. Examples of heterogeneous substrates include silicon (Si) substrates, sapphire (Al2O3) substrates, silicon carbide (SiC) substrates, etc. The surface orientation of the main substrate 1 is, for example, the (111) plane for a Si substrate, the (0001) plane for an Al2O3 substrate, and the 6H-SiC(0001) plane for a SiC substrate. However, these are examples, and the main substrate 1 is not particularly limited as long as it is a substrate and surface orientation on which the base semiconductor layer 8 can be grown by the ELO method.

[0038] The template substrate 7 may have a buffer section 2 and a seed section 3 as the base layer 4, in that order from the main substrate 1 side. The buffer section 2 and seed section 3 are typically layered. Therefore, the buffer section 2 can also be called the buffer layer 2, and the seed section 3 can also be called the seed layer 3. In the following explanation, we will refer to them as the buffer layer 2 and the seed layer 3, but the buffer layer 2 and the seed layer 3 are not necessarily limited to being layered.

[0039] The buffer layer 2 is a melting suppression layer that reduces the possibility of the main substrate 1 and the seed layer 3 directly contacting and melting each other. It also has the effect of improving the crystallinity of the seed layer 3. The seed layer 3 is the starting point for the growth of the base semiconductor layer 8 when the base semiconductor layer 8, which will be described later, is deposited. For example, if a main substrate 1 that does not melt with the seed layer 3, which is a GaN-based semiconductor, is used, it is possible to omit the buffer layer 2. On the other hand, if a Si substrate or the like is used for the main substrate 1, the GaN-based semiconductor contained in the seed layer 3 and the Si substrate may melt each other if they come into contact. Therefore, a buffer layer 2, such as an AlN layer or a SiC layer, is provided. This reduces the possibility of the GaN-based semiconductor and the Si substrate melting.

[0040] The mask layer 6 formed on the substrate UK has a plurality of mask portions 5 and a plurality of openings KS. Both the mask portions 5 and the openings KS may have a longitudinal shape with the first direction (X direction) being the width direction and the second direction (Y direction) being the longitudinal direction. The openings KS may also have a tapered shape (a shape in which the width narrows towards the bottom). An inorganic insulating film such as a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, a silicon oxynitride (SiON) film, or a titanium nitride (TiNx) film can be used as the mask layer 6. A laminated film containing the above materials may also be used for the mask layer 6, for example, a laminated film containing a silicon oxide film and a silicon nitride film can be used.

[0041] The mask layer 6 may be formed, for example, as follows: an SiO2 film is formed over the entire surface of the substrate UK using a sputtering method, and then wet etching is performed while partially protecting it with a resist. By removing a portion of the SiO2 film, the mask portion 5 and the opening KS are formed.

[0042] The opening KS of the mask layer 6 functions as a growth initiation hole that exposes the seed layer 3 and initiates the growth of the base semiconductor layer 8, while the mask portion 5 of the mask layer 6 functions as a selective growth mask that allows the base semiconductor layer 8 to grow laterally. The width WK of the opening KS may be, for example, about 0.1 μm to 20 μm. The smaller the width of the opening KS, the fewer the number of through-dislocations that propagate from the opening KS to the base semiconductor layer 8. Furthermore, peeling of the base semiconductor layer 8 in subsequent processes may become easier. In addition, the area of ​​the second portion B2 and the third portion B3, which have fewer surface defects, can be increased. The width WM of the mask portion 5 may be, for example, about 25 μm to 200 μm.

[0043] In the semiconductor laser element manufacturing method of this embodiment, for example, in the step of preparing the template substrate 7, the mask layer 6 may be formed such that the opening KS has a notch shape, in other words, the mask portion 5 partially protrudes in the X direction. Hereinafter, the portion of the mask portion 5 that partially protrudes in the X direction will be referred to as the initiation point initiation portion. By having the initiation point initiation portion in the mask layer 6, the base semiconductor layer 8 and the compound semiconductor layer 9 can be formed on the template substrate 7 such that they have an initiation point portion that serves as the starting point for cleavage. Details will be explained in Example 1 below.

[0044] (Process for forming a semiconductor layer) Figure 5 is a cross-sectional view illustrating the semiconductor substrate in this embodiment. A method for manufacturing a semiconductor laser element in one aspect of this disclosure may include a step of forming a semiconductor layer (see Figure 3). In the step of forming the semiconductor layer, for example, a base semiconductor layer 8 is formed on a template substrate 7 by the ELO method, and then a compound semiconductor layer 9 is formed above the base semiconductor layer 8.

[0045] In the ELO method, for example, a seed layer 3 containing a GaN-based semiconductor is used, and an inorganic compound film such as an SiO2 film is used as the mask layer 6, allowing a base semiconductor layer 8 to be grown laterally on the mask portion 5. The thickness direction (Z direction) of the base semiconductor layer 8 formed by the ELO method is the GaN-based crystal <0001> The direction (c-axis direction) and the width direction (X direction) of the aperture KS can be the <11-20> direction (a-axis direction) of the GaN-based crystal, and the longitudinal direction (Y direction) of the aperture KS can be the <1-100> direction (m-axis direction) of the GaN-based crystal.

[0046] As shown in Figure 5, the base semiconductor layer 8 includes a second part B2 and a third part B3 that overlap with the mask part 5 in a plan view and have relatively few threading dislocations KD, and a first part B1 that overlaps with the opening KS in a plan view and has more threading dislocations KD than the second part B2 and the third part B3. The compound semiconductor layer 9 is affected by the threading dislocations KD present on the surface of the first part B1 and contains many threading dislocations KD above the first part B1. The optical resonator LK can be provided so as to overlap with the second part B2 in a plan view. This reduces the possibility that the performance of the optical resonator LK will be degraded due to the influence of threading dislocations KD. This is because, in the compound semiconductor layer 9 on the second part B2, the amount of dislocations (defects) introduced due to surface defects in the second part B2 during the deposition of the compound semiconductor layer 9 is relatively small.

[0047] A threading dislocation (KD) is a dislocation (defect) that extends from the bottom surface or interior of the base semiconductor layer 8 to its surface or surface layer along the thickness direction of the base semiconductor layer 8. Threading dislocations (KDs) can be observed on the surface (parallel to the c-plane) of the base semiconductor layer 8, for example, by performing a CL (Cathode luminescence) measurement.

[0048] Part 2B2 or Part 3B3 is <0001> A configuration can be achieved in which the non-penetrating dislocation density in a cross-section parallel to the direction is greater than the penetrating dislocation density on the top surface. Non-penetrating dislocations are dislocations measured by CL in a cross-section with a plane parallel to the thickness direction, and are mainly basal plane (c-plane) dislocations.

[0049] The semiconductor substrate 10 in this embodiment may have a template substrate 7 and a base semiconductor layer 8 formed on the template substrate 7. Alternatively, the semiconductor substrate 10 may have a template substrate 7, a base semiconductor layer 8, and a compound semiconductor layer 9 formed above the base semiconductor layer 8.

[0050] In the semiconductor substrate 10 of this embodiment, a plurality of base semiconductor layers 8 are formed with a gap Gp between different base semiconductor layers 8. The width WG of the gap Gp may be 4 μm or less, or 3 μm or less. The semiconductor substrate 10 is not limited to having a gap Gp; the base semiconductor layers 8 that have grown laterally from seed layers 3 exposed at two adjacent openings KS may be in contact (meet) on the mask portion 5.

[0051] When forming the base semiconductor layer 8 using the ELO method, a template substrate 7 including a main substrate 1 and a mask layer 6 on the main substrate 1 may be used, and the template substrate 7 may have a growth suppression region corresponding to the mask portion 5 (for example, a region that suppresses crystal growth in the Z direction) and a seed region corresponding to the opening KS. For example, the growth suppression region and the seed region can be formed on the main substrate 1, and the base semiconductor layer 8 can be formed on the growth suppression region and the seed region using the ELO method.

[0052] (Process of separating elements on a template substrate) Figure 6A is a plan view illustrating an example of the element isolation process. Figure 6B is a cross-sectional view taken along the line B-VI shown in Figure 6A.

[0053] In the semiconductor laser element manufacturing method of this embodiment, the base semiconductor layer 8 and the compound semiconductor layer 9 may be separated into a plurality of semi-element parts (first element parts) sDS on the template substrate 7 so as to form a resonator surface on at least the compound semiconductor layer 9. Here, "semi-element part sDS" means a portion (laminated structure) that includes one piece 8V of the base semiconductor layer 8 and one piece 9V of the compound semiconductor layer 9 located above the piece 8V of the base semiconductor layer 8, which are among a plurality of individual pieces aligned along the Y-axis direction formed by dividing the base semiconductor layer 8 and the compound semiconductor layer 9 on the template substrate 7. A semi-element part sDS can be considered a type of element, but in that it does not have components such as electrodes for driving as an element, it may be positioned as a semi-finished product, in a state in the process of manufacturing an element as a product. Such a semi-element part sDS also falls within the scope of semiconductor devices of this disclosure. The boundary between adjacent semi-element parts sDS is called a dividing portion PS, and in Figures 6A and 6B, the dividing portion PS is shown by a thick black line.

[0054] In this specification, the separation of the base semiconductor layer 8 and the compound semiconductor layer 9 into a plurality of semi-element parts sDS on the template substrate 7 may be referred to as "element separation." "Element separation" means (i) and (ii) below. (i) When the base semiconductor layer 8 and the compound semiconductor layer 9 are separated on the template substrate 7, each of the multiple semi-element parts sDS has an optical resonator LK individually (in other words, each of the multiple semi-element parts sDS has a resonator surface formed on at least the compound semiconductor layer 9 individually). (ii) The base semiconductor layer 8 (8V) and compound semiconductor layer 9 (9V) of the semi-element portion sDS are not further divided during the process from the semi-element portion sDS to the element portion (second element portion) DS.

[0055] Figure 6B illustrates various forms of the divided portion PS, but is not limited thereto. As shown in Figure 6B, in the process of separating elements on the template substrate 7, part or all of the mask portion 5 in the thickness direction of the semiconductor substrate 10 may be divided in the divided portion PS, the mask portion 5 may not be divided, or the mask portion 5 and the underlayer 4 may be divided. In this process, the entire thickness direction of the main substrate 1 may not be divided. In addition, cracks may occur in a part of the thickness direction of the main substrate 1.

[0056] In the semiconductor laser element manufacturing method of this embodiment, the specific method for separating the element on the template substrate 7 is not particularly limited. For example, as described above, the mask layer 6 may be formed such that the mask portion 5 has a starting point induction portion, and then the base semiconductor layer 8 may be formed. In this case, the base semiconductor layer 8 may have a starting point portion, which is a portion that is prone to becoming the starting point for cleavage. Also, similar to the base semiconductor layer 8, the compound semiconductor layer 9 may also have a starting point portion for cleavage. Multiple semi-element portions sDS may be formed by cleavage occurring from the starting point portion due to thermal stress or physical external force. In addition, cleavage may be caused in the base semiconductor layer 8 before forming the compound semiconductor layer 9. In this case, after cleaving the base semiconductor layer 8, the compound semiconductor layer 9 may be formed on each of the multiple pieces of the base semiconductor layer 8. The element can be separated into multiple semi-element portions sDS by cleaving or dividing the compound semiconductor layer 9.

[0057] Furthermore, for example, the mask portion 5 does not necessarily have a starting point induction portion. In this case, a starting point for cleavage may be formed in the base semiconductor layer 8 or the compound semiconductor layer 9 by processing such as scribing. Cleavage may be induced from the starting point by applying an external force to at least one of the base semiconductor layer 8 and the compound semiconductor layer 9. Alternatively, scribing the compound semiconductor layer 9 may cause cleavage to proceed naturally due to the internal stress in the base semiconductor layer 8 and the compound semiconductor layer 9.

[0058] Furthermore, for example, the base semiconductor layer 8 or the compound semiconductor layer 9 can be etched to separate the element into multiple semi-element portions sDS, in which case the divided portion PS may be a trench formed by etching.

[0059] As described above, the method for manufacturing a semiconductor laser element in this embodiment may include the steps of: (i) preparing a main substrate 1, a base semiconductor portion 8 formed above the main substrate 1, and a compound semiconductor portion 9 formed on the base semiconductor portion 8; and (ii) separating the base semiconductor portion 8 and the compound semiconductor portion 9 so as to form a resonator surface on at least the compound semiconductor portion 9, and separating the base semiconductor portion 8 and the compound semiconductor portion 9 into a plurality of element portions (e.g., semi-element portions sDS). In the step of separating into a plurality of element portions, the element separation may be performed on a growth substrate (e.g., on a template substrate 7) into a plurality of semi-element portions sDS having resonator surfaces (e.g., an exit surface F1 and a facing surface F2). By separating the base semiconductor layer 8 and the compound semiconductor layer 9 into a plurality of element portions (e.g., semi-element portions sDS), an optical resonator LK including a resonator surface (e.g., an exit surface F1 and a facing surface F2) may be formed.

[0060] Furthermore, the method for manufacturing a semiconductor laser element in this embodiment includes the steps of (i) preparing a main substrate 1, a base semiconductor portion 8 formed above the main substrate 1, and a compound semiconductor portion 9 formed on the base semiconductor portion 8, and (ii) dividing the base semiconductor portion 8 and the compound semiconductor portion 9 to form a plurality of optical resonators LK, each including a resonator surface (e.g., an output surface F1 and an opposing surface F2). For example, the base semiconductor layer 8 and the compound semiconductor layer 9 may be divided on a growth substrate (e.g., on a template substrate 7) to form a plurality of optical resonators LK, each including a resonator surface. In the step of forming the plurality of optical resonators LK, the main substrate 1 does not need to be divided, or the main substrate 1 may be divided into fewer pieces than the plurality of optical resonators LK. For example, the main substrate 1 may be divided such that one of the plurality of pieces formed by dividing the main substrate 1 has a plurality of semi-element portions sDS on it.

[0061] According to the semiconductor laser element manufacturing method of this embodiment, even when the semiconductor laser element 20 is miniaturized, it is possible to easily form the resonator surface. Therefore, it is possible to easily form the optical resonator LK. Then, as described later, by peeling the formed element portion DS from the growth substrate, the element portion DS can be mounted on a support substrate to manufacture the semiconductor laser element 20. This improves handling. In addition, a substrate suitable for mounting can be used as the support substrate.

[0062] (Process for forming the element structure) In the semiconductor laser element manufacturing method of this embodiment, a step is performed to form an element structure on the semi-element portion sDS on the template substrate 7. This forms the element portion DS. At this stage, the base semiconductor layer 8 included in the element portion DS is van der Waals coupled with the mask portion 5, and the element portion DS may be part of the semiconductor substrate 10.

[0063] In the process of forming the device structure, for example, a ridge portion RJ is formed in the p-type semiconductor layer 9P of the compound semiconductor layer 9, then an insulating film DF is formed, and then a first electrode E1 (anode) is formed at a position in contact with the ridge portion RJ. Then, for example, if the semiconductor laser device 20 has a single-sided two-electrode structure, a second electrode E2 may be formed on the upper surface of the base semiconductor layer 8 after exposing a part of the upper surface of the base semiconductor layer 8 by etching or the like. This allows for the formation of the device portion DS. In the device portion DS, by providing the ridge portion RJ and the insulating film DF, the current path between the first electrode E1 and the base semiconductor layer 8 is narrowed on the anode side, allowing for efficient light emission within the resonator LK. Furthermore, the ridge portion RJ may overlap with the second portion B2 (low dislocation portion) of the base semiconductor portion 8 in a plan view, but may not overlap with the first portion B1. The second electrode E2 may overlap with the second portion B2 (low dislocation portion) of the base semiconductor portion 8 in a plan view. As a result, the current path from the first electrode E1 through the compound semiconductor portion 9 and the base semiconductor portion 8 to the second electrode E2 is formed in a region that overlaps with the second portion B2 in a plan view (a region with few threading dislocations), thereby increasing the luminescence efficiency in the active layer 9K. This is because threading dislocations act as non-luminescent recombination centers. Furthermore, the second electrode E2 may overlap with the second portion B2 and the third portion B3 (low-dislocation region) of the base semiconductor portion 8 in a plan view, in which case the electron injection efficiency from the second electrode E2 to the base semiconductor portion 8 is increased.

[0064] If the semiconductor laser element 20 has a double-sided electrode structure, a second electrode E2 may be formed in a later process. In this specification, an element having an element structure without a second electrode E2, obtained by the process of forming the element structure, is also referred to as the element section DS.

[0065] (Process of mounting the component part) Figure 7 is a flowchart showing an example of the mounting stage of the semiconductor laser element manufacturing method in this embodiment.

[0066] As shown in Figure 7, first, the element unit DS is separated from the template substrate 7. For example, after bonding the first electrode E1 to the pad of the support substrate, the element unit DS can be separated from the template substrate 7 using the support substrate. Subsequently, the semiconductor laser element 20 may be formed by coating the end face of the optical resonator LK of the element unit DS. Alternatively, the support substrate on which the element unit DS is mounted may be divided to form the semiconductor laser element 20. The support substrate may function as a submount, thereby enabling the formation of a chip on which the semiconductor laser element 20 is mounted on the divided support substrate. A specific example of the support substrate will be described later.

[0067] According to the manufacturing method for the semiconductor laser element 20 in this embodiment, the template substrate 7 or the base substrate UK can be reused. Furthermore, the element portion DS can be transferred from a substrate unsuitable for mounting to a substrate suitable for mounting (support substrate) to form the semiconductor laser element 20.

[0068] [Manufacturing equipment] Figure 8 is a block diagram showing an example of a manufacturing apparatus. As shown in Figure 8, the manufacturing apparatus 70 includes a semiconductor layer formation unit 72 that forms a base semiconductor layer 8 and a compound semiconductor layer 9 on a template substrate 7, a processing unit 73 that forms an element structure, and a control unit 74 that controls the semiconductor layer formation unit 72 and the processing unit 73.

[0069] The semiconductor layer formation unit 72 may include, for example, a MOCVD (Metal-Organic Chemical Vapor Deposition) apparatus, and forms a base semiconductor layer 8 using the ELO method, and forms a compound semiconductor layer 9 on the base semiconductor layer 8. When the object to be processed is removed from the processing apparatus (film deposition apparatus) such as the MOCVD apparatus, a device separation step may be performed. The semiconductor layer formation unit 72 may be controlled to remove the object to be processed from the processing apparatus after forming the base semiconductor layer 8, and then put the object to be processed back into the processing apparatus to form the compound semiconductor layer 9 on the base semiconductor layer 8. The semiconductor layer formation unit 72 may also have a function to manufacture a template substrate 7.

[0070] The processing unit 73 may perform an element separation process to form a semi-element portion sDS. The processing unit 73 performs various processes on the semi-element portion sDS located on the template substrate 7 to form an element portion DS. The processing unit 73 may perform a process to separate the element portion DS from the template substrate 7 using a support substrate, or it may perform a process to coat the end face of the optical resonator LK.

[0071] The control unit 74 may include a processor and memory. The control unit 74 may also be configured to control the semiconductor layer formation unit 72 and the processing unit 73 by executing a program stored, for example, in built-in memory, a communication device, or an accessible network. The above-mentioned program and the recording medium on which the above-mentioned program is stored are also included in this embodiment.

[0072] [Other embodiments] (a) In the manufacturing method of the semiconductor laser element 20 in other embodiments of the present disclosure, a GaN substrate may be used as the growth substrate instead of the base substrate UK, in which case the main substrate 1 may be a GaN substrate. That is, the main substrate 1 may be the growth substrate. A semiconductor substrate may also be used in which a semiconductor layer containing a nitride semiconductor (the aforementioned GE semiconductor layer) is formed on the GaN substrate without forming a mask layer 6.

[0073] For example, by etching away a portion of the GE semiconductor layer in the semiconductor substrate described above, multiple island-shaped semiconductor layers can be formed as shown in Figure 5. Then, after forming a compound semiconductor layer on these semiconductor layers, a device isolation process can be performed to form multiple semi-device portions sDS.

[0074] (b) In other embodiments of the present disclosure, the method for manufacturing the semiconductor laser element 20 is not limited to using a template substrate 7 in which the seed layer 3 overlaps the entire mask portion 5. Since the seed layer 3 only needs to be exposed from the opening KS, a template substrate 7 may be used in which the seed layer 3 is formed locally so as not to overlap part or all of the mask portion 5. For example, a buffer layer 2 may be located on a main substrate 1, and a seed layer 3 may be locally provided on the buffer layer 2 so as to overlap the opening KS of the mask layer 6.

[0075] (c) In the manufacturing method of the semiconductor laser element 20 in other embodiments of the present disclosure, a base substrate UK in which no buffer layer 2 is provided between the main substrate 1 and the seed layer 3 may be used as the growth substrate. That is, a template substrate 7 comprising a base substrate UK having a main substrate 1 and a seed layer 3, and a mask layer 6 formed on the base substrate UK may be used. The template substrate 7 can be configured without a buffer layer 2 when a main substrate 1 made of a material that does not melt with the seed layer 3 is used, or when a seed layer 3 made of a material with low reactivity with the main substrate 1 is used. As a result, the film deposition process for the buffer layer 2 is omitted, and the cost of the film deposition process can be reduced.

[0076] For example, the seed layer 3 may be made of a material that has low reactivity with the main substrate 1 and can serve as a growth starting point for the base semiconductor layer 8. The seed layer 3 may be, for example, an AlN layer or a SiC layer, and may be a layer containing at least one of AlN and SiC.

[0077] (d) In other embodiments of the present disclosure, the semiconductor laser element 20 may have a configuration in which the base semiconductor layer 8 does not have a first part B1, that is, a configuration in which it has one second part B2. For example, the first part B1 may be removed by etching or the like before separating the element part DS from the template substrate 7.

[0078] [Example 1] The methods for manufacturing semiconductor devices described herein will be explained in more detail below with reference to examples. However, this disclosure is not limited to the configurations described below, and various modifications are possible within the scope of the claims. Furthermore, in the following description, the same or corresponding parts of the configurations of the multiple embodiments of this disclosure will be denoted by the same reference numerals in the figures. Unless otherwise specified, forms obtained by appropriately combining the technical means disclosed in the above-described embodiments and the multiple different embodiments described later are also included in the technical scope of this disclosure.

[0079] Figure 9 is a flowchart showing an example of a method for manufacturing a semiconductor laser element 20 in Example 1. In Example 1, the mask layer 6 of the template substrate 7 includes a mask portion 5 having an initiation point. Then, an ELO semiconductor layer having an initiation point is formed on the template substrate 7. As shown in Figure 9, in Example 1, first, a template substrate 7 including an initiation point in the mask layer 6 is prepared, and then a semiconductor layer (base semiconductor layer 8 and compound semiconductor layer 9) including an initiation point is formed on the template substrate 7.

[0080] (Preparing the template board) Figure 10 is a cross-sectional view showing the configuration of the template substrate 7 in Example 1. Figure 11A is an enlarged view of the main part of Figure 10. As the main substrate 1 in the template substrate 7, a different type of substrate having a different lattice constant from the nitride semiconductor can be used. By using a Si substrate for the main substrate 1, the manufacturing cost of the template substrate 7 can be reduced. As a result, the manufacturing cost of the semiconductor laser element 20 can be reduced. The main substrate 1 may also be an Al2O3 substrate or a SiC substrate, which can reduce reactivity with Ga. The main substrate 1 is not particularly limited in terms of material and surface orientation, as long as it is a material and surface orientation that can grow an ELO semiconductor layer.

[0081] In Example 1, the base substrate UK may be manufactured by forming a base layer 4 (see Figure 4) on the main substrate 1, or a pre-prepared base substrate UK may be used. When a pre-prepared base substrate UK is used, it is easier to stably grow the base semiconductor layer 8, etc. This is because when a process is performed to deposit the base layer 4, the effects of this process may occur on the base semiconductor layer 8, etc.

[0082] The template substrate 7 may include, for example, a seed layer 3 as the underlayer 4. The seed layer 3 is the starting point for the growth of the base semiconductor layer 8 when it is deposited. The seed layer 3 may contain GaN-based semiconductors, aluminum nitride (AlN), SiC, graphene, etc. The silicon carbide used for the seed layer 3 may be hexagonal 6H-SiC or 4H-SiC. The seed layer 3 may be, for example, an AlGaN layer, or it may be a graded layer in which the Al composition gradually increases as it approaches GaN. The seed layer 3 can be configured to include a GaN layer. In this case, the seed layer 3 may be a single GaN layer, or the top layer of the graded layer which is the seed layer 3 may be a GaN layer. The seed layer 3 should be made of a material and have a surface orientation that allows for the growth of the base semiconductor layer 8 containing a nitride semiconductor.

[0083] The template substrate 7 may include a buffer layer 2 (see Figure 4) as the underlayer 4, which is located between the main substrate 1 and the seed layer 3. For example, if a silicon substrate is used for the main substrate 1 and a GaN-based semiconductor is used for the seed layer 3, providing a buffer layer 2 between the silicon substrate and the GaN-based semiconductor can reduce the melting of the silicon substrate and the GaN-based semiconductor. Furthermore, the buffer layer 2 may have at least one of the effects of increasing the crystallinity of the seed layer 3 and relaxing the internal stress of the seed layer 3.

[0084] The buffer layer 2 is typically an AlN layer, but may also be a SiC layer. The SiC used in the buffer layer 2 may be hexagonal (6H-SiC, 4H-SiC) or cubic (3C-SiC). The buffer layer 2 may be a multilayer film containing at least one of the AlN film and the SiC film. The buffer layer 2 may also contain a strain relaxation layer. Examples of strain relaxation layers include a superlattice structure of AlGaN and a grated structure in which the Al composition of AlGaN is changed in steps. The strain relaxation layer can relieve stress in the longitudinal direction of the base semiconductor layer 8. An example of the buffer layer 2, an AlN layer, can be formed to a thickness of about 10 nm to 5 μm using, for example, an MOCVD apparatus.

[0085] The base layer 4 can be formed by laminating various layers on the main substrate 1 using an MOCVD apparatus or a sputtering apparatus. For example, at least one of a buffer layer 2 (e.g., aluminum nitride) and a seed layer 3 (e.g., GaN-based semiconductor) can be deposited on the main substrate 1 using a sputtering apparatus (PSD: pulse sputter deposition, PLD: pulse laser deposition, etc.). This allows for the production of the base substrate UK.

[0086] A template substrate 7 is manufactured by forming a mask layer 6 on a base substrate UK. As the mask layer 6, for example, a single layer film containing one of the following can be used: a silicon oxide film (SiOx), a titanium nitride film (TiN, etc.), a silicon nitride film (SiNx), a silicon oxynitride film (SiON), and a metal film having a high melting point (e.g., 1000°C or higher), or a multilayer film containing at least two of these.

[0087] In Example 1, a mask layer 6 is formed on the substrate UK such that a starting point induction portion 5Y is present in a part of the mask portion 5. The starting point induction portion 5Y in Example 1 has a triangular shape in plan view. In plan view, the starting point induction portion 5Y has a vertex 5P and two sides 5A and 5B that intersect at vertex 5P. In plan view, the imaginary line segment connecting the end of side 5A and the end of side 5B on the opposite side of vertex 5P is called side 5C. Sides 5A, 5B, and 5C form an imaginary triangle. Side 5C can also be called the base of the imaginary triangle. The angle between side 5A and side 5B is called θ1, and the angle between side 5B and side 5C is called θ2. The distance from side 5C to vertex 5P is called the protrusion length H1 of the starting point induction portion 5Y.

[0088] The starting point induction portion 5Y may have the same thickness as the other parts of the mask portion 5. The angle θ1 may be 30° or approximately 30°, for example, about 20° to 40°. In this specification, "approximately" means within a range of ±10% variation. The angles θ1 and θ2 may be the same as each other, or of similar magnitude. The length of side 5A may be, for example, about 0.1 μm to 20 μm. The lengths of side 5A and side 5B may be the same as each other, or of similar magnitude. In this specification, "of similar magnitude" means within a range of 10% difference based on the larger value. The protruding length H1 of the starting point induction portion 5Y may be, for example, about 0.1 μm to 10 μm.

[0089] The starting point inductor 5Y only needs to be able to form a portion that serves as the starting point for cleavage in the base semiconductor layer 8, as will be described later, and its specific shape is not particularly limited. The starting point inductor 5Y is not limited to a shape in which the tip of the vertex 5P is pointed in a plan view, and the vertex 5P may have a rounded shape. The angles θ1 and θ2 of the starting point inductor 5Y may be different from each other. Also, the starting point inductor 5Y may have a rectangular shape in a plan view, or it may have any other shape. The part of the mask part 5 other than the starting point inductor 5Y will be called the main part, and the starting point inductor 5Y and the main part may have different thicknesses from each other. Also, the starting point inductor 5Y and the main part may be formed integrally, or the starting point inductor 5Y may be formed after the main part has been formed.

[0090] The opening KS is longitudinal except for the portion where the initiation point induction portion 5Y is provided, and its width is relatively narrow in the portion where the initiation point induction portion 5Y is provided. In Example 1, the mask layer 6 is formed such that the opening KS has a notch by providing the initiation point induction portion 5Y. Multiple openings KS may be arranged periodically in the X direction with a first period. The width of the opening KS may be about 0.1 μm to 20 μm. The smaller the width of the opening KS, the fewer the number of through dislocations propagating from the opening KS to the base semiconductor layer 8. Furthermore, peeling of the base semiconductor layer 8 in subsequent processes becomes easier. In addition, the area of ​​the second portion B2 with fewer surface defects can be increased.

[0091] In Example 1, the mask layer 6 having the mask portion 5 may be formed as follows. First, a silicon oxide film with a thickness of about 100 nm to 4 μm (preferably about 150 nm to 2 μm) is formed over the entire surface of the substrate layer 4 using the sputtering method. Then, a resist is applied to the entire surface of the silicon oxide film. After that, the resist is patterned using the photolithography method to form a resist with multiple stripe-shaped openings. In this case, in Example 1, the resist at the position corresponding to the starting point induction portion 5Y is not removed. Subsequently, a part of the silicon oxide film is removed by a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF) to form the mask portion 5 including the multiple openings KS and the starting point induction portion 5Y. Next, the mask layer 6 is formed by removing the resist with organic cleaning.

[0092] Furthermore, in the mask layer 6, for example, in one mask portion 5, the orientation of the multiple initiation point induction portions 5Y, in other words, the orientation of the multiple notches in the opening KS, may be aligned in one direction. As a result, as will be described later, the semiconductor laser element 20 manufactured using the template substrate 7 can have a pair of resonator surfaces (emission surface F1 and opposing surface F2) formed on the second portion B2 (see Figure 1, etc.), which is located further from the initiation point induction portion 5Y, among the second portion B2 and the third portion B3. The influence of the initiation point induction portion 5Y is less likely to occur on the second portion B2. As a result, the possibility of a decrease in the quality of the pair of resonator surfaces can be reduced. However, it goes without saying that the mask layer 6 can be formed by appropriately changing the orientation of the initiation point induction portion 5Y.

[0093] (Example of the shape of the initiation point) Another example of a specific shape for the initiation point 5Y is as follows:

[0094] Figure 11B is a plan view showing an example of an initiation point inductor 5Y. As shown in Figure 11B, an example of an initiation point inductor 5Y may have a shape in which the vertex 5P does not extend beyond the center of the opening KS. In other words, the initiation point inductor 5Y may have a protrusion length H1 of, for example, 0.1 μm or more and less than (WK / 2) (WK: width of the opening KS). The initiation point inductor 5Y may be, for example, an isosceles triangle or an equilateral triangle in plan view.

[0095] Figure 11C is a plan view showing another example of the initiation point inductor 5Y. As shown in Figure 11C, the initiation point inductor 5Y in one example may have a shape in which the vertex 5P extends beyond the center of the opening KS. In other words, the initiation point inductor 5Y may have a protrusion length H1 of, for example, (WK / 2) or more and less than WK. Also, for example, angles θ1 and θ2 may exceed 40°.

[0096] Figure 11D is a plan view showing another example of the starting point induction section 5Y. As shown in Figure 11D, one example of the starting point induction section 5Y may have a virtual pentagonal shape in plan view, which is a combination of a virtual triangle 5Y1 and a virtual quadrilateral 5Y2. The virtual quadrilateral 5Y2 may be square or rectangular. The length of the virtual side 5D of the virtual quadrilateral 5Y2, whose length is in the width direction of the opening KS, may be, for example, about 0.1 μm to 10 μm. Side 5D may be a line segment that extends parallel or approximately parallel to the width direction of the opening KS. The virtual quadrilateral 5Y2 may be, for example, trapezoidal. The vertex 5P of the virtual triangle 5Y1 may be located beyond the center of the opening KS, or not.

[0097] Figure 11E is a plan view showing another example of the starting point induction portion 5Y. As shown in Figure 11E, one example of the starting point induction portion 5Y may have a rectangular shape in plan view. In this case, it does not have a vertex 5P, and the distance between the side 5E, whose length is aligned with the longitudinal direction of the opening KS, and the main part of the mask portion 5 is defined as the protruding length H1. The side 5E may have a length of, for example, 0.1 μm to 10 μm. The starting point induction portion 5Y may have a trapezoidal shape or a parallelogram shape in plan view. The side 5E may be located beyond the center of the opening KS, or not. That is, the side 5D may have a length of, for example, 0.1 μm to 20 μm.

[0098] (Process for forming a semiconductor layer) Next, a base semiconductor layer 8 is deposited on the template substrate 7. In Example 1, for example, the template substrate 7 is placed in an MOCVD apparatus and a GaN-based semiconductor layer is deposited by the ELO method. Figure 12 is a cross-sectional view showing an example of lateral growth of the base semiconductor layer 8 in Example 1. The base semiconductor layer 8 in Example 1 is a nitride semiconductor (e.g., a GaN-based semiconductor layer) and is obtained by depositing a c-plane film on the template substrate 7. The base semiconductor layer 8 may be an n-type semiconductor layer having a donor. In Figure 12, etc., the [-1100] direction of the GaN-based semiconductor is the positive Y-axis direction, the [11-20] direction of the GaN-based semiconductor is the positive X-axis direction, and the

[0001] direction of the GaN-based semiconductor is the positive Z-axis direction (thickness direction).

[0099] As shown in Figure 12, in the ELO method, an initial growth layer SL is first formed on the seed layer 3, and then the base semiconductor layer 8 can be grown laterally from the initial growth layer SL. The initial growth layer SL is the starting point for the lateral growth of the base semiconductor layer 8 and is part of the first part B1. By appropriately controlling the ELO deposition conditions, it is possible to control the growth of the base semiconductor layer 8 in the Z direction (c-axis direction) or the X direction (a-axis direction).

[0100] Here, the ELO deposition conditions may be controlled so that the deposition of the initial growth layer SL is stopped just before the edge of the initial growth layer SL rides up onto the upper surface of the mask portion 5 (when it is in contact with the upper side of the mask portion 5), or immediately after it rides up onto the upper surface of the mask portion 5 (i.e., at this timing, the ELO deposition conditions are switched from c-axis deposition conditions to a-axis deposition conditions). In this way, since lateral deposition is performed from a state in which the initial growth layer SL protrudes slightly from the mask portion 5, less material is consumed in the thickness direction of the base semiconductor layer 8, and the base semiconductor layer 8 can be grown laterally at high speed. The initial growth layer SL may be formed to a thickness of, for example, 2.0 μm or more and 3.0 μm or less.

[0101] In Example 1, the base semiconductor layer 8 was an n-type GaN layer, and ELO deposition of Si-doped GaN was performed on a template substrate 7 using an MOCVD apparatus. As an example of ELO deposition conditions, the following conditions can be used: substrate temperature: 1120°C, growth pressure: 50kPa, TMG (trimethylgallium): 22sccm, NH3: 15slm, V / III = 6000 (ratio of the amount of Group V raw material supplied to the amount of Group III raw material supplied). An initial growth layer SL was selectively grown on the seed layer 3 (the uppermost GaN layer of the seed layer 3) exposed in the opening KS, and subsequently grew laterally on the mask portion 5. Then, before the base semiconductor layers 8 growing laterally from both sides on the mask portion 5 could meet, the lateral growth of these layers was stopped.

[0102] In Example 1, by including a starting point induction portion 5Y in the mask layer 6, disturbances may occur in the lateral growth of the base semiconductor layer 8 in the area where the starting point induction portion 5Y is present. Figure 13 is a plan view illustrating the base semiconductor layer 8 in Example 1.

[0103] As shown in Figure 13, in Example 1, the base semiconductor layer 8 has a starting point 8K that serves as the starting point for cleavage. This starting point 8K is naturally formed in the base semiconductor layer 8 by growing the base semiconductor layer 8 from an opening KS with a notch shape. The relationship between the shape of the starting point induction portion 5Y and the shape of the starting point portion 8K may change depending on the growth conditions of the base semiconductor layer 8. The starting point portion 8K may be smaller than, larger than, or about the same size as, the starting point induction portion 5Y. An example of the starting point portion 8K is described below.

[0104] For example, the base semiconductor layer 8 may have an oblique joint 8N that extends from the starting point 5Y of the mask layer 6 to the starting point 8K of the base semiconductor layer 8 in a plan view. This oblique joint 8N is a region where semiconductor layers grown obliquely to the X direction (a-axis direction) join together. The oblique joint 8N may be, for example, a grain boundary, or it may be a region with greater disorder in the crystal structure (i.e., more lattice defects) than other parts of the base semiconductor layer 8. In Figure 13, the oblique joint 8N is shown with a solid line. When the base semiconductor layer 8 has an oblique joint 8N, the oblique joint 8N can be observed, for example, by performing a CL measurement.

[0105] Figure 14 is an enlarged view illustrating the growth of the base semiconductor layer 8 around the initiation point 5Y in Example 1. As shown in Figure 14, first, the initial growth layer SL is formed from the opening KS. At this time, in the part of the opening KS other than the area around the initiation point 5Y, the initial growth layer SL is formed so as to ride up onto the upper surface of the mask portion 5 by lateral growth of the GaN-based semiconductor in the <11-20> direction (i.e., the a-axis direction). In contrast, in the area around the initiation point 5Y in the opening KS, the presence of the initiation point 5Y may cause a notch to form in a part of the initial growth layer SL that has grown so as to ride up onto the upper surface of the mask portion 5 from the opening KS. For example, in a plan view, the direction perpendicular to the edge 5A of the initiation point 5Y is the m-plane direction of the GaN-based semiconductor (e.g., the [10-10] direction), and the direction perpendicular to the edge 5B may be another m-plane direction of the GaN-based semiconductor (e.g., the [01-10] direction). In GaN-based semiconductors, the growth rate in the m-plane direction is smaller than the growth rate in the a-plane direction. The base semiconductor layer 8 can grow while maintaining the notch created in the initial growth layer SL.

[0106] The oblique joint portion 8N may be formed, for example, by the association of semiconductor layers grown in the [10-10] direction and the [01-10] direction. The oblique joint portion 8N may be formed near the mask portion 5 and then influence (propagate) to the surface of the base semiconductor layer 8 after film formation, and may also be present on the surface of the base semiconductor layer 8. The starting portion 8K may have a tapered shape, such as a triangle, in a plan view. This makes it easier for stress to concentrate at one point during cleavage. As a result, it is easier to obtain a good cleavage plane. The starting portion 8K may also have an end face that is the m-plane of the GaN-based semiconductor. However, the end face of the starting portion 8K does not have to be the m-plane of the GaN-based semiconductor.

[0107] If L2 (see Figure 17) is the distance between multiple starting points 8K in the base semiconductor layer 8 (the distance between the tips of two starting points 8K), then this distance L2 corresponds to the resonator length L1 (see Figure 2). The length of the distance L2 may be around 20 μm to 200 μm. When the distance L2 is short, there are more locations where internal stress is released by cleavage. Therefore, the possibility of unintended element isolation occurring during cleavage during cooling, as described later, can be reduced. The distance L2 may be 300 μm or more. When the distance L2 is long, the possibility of starting points 8K that do not undergo cleavage during cleavage during cooling, as described later, can be reduced, and the yield of semiconductor device manufacturing can be improved.

[0108] In forming the base semiconductor layer 8, it is preferable to reduce the interaction between the base semiconductor layer 8 and the mask portion 5 and maintain a state in which the base semiconductor layer 8 and the mask portion 5 are in contact by van der Waals forces. That is, the base semiconductor layer 8 and the mask portion 5 may be in contact mainly by van der Waals forces.

[0109] (Process for forming a compound semiconductor layer) In Example 1, a semiconductor substrate 10 with a base semiconductor layer 8 formed on a template substrate 7 is manufactured using an MOCVD apparatus. Then, without removing the semiconductor substrate 10 from the MOCVD apparatus, a compound semiconductor layer 9 is formed on the base semiconductor layer 8 using the same MOCVD apparatus. Furthermore, without removing the laminated structure, which is the compound semiconductor layer 9, from the MOCVD apparatus during the formation process, the film deposition process for the laminated structure is continuously performed using the same MOCVD apparatus. The compound semiconductor layer 9 includes a nitride semiconductor layer (for example, a GaN-based semiconductor layer).

[0110] Figure 15 is a cross-sectional view showing the configuration of the compound semiconductor layer 9 in Example 1. As shown in Figure 15, the compound semiconductor layer 9 is formed in the following order: an n-type semiconductor layer 9N having a donor, an active layer 9K, and a p-type semiconductor layer 9P having an acceptor. The n-type semiconductor layer 9N is formed in the following order: a first contact layer 9A, a first cladding layer 9B, and a first optical guide layer 9C. The p-type semiconductor layer 9P is formed in the following order: a second optical guide layer 9D, an electron blocking layer 9E, a second cladding layer 9F, and a second contact layer 9G. In the compound semiconductor portion 9, the second optical guide layer 9D and the electron blocking layer 9E may be swapped in the p-type semiconductor layer 9P. For example, the p-type semiconductor layer 9P may be formed in the following order: electron blocking layer 9E, second optical guide layer 9D, second cladding layer 9F, and second contact layer 9G.

[0111] For example, an n-type GaN layer can be used for the first contact layer 9A, and for example, an n-type AlGaN layer can be used for the first cladding layer 9B. The first cladding layer 9B may be an n-type GaN-based semiconductor layer, an n-type AlGaN-based semiconductor layer, or an n-type AlInGaN-based semiconductor layer, and may have a layer thickness of, for example, 0.8 μm to 2 μm. When GaN without Al is used for the first cladding layer 9B, the deposition of GaN-based semiconductor on the surface of the mask portion 5 can be suppressed, and the yield during delamination (the process of separating the device portion DS from the template substrate 7, as described later) is improved. Furthermore, for example, an n-type GaN layer may be used for the first optical guide layer 9C, and may be an InGaN layer with an In composition of about 3 to 10%. The first optical guide layer 9C may have a layer thickness of about 50 nm.

[0112] The active layer 9K can use an MQW (Multi-Quantum Well) structure, for example, one that includes an InGaN layer. The active layer 9K typically has a structure with 5 to 6 periods. The In composition varies depending on the desired emission wavelength; for example, for blue emission (around 450 nm), an In concentration of about 15-20% is acceptable. For green emission (around 530 nm), an In concentration of about 30% is acceptable.

[0113] For the second optical guide layer 9D, for example, a p-type AlGaN layer can be used. The second optical guide layer 9D may have an Al composition of about 15-25% and a layer thickness of about 5-25 nm. For the electron blocking layer 9E, for example, a p-type GaN layer may be used, or an InGaN layer with an In composition of about 3-10%. The electron blocking layer 9E may have a layer thickness of about 50 nm. For the second cladding layer 9F, for example, a p-type AlGaN layer may be used. The second cladding layer 9F may be a p-type GaN-based semiconductor layer, an AlGaN-based semiconductor layer, or an AlInGaN-based semiconductor layer, and may have a layer thickness of about 0.1 μm to 1 μm. For the second contact layer 9G, for example, a p-type GaN layer can be used. The second contact layer 9G may have a layer thickness of about 0.1 μm to 0.3 μm. Although not shown in the diagram, a highly doped layer with a thickness of approximately 10 nm, with Mg as the dopant, may be formed on the surface of the second contact layer 9G.

[0114] The thickness of each layer of the compound semiconductor layer 9 can be set as follows: base semiconductor layer 8 > first cladding layer 9B > first optical guide layer 9C > active layer 9K, and base semiconductor layer 8 > second cladding layer 9F > second optical guide layer 9D > active layer 9K. Furthermore, the refractive index of each layer of the compound semiconductor layer 9 (refractive index of light generated in the active layer 9K) can be set as follows: first cladding layer 9B < first optical guide layer 9C < active layer 9K, and insulating film DF < second cladding layer 9F < second optical guide layer 9D < active layer 9K.

[0115] Figure 16 is a plan view illustrating the compound semiconductor layer 9 in Example 1. As shown in Figure 16, the compound semiconductor layer 9 is formed in a shape having a starting point 9T corresponding to the starting point 8K of the base semiconductor layer 8. This is because the compound semiconductor layer 9 is difficult to deposit at the starting point 8K of the base semiconductor layer 8. The starting point 9T, formed in a shape corresponding to the starting point 8K, may have an end face that is the m-plane of the GaN-based semiconductor. Note that the end face of the starting point 9T does not have to be the m-plane of the GaN-based semiconductor.

[0116] The process described above can be summarized as follows. In Example 1, first, a main substrate 1, a base semiconductor layer 8 formed above the main substrate 1, and a compound semiconductor layer 9 formed on the base semiconductor layer 8 are prepared. A notch is formed in the opening KS of the mask layer 6. This naturally forms a starting point 8K in the base semiconductor layer 8. Then, the compound semiconductor layer 9 is formed on the base semiconductor layer 8 having the starting point 8K. This naturally forms a starting point 9T in the compound semiconductor layer 9.

[0117] (Process of separating elements on a template substrate) Next, the semiconductor substrate 10 on which the compound semiconductor layer 9 is formed is cooled, thereby separating the elements into multiple semi-element portions sDS on the template substrate 7. Figure 17 is a plan view illustrating an example of the element separation process in Example 1.

[0118] The compound semiconductor layer 9 may be deposited under high-temperature conditions using an MOCVD apparatus, in which case a cooling step is performed within the MOCVD apparatus.

[0119] In Example 1, the thermal expansion coefficients of the base semiconductor layer 8 and the compound semiconductor layer 9 may differ from those of the main substrate 1. In this case, internal stress is generated in the base semiconductor layer 8 and the compound semiconductor layer 9 due to the difference in thermal expansion coefficients between the base semiconductor layer 8 and the compound semiconductor layer 9 and the main substrate 1.

[0120] Furthermore, in Example 1, the main substrate 1 and the base semiconductor layer 8 may have different lattice constants. In this case, internal stress is generated in the base semiconductor layer 8 due to the difference in lattice constants between the main substrate 1 and the base semiconductor layer 8. Internal stress may also be generated in the compound semiconductor layer 9 due to the influence of the internal stress in the base semiconductor layer 8. By using a different type of substrate (e.g., a Si substrate) for the main substrate 1, it is possible to easily generate internal stress in the base semiconductor layer 8 and the compound semiconductor layer 9.

[0121] As shown in Figure 17, when the semiconductor substrate 10 is cooled, the internal stress of the base semiconductor layer 8 and the compound semiconductor layer 9 may cause cleavage starting from the notched starting points 8K and 9T, thereby generating a divided portion PS. In other words, in Example 1, cleavage may occur spontaneously during the cooling of the base semiconductor layer 8 and the compound semiconductor layer 9.

[0122] The base semiconductor layer 8 and the compound semiconductor layer 9 may each have starting points 8K and 9T, respectively, which have a tapered shape at the end of the notch. In this case, stress tends to concentrate at a single point, making it easier to produce a high-quality cleavage surface through cleavage. The shapes of the starting points 8K and 9T are influenced by the shape of the starting point induction portion 5Y of the mask portion 5 in the mask layer 6. The shape of the starting point induction portion 5Y can affect the quality of the cleavage surface.

[0123] Furthermore, tensile stress may be present as internal stress in the base semiconductor layer 8. For example, if the thermal expansion coefficient of the main substrate 1 is greater than that of the base semiconductor layer 8, compressive stress will be generated in the base semiconductor layer 8, and if the thermal expansion coefficient of the main substrate 1 is smaller than that of the base semiconductor layer 8, tensile stress will be generated in the base semiconductor layer 8. When cleaving a base semiconductor layer 8 under tensile stress, the possibility of the divided pieces of the base semiconductor layer 8 coming into contact with each other can be reduced. Therefore, the possibility of damage to the end faces of the divided base semiconductor layer 8 can be reduced. Moreover, since cleavage occurs in the base semiconductor layer 8 as if being torn from the starting point 8K, the cleaved surface tends to be smooth.

[0124] In Example 1, when cooling the semiconductor substrate 10, the base semiconductor layer 8 and the compound semiconductor layer 9 may be cleaved to separate the element into multiple semi-element sections sDS having optical resonators LK on the template substrate 7. In this case, there is no need to perform a separate process to cleave the base semiconductor layer 8 and the compound semiconductor layer 9, and the manufacturing cost of the semiconductor laser element 20 can be reduced. Furthermore, semi-element sections sDS having optical resonators LK with short resonator lengths can be manufactured. For example, the length of the spacing L2 can be set to about 20 μm to 200 μm, and therefore the resonator length L1 can be set to about 20 μm to 200 μm.

[0125] Furthermore, if, after cooling the semiconductor substrate 10, there are areas of the starting point 9T where a divided portion PS has not been formed, i.e., areas of the starting point 9T where cleavage has not occurred, a further process to cleave the starting point 9T may be performed. For example, cleavage may be induced in the starting point 9T by applying a blade to the starting point 9T and applying force in a direction perpendicular to the surface direction. In this case, cleavage can be induced in the starting point 9T relatively reliably, thus improving yield. Alternatively, cleavage may be induced in the starting point 9T by applying vibration to the starting point 9T. In this case, the process can be carried out relatively easily, thus simplifying the manufacturing process. In addition, cleavage may be induced in the starting point 9T by applying thermal stress to the starting point 9T by raising or lowering the temperature of the semiconductor substrate 10 above room temperature, utilizing the difference in thermal expansion coefficients between the main substrate 1 and the base semiconductor layer 8.

[0126] Figure 18 is an exploded perspective view illustrating the configuration of the semi-element portion sDS in Example 1. For illustrative purposes, Figure 18 shows the template substrate 7 and the base semiconductor layer 8 virtually separated; however, in reality, the base semiconductor layer 8 and the mask portion 5 are in contact. Furthermore, the base semiconductor layer 8 has a junction 8S on its lower surface corresponding to the initial growth layer SL, and the junction 8S and the seed layer 3 are bonded to each other. Also, Figure 18 shows only a portion of the template substrate 7, not the entire structure.

[0127] As shown in Figure 18, the base semiconductor layer 8 in the semi-element portion sDS has a first base end face 8X and a second base end face 8Y adjacent to the first base end face 8X at an angle. The base semiconductor layer 8 may also have a third base end face 8Z adjacent to the second base end face 8Y at an angle and corresponding to the a-plane of the GaN semiconductor (for example, parallel to the a-plane). The second base end face 8Y may be located between the first base end face 8X and the third base end face 8Z. The semi-element portion sDS may have two first base end faces 8X and two second base end faces 8Y as the end faces of the third portion B3.

[0128] The first base end face 8X may include a first partial face 8X1, a second partial face 8X2, and a third partial face 8X3. The first partial face 8X1 is a part of the first base end face 8X and is a surface located at a position corresponding to the first part B1 of the base semiconductor layer 8. The second partial face 8X2 is a partial face of the first base end face 8X located at a position corresponding to the second part B2. The third partial face 8X3 is a partial face of the first base end face 8X located at a position corresponding to the third part B3. The first partial face 8X1 is located between the second partial face 8X2 and the third partial face 8X3.

[0129] The third subsurface 8X3 may be a surface from which the portion corresponding to the aforementioned oblique meeting portion 8N has been divided, and may be an m-plane cleavage surface formed by the base semiconductor layer 8 cleaving from the starting point portion 8K. The second subsurface 8X2 may be an m-plane cleavage surface formed by the base semiconductor layer 8 cleaving from the starting point portion 8K, and may be flush with the exit surface F1 of the optical resonator LK. Furthermore, the first subsurface 8X1, the second subsurface 8X2, and the third subsurface 8X3 may be flush with each other. The surface roughness of the second subsurface 8X2 may be less than that of the third subsurface 8X3. The density of dislocations in the second subsurface 8X2 (dislocations measured by CL on the cleavage surface, mainly basal plane dislocations) may be greater than or equal to the penetration dislocation density of the second part B2.

[0130] The second base end face 8Y is a surface that was included in the starting point 8K of the notch shape in the base semiconductor layer 8 before cleavage, and is not a cleavage surface formed by cleavage. Depending on the shape of the starting point induction portion 5Y of the mask portion 5, the starting point 8K may have the end face of the ELO semiconductor layer grown in the m-axis direction, in which case the second base end face 8Y is not a cleavage surface but may be the m-plane of the GaN-based semiconductor. The compound semiconductor portion 9 may also have a side surface 9S located above the second base end face 8Y. The surface roughness of at least one of the pair of resonator surfaces (exit surface F1 and opposing surface F2) can be made smaller than the surface roughness of the side surface 9S.

[0131] The angle (interior angle) formed by the first base end face 8X and the second base end face 8Y is called θ3. The angle θ3 may be an obtuse angle, for example, 120° or approximately 120°, or for example, about 110° to 130°.

[0132] As described above, in Example 1, an optical resonator LK including a resonator surface (see Figures 1 and 2) can be formed by separating the base semiconductor layer 8 and the compound semiconductor layer 9 into a plurality of first element parts (semi-element parts sDS). In Figure 18, the optical resonator LK is shown exemplarily in a position overlapping the second part B2 in a plan view, but in the semi-element parts sDS, the position of the optical resonator LK in the X direction is not necessarily limited. The optical resonator LK will be described in more detail later.

[0133] Furthermore, in Example 1, it can be said that an optical resonator LK including the resonator surface is formed by dividing the base semiconductor layer 8 and the compound semiconductor layer 9 so that the entire thickness direction of the main substrate 1 is not divided.

[0134] The exit surface F1 and the opposing surface F2 of the optical resonator LK may each be the m-plane of the compound semiconductor layer 9 and may be included in the cleavage plane of the compound semiconductor layer 9. Each of the exit surface F1 and the opposing surface F2 can be formed by m-plane cleavage of the compound semiconductor layer 9, which is a nitride semiconductor layer (e.g., a GaN-based semiconductor layer). The semi-element portion sDS may have traces of a cleavage starting point for cleavage (e.g., a second base end face 8Y) on at least one of the base semiconductor layer 8 and the compound semiconductor layer 9. By having the exit surface F1 and the opposing surface F2 be the m-plane, the reflectivity of the resonator surface of the optical resonator LK can be improved.

[0135] (Process for forming the element structure) Next, a step is performed to form an element structure on the semiconductor substrate 10 having a plurality of semi-element portions sDS. For example, a ridge portion RJ is formed on the p-type semiconductor layer 9P, and then an insulating film DF and a first electrode E1 are formed to form the element portion DS. In Example 1, a semiconductor laser element 20 with a double-sided electrode structure is manufactured. Therefore, the element portion DS does not include a second electrode E2, and the second electrode E2 may be provided in a later step.

[0136] Figure 19 is a perspective view illustrating the configuration of the element unit DS in Example 1. In Figure 19, the template substrate 7 is omitted from the illustration. Figure 20 is a cross-sectional view showing the configuration of the element unit DS in Example 1.

[0137] As shown in Figures 19 and 20, the compound semiconductor layer 9 may include a ridge portion (ridge) RJ that overlaps with the first electrode E1 in a plan view. The ridge portion RJ may include a part of the second cladding layer 9F and the electron blocking layer 9E (see Figure 15) (the part that overlaps with the first electrode E1 in a plan view). The ridge portion RJ has a shape with the Y direction as its longitudinal direction, and an insulating film DF may be provided so as to cover the side surface of the ridge portion RJ. For example, the insulating film DF can be a single layer or a multilayer film containing oxides or nitrides of Si, Al, Zr, Ti, Nb, or Ta. The thickness of the insulating film DF can be about 10 to 500 nm.

[0138] The refractive index of the insulating film DF is smaller than that of the second optical guide layer 9D and the second cladding layer 9F. By providing the ridge portion RJ and the insulating film DF, the current path between the first electrode E1 and the base semiconductor layer 8 is narrowed on the anode side, allowing for efficient light emission within the resonator LK.

[0139] The first electrode E1 is provided, for example, on the upper surface of the ridge portion RJ and functions as an anode. Examples of materials for the first electrode E1 include single-layer or multi-layer films of conductive oxides containing at least one selected from metals or alloys such as Ni, Rh, Cr, Au, W, Pt, Ti, and Al, or Zn, In, and Sn. Examples of conductive oxides include ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), and GZO (Gallium-doped Zinc Oxide). The thickness of the first electrode E1 may be, for example, about 0.1 to 2 μm.

[0140] The optical resonator LK includes a portion of the n-type semiconductor layer 9N, the active layer 9K, and the p-type semiconductor layer 9P (the portion that overlaps with the first electrode E1 in a plan view). For example, the optical resonator LK consists of a portion of the first cladding layer 9B, the first optical guide layer 9C, the active layer 9K, the second optical guide layer 9D, the electron blocking layer 9E, and the second cladding layer 9F (the portion that overlaps with the first electrode E1 in a plan view).

[0141] In the optical resonator LK, the refractive index (optical refractive index) decreases in the order of the active layer 9K, the first optical guide layer 9C, and the first cladding layer 9B, and also decreases in the order of the active layer 9K, the second optical guide layer 9D, and the second cladding layer 9F. Therefore, the light generated when holes supplied from the first electrode E1 and electrons supplied from the second electrode E2 combine in the active layer 9K is confined within the optical resonator LK (particularly the active layer 9K), and laser oscillation occurs due to stimulated emission and feedback in the active layer 9K. The laser light generated by the laser oscillation is emitted from the optical emission region EA on the emission surface F1.

[0142] The exit surface F1 and opposing surface F2 of the optical resonator LK are formed by m-plane cleavage, resulting in excellent planarity and perpendicularity to the c-plane (parallelism between the exit surface F1 and the opposing surface F2), and thus high optical reflectivity. This reduces reflection loss, enabling stable laser oscillation even at short resonance lengths of 200 μm or less, where optical gain decreases. Because the exit surface F1 and opposing surface F2 are formed above the second section B2, which is a low-dislocation region, the planarity of the cleavage surface is excellent, resulting in high optical reflectivity.

[0143] In Example 1, the sum T1 of the thickness of the base semiconductor layer 8 and the thickness of the compound semiconductor layer 9 can be 50 [μm] or less. If this sum T1 is too large, it may become difficult to cleave the layers so that the resonator length is 200 μm or less. The ratio of the resonator length L1 (see Figure 2) to the thickness of the second part B2 of the base semiconductor layer 8 can be 1 to 20. Also, the direction perpendicular to the direction of the resonator length L1 is the first direction (X direction), and the size of the second part B2 in the X direction is the width W2 of the second part B2, and the ratio of the resonator length L1 to the width W2 of the second part B2 can be 1 to 10. Also, the size of the first part B1 in the X direction is the width W1 of the first part B1, and the ratio of the resonator length L1 to the width W1 of the first part can be 1 to 200.

[0144] (Step to separate the element from the template substrate) Next, a step is performed to separate the element portion DS from the template substrate 7. Figure 21 is a schematic cross-sectional view showing the step of separating the element portion DS from the template substrate 7 in the semiconductor laser element manufacturing method of Example 1. Although Figure 21 shows one element portion DS, it is of course possible to separate multiple element portions DS from the template substrate 7. Also, the illustration of the ridge portion RJ is simplified in Figure 21.

[0145] As shown in Figure 21, first, the mask portion 5 of the template substrate 7 may be removed by etching using hydrofluoric acid, buffered hydrofluoric acid, etc. The insulating film DF may be protected with a resist or the like so that it is not removed along with the mask portion 5. In Example 1, the mask portion 5 may be removed after the element portion DS is formed on the template substrate 7. In this case, the mask portion 5 can be removed while the element portion DS is fixed to the template substrate 7, which can improve the yield in the manufacturing of the semiconductor laser element 20. By removing the mask portion 5, the base semiconductor layer 8 and the underlying substrate UK are bonded via a junction 8S (weak portion), making it easier to separate the element portion DS from the underlying substrate UK.

[0146] Next, for example, a step of separating the element portion DS from the template substrate 7 may be performed, which also serves as a step of bonding the element portion DS to the support substrate SK. The specific shape of the support substrate SK is not particularly limited, but the support substrate SK in Example 1 will be described below with reference to Figures 22 and 23. Figure 22 is a schematic perspective view showing the state in which the element portion DS is bonded to the support substrate SK. Figure 23 is a schematic cross-sectional view showing the state in which the element portion DS is bonded to the support substrate SK.

[0147] As shown in Figures 21 to 23, the support substrate SK includes conductive first pads P1 and second pads P2, and for example, the first electrode E1 may be connected to the first pad P1 via a first junction A1. By joining at least the first electrode E1 and the first junction A1, the element portion DS is supported by the support substrate SK. This causes the downwardly protruding junction 8S (weak portion) on the back surface of the base semiconductor layer 8 to break, and the element portion DS can be separated from the template substrate 7. Alternatively, the insulating film DF and the second pad P2 may be joined to each other via a second junction A2 (not shown), in which case the stability of the state in which the element portion DS is supported by the support substrate SK may be improved. The back surface of the base semiconductor layer 8 may be planarized by polishing or CMP (Chemical Mechanical Polish). Then, while supported by the support substrate SK, the second electrode E2 can be formed on the lower surface of the base semiconductor layer 8 of the element portion DS.

[0148] Next, (i) an insulating film D1 covering the sides of the base semiconductor layer 8 and the compound semiconductor layer 9, and (ii) a conductive film MF are formed. The conductive film MF electrically connects the second electrode E2 to the second junction A2 or the second pad P2. The material of the conductive film MF is not particularly limited. The first pad P1 and the second pad P2 may be provided spaced apart from each other. The conductive film MF may be in contact with the second electrode E2, the insulating film D1, and at least one of the second junction A2 and the second pad P2.

[0149] In Example 1, the second electrode E2 is located on the back surface of the base semiconductor portion 8, and the compound semiconductor portion 9 and the first electrode E1 are closer to the support substrate SK than the base semiconductor portion 8 (junction-down configuration).

[0150] Multiple element units DS are arranged on a support substrate SK in a direction perpendicular to the direction defining the resonator length (X direction) so that the direction of the resonator length is aligned, and the support substrate SK may be provided with first and second pads P1 and P2 corresponding to each of the multiple element units DS.

[0151] The support substrate SK can be formed, for example, as follows: a plurality of recesses HL (rectangular in plan view) are arranged in a matrix on a Si substrate, SiC substrate, AlN substrate, etc., and a plurality of first pads P1, a plurality of second pads P2, and a plurality of first joints A1 are provided in the non-recessed areas. A plurality of second joints A2 may also be provided. The material constituting the main body of the support substrate SK is not particularly limited, and the support substrate SK may be formed of an insulator or semi-insulator, for example, or of a conductive material. Examples of conductive materials include metallic materials containing Cu, Al, etc. When the support substrate SK is formed of a conductive material, an insulating layer can be placed on the upper surface of the support substrate SK, and wiring can be placed on the insulating layer.

[0152] The shape of the support substrate SK is not particularly limited and may be a roughly rectangular prism shape (roughly rectangular parallelepiped shape), a roughly pentagonal prism shape, a roughly hexagonal prism shape, or any other shape. In Example 1, the shape of the support substrate SK is a roughly rectangular parallelepiped shape.

[0153] The first pad P1 and the second pad P2 may have a metal layer containing, for example, Au, Ti, Ni, etc. The first joint A1 and the second joint A2 may consist of a single metal layer or multiple metal layers. If the first joint A1 and the second joint A2 consist of multiple metal layers, the outermost surface may be a metal layer made of Au. This can suppress corrosion of the first joint A1 and the second joint A2. The first joint A1 is a solder material such as AuSi or AuSn. The first pad P1 and the first electrode E1 may be joined metal-to-metal without providing the first joint A1, and the second pad P2 and the second electrode E2 may be joined metal-to-metal without providing the second joint A2. In that case, for example, an Au-Au joint can be used.

[0154] The first pad P1 and the second pad P2 may be located on the same plane. In Embodiment 1, the second joint A2 may not be provided. The first joint A1 may be, for example, solder material, and the element DS may be held by the first joint A1 and placed on the support substrate SK.

[0155] (Process of forming a reflective film on the resonator surface) Next, a reflective film UF is formed on the exit surface F1 and the opposing surface F2 of the optical resonator LK in the element section DS mounted on the support substrate SK. This allows the semiconductor laser element 20 to be manufactured. Figure 24 is a schematic cross-sectional view showing the step of forming a reflective film on the resonator surface in the semiconductor laser element manufacturing method of Example 1. Figure 25 is a plan view showing the configuration of the compound semiconductor layer 9 after the reflective film UF has been formed.

[0156] As shown in Figures 24 and 25, a reflective film UF (e.g., a dielectric film) is formed on a first end face including the end face of the base semiconductor layer 8 and the end face of the compound semiconductor layer 9. The first end face includes the exit surface F1 of the optical resonator LK. Examples of materials for the reflective film UF include dielectrics such as SiO2, Al2O3, AlN, AlON, Nb2O5, Ta2O5, and ZrO2. The reflective film UF may be a multilayer film. The reflective film UF can be formed by electron beam deposition, electron cyclotron resonance sputtering, chemical deposition, etc.

[0157] The semiconductor laser element 20 can be configured such that at least one of its pair of resonator surfaces (emission surface F1 and opposing surface F2) has a light reflectance of 98% or more, and the resonator length L1 is 200 [μm] or less. The difference between the emission surface F1 and the opposing surface F2 may be their reflectance. The resonator surface with the lower reflectance can be designated as the emission surface F1. The reflectance can be controlled by the type, structure, and thickness of the reflective film UF.

[0158] A reflective mirror film UF may be provided so as to cover the opposing surface F2. The light reflectance of the output surface F1 and the opposing surface F2 may each be 98% or higher. The light reflectance of the opposing surface F2 on the light-reflecting surface side is greater than the light reflectance of the output surface F1. The reflective mirror film UF can be formed over the entire cleavage plane (m plane) of the base semiconductor layer 8 and the compound semiconductor layer 9.

[0159] As described above, the element unit DS can be electrically connected to the support substrate SK and mechanically fixed. As a result, the element unit DS is positioned on the support substrate SK with its end face exposed. Therefore, in the next step, it becomes possible to form a reflective film on the exit surface F1 and the opposing surface F2 of the optical resonator LK at the end face of the element unit DS. In other words, when the element unit DS is positioned on the template substrate 7 (before separating the element unit DS from the template substrate 7), the resonator surface is not exposed to the outside in the divided portion PS, making it difficult to form a reflective film on the exit surface F1 and the opposing surface F2 of the optical resonator LK.

[0160] Generally, in the manufacturing of semiconductor laser elements, dielectric layers can be deposited (edge ​​coating) so that the resonator surfaces of multiple elements have a desired reflectivity.

[0161] In contrast, by using the support substrate SK, the resonator surface of the element portion DS after element separation can be appropriately coated. The support substrate SK serves as a jig when coating the end face of the optical resonator LK, and also functions as a submount in the final device (semiconductor laser element 20). In Example 1, by performing a coating treatment on the element portion DS fixed to the support substrate SK, the reflection efficiency on the opposing surface F2 can be increased, making it possible to obtain a semiconductor laser element 20 with excellent luminescence efficiency. Furthermore, optical damage to the end face of the emission surface F1 can be suppressed, making it possible to obtain a semiconductor laser element 20 with excellent reliability.

[0162] Furthermore, in conventional CT methods, for example, when forming the resonator surface of an optical resonator by cleavage, both the growth substrate and the structure formed on the growth substrate are cleaved, thus limiting the range in which the resonator length can be shortened. To the best of the inventors' knowledge, the resonator length of commercially available semiconductor lasers manufactured by methods that form the resonator surface by cleavage is approximately 300 μm for the shortest semiconductor laser resonator length. In contrast, the semiconductor laser element 20 can have an ultrashort resonator of 20 to 200 μm. Because the optical reflectivity of at least one of the resonator surfaces (output surface F1 and opposing surface F2) is high and the reflection loss is small, stable laser oscillation is possible even at short resonant lengths of 200 μm or less, where the optical gain is small. The short resonator enables low power consumption in low optical output applications such as wearable devices.

[0163] (Process of dividing the support substrate) Next, the support substrate SK may be divided into multiple support bodies ST. This allows for the creation of a semiconductor laser chip 21 in which one or more semiconductor laser elements 20 are held on the support bodies ST. Figure 26 is a schematic cross-sectional view showing the step of dividing the support substrate SK in the manufacturing method of the semiconductor laser element of Example 1.

[0164] As shown in Figure 26, the support substrate SK is divided to form multiple semiconductor laser chips 21, each on which a semiconductor laser element 20 is arranged. The support ST can be used as a substrate (also called a submount) for the semiconductor laser chips 21. The semiconductor laser chips 21 function as COS (Chip on Submount).

[0165] The support substrate SK may be divided into a support body ST using known cutting methods such as dicing or scribing. The support substrate SK may be cut at any point while avoiding damage to the semiconductor laser element 20. The support body ST may contain one semiconductor laser element 20 or two or more semiconductor laser elements 20.

[0166] In the above-described embodiment 1, the base semiconductor layer 8 and the compound semiconductor layer 9 spontaneously cleave on the template substrate 7, separating them into multiple semi-element parts sDS. Therefore, there is no need to add a separate process for cleaving the base semiconductor layer 8 and the compound semiconductor layer 9. As a result, the manufacturing cost of the semiconductor laser element 20 can be reduced.

[0167] [Another configuration example 1] (1A) The ELO method does not limit the formation of multiple base semiconductor layers 8 in an island-like manner; adjacent base semiconductor layers 8 may be brought together by relatively increasing the growth time during film deposition of the base semiconductor layers 8. In this case, the upper surface of the base semiconductor layers 8 may be polished. A compound semiconductor layer 9 can be deposited on a flat base semiconductor layer 8. A compound semiconductor layer 9 having a starting point 9T may be formed by dry etching or the like on the base semiconductor layer 8 and the compound semiconductor layer 9. A base semiconductor layer 8 having a starting point 8K may also be formed. This makes it possible to create a semiconductor substrate 10 that can be isolated on a template substrate 7. For example, a semiconductor substrate 10 having a base semiconductor layer 8 and a compound semiconductor layer 9 in the form shown in Figure 16 may be used.

[0168] (1B) After growing a base semiconductor layer 8 on a template substrate 7 in the MOCVD apparatus, the semiconductor substrate 10 may be temporarily removed from the MOCVD apparatus before depositing the compound semiconductor layer 9. In this case, removing the semiconductor substrate 10 from the MOCVD apparatus may cause cleavage in the base semiconductor layer 8. Subsequently, the semiconductor substrate 10 having the cleaved base semiconductor layer 8 may be loaded into the MOCVD apparatus, and a compound semiconductor layer 9 having a starting point 9T may be deposited. In this case, the exit surface F1 and the opposing surface F2 are included in the end face of the epitaxially grown compound semiconductor layer 9. By epitaxially growing the compound semiconductor layer 9 on a base semiconductor layer 8 having a high-quality cleavage surface, the end face of the compound semiconductor layer 9 can be made high-quality. Therefore, the end face of the epitaxially grown compound semiconductor layer 9 can be used as the resonator surface.

[0169] (1C) In Example 1, the mask portion 5 was removed after the element portion DS was formed on the template substrate 7. However, in another configuration example, the mask portion 5 may be removed before the process of forming the element portion DS. For example, the mask portion 5 may be removed after forming the half-element portion sDS by separating the elements on the template substrate 7, and before forming the element portion DS. In this case, there is an advantage that it is not necessary to protect the insulating film DF so that it is not removed when the mask portion 5 is removed.

[0170] (1D) In another configuration example, the second electrode E2 and the reflective mirror film UF may be formed with the element portion DS supported using a temporary substrate, and then the semiconductor laser element 20 may be mounted on the support substrate SK. Alternatively, with the semiconductor laser element 20 sandwiched between the temporary substrate and the support substrate SK, both the temporary substrate DK and the support substrate SK may be separated. In this case, the separated pieces of the temporary substrate DK may be removed.

[0171] Alternatively, a first support substrate with wiring may be used instead of the temporary substrate DK. In this case, both the first support substrate and the support substrate SK (second support substrate) may be cut while the semiconductor laser element 20 is sandwiched between them. This may result in a semiconductor laser chip 21 comprising individual pieces of the first support substrate and a support ST.

[0172] (1E) Figure 27 is a plan view illustrating another example of the base semiconductor layer 8 in Example 1. As shown in Figure 27, the base semiconductor layer 8 in this example may have a starting point 8K in a plan view, where the notch is formed close to the starting point induction portion 5Y. The tip of the starting point 8K is referred to as the tip portion 8P. For example, in a plan view, the starting point 8K may be positioned so that the tip portion 8P overlaps with the starting point induction portion 5Y. The starting point 8K may also have a virtual triangular shape in a plan view. In this virtual triangle, the virtual line segment corresponding to the base when the tip portion 8P is the vertex is referred to as side 8C. The distance from side 8C to tip portion 8P is referred to as the notch length H2 of the starting point 8K. The notch length H2 may be WM / 4 or greater, and may be WM / 3 or greater, using the width WM of the mask portion 5 (see Figure 4). The notch length H2 may also be WM / 2 or less.

[0173] By forming a compound semiconductor layer 9 on a base semiconductor layer 8, the compound semiconductor layer 9 is formed in a shape having a starting point (not shown) corresponding to the starting point 8K. The starting point formed in the compound semiconductor layer 9 may have an end face that is the m-plane of the GaN-based semiconductor, as it is formed in a shape corresponding to the starting point 8K. The end face of the starting point formed in the compound semiconductor layer 9 does not have to be the m-plane of the GaN-based semiconductor.

[0174] Figure 28 is an exploded perspective view illustrating the configuration of the semi-device portion sDS formed by separating the base semiconductor layer 8 and the compound semiconductor layer 9. In Figure 28, for the sake of explanation, the template substrate 7 and the base semiconductor layer 8 are shown virtually separated, but in reality, the base semiconductor layer 8 and the mask portion 5 are in contact. The base semiconductor layer 8 also has a junction portion 8S on its lower surface that corresponds to the initial growth layer SL, and the junction portion 8S and the seed layer 3 are bonded to each other. Furthermore, in Figure 28, only a portion of the template substrate 7 is shown, not the entire structure.

[0175] As shown in Figure 28, in one example of a semi-element sDS, the base semiconductor layer 8 does not necessarily have a third sub-face 8X3 on the first base end face 8X. The angle (interior angle) between the second base end face 8Y and the third base end face 8Z is called θ4. θ4 may be an obtuse angle, for example, 120° or approximately 120°, or for example, around 110° to 130°. Alternatively, θ4 may exceed 130°. The second base end face 8Y may be the m-plane of a GaN-based semiconductor.

[0176] (1F) In another configuration example of Example 1, the element portion DS may have a portion of the compound semiconductor layer 9 removed by etching or the like, or the compound semiconductor layer 9 may be partially formed on the base semiconductor layer 8. In this case, the first electrode E1 may be connected to the first pad P1 via the first junction A1, and the second electrode E2 may be connected to the second pad P2 via the conductive film MF and the second junction A2. In this example, it is not necessary to form an insulating film D1 covering the sides of the base semiconductor layer 8 and the compound semiconductor layer 9, and the element portion DS can be mounted on the support substrate SK.

[0177] [Example 2] In Example 1, the semiconductor laser element 20 had a double-sided electrode structure, but in Example 2, the semiconductor laser element 20 may have a single-sided two-electrode structure. Figure 29 is a cross-sectional view showing the configuration of the semiconductor laser element 20 in Example 2.

[0178] As shown in Figure 29, the semiconductor laser element 20 in Example 2 may comprise an element portion DS including a base semiconductor layer 8 and a compound semiconductor layer 9, and a support substrate SK that holds the element portion DS. Examples of materials for the support substrate SK include Si, SiC, and AlN. The support substrate SK is arranged such that the compound semiconductor layer 9 and the first electrode E1 and second electrode E2 are positioned between the support substrate SK and the base semiconductor layer 8.

[0179] The first electrode E1 overlaps with the optical resonator LK (not shown) in a plan view and also overlaps with the second part B2 of the base semiconductor layer 8. The second electrode E2 is provided on the same side of the base semiconductor layer 8 as the first electrode E1. The second electrode E2 is in contact with the base semiconductor layer 8, and in a plan view, the first electrode E1 and the second electrode E2 do not overlap each other. Specifically, the base semiconductor layer 8 has a greater width in the X direction than the compound semiconductor layer 9, and the second electrode E2 is formed in the exposed portion where the compound semiconductor layer 9 is not formed. The exposed portion may be formed by removing a part of the compound semiconductor layer 9 by reactive ion etching (RIE) or the like, or it may be formed by partially depositing the compound semiconductor layer 9 on the base semiconductor layer 8. Although not shown, the compound semiconductor layer 9 may have an optical resonator LK, and the pair of resonator surfaces of the optical resonator LK may be covered with a reflective mirror film UF.

[0180] The support substrate SK includes conductive first pads P1 and second pads P2. The first electrode E1 is connected to the first pad P1 via a first junction A1, and the second electrode E2 is connected to the second pad P2 via a second junction A2. In Example 2, the second junction A2 is thicker than the first junction A1, and the difference in thickness between the first junction A1 and the second junction A2 is greater than or equal to the thickness of the compound semiconductor layer 9. This enables connection between the first and second electrodes E1 and E2 and the first and second pads P1 and P2, which are located on the same plane.

[0181] The support substrate SK may be a divided support ST, in which case the semiconductor laser element 20 may be a semiconductor laser chip 21. The support ST can be used as a substrate (also called a submount) for the semiconductor laser chip 21. The semiconductor laser chip 21 functions as a COS (Chip on Submount).

[0182] Figure 30 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor laser element 20 in Example 2. As shown in Figure 30, Example 2 includes the steps of: preparing a template substrate 7 including a base substrate UK and a mask layer 6; forming a first semiconductor layer S1 (and a third semiconductor layer S3) which will become the base semiconductor layer 8 using the ELO method (described later); and forming a second semiconductor layer S2 (and a fourth semiconductor layer S4) which will become the compound semiconductor layer 9. A mask layer 6 having an initiation point induction portion 5Y may be formed on the mask portion 5, in which case the first semiconductor layer S1 (and the third semiconductor layer S3) has an initiation point portion 8K. Furthermore, when the second semiconductor layer S2 is formed on the first semiconductor layer S1 at a position including the initiation point portion 8K, it can be formed to have an initiation point portion 9T.

[0183] The starting point 8K may be formed in the third part B3, and the second semiconductor layer S2 may be provided above the second part B2. In this case, the optical resonator LK is provided at a position that overlaps with the second part B2 in a plan view. The second semiconductor layer S2 does not have to have a starting point 9T, and a starting point for cleavage may be formed by scribing as described later (e.g., in Example 3).

[0184] Next, a semi-element portion sDS is formed by separating the elements on the template substrate 7. Subsequently, a ridge portion RJ is formed on the first semiconductor layer S1, and the first electrode E1 and the second electrode E2 are formed. This forms an element portion DS having a single-sided two-electrode structure on the template substrate 7.

[0185] Next, the element portion DS is bonded to the support substrate SK, and the first semiconductor layer S1 is separated from the template substrate 7. For example, after the formation of the element portion DS, the mask portion 5 is etched off, and the element portion DS is bonded to the support substrate SK while the first and second bonding portions A1 and A2 (e.g., solder) of the support substrate SK are heated and melted. Then, either or both of the support substrate SK and the base substrate UK are displaced so that the support substrate SK and the base substrate UK move away from each other. As a result, the bonding portion (downward protrusion) on the back surface of the first semiconductor layer S1 with the base substrate UK breaks, and the first semiconductor layer S1 is separated from the template substrate 7. As a result, a two-dimensional arrangement type semiconductor laser substrate (see Figure 22) is formed.

[0186] Then, the two-dimensional arrangement semiconductor laser substrate may be divided row by row to form a one-dimensional arrangement (rod-shaped) semiconductor laser substrate, and subsequently, a reflective mirror film UF may be formed on the emission surface F1 and the opposing surface F2, respectively. Next, the support substrate SK may be divided into a plurality of support bodies ST. By holding one or more semiconductor laser elements 20 on each support body ST, a plurality of semiconductor laser chips 21 can be formed.

[0187] [Example 3] In Example 3, a template substrate 7 without a starting point induction portion 5Y in the mask portion 5 may be used. In Example 3, a semiconductor laser element 20 with a single-sided two-electrode structure is manufactured. Figure 31 is a flowchart showing an example of a method for manufacturing a semiconductor laser element in Example 3.

[0188] As shown in Figure 31, in Example 3, first, a template substrate 7 (see Figure 4) without an initiation point in the mask layer 6 is prepared, and then a base semiconductor layer 8 and a compound semiconductor layer 9 are formed on the template substrate 7.

[0189] In Example 3, for example, the template substrate 7 may be prepared as follows. First, a silicon oxide film with a thickness of about 100 nm to 4 μm (preferably about 150 nm to 2 μm) is formed over the entire surface of the underlayer 4 using sputtering, CVD, or vapor deposition. Then, a resist is applied to the entire surface of the silicon oxide film. After that, the resist is patterned using photolithography to form a resist with multiple stripe-shaped openings. Subsequently, a portion of the silicon oxide film is removed using a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF) to form multiple openings KS and mask portions 5. Next, the mask layer 6 is formed by removing the resist with organic cleaning. This allows a template substrate 7 as shown in Figure 4 to be obtained.

[0190] Next, the template substrate 7 is placed in the MOCVD apparatus and a GaN-based semiconductor layer is deposited by the ELO method. In Example 3, the base semiconductor layer 8 is an n-type GaN layer, and Si-doped GaN is deposited on the template substrate 7 using the MOCVD apparatus. As an example of ELO deposition conditions, the following can be used: substrate temperature: 1120°C, growth pressure: 50kPa, TMG (trimethylgallium): 22sccm, NH3: 15slm, V / III = 6000 (ratio of the amount of Group V raw material supplied to the amount of Group III raw material supplied). An initial growth layer SL is selectively grown on the seed layer 3 (the uppermost GaN layer of the seed layer 3) exposed in the opening KS, and then grows laterally on the mask portion 5. Then, the lateral growth of these layers is stopped before the base semiconductor layers 8 growing laterally from both sides on the mask portion 5 meet.

[0191] Furthermore, the film deposition time may be extended to cause adjacent base semiconductor layers 8 to associate with each other. If they are associated, the associated portions of the base semiconductor layers 8 may be removed by dry etching or the like after forming the compound semiconductor layer 9 on the base semiconductor layer 8.

[0192] Figure 32 is a plan view showing the configuration of the semiconductor substrate 10 on which the base semiconductor layer 8 is deposited in Example 3. As shown in Figure 32, in Example 3, the base semiconductor layer 8 does not have a starting point 8K.

[0193] Next, the following steps are taken: forming a compound semiconductor layer 9, forming an element structure, and forming a cleavage starting point. Figure 33 is a plan view showing the configuration of the semiconductor substrate 10 on which the element structure in Example 3 is formed. Figure 34 is a cross-sectional view showing the configuration of the semiconductor substrate 10 in Figure 33. In Figure 34, the template substrate 7 is omitted from the illustration.

[0194] The compound semiconductor layer 9 may be formed over the entire surface of the base semiconductor layer 8, in which case a portion of the base semiconductor layer 8 may be exposed by reactive ion etching. Alternatively, the compound semiconductor layer 9 may be partially formed on the upper surface of the base semiconductor layer 8. A second electrode E2 may be formed on the exposed portion of the base semiconductor layer 8. Then, a ridge portion RJ is formed on the compound semiconductor layer 9, along with an insulating film DF and a first electrode E1. This makes it possible to obtain a semiconductor substrate 10 having a template substrate 7 and an element structure 22 formed on the template substrate 7.

[0195] Next, a cleavage starting point is formed in the element structure 22. The cleavage starting point may be formed in the base semiconductor layer 8 or in the compound semiconductor layer 9. The method for forming the cleavage starting point is not particularly limited. For example, the cleavage starting point may be formed by diamond scribing, in which case the starting point can be made into a thin shape, so the cleavage starting point tends to concentrate in one place. Therefore, a smooth cleavage surface can be easily obtained. Since the insulating film DF formed on the compound semiconductor layer 9 is thin, the presence of the insulating film DF can be ignored, and a cleavage starting point can be formed in the compound semiconductor layer 9. The insulating film DF does not need to be formed in the part of the compound semiconductor layer 9 where the cleavage starting point is formed. In other words, the compound semiconductor layer 9 may be exposed in the part of the insulating film DF where the cleavage starting point is formed.

[0196] Alternatively, the starting point for cleavage may be formed by laser scribing, in which case the variation in scribe length can be reduced, thus improving yield. The length of the laser scribe is the scanning distance of the laser. Alternatively, the starting point for cleavage may be formed by dry etching or wet etching, in which case the cleavage proceeds without deviating from the cleavage surface, making it easier to obtain a smooth cleavage surface.

[0197] The starting point for cleavage may be formed by combining the above methods. In this case, the advantages of each method can be enjoyed simultaneously. The starting point formed by diamond scribing or laser scribing may be further wet-etched, in which case the shape of the starting point for cleavage can be shaped. Alternatively, the starting point formed by dry etching may be further wet-etched, in which case the shape of the starting point for cleavage can be shaped.

[0198] Next, the element structure 22, which has a cleavage starting point, is cleaved. For example, a blade can be applied to the cleavage starting point and force can be applied in a direction perpendicular to the surface direction to generate a cleavage at the starting point. In this case, a strong force can be applied to the cleavage starting point, thus improving the yield. Alternatively, vibration can be applied to the cleavage starting point to generate a cleavage at the starting point. In this case, the process can be carried out relatively easily, thus simplifying the manufacturing process.

[0199] Alternatively, by raising or lowering the temperature of the semiconductor substrate 10 above room temperature, thermal stress may be applied to the starting point to induce cleavage by utilizing the difference in thermal expansion coefficients between the main substrate 1 and the base semiconductor layer 8. When the difference in thermal expansion coefficients is utilized, in-plane variations in how force is applied are eliminated, improving yield.

[0200] Alternatively, the template substrate 7, which has been thinned by polishing or the like, may be curved to apply stress to the element structure 22 on the template substrate 7 and perform cleavage. In this case, the element structure 22 can be separated into elements, and multiple element parts DS can be formed at once. Therefore, manufacturing costs can be reduced.

[0201] The element structure 22 may also be cleaved by combining the above cleavage techniques. In that case, the advantages of each technique can be enjoyed simultaneously.

[0202] In Example 3, it is desirable that the mask portion 5 be removed to separate the element portion DS from the template substrate 7 after the formation of the cleavage starting point or after cleavage. This allows for stable formation of the starting point or cleavage, improving the yield.

[0203] In Example 3, internal stress may be generated in the base semiconductor layer 8 due to a difference in thermal expansion coefficients between the template substrate 7 and the base semiconductor layer 8. Furthermore, internal stress may be generated in the base semiconductor layer 8 due to a difference in lattice constants between the template substrate 7 and the base semiconductor layer 8. The presence of internal stress in the base semiconductor layer 8 makes cleavage even more likely.

[0204] For example, internal stress is generated in the base semiconductor layer 8 and the compound semiconductor layer 9 due to the difference in thermal expansion coefficients between the base semiconductor layer 8 and the compound semiconductor layer 9 and the main substrate 1. For instance, when forming the base semiconductor layer 8 on a dissimilar substrate such as a Si substrate using the ELO method, the film deposition temperature can be as high as 1000°C or higher. Therefore, stress is generated in the base semiconductor layer 8 when the temperature is reduced to room temperature. In addition, strain is generated in the base semiconductor layer 8 due to the difference in lattice constants between the main substrate 1 and the base semiconductor layer 8.

[0205] Here, if the thermal expansion coefficient of the main substrate 1 is greater than that of the base semiconductor layer 8, compressive stress is generated in the base semiconductor layer 8, and if the thermal expansion coefficient of the main substrate 1 is smaller than that of the base semiconductor layer 8, tensile stress is generated in the base semiconductor layer 8. Due to the tensile stress in the base semiconductor layer 8, cleavage may occur by scribing the compound semiconductor layer 9. When cleaving the base semiconductor layer 8 under tensile stress, the possibility of the divided pieces of the base semiconductor layer 8 coming into contact with each other can be reduced. Therefore, the possibility of damage to the end faces of the divided base semiconductor layer 8 can be reduced. In addition, because cleavage occurs in the element structure 22 as if being torn from the starting point due to the application of tensile stress, the cleavage surface tends to be smooth.

[0206] For example, by scribing the base semiconductor layer 8, the internal stress of the base semiconductor layer 8 is released, and the cleavage of the device structure 22 may proceed naturally. Alternatively, by scribing the compound semiconductor layer 9, the internal stress of the base semiconductor layer 8 is released, and the cleavage of the device structure 22 may proceed naturally. When cleavage proceeds naturally by scribing, it means that scribing and cleavage occur at the same or approximately the same time (cleavage occurs spontaneously in conjunction with scribing). This makes it possible to omit the process of cleaving the starting point (break process) from the process of forming the starting point (scribing process). Therefore, the manufacturing cost of the semiconductor laser device 20 can be reduced.

[0207] Next, the element unit DS is separated from the template substrate 7. The subsequent steps are the same as in Examples 1 and 2, so the explanation will be omitted.

[0208] As described above, in Example 3, the cleavage initiation point can be formed at any position after the element structure has been formed. Therefore, the position where the cleavage initiation point is formed can be controlled. As a result, the position where cleavage occurs can be controlled, and the resonator length L1 can be adjusted. Consequently, it is easier to improve the yield.

[0209] [Another configuration example 3] In the above embodiment 3, the process of forming the element structure was performed first, followed by the process of forming the starting point and the process of separating the elements on the template substrate 7. However, the order is not limited to this. Alternatively, the process of forming the starting point may be performed first, followed by the process of forming the element structure, and then the process of separating the elements on the template substrate 7.

[0210] [Example 4] In Example 4, element separation may be performed by etching instead of cleavage. Figure 35 is a plan view showing an example of element separation in Example 4.

[0211] As shown in Figure 35, after forming the base semiconductor layer 8 and the compound semiconductor layer 9 on the template substrate 7, etching is performed to form a plurality of trenches TR (isolation grooves) on the semiconductor substrate 10. This allows for element isolation of the template substrate 7 into a plurality of semi-element portions sDS having optical resonators LK. The trenches TR penetrate the compound semiconductor layer 9 and the base semiconductor layer 8. The mask portion 5 and the seed layer 3 or main substrate 1 may be exposed within the trenches TR.

[0212] Note that etching may cause a taper angle to form on the edge face of the compound semiconductor layer 9 (the edge face may deviate from the perpendicular). Therefore, for example, element isolation may be performed as follows: First, the semiconductor substrate 10 is set in the etching apparatus with a slight tilt. Next, a trench TR corresponding to one side in the Y direction of the semi-element portion sDS, which will be formed by the subsequent etching process, is formed by etching. This forms one of the pair of resonator surfaces of the semi-element portion sDS (for example, the exit surface F1). As a result, for example, the exit surface F1 can be formed vertically or approximately vertically. Next, the semiconductor substrate 10 is set in the etching apparatus with a slight tilt to the opposite side (the side opposite to when the trench TR was formed). Then, a trench TR corresponding to one side in the Y direction of the semi-element portion sDS is formed by etching. This forms the other of the pair of resonator surfaces of the semi-element portion sDS (for example, the opposing surface F2). As a result, for example, the opposing surface F2 can be formed vertically or approximately vertically.

[0213] [Example 5] Figure 36 is a schematic diagram showing the configuration of an electronic device according to Example 5. The electronic device 50 in Figure 36 includes a semiconductor laser device ZD (semiconductor laser element 20 or semiconductor laser chip 21) and a control unit 80 which includes a processor and controls the semiconductor laser device ZD. Examples of electronic devices 50 include lighting devices, display devices, communication devices, information processing devices, medical devices, electric vehicles (EVs), etc.

[0214] [Example 6] In Example 1, the compound semiconductor portion 9 is provided on the c-plane of the base semiconductor portion 8, and the pair of resonator surfaces are the m-planes of the nitride semiconductor, but the invention is not limited to this. For example, the compound semiconductor portion 9 can be provided on the m-plane ((1-100) plane) of the base semiconductor portion 8, and the pair of resonator surfaces can be the c-plane ((0001) plane) of the nitride semiconductor. The resonator length L1 is the length in the c-axis direction. The exit surface F1 and the opposing surface F2 can be formed, for example, by c-plane cleavage of the nitride semiconductor.

[0215] [Additional notes] The inventions described in this disclosure have been explained above based on the drawings and embodiments. However, the inventions described in this disclosure are not limited to the embodiments described above. That is, the inventions described in this disclosure can be modified in various ways within the scope shown in this disclosure, and embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the inventions described in this disclosure. In other words, it should be noted that it is easy for those skilled in the art to make various modifications or alterations based on this disclosure. Furthermore, it should be noted that these modifications or alterations are included in the scope of this disclosure. [Explanation of Symbols]

[0216] 1 Main board 5 Mask section 5Y Initiation Point 6 Mask Layers (Mask) 7. Template board 8. Base semiconductor layer (base semiconductor portion) 8K, 9T starting point (starting point) 9. Compound semiconductor layer (compound semiconductor portion) 20. Semiconductor laser elements (semiconductor devices) 21 Semiconductor laser chips 70 Manufacturing equipment B1 Part 1 B2 Part 2 B3 Part 3 DS element section E1 1st electrode E2 2nd electrode F1 Output surface (resonator surface) F2 Opposing surface (resonator surface) LK optical resonator RJ Ridge Section sDS (Semi-element section) (Element section) SK support board

Claims

1. Main board and A mask pattern formed above the main substrate, having a mask portion and an opening with the first direction being the longitudinal direction and the second direction being the short direction, A base semiconductor portion comprising a nitride semiconductor, having a first portion located above the opening and a second portion extending from the first portion above the mask portion, The mask portion has a plurality of protrusions that project inward from the end of the opening in the second direction toward the inside of the opening, A semiconductor substrate in which, in the second direction, the orientation of the multiple protrusions is aligned in one direction.

2. The semiconductor substrate according to claim 1, wherein the protruding length of the convex portion is 0.1 μm or more and 10 μm or less.

3. The semiconductor substrate according to claim 1, wherein the protrusions are formed over the thickness direction of the mask portion.

4. The semiconductor substrate according to claim 1, wherein the apex of the convex portion has a rounded shape.

5. The semiconductor substrate according to claim 1, wherein the thickness of the protrusions in the mask portion is different from the thickness of the portions of the mask portion other than the protrusions.

6. The semiconductor substrate according to claim 1, wherein the opening is narrower in the portion where the protrusion is located.

7. The semiconductor substrate according to claim 1, comprising a plurality of base semiconductor portions arranged in the second direction, including the base semiconductor portion.

8. The semiconductor substrate according to claim 1, wherein the protrusion includes a portion that tapers in a direction toward the inside of the opening.

9. The semiconductor substrate according to claim 1, wherein the base semiconductor portion has recesses corresponding to the plurality of protrusions.

10. The semiconductor substrate according to claim 1, wherein the plurality of protrusions have a shape in which, in a plan view, the vertices of the protrusions extend beyond the center of the opening.

11. The semiconductor substrate according to claim 1, wherein the plurality of protrusions have a shape such that, in a plan view, the vertices of the protrusions do not extend beyond the center of the opening.

12. The semiconductor substrate according to any one of claims 1 to 11, wherein the main substrate is a heterogeneous substrate having a different lattice constant from the nitride semiconductor.

13. The semiconductor substrate according to any one of claims 1 to 11, wherein the through-dislocation density of the second part is 1 / 5 or less of the through-dislocation density of the first part.

14. The semiconductor substrate according to any one of claims 1 to 11, wherein the first direction is the m-axis direction of the nitride semiconductor, and the second direction is the a-axis direction of the nitride semiconductor.

15. A semiconductor substrate comprising: a main substrate; a mask pattern formed above the main substrate and having a mask portion and an opening with a first direction as the longitudinal direction and a second direction as the short direction; and a base semiconductor portion having a nitride semiconductor and having a first portion located above the opening and a second portion extending from the first portion above the mask portion, wherein the mask portion has a plurality of protrusions projecting inward from the edge of the opening in the second direction, and in the second direction, the direction in which the plurality of protrusions project is aligned in one direction; A method for manufacturing a semiconductor device, comprising the step of forming a compound semiconductor portion on top of the semiconductor substrate.

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