Optoelectronic semiconductor component, and method for manufacturing at least one optoelectronic semiconductor component

Abstract

An optoelectronic semiconductor component and a method for manufacturing at least one optoelectronic semiconductor component, comprising: a semiconductor layer stack (2), at least one recess (19), a first contact structure (11), and a second contact structure (21), wherein the semiconductor layer stack (2) comprises a first semiconductor region (4), a second semiconductor region (6), and an active region (5) arranged between the first and second semiconductor regions (4, 6), the second semiconductor region (6) comprising a first semiconductor layer (7) and a second semiconductor layer (8), the second semiconductor layer (8) being arranged on an opposite side of the first semiconductor layer (7) from the active region (5), the at least one recess (19) extending from a first main surface (2A) of the semiconductor layer stack (2) to the second semiconductor layer (8), through the first semiconductor region (4) and the active region (5), The first contact structure (11) is a structure for making electrical contact with the first semiconductor region (4) and is arranged in at least a portion of the first main surface (2A), the second contact structure (21) is a structure for making electrical contact with the second semiconductor region (6) and is arranged in a portion of the first main surface (2A) and in at least one of the recesses (19), the first semiconductor layer (7) is made of a first compound semiconductor material, and the second semiconductor layer (8) is made of a second compound semiconductor material, the first compound semiconductor material having a higher aluminum content than the second compound semiconductor material, an optoelectronic semiconductor component (1), and a method for manufacturing such an optoelectronic semiconductor component (1) are also provided.

Description

[Technical Field]

[0001] Optoelectronic semiconductor components and methods for manufacturing at least one optoelectronic semiconductor component are specified. For example, the optoelectronic semiconductor component is an InGaAlP-based semiconductor component. The optoelectronic semiconductor component may be intended to generate or emit electromagnetic radiation. [Background technology]

[0002] For example, in the case of radiation-emitting semiconductor components based on InGaAlP compound semiconductor materials, various electrical contacts are possible. For instance, a first electrode with a first polarity, such as a p-electrode, can be placed at the back, and a second electrode with a second polarity, such as an n-electrode, can be placed at the front. However, if the second electrode for radiation emission is placed at the front, absorption loss occurs there. As an alternative, a via can be provided that completely penetrates the semiconductor chip and extends forward. In this case, although the second electrode is small in size, it is again placed at the front, which may result in absorption loss. It is also possible to electrically contact a semiconductor region located at the front from the back with one or more vias that penetrate the semiconductor chip. However, because there are relatively high tolerances in the manufacturing of the recess where the via is created, the semiconductor layer contacted by the via needs to be as thick as possible. Therefore, relatively high absorption loss occurs due to its thickness and the potentially high doping levels. [Overview of the project]

[0003] One of the objectives of this disclosure is to provide more efficient optoelectronic semiconductor components. A further objective of this disclosure is, in particular, to provide a more efficient method for manufacturing at least one optoelectronic semiconductor component.

[0004] These objectives are achieved, in particular, by a method for manufacturing at least one optoelectronic semiconductor component having independently claimed features.

[0005] Further advantages and configurations of methods for manufacturing optoelectronic semiconductor components and optoelectronic semiconductor components are the subject of the dependent claims.

[0006] According to at least one embodiment of the optoelectronic semiconductor component, the semiconductor component comprises a semiconductor layer stack having a first semiconductor region, a second semiconductor region, and an active region, wherein the active region is located between the first and second semiconductor regions. The active region may be configured to generate or emit electromagnetic radiation in the visible to infrared spectral range, for example.

[0007] Furthermore, the active region may include a sequence of individual layers. These individual layers can form a quantum well structure, particularly a single quantum well (SQW) structure or a multiple quantum well (MQW) structure.

[0008] The first semiconductor region may have a first conductivity type, for example, p conductivity. Furthermore, the second semiconductor region may have a second conductivity type, for example, n conductivity. However, the second semiconductor region may be a p-conducting semiconductor region and the first semiconductor region may be an n-conducting semiconductor region. The first and second semiconductor regions may each have a sequence of individual layers, some of which may be undoped or lightly doped. The individual layers may be layers epitaxially grown on a growth substrate.

[0009] According to at least one embodiment, the second semiconductor region comprises a first semiconductor layer made of a first compound semiconductor material and a second semiconductor layer made of a second compound semiconductor material different from the first compound semiconductor material. The first compound semiconductor material may have a higher aluminum content than the second compound semiconductor material. By selecting a suitable etchant with sufficient selectivity, the higher the aluminum content in the first semiconductor layer, the higher the etching rate compared to the second semiconductor layer. As a result, the etching process can be stopped at the second semiconductor layer. This makes it possible to set the etching depth with particular precision and to determine the longitudinal extension of the generated recesses with relatively high accuracy.

[0010] According to at least one embodiment, the second semiconductor layer is located on the opposite side from the active region of the first semiconductor layer.

[0011] According to at least one embodiment, the optoelectronic semiconductor component includes at least one recess extending from a first main surface to a second semiconductor layer of the semiconductor layer stack, through a first semiconductor region and an active region. The first main surface may be a surface of the semiconductor layer stack that separates the optoelectronic semiconductor component on the side facing the back.

[0012] According to at least one embodiment, the optoelectronic semiconductor component comprises a first contact structure for electrically contacting a first semiconductor region and a second contact structure for electrically contacting a second semiconductor region. The first contact structure can be located in at least a portion of the first main surface. Furthermore, the second contact structure can be located in a portion of the first main surface and in at least one recess. The first and second contact structures allow the optoelectronic semiconductor component to be electrically connected from the outside on only one side of the semiconductor component, for example, the side. The first and second contact structures also enable a uniform current distribution in the semiconductor layer stack, and can also realize larger semiconductor components.

[0013] An optoelectronic semiconductor component according to at least one embodiment includes a semiconductor layer stack, At least one recess, First contact structure, A second contact structure is provided, The above semiconductor layer stack comprises a first semiconductor region, a second semiconductor region, and an active region disposed between the first and second semiconductor regions. The above-mentioned second semiconductor region comprises a first semiconductor layer and a second semiconductor layer. The second semiconductor layer is positioned on the opposite side of the active region of the first semiconductor layer. The at least one recess described above extends from the first main surface of the semiconductor layer stack to the second semiconductor layer, passing through the first semiconductor region and the active region. The above-mentioned first contact structure is a structure for electrically contacting the above-mentioned first semiconductor region, and is arranged in at least a portion of the area of ​​the first main surface. The above-mentioned second contact structure is a structure for electrically contacting the above-mentioned second semiconductor region, and is arranged in a portion of the first main surface and at least one of the above-mentioned recesses. The above-mentioned first semiconductor layer is made of a first compound semiconductor material. The above-mentioned second semiconductor layer is made of a second compound semiconductor material. The first compound semiconductor material has a higher aluminum content than the second compound semiconductor material.

[0014] For example, at least one recess or the contact area of ​​a second contact structure located in a recess may have a three-dimensional shape with an invariant cross-section, such as a cylinder or a rectangular parallelepiped. However, at least one recess or the contact area located in a recess may have a three-dimensional shape with a changing cross-section, such as a frustoconical or truncated square pyramidal shape. The cross-section may become smaller in the depth direction. For example, the shape and size of the contact area are determined by the shape and size of the recess. The shape and size of the contact area may be substantially the same as, at least, the shape and size of the recess.

[0015] If multiple recesses or contact regions exist, for example, their size and / or spacing may be varied to compensate for the contact resistance and / or surface resistance in the second semiconductor region.

[0016] According to at least one embodiment or configuration, the first compound semiconductor material is a phosphorus compound semiconductor material, i.e., a phosphorus-containing semiconductor material. Furthermore, the second compound semiconductor material may also be a phosphorus compound semiconductor material. InGaAlP can be used for the first and second phosphorus compound semiconductor materials.

[0017] According to at least one embodiment or configuration, the first compound semiconductor material is Al n Ga m In 1-n-mIt contains P, where 0.3 ≤ n ≤ 0.6, 0 ≤ m ≤ 0.2, and 0.4 ≤ n + m ≤ 0.6. The first semiconductor layer may have a function as a buffer layer. An indium content between 40% and 60% can achieve an appropriate lattice constant.

[0018] According to at least one embodiment or configuration, the second compound semiconductor material is Al n Ga m In 1-n-m It contains P, where 0 < n < 0.6, 0 < m < 0.6, and 0.4 ≤ n + m ≤ 0.6. The second semiconductor layer may have a function as, for example, a contact layer or a contact layer兼current diffusion layer. The second semiconductor layer may be formed thinner than the first semiconductor layer. For example, the second semiconductor layer may have a thickness of 10 nm to 500 nm, particularly 20 nm to 100 nm, and the manufacturing tolerance may be ±10%. By making the thickness relatively thin, the absorption loss in the second semiconductor layer or contact layer becomes relatively small.

[0019] According to at least one embodiment or configuration, the second semiconductor region has a third semiconductor layer disposed on the side of the second semiconductor layer opposite to the first semiconductor layer. For the third semiconductor layer, a phosphorus compound semiconductor material, particularly InGaAlP, is suitable as with the first and second semiconductor layers. The compound semiconductor materials of the second and third semiconductor layers may have different gallium contents and / or doping levels. For example, as described above, the second semiconductor layer may be a contact layer, and the third semiconductor layer may be a current diffusion layer.

[0020] According to at least one embodiment or configuration, the second main surface opposite to the first main surface of the semiconductor layer stack does not have the first and second contact structures. The second main surface may be located in front of the optoelectronic semiconductor component that emits radiation. Most of the emitted radiation passes through the second main surface and may be partially absorbed in the contact structure disposed on the second main surface. This can be advantageously prevented by disposing the contact structure outside the second main surface.

[0021] According to at least one embodiment or configuration, at least one recess has a widened region between the active region and the second semiconductor layer. The widened region can be regarded as indicating a two-step etching process for manufacturing at least one recess, as will be described in more detail below in relation to the manufacturing method.

[0022] For example, the widened region may have a depth or vertical extent that is at least about 25% of the thickness of the first semiconductor layer and at most corresponds to the thickness of the first semiconductor layer. The vertical extent may be, for example, an extent along a vertical direction that is antiparallel to the growth direction in which the semiconductor regions are stacked on top of each other. Also, the widened region may have a lateral extent that is shifted by about 10% with a tolerance of ±10% from the lateral extent in the case where the original shape of the recess is continued at the bottom of the recess. For example, the value of the lateral extent of the widened region can be a value of 5.5 μm to 7.5 μm with a tolerance of ±10%.

[0023] According to at least one embodiment or configuration, the second contact structure includes a connection layer. The connection layer can cover one or more surfaces of the semiconductor layer stack that delimit at least one recess. A material compound and / or layer stack that is a metal is suitable for the connection layer. For example, Au or Pd is suitable for the connection layer. The connection layer may have a dopant such as Ge.

[0024] According to at least one embodiment or configuration, a cavity is provided in the widened region of at least one recess between the semiconductor layer stack and the second contact structure. The cavity may be filled with a gas or may be substantially empty and in a vacuum state. For example, the connection layer and other layers applied to the semiconductor layer stack in the widened region may be formed along the original shape of the recess that would be assumed if the widened region were not provided. Therefore, a cavity may be formed because the second contact structure or the connection layer and other layers may not be conformally applied to the semiconductor layer stack in the widened region of the recess.

[0025] According to at least one embodiment or configuration, the optoelectronic semiconductor component comprises an insulating layer disposed between a semiconductor layer laminate and a connecting layer. The insulating layer may include an electrically insulating material such as silicon oxide or silicon nitride, or may consist of one of these materials. For example, the insulating layer may be disposed on one or more surfaces of the semiconductor layer laminate that laterally divide the recess. The bottom surface of the recess does not need to be covered by the insulating layer so that a second contact structure or connecting layer can come into contact with the second semiconductor layer.

[0026] According to at least one embodiment or configuration, the optoelectronic semiconductor component comprises a carrier on which a semiconductor layer stack is arranged. The first semiconductor region may be located on the carrier side of the active region, and the second semiconductor region may be located on the opposite side from the carrier of the active region. The carrier may include or consist of a semiconductor material such as Ge or Si, or a ceramic material such as SiN.

[0027] The method described below is suitable for manufacturing at least one of the optoelectronic semiconductor components described above. Therefore, the characteristics described for semiconductor components are also applicable to the method, and vice versa.

[0028] According to at least one embodiment or configuration of a method for manufacturing at least one optoelectronic semiconductor component, the method comprises, for example, the following steps in the following order: According to at least one embodiment or configuration of a method for manufacturing at least one optoelectronic semiconductor component, the method comprises, for example, the following steps in the following order: A step of providing a semiconductor layer sequence for manufacturing at least one semiconductor layer stack, The above semiconductor layer sequence comprises a first semiconductor region, a second semiconductor region, an active region disposed between the first and second semiconductor regions, and a first main surface. The above-mentioned second semiconductor region comprises a first semiconductor layer and a second semiconductor layer. The second semiconductor layer is positioned on the opposite side of the active region of the first semiconductor layer, in the process described above. The process involves forming a first contact structure on the first main surface described above, A step of generating at least one recess extending from the first main surface to the second semiconductor layer through the first semiconductor region and the active region, The process includes forming a second contact structure located in a portion of the first main surface and in at least one of the recesses, The above-mentioned at least one recess is generated by a two-stage etching process, wherein the semiconductor layer sequence is etched up to the first semiconductor layer in the first etching step and etched up to the second semiconductor layer in the second etching step.

[0029] In contrast to the two-stage etching process described here, the single-stage etching process requires the semiconductor layer that stops etching to be relatively thick. Conversely, in the two-stage etching process, the second semiconductor layer can be formed relatively thinly, for example, with a thickness between 10 nm and 500 nm, particularly between 20 nm and 100 nm, and a typical manufacturing tolerance of ±10%. On the other hand, the first semiconductor layer, which marks the end of the first etching process, can be formed thicker than the second semiconductor layer. For example, the thickness of the first semiconductor layer can be in the range of 0.4 μm to 0.6 μm, with a tolerance of ±10%. The thickness of the first semiconductor layer is determined, for example, by considering variations in thickness and etching rate that occur during the first etching process.

[0030] The semiconductor layer sequence corresponds to the manufactured semiconductor layer stack, for example, with respect to its layer structure and material composition, and therefore the details apply similarly to the semiconductor layer sequence. Preferably, the first semiconductor region of at least one semiconductor layer stack is formed from the first semiconductor region of the semiconductor layer sequence, the active region of at least one semiconductor layer stack is formed from the active region of the semiconductor layer sequence, and the second semiconductor region of at least one semiconductor layer stack is formed from the second semiconductor region of the semiconductor layer sequence. In particular, the first semiconductor layer of the second semiconductor region is formed from a first compound semiconductor material, for example, InAlP, and the second semiconductor layer is formed from a second compound semiconductor material, for example, InGaAlP, and the first compound semiconductor material has a higher aluminum content than the second compound semiconductor material.

[0031] The semiconductor layer sequence may be provided, for example, on a substrate formed by epitaxial growth.

[0032] Furthermore, the first and second contact structures formed on the semiconductor layer sequence are designed to enable the fabrication of first and second contact structures for at least one optoelectronic semiconductor component. Therefore, the details of the structure and suitable materials for the first and second contact structures of the optoelectronic semiconductor component are similarly applicable. That is, the second contact structure may include a connecting layer provided to generate a connecting layer for the second contact structure of at least one semiconductor component. The connecting layer may cover one or more surfaces of the semiconductor layer sequence that demarcate at least one recess.

[0033] According to at least one embodiment or configuration, the first etching step includes a dry etching process. Furthermore, the second etching step may include a wet chemical etching process. In particular, the second etching step or wet chemical etching process uses an etchant with sufficient selectivity that has a higher etching rate for the first semiconductor layer, which has a higher aluminum content, than for the second semiconductor layer, which has a lower aluminum content. For example, the etching rate in the second semiconductor layer may be an order of magnitude lower than the etching rate in the first semiconductor layer. This allows the etching process to be precisely terminated in the second semiconductor layer. In this way, the desired etching depth can be set as intended.

[0034] Aqueous solutions, such as dilute hydrochloric acid or dilute sulfuric acid, can be used as etching agents.

[0035] According to at least one embodiment or configuration, a widened region of at least one recess is generated by a second etching step. The widened region is created by under-etching in the first semiconductor layer. For the size of the widened region, refer to the description of the optoelectronic semiconductor component above.

[0036] According to at least one embodiment or configuration, an insulating layer is formed between the semiconductor layer sequence and the connecting layer to generate an insulating layer in at least one semiconductor component. Therefore, details regarding the structure and suitable materials of the insulating layer in, for example, an optoelectronic semiconductor component are similarly applicable. For example, the insulating layer may be provided as a closed layer within the semiconductor layer sequence such that it completely covers a first partial region of the recess or a surface demarcating the recess. The insulating layer may then be partially removed to expose the bottom of the recess or the surface of the semiconductor layer sequence located in the first partial region of the recess.

[0037] According to at least one embodiment or configuration, the insulating layer is provided before the second etching step is performed. In this case, the insulating layer may be under-etched during the second etching step and may be provided at a distance from the semiconductor layer sequence. However, the insulating layer may be provided after the second etching step. In this case, the insulating layer may be provided closer to the semiconductor layer sequence.

[0038] According to at least one embodiment or configuration, the active region has a quantum well structure, and hybridization of the quantum well structure is performed in a portion of the active region adjacent to the recess. In this process, the quantum well and the barrier layer are hybridized, resulting in a higher band gap, which in turn reduces charge carriers and suppresses surface recombination. This hybridization process may be applied, for example, to an insulating layer or a connecting layer in the semiconductor layer sequence within the recess. Alternatively, hybridization may be performed before the recess is formed.

[0039] Optoelectronic semiconductor components are suitable for projection and illumination applications in long-wavelength spectral ranges, such as the red to infrared region. [Brief explanation of the drawing]

[0040] Further advantages, favorable embodiments, and further modifications will become apparent from the embodiments described below with reference to the figures, as an example. [Figure 1] A schematic cross-sectional view of each step in a method for manufacturing an optoelectronic semiconductor component according to one embodiment is shown. [Figure 2] A schematic cross-sectional view of each step in a method for manufacturing an optoelectronic semiconductor component according to one embodiment is shown. [Figure 3] A schematic cross-sectional view of each step in a method for manufacturing an optoelectronic semiconductor component according to one embodiment is shown. [Figure 4] A schematic cross-sectional view of each step in a method for manufacturing an optoelectronic semiconductor component according to one embodiment is shown. [Figure 5] A schematic cross-sectional view of each step in a method for manufacturing an optoelectronic semiconductor component according to one embodiment is shown. [Figure 6] A schematic cross-sectional view of each step in a method for manufacturing an optoelectronic semiconductor component according to one embodiment is shown. [Figure 7] A schematic cross-sectional view of each step in a method for manufacturing an optoelectronic semiconductor component according to one embodiment is shown. [Figure 8] A schematic cross-sectional view of each step in a method for manufacturing an optoelectronic semiconductor component according to one embodiment is shown. [Figure 9] A schematic cross-sectional view of each step in a method for manufacturing an optoelectronic semiconductor component according to one embodiment is shown. [Figure 10] A schematic cross-sectional view of each step in a method for manufacturing an optoelectronic semiconductor component according to one embodiment is shown. [Figure 11] A schematic cross-sectional view of each step in a method for manufacturing an optoelectronic semiconductor component according to one embodiment is shown. [Figure 12] A schematic cross-sectional view of an optoelectronic semiconductor component according to one embodiment is shown. [Modes for carrying out the invention]

[0041] In this embodiment and in the drawings, identical elements, elements of the same type, or elements having similar functions may be given the same or similar reference numerals, and these reference numerals may be distinguished by the presence or absence of an apostrophe. Note that the illustrated elements and their relative sizes do not necessarily faithfully reproduce the actual scale, and the size of individual elements may be exaggerated to improve visibility and understanding.

[0042] Referring to Figures 1 to 11, and, for example, in relation to Figure 12, a method or embodiment of a layered composite 100 suitable for manufacturing optoelectronic semiconductor components 1, as described below, and possible modifications of that embodiment will be described. The dashed areas in the figures indicate, for example, further areas of the layered composite 100 that enable the manufacture of multiple optoelectronic semiconductor components 1.

[0043] This method includes a step of providing a semiconductor layer sequence 2' for manufacturing at least one semiconductor layer stack 2 (see Figure 12), the semiconductor layer sequence 2' being provided on a substrate 3 (see Figure 1). The semiconductor layer sequence 2' can be formed from a semiconductor material based on a phosphorus compound semiconductor. Furthermore, the substrate 3 can be formed from a semiconductor material based on an arsenide compound semiconductor. For example, GaAs can be used for the substrate 3. In particular, the substrate 3 is a growth substrate on which the semiconductor layer sequence 2' is epitaxially grown.

[0044] The semiconductor layer sequence 2' includes a first semiconductor region 4' of a first conductivity type, for example, p conductivity, a second semiconductor region 6' of a second conductivity type, for example, n conductivity, and an active region 5' positioned between these first and second semiconductor regions 4' and 6'. The first semiconductor region 4' is located on the opposite side of the active region 5' from the substrate 3, and the second semiconductor region 6' is located between the substrate 3 and the active region 5'.

[0045] The first and second semiconductor regions 4' and 6' may each have a sequence of individual layers. Each layer may be doped, or in some cases, undoped or lightly doped. For example, the first semiconductor region 4' may include a confinement layer near an active region 5' (not shown). Furthermore, the second semiconductor region 6' includes a first semiconductor layer 7' and a second semiconductor layer 8' located on the opposite side of the first semiconductor layer 7' from the active region 5'. The second semiconductor layer 8' may be designed to function as both a contact layer and a current diffusion layer. However, different functions can be realized in separate layers. In one exemplary embodiment, the second semiconductor layer 8' functions as a contact layer. For its function as a current diffusion layer, the third semiconductor layer 9' is located on the opposite side of the second semiconductor layer 8' from the first semiconductor layer 7'. Furthermore, the second semiconductor region 6' may include a radiation emission layer 10'. This radiation-emitting layer 10' is positioned on the substrate 3 side of the semiconductor layer sequence 2' and may have a radiation-emitting structure that improves radiation emission in the finished semiconductor component.

[0046] Furthermore, the active region 5' may include the sequences of individual layers. Each individual layer can form a quantum well structure, particularly a single quantum well (SQW) structure or a multiple quantum well (MQW) structure.

[0047] The first semiconductor layer 7' of the second semiconductor region 6' may be formed from a first phosphorus compound semiconductor material, the second semiconductor layer 8' may be formed from a second phosphorus compound semiconductor material, and the first compound semiconductor material has a higher aluminum content than the second compound semiconductor material. In particular, the first compound semiconductor material is Al n Ga m In 1-n-m P, where 0.3 ≦ n ≦ 0.6, 0 ≦ m ≦ 0.2, and 0.4 ≦ n + m ≦ 0.6. The first semiconductor layer 7' may have a function as a buffer layer. With an indium content between 40% and 60%, an appropriate lattice constant can be achieved. Furthermore, the second compound semiconductor material may be Al n Ga m In 1-n-m P. Here, 0 < n < 0.6, 0 < m < 0.6, and 0.4 ≦ n + m ≦ 0.6. The third semiconductor layer 9' may be formed from a phosphorus compound semiconductor material, particularly InGaAlP, similar to the first and second semiconductor layers 7', 8'. The compound semiconductor materials of the second and third semiconductor layers 8', 9' have different gallium contents and / or doping levels.

[0048] The second semiconductor layer 8' may be formed thinner than the first semiconductor layer 7'. For example, the second semiconductor layer 8' may have a thickness d2 in the range of 10 nm to 500 nm, particularly 20 nm to 100 nm, and the normal manufacturing tolerance may be ±10%. Such a relatively low thickness d2 can reduce the absorption loss in the second semiconductor layer 8' or the contact layer. The thickness can indicate, for example, the vertical extension along the vertical direction V parallel to the growth direction in which the semiconductor regions 6', 5', 4' are stacked on top of each other.

[0049] <0000Furthermore, this method includes the step of forming a first contact structure 11' on the first main surface 2A' of the semiconductor layer sequence 2', the first main surface 2A' of the semiconductor layer sequence 2' demarcates the semiconductor layer sequence 2' on the side opposite to the substrate (see Figure 1). The step of forming the first contact structure 11' may also include generating a first diffusion layer 12' on the first main surface 2A'. The first diffusion layer 12' can be provided in direct contact with the first semiconductor region 4'. The first diffusion layer 12' can be formed as a single layer or a multilayer. Suitable first diffusion layers 12' include, for example, TCO (transparent conductive oxide) such as ITO, ZnO, InZnO, and AlO.

[0050] Furthermore, the step of forming the first contact structure 11' may include the step of generating a second diffusion layer 14' which is located on the opposite side of the semiconductor layer sequence 2' of the first diffusion layer 12' and is electrically conductively connected to the first diffusion layer 12'. The second diffusion layer 14' can cover a larger area of ​​the first main surface 2A' than the first diffusion layer 12'. For example, the second diffusion layer 14'' is a metal layer that can be formed as a single layer or a multilayer.

[0051] Furthermore, the step of forming the first contact structure 11' may include the step of generating a mirror layer 13', for example, made of Ag, between the first and second diffusion layers 12', 14'. When the finished semiconductor component 1 (see Figure 12) is in operation, the radiation emitted from the active regions 5', 5 can mostly pass through the first diffusion layers 12', 12. In addition, the mirror layers 13', 13 can deflect the radiation in the direction of the second main surfaces 2B', 2B, opposite to the first main surfaces 2A', 2A, and can also shield the radiation to prevent absorption by the second diffusion layers 14', 14.

[0052] To achieve a favorable reflectivity on the back side of the semiconductor component as a finished product, a reflective element 15' may be placed on the first main surface 2A' (see Figure 1). The reflective element 15' may have alternating high refractive index layers and low refractive index layers. The layers may be dielectric layers, and preferred materials include SiO, SiN, NbO, or HfO. For example, the reflective element 15' includes a Bragg mirror. The reflective element 15' may cover the first main surface 2A' and partially cover the first diffusion layer 12'. The reflective element 15' may also have an opening 16, within which a second diffusion layer 14' and, optionally, a mirror layer 13' extend to the first diffusion layer 12'.

[0053] Furthermore, an opening 17 can be formed in the second diffusion layer 14', and possibly the mirror layer 13', at a position laterally separated from the opening 16.

[0054] On the side of the second diffusion layer 14' opposite to the semiconductor layer sequence 2', an insulating layer 18' can be provided that covers at least a large portion of the first main surface 2A' and extends into the opening 17. The insulating layer 18' is configured to electrically insulate the first contact structure 11' and the second contact structure 21' (see Figure 10) on the first main surface 2A'.

[0055] As shown in Figures 2 and 6, the method further comprises the step of generating at least one recess 19 that extends from the first main surface 2A' to the second semiconductor layer 8' through the first semiconductor region 4' and the active region 5'. The recess 19 may already extend from the insulating layer 18' through the opening 17.

[0056] The recess 19 is generated by a two-step etching process. In the first etching step, the semiconductor layer sequence 2' is etched toward the first semiconductor layer 7'. The first etching step includes, for example, a dry etching process. The first region 19A of the recess 19 generated by this process is laterally separated by one or more surfaces 2C' of the semiconductor layer sequence 2' and may extend in cross-section at an angle of 90° < α < 180°, particularly 95° < α < 115°, with respect to the surface 2D' of the semiconductor layer sequence 2' that separates the first region 19A at the bottom (see Figure 2). The first region 19A may have a frustoconical or truncated pyramidal shape.

[0057] Furthermore, as indicated by the arrows in Figure 3, the method may include a step of hybridizing the quantum well structure of the active region 5' in the recess 19 or the region adjacent to the first region 19A of the recess 19. In this step, the quantum well and the barrier layer are hybridized, for example by heat treatment or, if necessary, the introduction of impurities, thereby increasing the band gap, resulting in a decrease in charge carriers and suppressing surface recombination. This step is performed particularly when surface recombination would be a concern in the recess 19. Hybridization can be performed especially in the initial stages, for example, before the recess 19 is formed. This allows for processing at higher temperatures.

[0058] Furthermore, the method may include a step of generating an insulating layer 20', which is performed before the second etching step, as in one example embodiment. However, this step may also be performed after the second etching step.

[0059] As shown in Figure 4, the insulating layer 20' is provided, for example, as a closed layer on the semiconductor layer sequence 2', completely covering the surfaces 2C' and 2D' that demarcate the first region 19A of the recess 19. Then, by partially removing the insulating layer 20', the surface 2D' of the semiconductor layer sequence 2' located at the bottom of the first region 19A of the recess 19 is exposed (see Figure 5).

[0060] The insulating layer 20' can be formed from an electrical insulating material such as silicon oxide or silicon nitride, or a combination thereof.

[0061] After structuring the insulating layer 20', a second etching step is performed as shown in Figure 6, and the semiconductor layer sequence 2' is etched up to the second semiconductor layer 8'. For example, the second etching step includes a wet chemical etching process. The second etching step or wet chemical etching process uses an etchant with sufficient selectivity, such that the etching rate at the first semiconductor layer 7', which has a high aluminum content, is higher than the etching rate at the second semiconductor layer 8', which has a low aluminum content. For example, the etching rate at the second semiconductor layer 8' can be more than an order of magnitude lower than the etching rate at the first semiconductor layer 7'. This allows the etching process to be precisely terminated at the second semiconductor layer 8', and the desired etching depth can be specifically set. As the etchant, for example, an aqueous solution of dilute hydrochloric acid or dilute sulfuric acid can be used.

[0062] In low-precision single-step etching processes, the etching tolerance is large, requiring the contacted semiconductor layer to be formed relatively thickly. In contrast, this method allows for the formation of a relatively thin second semiconductor layer 8'. Specifically, the thickness d2 of the second semiconductor layer 8' can be in the range of 10 nm to 500 nm, particularly 20 nm to 100 nm, with a typical manufacturing tolerance of ±10%. On the other hand, the first semiconductor layer 7', formed after the first etching process, can be thicker than the second semiconductor layer 8'. For example, the thickness d1 of the first semiconductor layer 7' can be between 0.4 μm and 0.6 μm, with a tolerance of ±10%. The thickness d1 of the first semiconductor layer 7' is determined, for example, by considering variations in thickness and etching rate that occur during the first etching process.

[0063] In the second etching step, a widened region 19B of the recess 19 is formed. The widened region 19B is created by under-etching in the first semiconductor layer 7'. The insulating layer 20' is also under-etched in the second etching step, and a distance is created between it and the semiconductor layer sequence 2'.

[0064] For example, the widened region 19B may have a depth or longitudinal extension h that is at least about 25% of the thickness d1 of the first semiconductor layer 7', and at most corresponds to the thickness d1. The vertical extension h may represent an extension along the vertical direction V.

[0065] Furthermore, the widened region 19B may have a lateral extension b at the bottom of the recess 19 that is approximately 10% with a tolerance of ±10% from the lateral extension that would occur if the original shape of the recess 19 were continued, or if the shape of the first region 19A of the recess 19 were continued while maintaining the angle α (see Figure 2). For example, the lateral extension b of the widened region may be a value between 5.5 μm and 7.5 μm, with a tolerance of ±10%. The lateral extension b can extend along the lateral direction L. The lateral direction L may be, for example, a direction lateral to direction V, or a direction perpendicular to direction V.

[0066] This method further comprises the step of forming a second contact structure 21' located in a portion of the first main surface 2A' and in the recess 19 (see Figures 7-9).

[0067] The step of forming the second contact structure 21' may include the step of generating a connecting layer 22' so as to cover one or more surfaces 2C', 2D' of the semiconductor layer sequence 2' that demarcates the recess 19 (see Figure 7). For example, the connecting layer 22' can cover only the surface 2D' located at the bottom of the recess 19, or it can additionally cover surface 2C' as well. In particular, the connecting layer 22' is provided so that the second semiconductor layer 8' can make electrical contact. The connecting layer 22' can be manufactured from a laminate of one or more material compounds and / or metallic materials. For example, a material or material compound containing Au or Pd and doped with Ge is suitable as the connecting layer 22'. Surface oxides can be removed before providing the connecting layer 22'. After providing the connecting layer 22', a so-called annealing treatment can be performed.

[0068] As can be seen from Figure 7, a cavity 23 is provided in the widened region 19B of the recess 19 between the semiconductor layer sequence 2' and the insulating layer 20' or connecting layer 22'. The cavity 23 is, for example, filled with gas or substantially empty and under vacuum. This cavity can be formed by the insulating layer 20' or connecting layer 22' in the widened region 19B according to the original shape of the recess 19 or the shape of the first region 19A of the recess 19.

[0069] As shown in Figure 8, the step of forming the second contact structure 21' may further include the step of forming a solder barrier layer 24' and a first solder layer 25' such that the solder barrier layer 24' is placed between the semiconductor layer sequence 2 and the first solder layer 25'. The solder barrier layer 24' is configured, for example, to prevent the solder material from diffusing into layers 2', 13', 18', and 20'. The solder barrier layer 24' and the first solder layer 25' can cover the first main surface 2A' and fill the recess 19. Suitable materials for the solder barrier layer 24' include, for example, WTi, Ti, or Ta. Suitable materials for the first solder layer 25' include, for example, AuPt, Au, or Ni.

[0070] Furthermore, the step of forming the second contact structure 21' includes forming a second solder layer (not shown) on the first solder layer 25', and when the second solder layer (not shown) is bonded to the carrier 27', it is bonded to the first solder layer 25' to form a bonding layer 26' (see Figure 9). Suitable materials for the second solder layer include, for example, Sn and InSn. In this case, the bonding layer 26'' includes, for example, AuSn, AuInSn, NiSn, or NiInSn. The carrier 27' can be formed from a semiconductor material such as Ge or Si, or a ceramic material such as SiN. The carrier 27' is provided on the side of the semiconductor layer sequence 2' opposite to the substrate 3.

[0071] The method may further include a step of removing the substrate 3 (see Figure 10). This process can expose the second main surface 2B' of the semiconductor layer sequence 2'. For example, the substrate 3 may be removed by wet chemical etching. Furthermore, the method may include a step of forming a radiation-emitting structure 28' on the radiation-emitting layer 10'. For example, the radiation-emitting structure 28' can be generated by roughening the surface of the radiation-emitting layer 10' opposite to the carrier 27', or by roughening the second semiconductor region 6' on the second main surface 2B'. Roughening can be performed, for example, by lithography and dry etching processes.

[0072] This method may further include a step of structuring the semiconductor layer sequence 2' (see Figure 10). For example, structuring can be performed by dry etching. During structuring, by removing the edge regions of the semiconductor layer sequence 2', for example, the second diffusion layer 14' can protrude beyond the semiconductor layer sequence 2' in at least a portion of the semiconductor layer sequence 2', and in the protruding region, it can contact a contact pad 29 formed from, for example, Au (see Figure 11). The semiconductor layer sequence 2' may be structured to have a mesa-like shape such that the carriers 27' protrude beyond all sides of the semiconductor layer sequence 2' when viewed from above.

[0073] An example embodiment of the optoelectronic semiconductor component 1 will be described with reference to Figure 12. This optoelectronic semiconductor component 1 can be manufactured by the method described in relation to Figures 1 to 11, and after the process shown in Figure 11, it is separated from the layer structure 100 between the dashed lines to form individual components. Therefore, the features and relationships described in relation to this method are similarly applicable to the optoelectronic semiconductor component 11, and vice versa.

[0074] The optoelectronic semiconductor component 1 comprises a carrier 27 and a semiconductor layer stack 2 disposed thereon. The carrier 27 of the optoelectronic semiconductor component 1 is separated from the carrier 27' (see Figure 11) by a fragmentation process, and the semiconductor layer stack 2 corresponds to a structured semiconductor layer sequence 2' (see Figure 11).

[0075] Corresponding to semiconductor layer sequence 2', the semiconductor layer stack 2 comprises a first semiconductor region 4, a second semiconductor region 6, and an active region 5 positioned between the first and second semiconductor regions 4 and 6, configured to generate or emit electromagnetic radiation, for example, in the visible to infrared spectral range. This allows the optoelectronic semiconductor component 1 to emit electromagnetic radiation during operation, for example, in the visible to infrared spectral range. In this case, the majority of the radiation can be emitted from the second main surface 2B of the semiconductor layer stack 2 positioned in front of the semiconductor component 1.

[0076] Since the second main surface 2B has no contact structure, as a result, no radiation loss due to light shielding occurs on the second main surface 2B. The optoelectronic semiconductor component 1 includes a first contact structure 11 that electrically contacts the first semiconductor region 4, and the first contact structure 11 is located in a portion of the first main surface 2A of the semiconductor layer stack 2. As described in relation to Figure 1, the first contact structure 11 may include a first diffusion layer 12 located on the first main surface 2A and a second diffusion layer 14 located between the first diffusion layer 12 and the carrier 27. The mirror layer 13 may be located between the first and second diffusion layers 12 and 14, and if it has good conductivity, it may form part of the first contact structure 11.

[0077] Furthermore, the optoelectronic semiconductor component 1 includes a second contact structure 21 for electrically contacting the second semiconductor region 6, the second contact structure 21 being located in a portion of the first main surface 2A and in a recess 19 of the semiconductor layer stack 2. As described in detail with reference to Figures 7-10, the second contact structure 21 may include a connecting layer 22 located in the recess 19, a bonding layer 26 adjacent to the carrier 27, and a solder barrier layer 24 located on the bonding layer 26 side of the semiconductor layer stack 2.

[0078] The first main surface 2A may be formed, for example, by the surface of the first semiconductor region 4 and is located on the opposite side of the second main surface 2B. The second main surface 2B may be formed, for example, by the surface of the second semiconductor region 6 and is located on the side of the semiconductor layer stack 2 facing the carriers 27. The first semiconductor region 4 may be, for example, a p-conducting region and is located on the side of the active region 5 facing the carriers 27. The second semiconductor region 6 may be, for example, an n-conducting region and is located on the opposite side of the active region 5 from the carriers 27.

[0079] As explained in relation to Figure 1, the second semiconductor region 6 comprises a first semiconductor layer 7 made of a first compound semiconductor material with a high aluminum content, and a second semiconductor layer 8 made of a second compound semiconductor material with a lower aluminum content, which is different from the first compound semiconductor material. For example, the first and second compound semiconductor materials are phosphorus compound semiconductor materials, respectively. Because the first and second semiconductor layers 7 and 8 have different aluminum content, the two-stage etching process for manufacturing the recess 19 can be precisely controlled to stop at the second semiconductor layer 8, and as a result, the second semiconductor region 6 is electrically contacted. The precise two-stage etching process allows for relatively low thicknesses d1 and d2 (see explanations related to Figures 1 and 6), and due to factors such as low absorption rate, a highly efficient semiconductor component 1 can be realized. The first semiconductor layer 7 is positioned between the active region 5 and the second semiconductor layer 8.

[0080] A recess 19 in which the second contact structure 21 is located in a portion of the region extends from the first main surface 2A of the semiconductor layer stack 2 to the second semiconductor layer 8, passing through the first semiconductor region 4 and the active region 5. For example, the contact region 21A of the second contact structure 21 located in the recess 19 or the recess 19 may have a three-dimensional shape with a variable cross-section, such as a frustoconical or frustopyroconical shape. The cross-section may decrease as the depth increases, and this depth may be set parallel to the vertical direction V in which the semiconductor regions 4, 5, and 6 are stacked in order from the carrier 27. For example, the shape and size of the contact region 21A is determined by the shape and size of the recess 19. The shape and size of the contact region 21 may be at least, generally the same as the shape and size of the recess 19. If the contact and / or surface resistance of the semiconductor component 1 is too high, it may have multiple recesses 19 or multiple contact regions 21A, and the multiple recesses 19 or contact regions 21A may have different sizes and / or spacings from one another.

[0081] The recess 19 includes a widened region 19B between the active region 5 and the second semiconductor layer 8. The widened region 19B can be interpreted as representing a two-step etching process. The longitudinal extension h and transverse extension b of the widened region 19B will be explained with reference to Figure 6.

[0082] In the widened region 19B, a cavity 23 is provided between the semiconductor layer stack 2 and the second contact structure 21, and the cavity 23 is either filled with air or substantially empty to create a vacuum. For example, the connecting layer 22 and other layers provided in the semiconductor layer stack 2 (e.g., the insulating layer 20) may extend in the widened region 19B along the original shape of the recess 19 that would be assumed if the widened region were not provided (see also the explanation with respect to Figure 2).

[0083] According to the first and second contact structures 11 and 21, the optoelectronic semiconductor component 1 can be electrically connected from the outside only from one side of the semiconductor component 1. For example, the first contact pad 29 of the first contact structure 11, which functions as the first electrode of the semiconductor component 1, and the second contact pad (not shown) of the second contact structure 21, which functions as the second electrode of the semiconductor component 1, may be arranged on the side of the semiconductor layer laminate 2 in the protruding region of the carrier 27 to connect to contact means such as a bonding wire.

[0084] The first contact pad 29 is located in a region of the reflective element 15 that is not covered by the semiconductor layer stack 2, which is positioned in a portion of the first main surface 2A, and extends through the opening of the reflective element 15 to the second diffusion layer 14 of the first contact structure 11. As described in detail with reference to Figure 1, the second diffusion layer 14, like the mirror layer 13, extends through the opening 16 of the reflective element 15 to the first diffusion layer 12.

[0085] The first contact structure 11 may be electrically insulated from the second contact structure 21 by an insulating layer 20 (see the explanation in Figures 4-6 for details) and an insulating layer 18 (see the explanation in Figure 1 for details).

[0086] The first and second contact structures 11 and 21 enable a uniform current distribution in the semiconductor layer stack 2, allowing for the realization of larger semiconductor components.

[0087] The scope of the carrier is not limited by the description based on the embodiments as an example. Rather, the present invention includes any novel features and any combination of features, and in particular any combination of features in the claims, even if such features or combinations themselves are not expressly described in the claims or embodiments.

[0088] This patent application claims priority to German patent application 102022119108.7, the disclosures of which are incorporated herein by reference. [Explanation of symbols]

[0089] 1 Optoelectronic semiconductor components 2 Semiconductor layer stack 2A 1st main surface 2B 2nd main surface 2C, 2D surface 2' Semiconductor layer sequence 2A' 1st main surface 2B' 2nd principal surface 2C', 2D' surface 2E, 2E' side 3 circuit boards 4, 4' First Semiconductor Region 5, 5' active region 6, 6' Second semiconductor region 7, 7' First semiconductor layer 8, 8' Second semiconductor layer 9. Third Semiconductor Layer 10, 10' Radiation emission layer 11, 11' First contact structure 12, 12' First diffusion layer 13, 13' mirror layer 14, 14' Second diffusion layer 15, 15' Reflector 16, 17 aperture 18, 18' insulating layer 19 Recess 19A 1st area 19B Second widening area 20, 20' insulating layer 21, 21' Second contact structure 21A Contact area 22, 22' Connecting layer 23 Cavity 24, 24' solder barrier layer 25' First solder layer 26, 26' bonding layer 27, 27' Career 28, 28' radiation emitting structure 29. First contact pad 100 layer composite α angle b. Lateral extension d1, d2 thickness h depth, vertical extension V vertical direction L (horizontal direction)

Claims

1. Optoelectronic semiconductor component (1), Semiconductor layer stack (2), At least one recess (19) and First contact structure (11), The second contact structure (21) is provided, The semiconductor layer stack (2) is First semiconductor region (4), Second semiconductor area (6), The device comprises an active region (5) positioned between the first and second semiconductor regions (4, 6), The second semiconductor region (6) comprises a first semiconductor layer (7) and a second semiconductor layer (8), The second semiconductor layer (8) is located on the opposite side of the first semiconductor layer (7) from the active region (5). The at least one recess (19) extends from the first main surface (2A) of the semiconductor layer laminate (2) to the second semiconductor layer (8) through the first semiconductor region (4) and the active region (5), The first contact structure (11) is a structure for electrically contacting the first semiconductor region (4), and is arranged in at least a portion of the first main surface (2A), The second contact structure (21) is a structure for electrically contacting the second semiconductor region (6), and is arranged in a portion of the first main surface (2A) and in at least one of the recesses (19). The first semiconductor layer (7) is made of a first compound semiconductor material, The second semiconductor layer (8) is made of a second compound semiconductor material, The first compound semiconductor material has a higher aluminum content than the second compound semiconductor material. The second main surface (2B) of the semiconductor layer stack (2), opposite to the first main surface (2A), does not have the first and second contact structures (11, 21). The second main surface (2B) is located on the front side of the optoelectronic semiconductor component (1) that is provided for radiation emission. Optoelectronic semiconductor component (1).

2. The first compound semiconductor material and the second compound semiconductor material are each phosphorus compound semiconductor materials. The optoelectronic semiconductor component (1) according to claim 1.

3. The first compound semiconductor material is Al ｎ Ga ｍ In １－ｎ－ｍ The function includes P, and satisfies 0.3 ≤ n ≤ 0.6, 0 ≤ m ≤ 0.2, and 0.4 ≤ n + m ≤ 0.

6. The optoelectronic semiconductor component (1) according to claim 1 or 2.

4. The second compound semiconductor material is Al ｎ Ga ｍ In １－ｎ－ｍ The function includes P, where 0 < n < 0.6, 0 < m < 0.6, and 0.4 ≤ n + m ≤ 0.

6. The optoelectronic semiconductor component (1) according to claim 1 or 2.

5. The second semiconductor layer (8) is formed to be thinner than the first semiconductor layer (7). The optoelectronic semiconductor component (1) according to claim 1 or 2.

6. The second semiconductor region (6) is located on the opposite side of the second semiconductor layer (8) from the first semiconductor layer (7) and comprises a third semiconductor layer (9) containing InGaAlP. The compound semiconductor materials of the second and third semiconductor layers (8, 9) differ in their gallium content and / or doping level. The optoelectronic semiconductor component (1) according to claim 1 or 2.

7. The recess (19) has a widened region (19B) between the active region (5) and the second semiconductor layer (8). The optoelectronic semiconductor component (1) according to claim 1 or 2.

8. The second contact structure (21) comprises a connecting layer (22), The connecting layer (22) covers one or more surfaces (2C, 2D) of the semiconductor layer stack (2) that separate the at least one recess (19). The optoelectronic semiconductor component (1) according to claim 1 or 2.

9. The recess (19) has a widened region (19B) between the active region (5) and the second semiconductor layer (8), and a cavity (23) is provided in the widened region (19B) between the semiconductor layer laminate (2) and the second contact structure (21). The optoelectronic semiconductor component (1) according to claim 1 or 2.

10. It is equipped with an insulating layer (20), The insulating layer (20) is disposed between the semiconductor layer laminate (2) and the connecting layer (22), and the connecting layer (22) covers one or more surfaces (2C, 2D) of the semiconductor layer laminate (2) that separate the at least one recess (19). The optoelectronic semiconductor component (1) according to claim 1 or 2.

11. A method for manufacturing at least one optoelectronic semiconductor component (1), wherein the method is: A step of providing a semiconductor layer sequence (2') on a substrate (3) for manufacturing at least one semiconductor layer stack (2), The semiconductor layer sequence (2') comprises a first semiconductor region (4'), a second semiconductor region (6'), an active region (5') disposed between the first and second semiconductor regions (4', 6'), and a first main surface (2A'). The second semiconductor region (6') comprises a first semiconductor layer (7') and a second semiconductor layer (8'), The second semiconductor layer (8') is positioned on the side opposite to the active region (5') of the first semiconductor layer (7'), and the process is as follows: The steps include forming a first contact structure (11') on the first main surface (2A'), A step of generating at least one recess (19) that extends from the first main surface (2A') to the second semiconductor layer (8') through the first semiconductor region (4') and the active region (5'), The process includes the step of forming a second contact structure (21') disposed in a portion of the first main surface (2A') and in the at least one recess (19), The at least one recess (19) is generated by a two-step etching process, wherein the semiconductor layer sequence (2') is etched up to the first semiconductor layer (7') in the first etching step, and etched up to the second semiconductor layer (8') in the second etching step. The first semiconductor layer (7') is formed of a first compound semiconductor material, The second semiconductor layer (8') is formed of a second compound semiconductor material, The first compound semiconductor material has a higher aluminum content than the second compound semiconductor material. The method further includes the step of removing the substrate (3). method.

12. The first etching step includes a dry etching process. The method according to claim 11.

13. The second etching step includes a wet chemical etching process. The method according to claim 11 or 12.

14. The second etching step includes a wet chemical etching process, wherein in the wet chemical etching process, an etching agent is used that has a higher etching rate for the first semiconductor layer (7') with a higher aluminum content than for the second semiconductor layer (8') with a lower aluminum content. The method according to claim 11 or 12.

15. The widened region (19B) of the at least one recess (19) is generated by the second etching step. The method according to claim 11 or 12.

16. The active region (5') has a quantum well structure, The hybridization of the quantum well structure is carried out in a portion of the active region (5') adjacent to the at least one recess (19). The method according to claim 11 or 12.

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