Method and system for measuring etching amount

Abstract

The present invention addresses the problem of providing a novel technology for measuring an etching amount in heat treatment in which growth and etching proceed simultaneously. The present invention includes: a first substrate thickness measuring step S10 for measuring the thickness 10D of a to-be-heat-treated semiconductor substrate 10; a second substrate thickness measuring step S20 for measuring the thickness 20D of a heat-treated semiconductor substrate 20; a growth layer thickness measuring step S30 for measuring the thickness 21D of a growth layer 21 which has gone through crystal growth by heat treatment; and an etching amount calculating step S40 for calculating the etching amount ED on the basis of the thickness 10D of the to-be-heat-treated semiconductor substrate 10, the thickness 20D of the heat-treated semiconductor substrate 20, and the thickness 21D of the growth layer 21.

Description

Technical Field

[0001] The present invention relates to a method for measuring an etching amount of a semiconductor substrate and a measurement system therefor.

Background Art

[0002] Conventionally, a process for manufacturing a semiconductor device has a polishing process of polishing the surface of a semiconductor substrate (so-called wafer) to obtain a surface suitable for device manufacturing. In this polishing process, when polishing treatments on both sides (for example, the upper and lower surfaces) of the wafer are required, an industrially beneficial double-sided simultaneous polishing method can be adopted.

[0003] Normally, when polishing a semiconductor substrate, it is necessary to accurately measure the thickness of the substrate for quality control. However, in the double-sided simultaneous polishing method of polishing both sides of a wafer simultaneously, there is a problem that it is difficult to measure the polishing amount for each polished surface.

[0004] For such problems, various methods for accurately measuring the polishing amounts of both sides of a wafer have been proposed. For example, Patent Document 1 discloses a technique of "a method for measuring a polishing amount when simultaneously polishing both sides of a flat substrate, characterized by calculating the polishing amount for each surface from the change amount before and after chamfering applied to the end face of the substrate in advance".

[0005] Also, as a technique alternative to polishing, a technique of etching a wafer by heat treatment has been proposed. For example, Patent Document 2 discloses a technique of "a method for manufacturing a SiC substrate, which simultaneously performs a growth process of forming a growth layer on one side of a SiC base substrate and an etching process of etching the other side of the SiC base substrate".

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

[0007] Incidentally, in the measurement method described in Patent Document 1, the amount of polishing is calculated from the chamfer shape applied to the edge face of the semiconductor substrate. Therefore, there was a problem in that the accuracy of the measurement decreased as the distance from the edge face of the substrate increased. In other words, at positions far from the edge face, which is the reference point for the amount of change before and after polishing (for example, near the center of the substrate), the uniformity of the amount of polishing at each polishing position and the influence of the warping of the substrate were reflected. Therefore, it was difficult to guarantee the accuracy of the measurement of the amount of polishing.

[0008] Furthermore, Patent Document 2 discloses a technique for growing one side of a semiconductor substrate and etching the other side by heat treatment of the semiconductor substrate. In order to mass-produce semiconductor substrates using such a thermal etching method, it is necessary to confirm that the amount of etching is precisely controlled from a quality assurance perspective. However, there has been a problem in that a method for measuring the amount of etching when semiconductor substrate growth and etching proceed simultaneously has not been established.

[0009] In view of the above-mentioned problems, the problem that the present invention aims to solve is to provide a novel technique for measuring the amount of etching in a heat treatment in which the growth and etching of a semiconductor substrate proceed simultaneously. Furthermore, the problem that the present invention aims to solve is to provide a novel technology for non-destructively and accurately measuring the amount of etching on a semiconductor substrate over a wide area across the entire surface of the semiconductor substrate. [Means for solving the problem]

[0010] The present invention, which solves the above-mentioned problems, is a method for measuring the amount of etching, comprising: a first substrate thickness measurement step for measuring the thickness of a semiconductor substrate before heat treatment; a second substrate thickness measurement step for measuring the thickness of a semiconductor substrate after heat treatment; a growth layer thickness measurement step for measuring the thickness of a growth layer that has undergone crystal growth by heat treatment; and an etching amount calculation step for calculating the amount of etching based on the thickness of the semiconductor substrate before heat treatment, the thickness of the semiconductor substrate after heat treatment, and the thickness of the growth layer.

[0011] In a preferred embodiment of the present invention, the etching amount calculation step is a step of adding the thickness of the growth layer to the thickness of the semiconductor substrate before heat treatment, and further subtracting the thickness of the semiconductor substrate after heat treatment.

[0012] In a preferred embodiment of the present invention, the invention further includes a heat treatment step of forming a growth layer on one side of the semiconductor substrate by heat treatment and etching the other side.

[0013] In a preferred embodiment of the present invention, the etching amount calculation step is a step of setting up a plurality of arbitrary areas by dividing the semiconductor substrate into arbitrary areas, and calculating the etching amount for each of the arbitrary areas.

[0014] In a preferred embodiment of the present invention, the growth layer thickness measurement step is a step of measuring the thickness of the growth layer using Fourier transform infrared spectroscopy.

[0015] In a preferred embodiment of the present invention, the growth layer thickness measurement step is a step of measuring the thickness of the growth layer using Raman spectroscopy.

[0016] In a preferred embodiment of the present invention, the semiconductor substrate is silicon carbide.

[0017] Furthermore, the present invention relates to an etching amount measurement system that causes a computer processor to execute the above-described measurement method. [Effects of the Invention]

[0018] According to the disclosed technology, it is possible to provide a novel technology for measuring an etching amount in a heat treatment in which the growth and etching of a semiconductor substrate proceed simultaneously. Also, according to the disclosed technology, it is possible to provide a novel technology for non-destructively and accurately measuring the etching amount of a semiconductor substrate over a wide range of the entire surface of the semiconductor substrate.

[0019] Other problems, features, and advantages will become apparent when the invention described below is read in conjunction with the drawings and the claims.

Brief Description of the Drawings

[0020] [Figure 1] It is an explanatory diagram showing a method for measuring an etching amount according to an embodiment. [Figure 2] It is an explanatory diagram explaining a heat treatment apparatus used in a heat treatment step according to an embodiment. [Figure 3] It is an explanatory diagram explaining a heat treatment step according to an embodiment. [Figure 4] It is an explanatory diagram showing an example of an arbitrary area of a method for measuring an etching amount according to an embodiment.

Embodiments of the Invention

[0021] Hereinafter, with reference to the accompanying drawings, preferred embodiments of a method and a system for measuring an etching amount according to this invention will be described in detail. The technical scope of the present invention is not limited to the embodiments shown in the accompanying drawings, and can be appropriately changed within the scope described in the claims. In the following description of the embodiments and the accompanying drawings, the same components are denoted by the same reference numerals, and redundant descriptions are omitted.

[0022] The etching amount measurement method according to the present invention includes a first substrate thickness measurement step S10 for measuring the thickness 10D of a semiconductor substrate 10 before heat treatment, a second substrate thickness measurement step S20 for measuring the thickness 20D of a semiconductor substrate 20 after heat treatment, a growth layer thickness measurement step S30 for measuring the thickness 21D of a growth layer 21 crystal grown by heat treatment, and an etching amount calculation step S40 for calculating the etching amount ED based on the thickness 10D of the semiconductor substrate 10 before heat treatment, the thickness 20D of the semiconductor substrate 20 after heat treatment, and the thickness 21D of the growth layer 21.

[0023] The etching amount measurement method according to this embodiment may further include a heat treatment step SA in which a growth layer 21 is formed on one side of the semiconductor substrate 10 by heat treatment, and the other side is etched. In this heat treatment step SA, the crystal growth and etching proceed simultaneously.

[0024] Examples of semiconductor substrates 10 include substrates made of compound semiconductor materials such as SiC (silicon carbide), GaN (gallium nitride), and AlN (aluminum nitride). While there are no restrictions on the diameter of the semiconductor substrate 10 to be measured, a key feature is the ability to measure large-diameter substrates. Therefore, the semiconductor substrate 10 is preferably 4 inches or larger, more preferably 6 inches or larger, and even more preferably 8 inches or larger.

[0025] Figure 1 is an explanatory diagram showing a method for measuring the amount of etching according to an embodiment. On the surface 101 side of the semiconductor substrate 10, crystal growth progresses during the heat treatment process SA as growth atoms are supplied, forming a growth layer 21 on top of the bulk layer 11. Therefore, the thickness 21D of the growth layer 21 extends from the surface 101 of the semiconductor substrate 10 before heat treatment to the surface 201 of the growth layer 21.

[0026] Furthermore, on the back surface 102 of the semiconductor substrate 10, etching of the bulk layer 11 progresses during the heat treatment process SA as atoms constituting the semiconductor substrate detach from the surface. Therefore, the etching amount ED extends from the back surface 102 of the semiconductor substrate 10 before heat treatment to the back surface 202 of the semiconductor substrate 20 after heat treatment. The following describes each step in detail according to embodiments of the present invention.

[0027] <First substrate thickness measurement process S10> The first substrate thickness measurement step S10 is a step in which the thickness 10D of the semiconductor substrate 10 is measured prior to the heat treatment step SA. It is desirable that this first substrate thickness measurement step S10 acquires measurement position information of the semiconductor substrate 10 and thickness 10D information corresponding to this measurement position information.

[0028] The first substrate thickness measurement step S10 can be performed using any method that can acquire the thickness information 10D of the semiconductor substrate 10 and the measurement position information. Specifically, examples include a micrometer (contact type displacement meter), a capacitive thickness measuring instrument, and light transmission or spectral interference type thickness measurement using a laser.

[0029] <Heat treatment process SA> The heat treatment step SA is a process in which a growth layer 21 is formed on one side of the semiconductor substrate 10 by heat treatment, and at the same time, the other side is etched. An example of a method for this heat treatment step SA is the manufacturing method of the SiC substrate described in Patent Document 2 (International Publication No. 2020 / 179795). An example of the heat treatment process SA according to the embodiment will be described in detail below with reference to Figures 2 and 3.

[0030] Figures 2 and 3 are explanatory diagrams illustrating the heat treatment process SA according to the embodiment. Figure 2 shows an example of a heat treatment apparatus used in the heat treatment process SA. Figure 3 shows the formation of a growth layer 21 on one side of the semiconductor substrate 10 to be heat treated, while the other side is etched at the same time.

[0031] As shown in Figure 2, the heat treatment apparatus comprises a main container 30 capable of housing a semiconductor substrate 10, a high-melting-point container 40 capable of housing the main container 30, and a heating furnace 50 capable of forming a temperature gradient within the main container 30.

[0032] (Main container) The main container 30 is a fitted container comprising an upper container 31 and a lower container 32 that can be fitted together. A minute gap 33 is formed in the fitting portion between the upper container 31 and the lower container 32, and this gap 33 is configured to allow exhaust (vacuuming) from inside the main container 30. This main container 30 is made of the same material as, for example, the semiconductor substrate 10.

[0033] Furthermore, a substrate holder 34 is placed between the semiconductor substrate 10 and the lower container 32 to form a space below the semiconductor substrate 10. This substrate holder 34 forms a crystal growth space X where crystal growth of the growth layer 21 proceeds and an etching space Y where etching proceeds, at the top and bottom of the semiconductor substrate 10.

[0034] The crystal growth space X and the etching space Y are spaces in which crystal growth or etching proceeds, driven by the temperature gradient formed within the main container 30. Specifically, the crystal growth space X is a space in which raw materials are transported from the main container 30 to the semiconductor substrate 10 by the temperature gradient formed within the main container 30. The etching space Y is a space in which raw materials are transported from the semiconductor substrate 10 to the main container 30 by the temperature gradient formed within the main container 30.

[0035] (High melting point container) The high-melting-point container 40, like the main container 30, is a fitted container comprising an upper container 41 and a lower container 42 that can be fitted together, and is configured to accommodate the main container 30. A minute gap 43 is formed in the fitting portion between the upper container 41 and the lower container 42, and the container is configured to allow exhaust (vacuuming) of the inside of the high-melting-point container 40 through this gap 43.

[0036] The high-melting-point container 40 is composed of a high-melting-point material. Examples include C, a general-purpose heat-resistant material; W, Re, Os, Ta, Mo, carbides such as Ta9C8, HfC, TaC, NbC, ZrC, Ta2C, TiC, WC, MoC; nitrides such as HfN, TaN, BN, Ta2N, ZrN, TiN; borides such as HfB2, TaB2, ZrB2, NB2, TiB2; and polycrystalline SiC.

[0037] The high-melting-point container 40 preferably has a steam supply source 44 capable of supplying the vapor pressure of a gaseous species containing the elements of the semiconductor substrate 10 into the high-melting-point container 40. The steam supply source 44 only needs to be configured to generate steam into the high-melting-point container 40 when heated. For example, when heat-treating a SiC substrate, solid Si (Si pellets such as single-crystal Si pieces or Si powder) or Si compounds can be used.

[0038] (heating furnace) The heating furnace 50 includes a main heating chamber 51 capable of heating the workpiece to a temperature of 1000°C to 2300°C, a preheating chamber 52 capable of preheating the workpiece to a temperature of 500°C or higher, a moving means 53 (moving platform) for moving the workpiece from the preheating chamber 52 to the main heating chamber 51, and a heating heater 54. The main heating chamber 51 may also be connected to a vacuum forming valve 55 for exhausting the contents of the main heating chamber 51, an inert gas injection valve 56 for introducing inert gas into the main heating chamber 51, and a vacuum gauge 57 for measuring the vacuum level inside the main heating chamber 51.

[0039] The heating furnace 50 is configured to create a temperature gradient within the main container 30. For example, by releasing a small amount of heat from the contact area between the high-melting-point container 40 and the moving means 53 (moving platform), a temperature gradient can be created within the high-melting-point container 40 (and within the main container 30).

[0040] Alternatively, a configuration may be adopted in which a temperature gradient is formed by the heating element 54. For example, a configuration may be adopted in which many heating elements 54 are placed at the top of the heating chamber 51. Alternatively, a configuration may be adopted in which the width and output of the heaters increase towards the top of the heating chamber 51. Or, a configuration may be adopted in which the power supplied increases towards the top of the heating chamber 51.

[0041] <Second substrate thickness measurement process S20> The second substrate thickness measurement step S20 is a step in which the thickness 20D of the semiconductor substrate 20 after the heat treatment step SA is measured. In this second substrate thickness measurement step S20, it is desirable to acquire measurement position information of the semiconductor substrate 20 and thickness 20D information corresponding to this measurement position information, similar to the first substrate thickness measurement step S10. Furthermore, the second substrate thickness measurement step S20 can employ the same means as the first substrate thickness measurement step S10.

[0042] <Growth layer thickness measurement step S30> The growth layer thickness measurement step S30 is a step in which the thickness 21D of the growth layer 21 that has been crystallized by the heat treatment step SA is measured. It is desirable that this growth layer thickness measurement step S30 acquires measurement position information of the semiconductor substrate 20 and thickness 21D information of the growth layer 21 corresponding to this measurement position information.

[0043] The growth layer thickness measurement process S30 can employ any method that can non-destructively acquire the thickness 21D information of the growth layer 21. Specifically, Fourier transform infrared spectroscopy (FTIR) and Raman spectroscopy can be used as examples. Other methods for measuring the growth layer thickness include SIMS and cross-sectional SEM, but these are destructive tests and cannot be used because they render the semiconductor substrate unusable for subsequent device manufacturing. Furthermore, these methods are time-consuming and costly, making them unsuitable for mass production.

[0044] The growth layer thickness measurement step S30 employs Raman spectroscopy, which allows for the measurement of the growth layer thickness 21D and the nitrogen carrier concentration in the growth layer 21 simultaneously.

[0045] <Etching amount calculation process S40> The etching amount calculation step S40 is a step in which the etching amount ED is calculated based on the thickness 10D of the semiconductor substrate 10 before heat treatment, the thickness 20D of the semiconductor substrate 20 after heat treatment, and the thickness 21D of the growth layer 21.

[0046] Specifically, the etching amount calculation step S40 is a step in which the thickness 21D of the growth layer 21 is added to the thickness 10D of the semiconductor substrate 10 before heat treatment, and then the thickness 20D of the semiconductor substrate 20 after heat treatment is subtracted.

[0047] The thickness 10D of the semiconductor substrate 10 before heat treatment, the thickness 20D of the semiconductor substrate 20 after heat treatment, and the thickness 21D of the growth layer 21 are thickness information linked to measurement position information. By performing the above addition and subtraction processes for each measurement position on the semiconductor substrate 10 (20), the etching amount ED at each measurement position on the semiconductor substrate 10 can be calculated.

[0048] Alternatively, the etching amount calculation step S40 may be a step in which a plurality of arbitrary areas AA are set by dividing the semiconductor substrate 10 (20) into arbitrary areas, and the etching amount ED is calculated for each of these arbitrary areas AA.

[0049] Figure 4 is an explanatory diagram showing an example of an arbitrary area AA in the etching amount measurement method according to the embodiment. That is, statistical quantities for each thickness may be calculated for each set arbitrary area AA, and addition and subtraction operations may be performed based on these statistical quantities for the arbitrary area AA. The statistical quantities that can be used include the mean, median, mode, etc.

[0050] Furthermore, while Figure 4 shows a grid-like arrangement of arbitrary rectangular areas AA, it is possible to set any shape and area, such as setting fan-shaped areas AA on concentric circles.

[0051] According to the etching amount measurement method of the present invention, the etching amount ED can be accurately measured in a heat treatment in which crystal growth and etching of the semiconductor substrate 10 proceed simultaneously. This makes it possible to monitor whether the heat treatment environment of the semiconductor substrate is being controlled as intended.

[0052] Furthermore, the etching amount measurement method according to the present invention allows for accurate measurement of the etching amount of a semiconductor substrate over a wide range. For example, as in Patent Document 1 (Japanese Patent Application Publication No. 2005-297129), when a reference is set on the edge face of the substrate, there is a problem that the accuracy of the measurement decreases as the distance from the edge face increases.

[0053] In this respect, the etching amount measurement method according to the present invention calculates the etching amount ED based on thickness information linked to the measurement position information of the semiconductor substrate, so the etching amount ED can be calculated with the same accuracy regardless of the position on the semiconductor substrate. In other words, it is possible to provide etching amount ED measurement results that are not biased in the circumferential and radial directions within the wafer surface. This function becomes more important as the wafer diameter increases, from 4 inches to 6 inches, and from 6 inches to 8 inches. This is because, generally, as the diameter increases, it becomes more difficult to uniformly control etching and growth across the entire surface of the semiconductor substrate, so measurement values ​​for each position within the surface are extremely important for PDCA in process development and for quality assurance.

[0054] Furthermore, the measurement means for the first substrate thickness measurement step S10, the measurement means for the second substrate thickness measurement step S20, the measurement means for the growth layer thickness measurement step S30, and the calculation means for the etching amount calculation step S40 may be configured to communicate with each other via a local area network or the like.

[0055] Furthermore, the calculation means for the etching amount calculation step S40 may employ a hardware configuration such as a processor and storage, and configure an etching amount measurement system that causes the above etching amount measurement method to be executed by the computer's processor. [Explanation of symbols]

[0056] 10 Semiconductor substrate before heat treatment 11 Bulk layer 20 Semiconductor substrate after heat treatment 21 Growth layer 30 Main container 31 Upper container 32 Lower container 33 Gap 34. Circuit board holder 40 High melting point containers 41 Upper container 42 Lower container 43 Gap 44 Steam supply source 50 Furnace 51 main heating chamber 52 Preheating chamber 53 Means of Transportation 54 Heating heater 55 Vacuum forming valve 56 Valve for inert gas injection 57 Vacuum Gauge X crystal growth space Y Etching Space S10 First substrate thickness measurement process S20 Second substrate thickness measurement process S30 Growth layer measurement process S40 Etching amount measurement process SA Heat Treatment Process ED etching amount

Claims

1. A heat treatment process that forms a growth layer on one side of a semiconductor substrate and simultaneously etches the other side, A first substrate thickness measurement step for measuring the thickness of the semiconductor substrate before heat treatment, A second substrate thickness measurement step for measuring the thickness of the semiconductor substrate after the heat treatment, A growth layer thickness measurement step for measuring the thickness of the growth layer that has grown crystallically by the heat treatment, The process includes an etching amount calculation step, which calculates the amount of etching due to the heat treatment based on the thickness of the semiconductor substrate before heat treatment, the thickness of the semiconductor substrate after heat treatment, and the thickness of the growth layer. The etching amount calculation step is a step of adding the thickness of the growth layer to the thickness of the semiconductor substrate before heat treatment, and further subtracting the thickness of the semiconductor substrate after heat treatment, in a method for measuring etching amount.

2. The etching amount calculation step is a step of setting a plurality of arbitrary areas by dividing the semiconductor substrate into arbitrary areas, and calculating the etching amount for each of the arbitrary areas, as described in claim 1.

3. The method for measuring etching amount according to claim 1 or 2, wherein the growth layer thickness measurement step is a step of measuring the thickness of the growth layer using Fourier transform infrared spectroscopy.

4. The method for measuring etching amount according to claim 1 or 2, wherein the growth layer thickness measurement step is a step of measuring the thickness of the growth layer using Raman spectroscopy.

5. The method for measuring the amount of etching according to any one of claims 1 to 4, wherein the semiconductor substrate is silicon carbide.

6. An etching amount measurement system that causes a computer processor to execute the measurement method described in any one of claims 1 to 5.

Images