静的プログラム·コードのメモリ·アクセス·パターンの有効化

Abstract

A computer system configured to perform operations for validating a memory access pattern of a static variant of a program instruction stream, the operations including randomizing a first set of input arguments, generating an address translation list for virtual addresses based on the memory access pattern, storing the memory accesses in a first table, and executing the static variant of the program instruction stream on an accelerator processing unit. During execution, virtual addresses may be discarded and replaced by addresses provided in the address translation list. The operations may include recording and storing each memory access of the execution of the static variant of the program instruction stream in a second table, and comparing the memory access pattern stored in the second table with the memory access pattern stored in the first table. The memory access pattern may be validated or discarded.

Images