Imaging device and electronic equipment

The imaging device addresses computational and power consumption issues in image processing by employing a novel configuration with pooling and neural network functions, achieving reduced load and faster processing for enhanced automotive applications.

JP7892105B2Active Publication Date: 2026-07-17SEMICON ENERGY LAB CO LTD
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Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
SEMICON ENERGY LAB CO LTD
Filing Date
2025-05-26
Publication Date
2026-07-17

AI Technical Summary

Technical Problem

In imaging devices with solid-state image sensors, the increasing computational load and power consumption for image processing, particularly in automotive applications, pose challenges due to the need for advanced image recognition and large data handling, which can impact safety and efficiency.

Method used

An imaging device with a novel configuration incorporating a pixel region, pooling module, and neural network functionality that includes pooling circuits, comparison modules, and arithmetic circuits to reduce computational load and power consumption by performing pooling processing efficiently.

Benefits of technology

The imaging device reduces computational load and power consumption by pooling image data features, allowing for faster processing and efficient data transfer to neural networks, thereby enhancing safety and performance in automotive applications.

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Abstract

To provide an imaging apparatus for facilitating pooling processing.SOLUTION: The pixel area of the imaging apparatus includes a plurality of pooling modules and an output circuit. The pooling module includes a pooling circuit and a comparison module. The pooling circuit includes a plurality of pixels and an arithmetic circuit. The comparison module includes a plurality of comparison circuits and a determination circuit. The pixel acquires a first signal by photoelectric conversion and multiplies the first signal by an arbitrary magnification, to generate a second signal. The pooling circuit adds a plurality of second signals by the arithmetic circuit, to generate a third signal. The comparison module compares a plurality of third signals and outputs the largest third signal to the determination circuit. The determination circuit determines the largest third signal and binarizes it, to generate a fourth signal.SELECTED DRAWING: Figure 1
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