Semiconductor equipment and image reading device

Abstract

To provide a semiconductor device that can reduce variations in the amount of offset between pixel signals occurring due to fluctuations in power supply voltage.SOLUTION: A semiconductor device comprises: first power supply wiring; second power supply wiring that is different from the first power supply wiring; a pixel circuit that is connected with the first power supply wiring, and converts incident light into an electric signal; a storage circuit that has a capacitive element storing a pixel signal output from the pixel circuit and a switch element connected between the pixel circuit and the capacitive element; a buffer circuit that drives the switch element; and a logic circuit that is connected with the second power supply wiring, and controls the pixel circuit and the storage circuit. The buffer circuit is connected with the second power supply wiring.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present invention relates to a semiconductor device and an image reading device.

Background Art

[0002] In Patent Document 1, a plurality of pixels that are arranged in one direction for each color of light to be received and convert the light into an electrical signal, and a plurality of pixels determined in advance as a pixel group, and a plurality of electrical signals respectively converted by the pixels are frequency-diffused. A parallel processing unit that performs parallel processing for each pixel group in synchronization with a clock, and a correction unit that corrects an offset level based on a common value for each pixel group for each of the plurality of electrical signals parallel-processed by the parallel processing unit are described. According to the photoelectric conversion element described in Patent Document 1, it is possible to reduce the occurrence of streaks in the read image due to the frequency-diffusion clock while suppressing an increase in the circuit scale.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the photoelectric conversion element described in Patent Document 1, it is not possible to reduce the variation in the offset amount of the pixel signal caused by the fluctuation of the power supply voltage.

Means for Solving the Problems

[0005] One aspect of the semiconductor device according to the present invention is a first power supply wiring, a second power supply wiring different from the first power supply wiring, a pixel circuit to which the first power supply wiring is connected and that converts incident light into an electrical signal, A memory circuit having a capacitive element for storing the pixel signal output from the pixel circuit and a switch element connected between the pixel circuit and the capacitive element, A buffer circuit that drives the aforementioned switch element, The second power supply wiring is connected to a logic circuit that controls the pixel circuit and the memory circuit, Equipped with, The buffer circuit is connected to the second power supply wiring.

[0006] Another aspect of the semiconductor device according to the present invention is: Power terminals, A pixel circuit that converts incident light into an electrical signal, A memory circuit having a capacitive element for storing the pixel signal output from the pixel circuit and a switch element connected between the pixel circuit and the capacitive element, A buffer circuit that drives the aforementioned switch element, A logic circuit that controls the pixel circuit and the memory circuit, A rectangular semiconductor substrate, Equipped with, The semiconductor substrate has a first long side, a second long side opposite to the first long side, a first short side, and a second short side opposite to the first short side. The pixel circuit and the memory circuit are arranged in a first region along the first long side of the semiconductor substrate. The power terminal, the logic circuit, and the buffer circuit are arranged in a second region along the second long side of the semiconductor substrate.

[0007] One aspect of the image reading device according to the present invention is: One embodiment of the semiconductor device, Light source and It is equipped with. [Brief explanation of the drawing]

[0008] [Figure 1] This is an external perspective view showing a multifunction device according to this embodiment. [Figure 2]A perspective view showing the internal structure of the scanner unit. [Figure 3] A schematic exploded perspective view showing the configuration of the image sensor module. [Figure 4] A schematic plan view showing the arrangement of the image reading chips. [Figure 5] A diagram showing the functional configuration of the scanner unit. [Figure 6] A diagram showing the circuit configuration of the image reading chip in the first embodiment. [Figure 7] A diagram showing an example of the circuit layout of an image reading chip. [Figure 8] A diagram showing the configuration of the pixel circuit and line memory. [Figure 9] A diagram showing the configuration of the first CDS circuit. [Figure 10] A diagram showing the configuration of the 2nd to nth CDS circuits. [Figure 11] A diagram showing the configuration of the bias current generation circuit. [Figure 12] A timing chart showing the timing of image reading operations by the image reading chip. [Figure 13] Detailed timing chart for the period from time t8 to time t9 in Figure 12. [Figure 14] A diagram showing the circuit arrangement and some wiring patterns of the image reading chip in the first embodiment. [Figure 15] A diagram illustrating the propagation of power supply voltage fluctuations. [Figure 16] A diagram showing the circuit configuration of the image reading chip in the second embodiment. [Figure 17] A diagram showing the circuit arrangement and some wiring patterns of the image reading chip in the third embodiment. [Figure 18] Timing chart diagram of the clock signal, readout signal, and pixel signal in the third embodiment. [Modes for carrying out the invention]

[0009] Preferred embodiments of the present invention will be described in detail below with reference to the drawings. The drawings used are for illustrative purposes only. The embodiments described below are not intended to unduly limit the scope of the present invention as described in the claims. Furthermore, not all of the configurations described below are essential components of the present invention.

[0010] The following describes a multifunction device 1 to which the image reading device of the present invention is applied, with reference to the attached drawings.

[0011] 1. First Embodiment 1-1. Structure of a multifunction printer Figure 1 is an external perspective view of the multifunction device 1. As shown in Figure 1, the multifunction device 1 includes a printer unit 2, which is an image recording device, and a scanner unit 3, which is an image reading device. Specifically, the multifunction device 1 integrates the printer unit 2, which is the main body of the device, and the scanner unit 3, which is an upper unit located on top of the printer unit 2. In the following description, the front-to-back direction in Figure 1 will be referred to as the X-axis direction, and the left-to-right direction as the Y-axis direction.

[0012] As shown in Figure 1, the printer unit 2 comprises a transport unit (not shown) that feeds recording media such as printing paper or single sheets along a feed path, a printing unit (not shown) positioned above the feed path and performing inkjet printing on the recording media, a panel-type operation unit 63 positioned on the front, a device frame (not shown) that mounts the transport unit, the printing unit, and the operation unit 63, and a device housing 65 that covers them. The device housing 65 is provided with an outlet 66 through which the printed recording media is discharged. Although not shown, a USB port and a power port are located on the lower rear of the printer unit 2. In other words, the multifunction device 1 is configured to be connectable to a computer or the like via the USB port.

[0013] The scanner unit 3 is rotatably supported on the printer unit 2 via a hinge 4 at its rear end, and covers the top of the printer unit 2 in an openable and closable manner. Specifically, by pulling the scanner unit 3 up in the rotational direction, the top opening of the printer unit 2 is exposed, and the inside of the printer unit 2 is exposed through this top opening. On the other hand, by pulling the scanner unit 3 down in the rotational direction and placing it on the printer unit 2, the top opening is closed by the scanner unit 3. In this way, opening the scanner unit 3 allows for the replacement of ink cartridges, clearing paper jams, and other such operations.

[0014] Figure 2 is a perspective view showing the internal structure of the scanner unit 3. As shown in Figures 1 and 2, the scanner unit 3 comprises an upper frame 11 which is the housing, an image reading unit 12 housed in the upper frame 11, and an upper cover 13 that is rotatably supported on the upper part of the upper frame 11. As shown in Figure 2, the upper frame 11 comprises a box-shaped lower case 16 that houses the image reading unit 12, and an upper case 17 that covers the top surface of the lower case 16. The upper case 17 has a wide glass document placement plate (not shown) on which the medium to be read is placed with the reading surface facing downwards. On the other hand, the lower case 16 is formed in a shallow box shape with an open top.

[0015] As shown in Figure 2, the image reading unit 12 includes a line sensor type sensor unit 31, a sensor carriage 32 on which the sensor unit 31 is mounted, a guide shaft 33 extending in the Y-axis direction and supporting the sensor carriage 32 so that it can slide freely, and a self-propelled sensor movement mechanism 34 that moves the sensor carriage 32 along the guide shaft 33. The sensor unit 31 has an image sensor module 41 which is a CMOS line sensor extending in the X-axis direction, and reciprocates in the Y-axis direction along the guide shaft 33 by the motor-driven sensor movement mechanism 34. CMOS stands for Complementary Metal-Oxide-Semiconductor. This allows the image of the medium to be read on the document placement plate to be read. The sensor unit 31 may also be a CCD line sensor. CCD stands for Charge Coupled Device.

[0016] Figure 3 is a schematic exploded perspective view showing the configuration of the image sensor module 41. In the example shown in Figure 3, the image sensor module 41 comprises a case 411, a light source 412, a lens 413, a module substrate 414, and an image reading chip 415, which is a semiconductor device for reading images. The light source 412, lens 413, and image reading chip 415 are housed between the case 411 and the module substrate 414. A slit is provided in the case 411. The light source 412 has, for example, R, G, and B light-emitting diodes, and sequentially emits light by rapidly switching between the R, G, and B light-emitting diodes, i.e., red LED, green LED, and blue LED. LED stands for Light-emitting diode. The light emitted from the light source 412 is irradiated onto the medium to be read through the slit, and the light from the medium to be read is input to the lens 413 through the slit. The lens 413 guides the input light to the image reading chip 415. The image reading chip 415 then reads the image formed on the medium to be read based on the light reflected by the medium from the light source 412.

[0017] Figure 4 is a schematic plan view showing the arrangement of the image reading chips 415. As shown in Figure 4, multiple image reading chips 415 are arranged in a one-dimensional direction, specifically along the X-axis, on the module substrate 414. Each image reading chip 415 has a large number of light-receiving elements arranged in a row, and the higher the density of light-receiving elements in each image reading chip 415, the higher the resolution of the scanner unit 3 that can read images can be realized. Also, the more image reading chips 415 there are, the more large images the scanner unit 3 that can read can be realized.

[0018] 1-2. Functional Configuration of the Scanner Unit Figure 5 is a functional block diagram showing the functional configuration of a scanner unit 3, which is an image reading device. In the example shown in Figure 5, the scanner unit 3 is composed of a control unit 300, an analog front end 302, a red LED 412R, a green LED 412G, a blue LED 412B, and a plurality of image reading chips 415. As mentioned above, the red LED 412R, green LED 412G, and blue LED 412B are provided on the light source 412, and the plurality of image reading chips 415 are arranged in a row on the module board 414. There may be multiple instances of each of the red LED 412R, green LED 412G, and blue LED 412B. In addition, the control unit 300 and the analog front end 302 are provided on the module board 414 or on a different board (not shown) from the module board 414. The control unit 300 and the analog front end 302 may each be implemented as integrated circuits.

[0019] The control unit 300 supplies a drive signal DrvR to the red LED 412R at a predetermined timing for a fixed exposure time Δt, causing the red LED 412R to light up. Similarly, the control unit 300 supplies a drive signal DrvG to the green LED 412G at a predetermined timing for an exposure time Δt, causing the green LED 412G to light up, and supplies a drive signal DrvB to the blue LED 412B at a predetermined timing for an exposure time Δt, causing the blue LED 412B to light up. The control unit 300 causes the red LED 412R, green LED 412G, and blue LED 412B to light up one by one.

[0020] Furthermore, the control unit 300 supplies a clock signal CLK and a command signal CMD to the multiple image reading chips 415. The clock signal CLK is the operating clock signal of the image reading chip 415, and the command signal CMD is a signal that includes various commands such as commands for setting the resolution of image reading by the scanner unit 3, and commands for instructing the start and end of image reading. In the following, the resolution of image reading by the scanner unit 3 will be set to one of 4800 dpi, 2400 dpi, 1200 dpi, 600 dpi, or 300 dpi by the command signal CMD. dpi is an abbreviation for dots per inch.

[0021] Each image reading chip 415 operates in synchronization with the clock signal CLK, and generates and outputs an image signal OS containing image information of a set resolution based on the light received by each photodetector from the image formed on the reading medium, through the emission of a red LED 412R, a green LED 412G, or a blue LED 412B. The detailed circuit configuration and operation of this image reading chip 415 will be described later.

[0022] The analog front-end 302 receives multiple image signals OS output by each image reading chip 415, performs amplification and A / D conversion processing on each image signal OS to convert it into a digital signal that includes a digital value corresponding to the amount of light received by each photodetector, and transmits each digital signal sequentially to the control unit 300.

[0023] The control unit 300 receives each digital signal transmitted sequentially from the analog front end 302 and generates image information read by the image sensor module 41.

[0024] 1-3. Configuration of the image reading chip Figure 6 shows the circuit configuration of the image reading chip 415. As shown in Figure 6, the image reading chip 415 includes a logic circuit 101, a scanning circuit 102, a buffer circuit 104, N pixel circuits 110, N line memories 120, n CDS circuits 130, a preamplifier 140, an output buffer 150, and a bias circuit 160. CDS stands for Correlated Double Sampling. Each of these circuits operates with power supply voltage VDD and ground voltage VSS supplied from the external terminals of the image reading chip 415. The power supply voltage VDD is separated into analog power supply voltage AVDD and digital power supply voltage DVDD. The logic circuit 101 and buffer circuit 104 operate with the digital power supply voltage DVDD, while the other circuits operate with the analog power supply voltage AVDD.

[0025] In Figure 6, the n blocks 103-1 to 103-n all have the same configuration and each contains m pixel circuits 110, m line memories 120, and one CDS circuit 130. That is, the integer N is m times the integer n, and the integers n and m are both greater than or equal to 1. For example, N=3456, n=24, and m=144.

[0026] The bias circuit 160 generates various constant currents, reference voltages, bias voltages, etc., and supplies them to each circuit. The bias circuit 160 includes a VREFH amplifier 161, a bias current generation circuit 162, and current mirror circuits 163 and 164.

[0027] The VREFH amplifier 161 is a reference voltage circuit that generates and outputs a reference voltage VREFH, which is a voltage between the analog power supply voltage AVDD and the ground voltage VSS, based on the analog power supply voltage AVDD and the ground voltage VSS. The reference voltage VREFH is supplied to each of the n CDS circuits 130.

[0028] The bias current generation circuit 162 generates respective constant bias currents I bias1 , I bias2 , I bias3 , I bias4 , I bias5 based on the analog power supply voltage AVDD and the ground voltage VSS. The bias currents I bias1 , I bias2 are respectively supplied to the current mirror circuits 163 and 164. The bias current I bias3 is supplied to each of the n CDS circuits 130. The bias current I bias4 is supplied to the preamplifier 140. The bias current I bias5 is supplied to the output buffer 150.

[0029] The current mirror circuit 163 generates a reference current I bias1 that is a predetermined multiple of the bias current I ref1 supplied from the bias current generation circuit 162. For example, the reference current I ref1 may have the same magnitude as the bias current I bias1 . The reference current I ref1 is supplied to each of the N pixel circuits 110.

[0030] The current mirror circuit 164 generates a reference current I bias2 that is a predetermined multiple of the bias current I ref2 supplied from the bias current generation circuit 162. For example, the reference current I ref2 may have the same magnitude as the bias current I bias2 . The reference current I ref2 is supplied to each of the N line memories 120.

[0031] The logic circuit 101 operates in synchronization with the clock signal CLK and controls N pixel circuits 110, N line memories 120, n CDS circuits 130, a preamplifier 140, an output buffer 150, and a VREFH amplifier 161. Specifically, the logic circuit 101 has a counter (not shown) that counts the pulses of the clock signal CLK, and generates various control signals to control the operation of each circuit based on the count value of the counter.

[0032] Specifically, logic circuit 101 generates a power-down signal PD and supplies it to VREFH amplifier 161. Logic circuit 101 also generates a pixel reset signal PIX_RST and supplies it to each pixel circuit 110. Furthermore, logic circuit 101 generates read signals READN and READS and supplies them to each line memory 120. Logic circuit 101 also generates a read signal RD and outputs it to buffer circuit 104. Additionally, logic circuit 101 generates a standby signal PD_STBY, a CDS reset signal CDS_RST, and a dummy end signal DUMMY_END and supplies them to each CDS circuit 130. Finally, logic circuit 101 generates n-1 start signals ST_BLK[0] to ST_BLK[n-1] that are mutually exclusive and at a high level. The start signal ST_BLK[0] is supplied in common to the n CDS circuits 130, while the start signals ST_BLK[i-2] and ST_BLK[i-1] are supplied to the i-th CDS circuit 130 among the 2nd to nth CDS circuits 130. The logic circuit 101 also generates various control signals that control the operation of the scanning circuit 102, the preamplifier 140, and the output buffer 150.

[0033] The buffer circuit 104 delays and buffers the read signal RD generated by the logic circuit 101 to generate a read signal READ, which is then supplied to each line memory 120.

[0034] The scanning circuit 102 outputs N selection signals SEL[0] to SEL[N-1] based on the control signal from the logic circuit 101. When the resolution is set to 4800 dpi, the scanning circuit 102 outputs N selection signals SEL[0] to SEL[N-1] that become high one by one in sequence. When the resolution is set to 2400 dpi, the scanning circuit 102 outputs N selection signals SEL[0] to SEL[N-1] that become high two by two in sequence simultaneously. When the resolution is set to 1200 dpi, the scanning circuit 102 outputs N selection signals SEL[0] to SEL[N-1] that become high four by four in sequence simultaneously. When the resolution is set to 600 dpi, the scanning circuit 102 outputs N selection signals SEL[0] to SEL[N-1] that become high eight by eight in sequence simultaneously. Furthermore, when the resolution is set to 300 dpi, the scanning circuit 102 outputs N selection signals SEL[0] to SEL[N-1] that are simultaneously and sequentially high-level in groups of 16. These N selection signals SEL[0] to SEL[N-1] are supplied to N line memories 120, respectively.

[0035] Light from the light source 412 reflected by the reading medium is incident on the N pixel circuits 110. Each of the N pixel circuits 110 then converts the incident light into an electrical signal, which is a pixel signal. Specifically, each pixel circuit 110 outputs a pixel signal with a voltage corresponding to the light received from the reading medium during the exposure time Δt, by the emission of a red LED 412R, a green LED 412G, or a blue LED 412B. The pixel signal is reset to a predetermined voltage when the pixel reset signal PIX_RST is high level. In other words, the pixel reset signal PIX_RST is a reset signal that initializes the N pixel circuits 110.

[0036] Each of the N line memories 120 is a memory circuit that stores the pixel signals output from the N pixel circuits 110 at predetermined timings. Specifically, each line memory 120 acquires a first pixel signal, which is the pixel signal output from the pixel circuit 110, during the period when the read signal READ is high, and stores the acquired first pixel signal in the first memory element when the read signal READN is high. Subsequently, each line memory 120 acquires a second pixel signal, which is the pixel signal output from the pixel circuit 110 during the next period when the read signal READ is high, and stores the acquired second pixel signal in the second memory element when the read signal READS is high. Then, the j-th line memory 120 outputs the first and second pixel signals when the selection signal SEL[j-1] is high. j is an integer between 1 and N, inclusive.

[0037] In this embodiment, when the resolution is set to 4800 dpi, the N selection signals SEL[0] to SEL[N-1] become high one by one in sequence, so the first pixel signal and the second pixel signal are output one by one from the N line memories 120 in sequence. When the resolution is set to 2400 dpi, the N selection signals SEL[0] to SEL[N-1] become high two by two in sequence simultaneously, so the first pixel signal and the second pixel signal are output two by two from the N line memories 120 in sequence. When the resolution is set to 1200 dpi, the N selection signals SEL[0] to SEL[N-1] become high four by four in sequence simultaneously, so the first pixel signal and the second pixel signal are output four by four from the N line memories 120 in sequence. Furthermore, when the resolution is set to 600 dpi, the N selection signals SEL[0] to SEL[N-1] become high level in groups of eight simultaneously and sequentially, so eight first pixel signals and eight second pixel signals are output sequentially from the N line memories 120. Furthermore, when the resolution is set to 300 dpi, the N selection signals SEL[0] to SEL[N-1] become high level in groups of sixteen simultaneously and sequentially, so sixteen first pixel signals and sixteen second pixel signals are output sequentially from the N line memories 120.

[0038] Each of the n CDS circuits 130 is a differential amplifier circuit that receives a first signal and a second signal as inputs and outputs a third signal obtained by differentially amplified the first signal and the second signal. In this embodiment, when the resolution is set to 4800 dpi, the i-th CDS circuit 130 receives the first pixel signal and the second pixel signal, which are output one by one sequentially from the m line memories 120 from the (i-1)×m+1th to the i×mthth. i is an integer between 1 and n. For example, N=3456, n=24, and m=144. That is, the i-th CDS circuit 130 receives the first pixel signal and the second pixel signal stored in each line memory 120 as the first signal and the second signal, respectively, and outputs a pixel signal CDSO[i-1] obtained by differentially amplified the first pixel signal and the second pixel signal as the third signal.

[0039] Furthermore, when the resolution is set to 2400 dpi, the i-th CDS circuit 130 simultaneously receives the first pixel signal and the second pixel signal, which are output in pairs sequentially from the m line memories 120 from the (i-1) × m+1th to i × mth positions. Therefore, the i-th CDS circuit 130 outputs a pixel signal CDSO[i-1] as the third signal, which is obtained by differentially amplified the first signal, which is the voltage sum of two second pixel signals, and the second signal, which is the voltage sum of two second pixel signals. Furthermore, when the resolution is set to 1200 dpi, the i-th CDS circuit 130 simultaneously receives the first pixel signal and the second pixel signal, which are output in pairs sequentially from the m line memories 120 from the (i-1) × m+1th to i × mth positions. Therefore, the i-th CDS circuit 130 outputs a pixel signal CDSO[i-1] as the third signal, which is obtained by differentially amplified the first signal obtained by voltage summing the four first pixel signals and the second signal obtained by voltage summing the four second pixel signals. Also, when the resolution is set to 600 dpi, the i-th CDS circuit 130 simultaneously receives the first pixel signals and the second pixel signals, which are output in groups of eight from the m line memories 120 from the (i-1)×m+1th to i×mthth. Therefore, the i-th CDS circuit 130 outputs a pixel signal CDSO[i-1] as the third signal, which is obtained by differentially amplified the first signal obtained by voltage summing the eight first pixel signals and the second signal obtained by voltage summing the eight second pixel signals. Furthermore, when the resolution is set to 300 dpi, the i-th CDS circuit 130 simultaneously receives the first pixel signal and the second pixel signal, which are output in groups of 16 from the m line memories 120 from the (i-1) × m+1th to i × mthth. Therefore, the i-th CDS circuit 130 outputs a pixel signal CDSO[i-1] as the third signal, which is obtained by differentially amplified the first signal, which is the voltage sum of the 16 first pixel signals, and the second signal, which is the voltage sum of the 16 second pixel signals.

[0040] In this embodiment, each line memory 120 acquires a pixel signal during a predetermined period after the pixel reset signal PIX_RST changes from a high level to a low level and stores it in the first memory element as a first pixel signal, and acquires a pixel signal during a predetermined period after the exposure is completed and stores it in the second memory element as a second pixel signal. Therefore, the voltage difference between the second pixel signal and the first pixel signal corresponds to the voltage corresponding to the light received by each pixel circuit 110 from the reading medium during the exposure time Δt. Accordingly, the i-th CDS circuit 130 removes noise contained in the second pixel signal output from each pixel circuit 110 by correlated double sampling and outputs a pixel signal CDSO[i-1] with a voltage corresponding to the light received by each pixel circuit 110.

[0041] The n CDS circuits 130 operate one by one in sequence, outputting pixel signals CDSO[0] to CDSO[n-1] mutually.

[0042] In this way, the N line memories 120 and the n CDS circuits 130 constitute a readout circuit 170 that reads out pixel signals from the N pixel circuits 110 and outputs pixel signals CDSO[0] to CDSO[n-1].

[0043] The pixel signals CDSO[0] to CDSO[n-1] are input to the preamplifier 140 in order as pixel signals CDSO. The preamplifier 140 outputs a signal that is an amplified version of the pixel signals CDSO. The signal output from the preamplifier 140 is input to the output buffer 150 as an image signal PAO corresponding to the image read by the N pixel circuits 110.

[0044] The output buffer 150 buffers the image signal PAO and outputs the image signal OS. The image signal OS is output from the external terminal of the image reading chip 415 and supplied to the analog front end 302 shown in Figure 5.

[0045] 1-4. Circuit layout of the image reading chip Figure 7 shows an example of the circuit layout of the image reading chip 415. As shown in Figure 7, the circuits constituting the image reading chip 415 are integrally formed on the semiconductor substrate 100 by a semiconductor process including photolithography. In other words, in this embodiment, the image reading chip 415 is configured as a single IC chip.

[0046] In plan view, the semiconductor substrate 100 is rectangular and has a first long side 100a, a second long side 100b opposite the first long side 100a, a first short side 100c, and a second short side 100d opposite the first short side 100c. The semiconductor substrate 100 is, for example, a silicon substrate.

[0047] Each of the N pixel circuits 110 and each of the N line memories 120 are arranged in a first region A1 along the first long side 100a of the semiconductor substrate 100. Specifically, in the first region A1, the N pixel circuits 110 are arranged in a line along the first long side 100a of the semiconductor substrate 100. Also in the first region A1, a read circuit 170, which consists of N line memories 120 and n CDS circuits 130, is arranged opposite the N pixel circuits 110. In other words, in the first region A1, the N pixel circuits 110 are arranged between the first long side 100a and the read circuit 170.

[0048] The scanning circuit 102 is positioned opposite the readout circuit 170. In other words, the readout circuit 170 is positioned between the N pixel circuits 110 and the scanning circuit 102.

[0049] The logic circuit 101 and the buffer circuit 104 are arranged in a second region A2 along the second long side 100b of the semiconductor substrate 100. The second region A2 also contains a plurality of pads 180, a preamplifier 140, an output buffer 150, and a bias circuit 160. Specifically, in the second region A2, the plurality of pads 180, the logic circuit 101, the preamplifier 140, the output buffer 150, and the bias circuit 160 are arranged in approximately a single line along the second long side 100b.

[0050] One of the multiple pads 180 is a power terminal to which the power supply voltage VDD is supplied, and another of the multiple pads 180 is a ground terminal to which the ground voltage VSS is supplied. The other two of the multiple pads 180 are input terminals to which the clock signal CLK and command signal CMD are input, respectively, and the last of the multiple pads 180 is an output terminal to which the image signal OS is output.

[0051] 1-5. Pixel Circuit and Line Memory Configuration The N pixel circuits 110 shown in Figure 6 all have the same configuration. Similarly, the N line memories 120 all have the same configuration. Figure 8 shows the configurations of the pixel circuits 110 and line memories 120. As shown in Figure 8, the pixel circuit 110 includes a light-receiving element 111, an inverting amplifier 112, a capacitive element 113, and a switching element 114.

[0052] The light-receiving element 111 receives light and converts it into an electrical signal, i.e., photoelectric conversion. Specifically, the light-receiving element 111 receives light that has been reflected from the reading medium after being irradiated from the light source 412 and converts it into an electrical signal. In this embodiment, the light-receiving element 111 is composed of a photodiode, with the anode grounded and the cathode connected to the input terminal of the inverting amplifier 112.

[0053] The inverting amplifier 112 is connected to the photodetector 111 and inverts and amplifies the signal generated by the photoelectric conversion of the photodetector 111. Specifically, the input terminal of the inverting amplifier 112 is connected to the cathode of the photodetector 111, and a reference current I ref1 Based on this, the voltage at the input terminal is inverted and amplified, and the resulting voltage is output from the output terminal.

[0054] The capacitive element 113 is connected at both ends to the input and output terminals of the inverting amplifier 112, respectively. In other words, the capacitive element 113 functions as a feedback capacitor provided in the signal feedback path from the output terminal to the input terminal of the inverting amplifier 112.

[0055] The switch element 114 has its ends connected to the input and output terminals of the inverting amplifier 112, respectively. The control terminal of the switch element 114 receives the pixel reset signal PIX_RST. When the pixel reset signal PIX_RST is high level, both ends of the switch element 114 conduct, and when the pixel reset signal PIX_RST is low level, both ends of the switch element 114 do not conduct. When the pixel reset signal PIX_RST is high level, both ends of the switch element 114 conduct, causing the capacitive element 113 to short-circuit and reset its accumulated charge.

[0056] The signal output from the output terminal of the inverting amplifier 112 is input to the line memory 120 as a pixel signal PIXO.

[0057] The voltage V of the first pixel signal, which is the pixel signal PIXO immediately after reset by the pixel reset signal PIX_RST. PIXO1 The equation is as shown in equation (1). Also, the voltage V of the second pixel signal, which is the pixel signal PIXO after exposure. PIXO2 This is given by equation (2). In equations (1) and (2), V rst This is the voltage of the pixel signal PIXO immediately after the charge of the capacitive element 113 is reset. Also, in equation (2), I pd is the current flowing through the photodetector 111 due to exposure, Δt is the exposure time, and C d This is the capacitance of the capacitive element 113.

[0058]

number

[0059]

number

[0060] The line memory 120 includes a switch element 121, a capacitive element 122, an NMOS transistor 123, a constant current source 124, a switch element 125, a switch element 126, a capacitive element 127, a capacitive element 128, a switch element 129p, and a switch element 129n.

[0061] Switch element 121 has one end connected to the output terminal of the inverting amplifier 112 and the other end of the capacitive element 113, and the other end connected to one end of the capacitive element 122. That is, switch element 114 is connected between the pixel circuit 110 and the capacitive element 113. A read signal READ is input to the control terminal of switch element 121. In other words, the read signal READ is the control signal for switch element 121, and the buffer circuit 104 drives switch element 114 according to the read signal READ. When the read signal READ is high level, both ends of switch element 121 conduct, and when the read signal READ is low level, both ends of switch element 121 do not conduct.

[0062] Capacitive element 122 has one end connected to the other end of switch element 121 and the other end grounded. When the read signal READ is high level, both ends of switch element 121 conduct, and a charge corresponding to the difference between the voltage of the pixel signal PIXO output from the pixel circuit 110 and the ground voltage VSS is accumulated in the capacitive element 122. That is, when the read signal READ is high level, the capacitive element 122 temporarily stores the pixel signal PIXO output from the pixel circuit 110. In this embodiment, the read signal READ becomes high level during a predetermined period after the pixel reset signal PIX_RST changes from high level to low level, and the pixel signal PIXO during this period when the read signal READ is high level is temporarily stored in the capacitive element 122 as the first pixel signal. Also, the read signal READ becomes high level during a predetermined period after the end of exposure, and the pixel signal PIXO during this period when the read signal READ is high level is temporarily stored in the capacitive element 122 as the second pixel signal.

[0063] The voltage V of the capacitive element 122 where the first pixel signal, PIXO, which is the pixel signal immediately after reset by the pixel reset signal PIX_RST, is stored. mem1 The equation is as shown in equation (3). Also, the voltage V of the capacitive element 122 where the second pixel signal, which is the pixel signal PIXO after exposure, is stored. mem2 The result is as shown in equation (4).

[0064]

number

[0065]

number

[0066] The gate of NMOS transistor 123 is connected to the other end of switch element 121 and one end of capacitive element 122. The drain of NMOS transistor 123 is supplied with the analog power supply voltage AVDD. The source of NMOS transistor 123 is connected to one end of constant current source 124, one end of switch element 125, and one end of switch element 126. The other end of constant current source 124 is grounded. Constant current source 124 supplies a reference current I ref2 A constant current is generated based on this. The NMOS transistor 123 and the constant current source 124 constitute a source-follower circuit, and the source of the NMOS transistor 123 becomes a voltage corresponding to the gate voltage of the NMOS transistor 123, that is, a voltage corresponding to the charge stored in the capacitive element 122.

[0067] Switch element 125 has one end connected to the source of NMOS transistor 123, one end of constant current source 124, and one end of switch element 126, and the other end connected to one end of capacitive element 127. A read signal READN is input to the control terminal of switch element 125. When the read signal READN is high level, both ends of switch element 125 conduct, and when the read signal READN is low level, both ends of switch element 125 become non-conductive.

[0068] Capacitive element 127 has one end connected to the other end of switch element 125 and the other end grounded. When the read signal READN is high level, both ends of switch element 125 conduct, and a charge corresponding to the difference between the source voltage of NMOS transistor 123 and the ground voltage VSS is accumulated in capacitive element 127. The source voltage of NMOS transistor 123 becomes a voltage corresponding to the charge accumulated in capacitive element 122, so when the read signal READN is high level, a charge corresponding to the charge accumulated in capacitive element 122 is accumulated in capacitive element 127. In this embodiment, when the pixel signal PIXO as the first pixel signal is temporarily stored in capacitive element 122, the read signal READN becomes high level, and the pixel signal PIXO as the first pixel signal is stored in capacitive element 127.

[0069] Switch element 126 has one end connected to the source of NMOS transistor 123, one end of constant current source 124, and one end of switch element 125, and the other end connected to one end of capacitive element 128. A read signal READS is input to the control terminal of switch element 126. When the read signal READS is high level, both ends of switch element 126 conduct, and when the read signal READS is low level, both ends of switch element 126 become non-conductive.

[0070] Capacitive element 128 has one end connected to the other end of switch element 126 and the other end grounded. When the read signal READS is high level, both ends of switch element 126 conduct, and a charge corresponding to the difference between the source voltage of NMOS transistor 123 and the ground voltage VSS is accumulated in capacitive element 128. The source voltage of NMOS transistor 123 becomes a voltage corresponding to the charge accumulated in capacitive element 122, so when the read signal READS is high level, a charge corresponding to the charge accumulated in capacitive element 122 is accumulated in capacitive element 128. In this embodiment, when the pixel signal PIXO as a second pixel signal is temporarily stored in capacitive element 122, the read signal READS becomes high level, and the pixel signal PIXO as a second pixel signal is stored in capacitive element 128.

[0071] One end of the switch element 129p is connected to the other end of the switch element 125 and one end of the capacitive element 127. A selection signal SEL[j-1] is input to the control terminal of the switch element 129p. When the selection signal SEL[j-1] is high level, both ends of the switch element 129p conduct, and when the selection signal SEL[j-1] is low level, both ends of the switch element 129p do not conduct. When the selection signal SEL[j-1] is high level, both ends of the switch element 129p conduct, and the voltage at the other end of the switch element 129p becomes equal to the voltage at one end of the capacitive element 127. That is, when the selection signal SEL[j-1] is high level, the first pixel signal stored in the capacitive element 127 is output from the other end of the switch element 129p.

[0072] One end of the switch element 129n is connected to the other end of the switch element 126 and one end of the capacitive element 128. A selection signal SEL[j-1] is input to the control terminal of the switch element 129n. When the selection signal SEL[j-1] is high level, both ends of the switch element 129n conduct, and when the selection signal SEL[j-1] is low level, both ends of the switch element 129n do not conduct. When the selection signal SEL[j-1] is high level, both ends of the switch element 129n conduct, and the voltage at the other end of the switch element 129n becomes equal to the voltage at one end of the capacitive element 128. That is, when the selection signal SEL[j-1] is high level, the second pixel signal stored in the capacitive element 128 is output from the other end of the switch element 129n.

[0073] The voltage V of the capacitive element 127, which stores the first pixel signal PIXO, the pixel signal immediately after a reset by the pixel reset signal PIX_RST, is the voltage V of the capacitive element 127. N The equation is as shown in equation (5). Also, the voltage V of the capacitive element 128 where the second pixel signal, which is the pixel signal PIXO after exposure, is stored. S This is given by equation (6). In equations (5) and (6), V t This is the threshold voltage of NMOS transistor 123.

[0074]

number

[0075]

number

[0076] 1-6. CDS Circuit Configuration Of the n CDS circuits 130 shown in Figure 6, the 2nd to the nth CDS circuits 130 all have the same configuration, while the 1st CDS circuit 130 has a slightly different configuration from the 2nd to the nth CDS circuits 130. Figure 9 shows the configuration of the 1st CDS circuit 130 shown in Figure 6. Figure 10 shows the configurations of the 2nd to the nth CDS circuits 130 shown in Figure 6.

[0077] As shown in Figures 9 and 10, the CDS circuit 130 includes a capacitive element 131p, a capacitive element 131n, a switch element 132p, a switch element 132n, an operational amplifier 133, an NMOS transistor 134, a constant current source 135, a switch element 136, a switch element 137, and a logic circuit 138.

[0078] Capacitive element 131p has one end connected to the non-inverting input terminal of operational amplifier 133 and one end of switch element 132p, and the other end connected to the other end of switch element 132p and one end of switch element 136. The other end of switch element 136 is connected to reference voltage node N VREFH It is connected to the reference voltage node N. VREFH This node is where the VREFH amplifier 161 outputs a reference voltage VREFH, and the reference voltage VREFH is supplied to the other end of the switch element 136.

[0079] The capacitive element 131n is connected at both ends to the inverting input terminal and output terminal of the operational amplifier 133, respectively. In other words, the capacitive element 131n functions as a feedback capacitor provided in the signal feedback path from the output terminal to the inverting input terminal of the operational amplifier 133.

[0080] The switch element 132n is connected at both ends to the inverting input terminal and output terminal of the operational amplifier 133, respectively. The CDS reset signal CDS_RST is input to the control terminals of the switch element 132p and the switch element 132n. When the CDS reset signal CDS_RST is high level, both ends of the switch elements 132p and 132n conduct, and when the CDS reset signal CDS_RST is low level, both ends of the switch elements 132p and 132n do not conduct. When the CDS reset signal CDS_RST is high level, both ends of the switch elements 132p and 132n conduct, so the capacitive elements 131p and 131n are short-circuited and their accumulated charge is reset.

[0081] The non-inverting input terminal of the operational amplifier 133 is electrically connected to one end of each of the m capacitive elements 127 when each of the m switch elements 129p is conducting. The inverting input terminal of the operational amplifier 133 is electrically connected to one end of each of the m capacitive elements 128 when each of the m switch elements 129n is conducting.

[0082] When the resolution is set to 4800 dpi, in the i-th block 103-i, the m selection signals SEL[(i-1)×m]~SEL[i×m-1] become high one by one in sequence, so that the m switch elements 129p conduct one by one in sequence, and the m capacitive elements 127 are electrically connected one by one to the non-inverting input terminal of the operational amplifier 133, and the m switch elements 129n conduct one by one in sequence, and the m capacitive elements 128 are electrically connected one by one to the inverting input terminal of the operational amplifier 133 in sequence. Therefore, the first pixel signals stored in the m capacitive elements 127 are input one by one as non-inverting input signals CDS_INP[i-1] to the non-inverting input terminal of the operational amplifier 133, and the second pixel signals stored in the m capacitive elements 128 are input one by one as inverting input signals CDS_INN[i-1] to the inverting input terminal of the operational amplifier 133.

[0083] Furthermore, when the resolution is set to 2400 dpi, the m selection signals SEL[(i-1)×m]~SEL[i×m-1] become high in pairs in sequence, so the m switch elements 129p conduct in pairs in sequence, and the m capacitive elements 127 are electrically connected to the non-inverting input terminal of the operational amplifier 133 in pairs in sequence, and the m switch elements 129n conduct in pairs in sequence, and the m capacitive elements 128 are electrically connected to the inverting input terminal of the operational amplifier 133 in pairs in sequence. Therefore, the first pixel signals stored in m capacitive elements 127 are sequentially voltage-added to form a pixel signal, which is input to the non-inverting input terminal of the operational amplifier 133 as the non-inverting input signal CDS_INP[i-1]. The second pixel signals stored in m capacitive elements 128 are sequentially voltage-added to form a pixel signal, which is input to the inverting input terminal of the operational amplifier 133 as the inverting input signal CDS_INN[i-1].

[0084] Furthermore, when the resolution is set to 1200 dpi, the m selection signals SEL[(i-1)×m]~SEL[i×m-1] become high level in groups of four, so the m switch elements 129p conduct in groups of four, and the m capacitive elements 127 are electrically connected to the non-inverting input terminal of the operational amplifier 133 in groups of four, and the m switch elements 129n conduct in groups of four, and the m capacitive elements 128 are electrically connected to the inverting input terminal of the operational amplifier 133 in groups of four. Therefore, the first pixel signals stored in m capacitive elements 127 are sequentially voltage-added in groups of four to form a pixel signal which is input to the non-inverting input terminal of the operational amplifier 133 as the non-inverting input signal CDS_INP[i-1], and the second pixel signals stored in m capacitive elements 128 are sequentially voltage-added in groups of four to form a pixel signal which is input to the inverting input terminal of the operational amplifier 133 as the inverting input signal CDS_INN[i-1].

[0085] Furthermore, when the resolution is set to 600 dpi, the m selection signals SEL[(i-1)×m]~SEL[i×m-1] become high level in groups of eight, so the m switch elements 129p conduct in groups of eight, and the m capacitive elements 127 are electrically connected to the non-inverting input terminal of the operational amplifier 133 in groups of eight, and the m switch elements 129n conduct in groups of eight, and the m capacitive elements 128 are electrically connected to the inverting input terminal of the operational amplifier 133 in groups of eight. Therefore, the first pixel signals stored in m capacitive elements 127 are sequentially voltage-added in groups of eight to form a pixel signal which is input to the non-inverting input terminal of the operational amplifier 133 as the non-inverting input signal CDS_INP[i-1], and the second pixel signals stored in m capacitive elements 128 are sequentially voltage-added in groups of eight to form a pixel signal which is input to the inverting input terminal of the operational amplifier 133 as the inverting input signal CDS_INN[i-1].

[0086] Furthermore, when the resolution is set to 300 dpi, the m selection signals SEL[(i-1)×m]~SEL[i×m-1] become high level in groups of 16, so the m switch elements 129p conduct in groups of 16, and the m capacitive elements 127 are electrically connected to the non-inverting input terminal of the operational amplifier 133 in groups of 16, and the m switch elements 129n conduct in groups of 16, and the m capacitive elements 128 are electrically connected to the inverting input terminal of the operational amplifier 133 in groups of 16. Therefore, the first pixel signals stored in m capacitive elements 127 are sequentially voltage-added 16 times each to form a pixel signal which is input to the non-inverting input terminal of the operational amplifier 133 as the non-inverting input signal CDS_INP[i-1], and the second pixel signals stored in m capacitive elements 128 are sequentially voltage-added 16 times each to form a pixel signal which is input to the inverting input terminal of the operational amplifier 133 as the inverting input signal CDS_INN[i-1].

[0087] The standby signal PD_STBY is input to the standby terminal of the operational amplifier 133. When the standby signal PD_STBY is at a high level, the inverting input terminal and the non-inverting input terminal of the operational amplifier 133 are pulled up to the analog power supply voltage AVDD.

[0088] The gate of NMOS transistor 134 is connected to the output terminal of operational amplifier 133. The analog power supply voltage AVDD is supplied to the drain of NMOS transistor 134. The source of NMOS transistor 134 is connected to one end of constant current source 135 and one end of switch element 137. The other end of constant current source 135 is grounded. Constant current source 135 supplies bias current I bias3 A constant current is generated based on this. The NMOS transistor 134 and the constant current source 135 constitute a source-follower circuit, and the source of the NMOS transistor 134 becomes a voltage corresponding to the gate voltage of the NMOS transistor 134, that is, a voltage corresponding to the output terminal voltage of the operational amplifier 133.

[0089] As shown in Figure 9, in the first block 103-1, the logic circuit 138 included in the CDS circuit 130 generates the CDS enable signal CDS_EN[0] and the VREF switch control signal VREFSW[0] based on the standby signal PD_STBY, the start signal ST_BLK[0], and the dummy end signal DUMMY_END. Specifically, when the standby signal PD_STBY is at a high level, the logic circuit 138 generates a low-level CDS enable signal CDS_EN[0] and a high-level VREF switch control signal VREFSW[0]. Also, when the standby signal PD_STBY changes from a high level to a low level, the logic circuit 138 changes the CDS enable signal CDS_EN[0] from a low level to a high level. Furthermore, when the standby signal PD_STBY is at a low level, the logic circuit 138 starts counting the number of pulses of the clock signal CLK when the start signal ST_BLK[0] changes from a low level to a high level. When the count value reaches a predetermined value, it changes the CDS enable signal CDS_EN[0] from a high level to a low level, and also changes the VREF switch control signal VREFSW[0] from a high level to a low level. The timing at which both the CDS enable signal CDS_EN[0] and the VREF switch control signal VREFSW[0] change from a high level to a low level coincides with the timing at which the start signal ST_BLK[1] changes from a low level to a high level. Also, when the dummy end signal DUMMY_END changes from a low level to a high level, the logic circuit 138 changes the VREF switch control signal VREFSW[0] from a low level to a high level.

[0090] The CDS enable signal CDS_EN[0] is input to the enable terminal of the operational amplifier 133 and the control terminal of the switch element 137. The operational amplifier 133 operates when the CDS enable signal CDS_EN[0] is high level and stops operating when the CDS enable signal CDS_EN[0] is low level. Also, when the CDS enable signal CDS_EN[0] is high level, both ends of the switch element 137 conduct, and when the CDS enable signal CDS_EN[0] is low level, both ends of the switch element 137 do not conduct. When the CDS enable signal CDS_EN[0] is high level, both ends of the switch element 137 conduct, and the voltage at the other end of the switch element 137 becomes equal to the source voltage of the NMOS transistor 134. That is, when the CDS enable signal CDS_EN[0] is high level, a pixel signal CDSO[0] with a voltage corresponding to the voltage at the output terminal of the operational amplifier 133 is output from the other end of the switch element 137.

[0091] The VREF switch control signal VREFSW[0] is input to the control terminal of the switch element 136. When the VREF switch control signal VREFSW[0] is high level, both ends of the switch element 136 conduct, and when the VREF switch control signal VREFSW[0] is low level, both ends of the switch element 136 do not conduct. When the VREF switch control signal VREFSW[0] is high level, both ends of the switch element 136 conduct, and the voltage at the other end of the capacitive element 131p becomes equal to the reference voltage VREFH.

[0092] As shown in Figure 10, in the i-th block 103-i of the 2nd to nth blocks 103-2 to 103-n, the logic circuit 138 included in the CDS circuit 130 generates the CDS enable signal CDS_EN[i-1], the VREF switch control signal VREFSW[i-1], and the output enable signal OUT_EN[i-1] based on the standby signal PD_STBY, the start signal ST_BLK[0], the start signal ST_BLK[i-2], the start signal ST_BLK[i-1], and the dummy end signal DUMMY_END. Specifically, when the standby signal PD_STBY is at a high level, the logic circuit 138 generates a low-level CDS enable signal CDS_EN[i-1] and a high-level VREF switch control signal VREFSW[i-1]. Also, when the start signal ST_BLK[0] changes from a low level to a high level, the logic circuit 138 changes the VREF switch control signal VREFSW[i-1] from a high level to a low level. Furthermore, when the standby signal PD_STBY is at a low level, the logic circuit 138 starts counting the number of pulses of the clock signal CLK when the start signal ST_BLK[i-2] changes from a low level to a high level. When the count value reaches a predetermined value, it changes the CDS enable signal CDS_EN[i-1] from a low level to a high level. The timing of the CDS enable signal CDS_EN[i-1] changing from a low level to a high level is predetermined time before the timing of the start signal ST_BLK[i-1] changing from a low level to a high level. Also, when the start signal ST_BLK[i-1] changes from a low level to a high level, the logic circuit 138 changes the VREF switch control signal VREFSW[i-1] from a low level to a high level and starts counting the number of pulses of the clock signal CLK. Then, when the count value reaches a predetermined value, the logic circuit 138 changes the CDS enable signal CDS_EN[i-1] from a high level to a low level, and also changes the VREF switch control signal VREFSW[i-1] from a high level to a low level.The timing at which both the CDS enable signal CDS_EN[i-1] and the VREF switch control signal VREFSW[i-1] change from high to low coincides with the timing at which the start signal ST_BLK[i] changes from low to high. Furthermore, when the dummy end signal DUMMY_END changes from low to high, the logic circuit 138 changes the VREF switch control signal VREFSW[i-1] from low to high. The logic circuit 138 also generates a logical AND signal of the CDS enable signal CDS_EN[i-1] and the VREF switch control signal VREFSW[i-1] as the output enable signal OUT_EN[i-1]. In other words, the output enable signal OUT_EN[i-1] is high when both the CDS enable signal CDS_EN[i-1] and the VREF switch control signal VREFSW[i-1] are high, and the output enable signal OUT_EN[i-1] is low when at least one of the CDS enable signal CDS_EN[i-1] and the VREF switch control signal VREFSW[i-1] is low.

[0093] The CDS enable signal CDS_EN[i-1] is input to the enable terminal of the operational amplifier 133. The operational amplifier 133 operates when the CDS enable signal CDS_EN[i-1] is at a high level and stops operating when the CDS enable signal CDS_EN[i-1] is at a low level.

[0094] The VREF switch control signal VREFSW[i-1] is input to the control terminal of the switch element 136. When the VREF switch control signal VREFSW[i-1] is high level, both ends of the switch element 136 conduct, and when the VREF switch control signal VREFSW[i-1] is low level, both ends of the switch element 136 do not conduct. When the VREF switch control signal VREFSW[i-1] is high level, both ends of the switch element 136 conduct, and the voltage at the other end of the capacitive element 131p becomes equal to the reference voltage VREFH.

[0095] The output enable signal OUT_EN[i-1] is input to the control terminal of the switch element 137. When the output enable signal OUT_EN[i-1] is high level, both ends of the switch element 137 conduct, and when the output enable signal OUT_EN[i-1] is low level, both ends of the switch element 137 do not conduct. When the output enable signal OUT_EN[i-1] is high level, both ends of the switch element 137 conduct, and the voltage at the other end of the switch element 137 becomes equal to the source voltage of the NMOS transistor 134. That is, when the output enable signal OUT_EN[i-1] is high level, a pixel signal CDSO[i-1] with a voltage corresponding to the voltage at the output terminal of the operational amplifier 133 is output from the other end of the switch element 137.

[0096] In Figure 9 or Figure 10, the voltage V at the output terminal of the operational amplifier 133 is obtained when both ends of switch elements 132p and 132n are conducting, and both ends of switch element 136 are conducting. CDS_rst The equation is as shown in equation (7).

[0097]

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[0098] Furthermore, when both ends of switch elements 132p and 132n are non-conductive, and both ends of switch element 136 are conductive, the voltage V at the output terminal of the operational amplifier 133 is... CDS_sig This is given by equation (8). In equation (8), C INP C is the sum of the capacitances of one or more capacitive elements 127 electrically connected to the non-inverting input terminal of the operational amplifier 133. INN C is the sum of the capacitances of one or more capacitive elements 128 electrically connected to the inverting input terminal of the operational amplifier 133. f1 This is the capacitance of the capacitive element 131p, C f2 This is the capacitance of the capacitive element 131n. Also, V INP V is the voltage of the non-inverting input signal CDS_INP[i-1] input to the non-inverting input terminal of the operational amplifier 133, INNThis is the voltage of the inverting input signal CDS_INN[i-1] input to the inverting input terminal of the operational amplifier 133.

[0099]

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[0100] In equation (8), C INP =C INN , C f1 =C f2 Therefore, the voltage V at the output terminal of the operational amplifier 133 CDS_sig The result is as shown in equation (9).

[0101]

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[0102] 1-7. Configuration of the bias current generation circuit Figure 11 shows the configuration of the bias current generation circuit 162 shown in Figure 6. As shown in Figure 11, the bias current generation circuit 162 includes a constant current source 201, NMOS transistors 202, 203, 204 and PMOS transistors 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217.

[0103] The constant current source 201 has an analog power supply voltage AVDD supplied to one end, and the other end is connected to the drain and gate of an NMOS transistor 202. The source of the NMOS transistor 202 is grounded.

[0104] The gate of NMOS transistor 203 is connected to the gate and drain of NMOS transistor 202, its drain is connected to the gate of PMOS transistor 205 and the drain of PMOS transistor 206, and its source is grounded.

[0105] The gate of NMOS transistor 204 is connected to the gate and drain of NMOS transistor 202, its drain is connected to the drain of PMOS transistor 207 and the gates of PMOS transistors 206 and 207, and its source is grounded.

[0106] PMOS transistor 205 has its gate connected to the gates of PMOS transistors 208, 210, 212, 214, and 216, as well as the drain of PMOS transistor 206. The analog power supply voltage AVDD is supplied to its source, and its drain is connected to the source of PMOS transistor 206.

[0107] The sources of PMOS transistors 208, 210, 212, 214, and 216 are supplied with the analog power supply voltage AVDD, and the drains of PMOS transistors 208, 210, 212, 214, and 216 are connected to the sources of PMOS transistors 209, 211, 213, 215, and 217.

[0108] The source of PMOS transistor 207 is supplied with the analog power supply voltage AVDD, and the gate of PMOS transistor 207 is connected to the gates of PMOS transistors 206, 209, 211, 213, 215, and 217.

[0109] The bias current generation circuit 162 configured in this way generates bias current I from the currents flowing through the drains of the PMOS transistors 209, 211, 213, 215, and 217, respectively. bias1 ,I bias2 ,I bias3 ,I bias4 ,I bias5 Output as follows.

[0110] 1-8. Operation of the image reading chip Figure 12 is a timing chart showing the timing of the image reading operation by the image reading chip 415. Note that Figure 12 is a timing chart when the resolution of the image reading by the scanner unit 3 is set to 4800 dpi.

[0111] As shown in Figure 12, the pixel reset signal PIX_RST becomes high level during the period from time t1 to time t2, and each pixel signal PIXO output from the N pixel circuits 110 is reset to a predetermined voltage.

[0112] The red LED 412R lights up during the time period Δt from time t2 to time t5. During the period from time t1 to time t3, the read signal READ becomes high level, and the pixel signals PIXO of a predetermined voltage output from the N pixel circuits 110 are temporarily stored in each capacitive element 122 of the N line memory 120. The voltage of each capacitive element 122 is a predetermined voltage reset by the pixel reset signal PIX_RST, as shown in equation (3) above.

[0113] During the period from time t4 to time t5, the read signal READN becomes high level, and the pixel signals temporarily stored in the capacitive element 122 in each line memory 120 are stored in the capacitive element 127. The voltage of each capacitive element 127 is as shown in equation (5) above.

[0114] During the period from time t5 to time t6, the read signal READ becomes high level, and each pixel signal PIXO output from the N pixel circuits 110 is temporarily stored in each capacitive element 122 of the N line memory 120. The voltage of each capacitive element 122 is the voltage corresponding to the light that each photodetector 111 received from the reading medium during the exposure time Δt due to the emission of the red LED 412R, and is given by equation (4) above.

[0115] During the period from time t5 to time t7, the read signal READS becomes high level, and the pixel signals temporarily stored in the capacitive element 122 in each line memory 120 are stored in the capacitive element 128. The voltage of each capacitive element 128 is as shown in equation (6) above.

[0116] Then, the image signal OS is output during the period from time t8 to time t9. Figure 13 is a detailed timing chart of the period from time t8 to time t9 in Figure 12.

[0117] As shown in Figure 13, during the period from time t8 to time t9, the CDS reset signal CDS_RST periodically alternates between low and high levels. Then, the n CDS enable signals CDS_EN[0] to CDS_EN[n-1] sequentially become high levels, and when the CDS reset signal CDS_RST is low level, the selection signals SEL[0] to SEL[N-1] sequentially become high levels one by one. When the selection signal SEL[i-1] is high level, the output voltage of the operational amplifier 133 of the i-th CDS circuit 130 is as shown in equation (8) or equation (9) above.

[0118] Then, during the period from time t8 to time t9, an image signal OS is output, which is a time series of voltages corresponding to the light received by each photodetector 111 due to the emission of light from the red LED 412R.

[0119] At time t8, after the pixel reset signal PIX_RST remains high for a predetermined time, the green LED 412G emits light, and the image signal OS, which is a time series of voltages corresponding to the light received by each photodetector 111, is output by the emission of the green LED 412G. The period during which the green LED 412G emits light partially overlaps with the period during which the image signal OS generated by the emission of the red LED 412R is output. Furthermore, after the emission of the green LED 412G ends, and after the pixel reset signal PIX_RST remains high for a predetermined time, the blue LED 412B emits light, and the image signal OS, which is a time series of voltages corresponding to the light received by each photodetector 111, is output by the emission of the blue LED 412B. The period during which the blue LED 412B emits light partially overlaps with the period during which the image signal OS generated by the emission of the green LED 412G is output. The timing of the operation from when the green LED 412G or blue LED 412B starts emitting light until the output of the image signal OS ends is the same as the timing of the operation from when the red LED 412R starts emitting light until the output of the image signal OS ends, so the explanation is omitted.

[0120] 1-9. Reduction of pixel signal offset variation At the falling edge of the read signal READ, which changes from a high level to a low level, the N switch elements 121 of the line memory 120 simultaneously change from a conductive state to a non-conductive state, thereby determining the pixel signals stored in the N capacitive elements 122. For example, if N > 1000, when the state of thousands of switch elements 121 changes simultaneously, the parasitic capacitance of each switch element 121 is charged and discharged by the current output from the buffer circuit 104, resulting in a large fluctuation in the analog power supply voltage AVDD. This fluctuation in the analog power supply voltage AVDD introduces noise into the pixel signal PIXO output from each pixel circuit 110, causing an offset corresponding to the noise in the pixel signal stored in each capacitive element 122. On the other hand, due to MOS thermal noise and 1 / f noise, the read signal READ falls in a wave-like manner, causing variations in the timing of the change of each switch element 121 from a conductive state to a non-conductive state. As a result, the amount of offset in the pixel signal stored in each capacitive element 122 varies for each line in which the image sensor module 41 reads the image of the medium being read. In contrast, the N pixel circuits 110 and the N line memories 120 all receive the same analog power supply voltage AVDD and read signal READ. Therefore, the offset amount of the N pixel signals stored in the N capacitive elements 122 on each line is approximately the same. Consequently, if the timing of the change of each switch element 121 from a conductive state to a non-conductive state varies from line to line, horizontal lines will appear in the read image. In particular, when the resolution is set to 300 dpi, 16 pixel signals are voltage-summed. However, if the exposure time Δt is reduced to, for example, 1 / 16 to read the image quickly, the pixel signal PIXO output from each pixel circuit 110 becomes 1 / 16, while the offset amount of the pixel signals stored in each capacitive element 122 remains unchanged. As a result, the offset amount becomes 16 times greater than that of the voltage-summed pixel signals, making the horizontal lines in the read image more pronounced.

[0121] Shortening the slew rate of the falling edge of the read signal READ reduces the variation in the timing of each switch element 121 changing from a conductive state to a non-conductive state. However, this increases the instantaneous current, which conversely increases the fluctuation amount of the analog power supply voltage AVDD. Therefore, even if the slew rate of the falling edge of the read signal READ is changed, it is difficult to reduce the variation in the offset amount of the pixel signal stored in each capacitive element 122. Furthermore, since the frequency components of the fluctuations in the analog power supply voltage AVDD are on the order of, for example, 100MHz to GHz, it is generally difficult to implement a circuit that eliminates such high-frequency fluctuations.

[0122] Therefore, in this embodiment, as a measure to reduce the variation in the offset amount of the pixel signals stored in each capacitive element 122, the buffer circuit 104 that outputs the read signal READ is supplied with a digital power supply voltage DVDD instead of an analog power supply voltage AVDD, as shown in Figure 6.

[0123] Figure 14 shows the circuit layout and some wiring patterns of the image reading chip 415 in the first embodiment. In Figure 14, a first power supply wiring 191, a second power supply wiring 192, and a signal wiring 193 are added compared to Figure 7. As shown in Figure 14, on the semiconductor substrate 100, the first power supply wiring 191 and the second power supply wiring 192 are connected to pads 80 corresponding to power supply terminals to which the power supply voltage VDD is supplied. The first power supply wiring 191 and the second power supply wiring 192 are different wirings and are separated in the vicinity of pads 80 to which the power supply voltage VDD is supplied. The first power supply wiring 191 is the wiring for the analog power supply voltage AVDD, and the second power supply wiring 192 is the wiring for the digital power supply voltage DVDD. Each pixel circuit 110 and each line memory 120 are connected to the first power supply wiring 191, and the analog power supply voltage AVDD is supplied from pads 80 via the first power supply wiring 191. The logic circuit 101 and the buffer circuit 104 are connected to a second power supply wire 192, and a digital power supply voltage DVDD is supplied from the pad 80 via the second power supply wire 192.

[0124] The logic circuit 101 is located in the center of the first region A1, and the buffer circuit 104 is located in a part of the rectangular region where the logic circuit 101 is located. Therefore, the distance between the buffer circuit 104 and each pixel circuit 110 is longer than the distance between the buffer circuit 104 and the logic circuit 101. Similarly, the distance between the buffer circuit 104 and each line memory 120 is longer than the distance between the buffer circuit 104 and the logic circuit 101. In other words, the N pixel circuits 110 and N line memories 120, which are supplied with the analog power supply voltage AVDD via the first power supply wiring 191, and the logic circuit 101 and buffer circuit 104, which are supplied with the digital power supply voltage DVDD via the second power supply wiring 192, are located far apart. The read signal READ output from the buffer circuit 104 propagates through the signal wiring 193 and is supplied in common to the N line memories 120.

[0125] With this arrangement, when the parasitic capacitance of each switch element 121 is charged and discharged by the read signal READ output from the buffer circuit 104, the digital power supply voltage DVDD first fluctuates, as shown by the dashed line in Figure 15. This fluctuation in the digital power supply voltage DVDD propagates along the second power supply wiring 192 to the pad 80, and then this fluctuation propagates from the pad 80 to the first power supply wiring 191, causing the analog power supply voltage AVDD to fluctuate. Then, the fluctuation in the analog power supply voltage AVDD propagates along the first power supply wiring 191 to each pixel circuit 110, causing noise to be introduced into the pixel signal PIXO. Thus, because there is a time lag between the fluctuation of the digital power supply voltage DVDD and the fluctuation of the analog power supply voltage AVDD, the analog power supply voltage AVDD is not fluctuating at the falling edge timing of the read signal READ, and no noise is introduced into the pixel signal PIXO. Therefore, the variation in the offset amount of the pixel signal stored in each capacitive element 122 for each line is reduced.

[0126] In Figure 14, the first power supply wiring 191 and the second power supply wiring 192 are separated near the pad 80 to which the power supply voltage VDD is supplied. However, the pad 80 to which the first power supply wiring 191 is connected and the pad 80 to which the second power supply wiring 192 is connected may be different from each other. That is, the image reading chip 415 may have two power supply terminals to which the analog power supply voltage AVDD and the digital power supply voltage DVDD are supplied, respectively.

[0127] 1-10. Effects As described above, in the image reading chip 415 of the first embodiment, the buffer circuit 104 is connected to the second power supply wiring 192. Therefore, the digital power supply voltage DVDD supplied to the second power supply wiring 192 fluctuates before and after the buffer circuit 104 drives the switch element 121 of each line memory 120 and the pixel signal stored in the capacitive element 122 is determined. This fluctuation in the digital power supply voltage DVDD propagates along the second power supply wiring 192 and reaches the first power supply wiring 191, causing the analog power supply voltage AVDD supplied to the first power supply wiring 191 to fluctuate. Since each pixel circuit 110 is connected to the first power supply wiring 191, the fluctuation in the analog power supply voltage AVDD introduces noise into the pixel signal PIXO output from each pixel circuit 110. However, there is a time lag between the fluctuation of the digital power supply voltage DVDD and the fluctuation of the analog power supply voltage AVDD.

[0128] In particular, each pixel circuit 110 and each line memory 120 are located in a first region A1 along the first long side 100a of the semiconductor substrate 100, while the pads 80 corresponding to power terminals, logic circuits 101, and buffer circuits 104 are located in a second region A2 along the second long side 100b of the semiconductor substrate 100. Furthermore, the distance between the buffer circuit 104 and each pixel circuit 110 is longer than the distance between the buffer circuit 104 and logic circuits 101, so the distances between each pixel circuit 110 and each line memory 120 and the pads 80 corresponding to power terminals, logic circuits 101, and buffer circuits 104 are large. As a result, the first power wiring 191 and the second power wiring 192 become longer, and the time difference between when the digital power supply voltage DVDD changes and when the analog power supply voltage AVDD changes becomes large.

[0129] Therefore, when the pixel signal stored in each capacitive element 122 is determined, the analog power supply voltage AVDD has not yet fluctuated, and noise has not yet entered the pixel signal. Consequently, the image reading chip 415 in the first embodiment reduces the variation in the offset amount of the pixel signal stored in each capacitive element 122.

[0130] Furthermore, the scanner unit 3 of the first embodiment is equipped with an image reading chip 415 that can reduce variations in the offset amount of each pixel signal caused by fluctuations in the power supply voltage, thereby reducing the risk of horizontal lines appearing in the read image.

[0131] 2. Second Embodiment In the following description of the second embodiment, the same reference numerals are used for components similar to those in the first embodiment, and descriptions similar to those in the first embodiment are omitted or simplified. The description will primarily focus on the differences from the first embodiment.

[0132] In addition to fluctuations in the analog power supply voltage AVDD, other factors that cause variations in the offset amount of the pixel signals stored in the capacitive elements 122 of each line memory 120 include the bias current I bias1 ,I bias2Thermal noise and 1 / f noise are possible causes. Thermal noise is noise generated by the thermal vibration of free electrons in the resistor, and its bandwidth is limited by the output capacitance. On the other hand, 1 / f noise is a phenomenon in which electrons are irregularly trapped in energy levels formed at the interface between the gate oxide film and SiO2 of the MOS, and 1 / f noise is inversely proportional to the square root of the gate capacitance. Based on these properties, in the second embodiment, the bias current I is set to the same value as in the first embodiment. bias1 ,I bias2 Further measures will be taken to reduce thermal noise and 1 / f noise.

[0133] Figure 16 shows the circuit configuration of the image reading chip 415 in the second embodiment. As shown in Figure 16, in the image reading chip 415 in the second embodiment, the bias current I bias1 ,I bias2 As a measure to reduce thermal noise, capacitive elements 165 and 166 are provided in the bias circuit 160.

[0134] Capacitive element 165 has one end connected to a bias current I bias1 It is connected to a wiring through which a current flows, and the other end is grounded. In addition, one end of the capacitive element 166 is connected to a wiring that carries a bias current I bias2 It is connected to the wiring through which the current flows, and the other end is grounded. Capacitive elements 165 and 166 are, for example, 1000pF. Capacitive elements 165 and 166 provide the bias current I bias1 ,I bias2 The thermal noise bandwidth is limited.

[0135] Furthermore, in the image reading chip 415 of the second embodiment, the bias current I bias1 ,I bias2As a measure to reduce the 1 / f noise, the gate widths of the NMOS transistors 202, 203, and 204 included in the bias current generation circuit 162 shown in Figure 11 are made larger than in the first embodiment. For example, the gate widths W2 of the NMOS transistors 202, 203, and 204 in the second embodiment are more than twice, for example four times, the gate widths W1 of the NMOS transistors 202, 203, and 204 in the first embodiment. By increasing the gate widths of the NMOS transistors 202, 203, and 204, the bias current I generated by the NMOS transistors 202, 203, and 204 is increased. bias1 ,I bias2 The 1 / f noise mixed in is reduced.

[0136] The other configurations of the image reading chip 415 in the second embodiment are the same as in the first embodiment, so their description will be omitted.

[0137] As described above, according to the scanner unit 3 of the second embodiment, the fluctuation of the analog power supply voltage AVDD at the falling edge of the read signal READ in the image reading chip 415 is reduced, and furthermore, the bias current I supplied to each pixel circuit 110 is reduced. bias1 and the bias current I supplied to each line memory 120 bias2 Thermal noise and 1 / f noise are reduced. Consequently, variations in the offset amount of the pixel signal stored in each capacitive element 122 are reduced.

[0138] 3. Third Embodiment In the following description of the third embodiment, components similar to those in the first or second embodiment will be denoted by the same reference numerals, descriptions similar to those in the first or second embodiment will be omitted or simplified, and the differences from the first and second embodiments will be described primarily.

[0139] Factors causing variations in the offset amount of the pixel signals stored in the capacitive elements 122 of each line memory 120 include fluctuations in the analog power supply voltage AVDD and bias current I bias1 ,I bias2In addition to thermal noise and 1 / f noise, noise can also be generated in synchronization with the clock signal CLK when the logic circuit 101 is operating. Specifically, noise generated in synchronization with the clock signal CLK is generated by the reference current I supplied to all pixel circuits 110 in common. ref1 And the pixel reset signal PIX_RST and the reference current I supplied to all line memories 120 in common. ref2 When each pixel signal PIXO, which is mixed in or contaminated with noise, is stored in each capacitive element 122, the offset amount of the pixel signal stored in each capacitive element 122 will vary. Therefore, in the third embodiment, compared to the first or second embodiment, the reference current I ref1 ,I ref2 Furthermore, measures are taken to reduce noise introduced into the pixel reset signal PIX_RST, as well as to reduce noise introduced into the pixel signal stored in each capacitive element 122.

[0140] Figure 17 shows the circuit layout and some wiring patterns of the image reading chip 415 in the third embodiment. In Figure 17, reference current wiring 194, shield wiring 195, 196, and signal wiring 197 are added compared to Figure 14.

[0141] Reference current wiring 194 is for reference current I ref1 This is the wiring through which current flows. The reference current I output from the current mirror circuit 163 of the bias circuit 160. ref1 The current propagates through the reference current wiring 194 and is supplied to N pixel circuits 110. Shield wirings 195 and 196 run parallel to the reference current wiring 194, and the reference current I ref1 It shields against other signals. Therefore, the reference current I ref1 This reduces noise introduced by interference with other signals. Although not shown in the diagram, the reference current I supplied to the N line memories 120 is also reduced. ref2 Shielded wiring is also provided running parallel to the reference current wiring through which the current flows.

[0142] The signal wiring 197 is a wiring through which the pixel reset signal PIX_RST is propagated, and includes a first signal wiring 197a, a second signal wiring 197b, a third signal wiring 197c, and a fourth signal wiring 197d. The first signal wiring 197a is located in a first region A1 of the semiconductor substrate 100 and is connected to N pixel circuits 110. The second signal wiring 197b is located in a second region A2 of the semiconductor substrate 100 and is connected to a logic circuit 101. The third signal wiring 197c is located in a third region A3 along the first short side 100c of the semiconductor substrate 100 and is connected to the first signal wiring 197a and the second signal wiring 197b. The fourth signal trace 197d is located in a fourth region A4 along the second short side 100d of the semiconductor substrate 100 and is connected to the first signal trace 197a and the second signal trace 197b. The pixel reset signal PIX_RST propagates from the second signal trace 197b through the third signal trace 197c and the fourth signal trace 197d to the first signal trace 197a and is supplied to the N pixel circuits 110. In this way, the pixel reset signal PIX_RST propagates by bypassing the edges of the semiconductor substrate 100 rather than the center, resulting in less interference with other signals. Therefore, noise introduced into the pixel reset signal PIX_RST due to interference with other signals is reduced.

[0143] Furthermore, as a measure to reduce noise mixed into the pixel signals stored in each capacitive element 122, the falling edge timing of the read signal READ is made so that it does not overlap in time with the edge of the clock signal CLK. That is, in the third embodiment, the buffer circuit 104 outputs a read signal READ which is a delayed read signal RD output from the logic circuit 101 in synchronization with the clock signal CLK. For example, the buffer circuit 104 is realized as a delay circuit in which an even number of inverter elements are connected in series.

[0144] Figure 18 is a timing chart of the clock signal CLK, read signal RD, read signal READ, and pixel signal PIXO. As shown in Figure 18, the rising and falling edges of the read signal RD are synchronized with the rising edge of the clock signal CLK. In contrast, the rising and falling edges of the read signal READ are delayed by about 1 / 4 of a period relative to the rising edge of the clock signal CLK. Therefore, as shown by the dashed line in Figure 18, even if fluctuations in the digital power supply voltage DVDD that occur at the edge of the clock signal CLK propagate to the analog power supply voltage AVDD and introduce noise into each pixel signal PIXO, the noise introduced into the pixel signal stored in each capacitive element 122 at the falling edge timing of the read signal READ can be reduced.

[0145] The other configurations of the image reading chip 415 in the third embodiment are the same as those in the first or second embodiment, so their description will be omitted.

[0146] As described above, according to the scanner unit 3 of the third embodiment, the fluctuation of the analog power supply voltage AVDD at the falling edge of the read signal READ is reduced in the image reading chip 415, and furthermore, the reference current I ref1 ,I ref2 Furthermore, noise introduced into the pixel reset signal PIX_RST is reduced, and noise introduced into the pixel signal stored in each capacitive element 122 is reduced. Consequently, the variation in the offset amount of the pixel signal stored in each capacitive element 122 is reduced.

[0147] The present invention is not limited to this embodiment, and various modifications can be implemented within the scope of the gist of the present invention.

[0148] For example, in the above embodiment, the maximum resolution for image reading by the scanner unit 3 is 4800 dpi, and the configurable resolutions are 4800 dpi, 2400 dpi, 1200 dpi, 600 dpi, or 300 dpi. However, the maximum resolution and configurable resolutions are not limited to these, and various resolutions can be set according to the configuration of the image reading chip 415. For example, the maximum resolution may be 1200 dpi, and the configurable resolutions may be 1200 dpi, 600 dpi, or 300 dpi. Furthermore, in the above embodiment, each image reading chip 415 is configured to output one pixel signal at a time from the line memory 120 when the resolution is set to the maximum resolution of 4800 dpi, and to output two, four, eight, or sixteen pixel signals at a time from the line memory 120 and add the voltages when the resolution is set to 2400 dpi, 1200 dpi, 600 dpi, or 300 dpi, but the configuration of each image reading chip 415 is not limited to this. For example, if the maximum resolution is set to 1200 dpi, the image reading chip 415 may be configured to output one pixel signal at a time from the line memory 120 when the resolution is set to 1200 dpi, and to output two or four pixel signals at a time from the line memory 120 and add the voltages when the resolution is set to 600 dpi or 300 dpi.

[0149] Although embodiments and modified examples have been described above, the present invention is not limited to these embodiments or modified examples, and can be implemented in various forms without departing from its essence. For example, the above embodiments and their respective modifications can be combined as appropriate.

[0150] The semiconductor device and image reading device of the present invention are suitable for scanners and image sensors for scanners, but can also be applied to devices and sensors that require high-speed image reading by analog signal processing.

[0151] The present invention includes configurations substantially identical to those described in the embodiments, for example, configurations with the same function, method, and results, or configurations with the same purpose and effect. Furthermore, the present invention includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. Furthermore, the present invention includes configurations that produce the same effects or achieve the same purpose as those described in the embodiments. Finally, the present invention includes configurations that add known technology to the configurations described in the embodiments.

[0152] The following can be derived from the embodiments and modifications described above.

[0153] One aspect of a semiconductor device is: First power wiring and A second power supply wiring, which is different from the first power supply wiring, The first power supply wiring is connected, and the pixel circuit converts incident light into an electrical signal, A memory circuit having a capacitive element for storing the pixel signal output from the pixel circuit and a switch element connected between the pixel circuit and the capacitive element, A buffer circuit that drives the aforementioned switch element, The second power supply wiring is connected to a logic circuit that controls the pixel circuit and the memory circuit, Equipped with, The buffer circuit is connected to the second power supply wiring.

[0154] In this semiconductor device, the buffer circuit is connected to the second power supply wiring. Therefore, the second power supply voltage supplied to the second power supply wiring fluctuates before and after the buffer circuit drives the switch element and the pixel signal stored in the capacitive element of the memory circuit is determined. This fluctuation in the second power supply voltage propagates through the second power supply wiring to the first power supply wiring, causing the first power supply voltage supplied to the first power supply wiring to fluctuate. Since the pixel circuit is connected to the first power supply wiring, the fluctuation in the first power supply voltage introduces noise into the pixel signal output from the pixel circuit. However, because there is a time lag between the fluctuation of the second power supply voltage and the fluctuation of the first power supply voltage, the first power supply voltage has not yet fluctuated when the pixel signal stored in the capacitive element is determined, and therefore the pixel signal is not mixed with noise. Consequently, this semiconductor device reduces the variation in the offset amount of the pixel signal stored in the capacitive element.

[0155] One embodiment of the semiconductor device is, A power terminal to which the first power wiring and the second power wiring are connected, A rectangular semiconductor substrate, Equipped with, The semiconductor substrate has a first long side, a second long side opposite to the first long side, a first short side, and a second short side opposite to the first short side. The pixel circuit and the memory circuit are arranged in a first region along the first long side of the semiconductor substrate. The power terminal, the logic circuit, and the buffer circuit may be arranged in a second region along the second long side of the semiconductor substrate.

[0156] In this semiconductor device, the pixel circuit and memory circuit are arranged in a first region along the first long side of the semiconductor substrate, while the power terminals, logic circuit and buffer circuit are arranged in a second region along the second long side of the semiconductor substrate. As a result, the distance between the pixel circuit and memory circuit and the power terminals, logic circuit and buffer circuit is large. Consequently, the first and second power supply wirings become longer, and the time difference between when the second power supply voltage changes and when the first power supply voltage changes becomes larger. Therefore, this semiconductor device reduces the variation in the offset amount of the pixel signal stored in the capacitive elements.

[0157] Another aspect of a semiconductor device is, Power terminals, A pixel circuit that converts incident light into an electrical signal, A memory circuit having a capacitive element for storing the pixel signal output from the pixel circuit and a switch element connected between the pixel circuit and the capacitive element, A buffer circuit that drives the aforementioned switch element, A logic circuit that controls the pixel circuit and the memory circuit, A rectangular semiconductor substrate, Equipped with, The semiconductor substrate has a first long side, a second long side opposite to the first long side, a first short side, and a second short side opposite to the first short side. The pixel circuit and the memory circuit are arranged in a first region along the first long side of the semiconductor substrate. The power terminal, the logic circuit, and the buffer circuit are arranged in a second region along the second long side of the semiconductor substrate.

[0158] In this semiconductor device, the pixel circuit and memory circuit are arranged in a first region along the first long side of the semiconductor substrate, while the power supply terminals, logic circuit and buffer circuit are arranged in a second region along the second long side of the semiconductor substrate. Therefore, the pixel circuit and memory circuit are far from the power supply terminals, logic circuit and buffer circuit. The second power supply voltage supplied to the buffer circuit fluctuates before and after the buffer circuit drives the switch element and the pixel signal stored in the capacitive element of the memory circuit is determined. This fluctuation in the second power supply voltage causes the first power supply voltage supplied to the pixel circuit to fluctuate, and this fluctuation in the first power supply voltage introduces noise into the pixel signal output from the pixel circuit. However, since the pixel circuit is far from the buffer circuit, there is a time lag between the fluctuation of the second power supply voltage and the fluctuation of the first power supply voltage. Therefore, when the pixel signal stored in the capacitive element is determined, the first power supply voltage has not yet fluctuated, and the pixel signal is not yet mixed with noise. Consequently, this semiconductor device reduces the variation in the offset amount of the pixel signal stored in the capacitive element.

[0159] In one embodiment of the semiconductor device, The distance between the buffer circuit and the pixel circuit may be longer than the distance between the buffer circuit and the logic circuit.

[0160] One embodiment of the semiconductor device is, A bias circuit that generates a reference current supplied to the aforementioned pixel circuit, A reference current wiring through which the aforementioned reference current flows, The shield wiring runs parallel to the aforementioned reference current wiring, It may be provided.

[0161] According to this semiconductor device, the shield wiring running parallel to the reference current wiring reduces noise that is mixed into the reference current supplied to the pixel circuit by interference from other signals, thereby reducing the variation in the offset amount of the pixel signal stored in the capacitive element.

[0162] In one embodiment of the semiconductor device, The aforementioned logic circuit operates in synchronization with the clock signal. The buffer circuit outputs a control signal that is a delayed version of the signal output from the logic circuit in synchronization with the clock signal. The switch element may be driven by the control signal.

[0163] This semiconductor device creates a time difference between the edge of the clock signal and the timing at which the pixel signal stored in the capacitive element is determined by the control signal that drives the switch element. This reduces noise that is mixed into the pixel signal stored in the capacitive element due to fluctuations in the power supply voltage that occur at the edge of the clock signal. Therefore, this semiconductor device reduces variations in the offset amount of the pixel signal stored in the capacitive element.

[0164] One embodiment of the semiconductor device is, A first signal wiring is provided in the first region and is connected to the pixel circuit, A second signal wiring is provided in the second region and is connected to the logic circuit, A third signal wiring is located in a third region along the first short side of the semiconductor substrate and is connected to the first signal wiring and the second signal wiring, A fourth signal wiring is located in a fourth region along the second short side of the semiconductor substrate and is connected to the first signal wiring and the second signal wiring, Equipped with, The logic circuit outputs a reset signal to initialize the pixel circuit, The reset signal may propagate from the second signal wiring through the third and fourth signal wiring to the first signal wiring and be supplied to the pixel circuit.

[0165] According to this semiconductor device, the reset signal supplied to the pixel circuit bypasses the edges of the semiconductor substrate rather than the center, resulting in less interference with other signals. Therefore, noise introduced into the reset signal due to interference with other signals is reduced. Consequently, this semiconductor device reduces variations in the offset amount of the pixel signal stored in the capacitive elements.

[0166] One embodiment of an image reading device is: One embodiment of the semiconductor device, Light source and It is equipped with.

[0167] This image reading device includes a semiconductor device capable of reducing variations in the offset amount of pixel signals caused by fluctuations in power supply voltage, thereby reducing the risk of horizontal lines appearing in the read image. [Explanation of symbols]

[0168] 1…Multifunction device, 2…Printer unit, 3…Scanner unit, 4…Hinge section, 11…Upper frame, 12…Image reading section, 13…Top cover, 16…Bottom case, 17…Top case, 31…Sensor unit, 32…Sensor carriage, 33…Guide axis, 34…Sensor movement mechanism, 41…Image sensor module, 63…Operation section, 65…Device housing, 66…Outlet, 100…Semiconductor substrate, 100a…First long side, 100b…Second long side, 100c…First short side, 100d…Second short side, 101…Logic circuit, 102… Scanning circuit, 103-1~103-n...block, 104...buffer circuit, 110...pixel circuit, 111...photodetector, 112...inverting amplifier, 113...capacitor, 114...switching element, 120...line memory, 121...switching element, 122...capacitor, 123...NMOS transistor, 124...constant current source, 125...switching element, 126...switching element, 127...capacitor, 128...capacitor, 129p...switching element, 129n...switching element, 130...CDS circuit, 131p...capacitor, 131n...capacitor, 132 p...switch element, 132n...switch element, 133...operational amplifier, 134...NMOS transistor, 135...constant current source, 136...switch element, 137...switch element, 138...logic circuit, 140...preamplifier, 150...output buffer, 160...bias circuit, 161...VREFH amplifier, 162...bias current generation circuit, 163...current mirror circuit, 164...current mirror circuit, 170...readout circuit, 180...pad, 191...first power supply wiring, 192...second power supply wiring, 193...signal wiring, 194...reference Current wiring, 195...Shield wiring, 196...Shield wiring, 197...Signal wiring, 201...Constant current source, 202, 203, 204...NMOS transistors, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217...PMOS transistors, 300...Control unit, 302...Analog front end, 411...Case, 412...Light source, 412R...Red LED, 412G...Green LED, 412B...Blue LED, 413...Lens, 414...Module board, 415...Image reading chip

Claims

1. First power wiring and A second power supply wiring, which is different from the first power supply wiring, The first power supply wiring is connected, and a pixel circuit that converts incident light into an electrical signal is connected, A memory circuit having a capacitive element for storing the pixel signal output from the pixel circuit and a switch element connected between the pixel circuit and the capacitive element, A buffer circuit that drives the aforementioned switch element, The second power supply wiring is connected to a logic circuit that controls the pixel circuit and the memory circuit, Equipped with, The buffer circuit is connected to the second power supply wiring, A power terminal to which the first power wiring and the second power wiring are connected, A rectangular semiconductor substrate, Equipped with, The semiconductor substrate has a first long side, a second long side opposite to the first long side, a first short side, and a second short side opposite to the first short side. The pixel circuit and the memory circuit are arranged in a first region along the first long side of the semiconductor substrate. A semiconductor device wherein the power terminal, the logic circuit, and the buffer circuit are arranged in a second region along the second long side of the semiconductor substrate.

2. Power terminals, A pixel circuit that converts incident light into an electrical signal, A memory circuit having a capacitive element for storing the pixel signal output from the pixel circuit and a switch element connected between the pixel circuit and the capacitive element, A buffer circuit that drives the aforementioned switch element, A logic circuit that controls the pixel circuit and the memory circuit, A rectangular semiconductor substrate, Equipped with, The semiconductor substrate has a first long side, a second long side opposite to the first long side, a first short side, and a second short side opposite to the first short side. The pixel circuit and the memory circuit are arranged in a first region along the first long side of the semiconductor substrate. A semiconductor device wherein the power terminal, the logic circuit, and the buffer circuit are arranged in a second region along the second long side of the semiconductor substrate.

3. In claim 1 or 2, A semiconductor device wherein the distance between the buffer circuit and the pixel circuit is longer than the distance between the buffer circuit and the logic circuit.

4. In claim 1 or 2, A bias circuit that generates a reference current supplied to the aforementioned pixel circuit, A reference current wiring through which the aforementioned reference current flows, The shield wiring runs parallel to the aforementioned reference current wiring, A semiconductor device equipped with the following features.

5. In claim 1 or 2, The aforementioned logic circuit operates in synchronization with the clock signal. The buffer circuit outputs a control signal that is a delayed version of the signal output from the logic circuit in synchronization with the clock signal. The switch element is a semiconductor device driven by the control signal.

6. In claim 1 or 2, A first signal wiring is provided in the first region and is connected to the pixel circuit, A second signal wiring is provided in the second region and is connected to the logic circuit, A third signal wiring is located in a third region along the first short side of the semiconductor substrate and is connected to the first signal wiring and the second signal wiring, A fourth signal wiring is located in a fourth region along the second short side of the semiconductor substrate and is connected to the first signal wiring and the second signal wiring, Equipped with, The logic circuit outputs a reset signal to initialize the pixel circuit, A semiconductor device in which the reset signal propagates from the second signal wiring through the third and fourth signal wiring to the first signal wiring and is supplied to the pixel circuit.

7. The semiconductor device according to claim 1, Light source and An image reading device equipped with [a specific feature / equipment].

Images