Nitride semiconductor equipment

The nitride semiconductor device with a dual well region structure addresses the issue of high threshold voltage and switching loss in vertical MOS transistors by reducing hole traps at the GaN/SiO2 interface, enhancing electrical characteristics.

JP7893038B2Active Publication Date: 2026-07-22FUJI ELECTRIC CO LTD
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Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
FUJI ELECTRIC CO LTD
Filing Date
2022-05-30
Publication Date
2026-07-22

AI Technical Summary

Technical Problem

The direct application of a MOS capacitor structure with high-concentration P-type GaN/oxide film to a vertical MOS transistor results in excessively high threshold voltage and increased switching loss, deteriorating the electrical characteristics due to hole traps at the GaN/SiO2 interface.

Method used

A nitride semiconductor device with a vertical MOSFET structure that includes a gallium nitride substrate, an N-type drift region, a P-type well region with a first and second well region, an N-type source region, a gate insulating film, and a gate electrode, where the second well region has a higher acceptor element concentration and is located between the gate insulating film and the source region.

Benefits of technology

This configuration reduces hole traps, stabilizes channel mobility, and allows for controlled threshold voltage, thereby suppressing the deterioration of electrical characteristics and switching loss in the vertical MOSFET.

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Patent Text Reader

Abstract

To provide a nitride semiconductor device capable of reducing a hole trap while preventing a vertical MOSFET from decreasing in electric characteristics.SOLUTION: A nitride semiconductor layer comprises a gallium nitride substrate and a vertical MOSFET provided on the gallium nitride substrate. The vertical MOSFET has an N type drift region provided on the gallium nitride substrate, a P type wall region provided in the drift region, an N type source region provided in the well region, a gate insulation film provided on a surface of the well region, and a gate electrode provided on a surface of the well region across the gate insulation film. The well region has a first well region and a second well region higher in acceptor element density than the first well region. The second well region is located between the first well region and the gate insulation film, and also in contact with the source region.SELECTED DRAWING: Figure 3
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