Semiconductor equipment

Abstract

To enable increase in warpage of a semiconductor chip to be suppressed while reducing on-resistance.SOLUTION: In a region where a pad arrangement region Re and an active region Rb overlap each other, pads 12a to 12e are arranged on a source electrode 113 functioning as a surface electrode via a separation insulating film, and as a result, a semiconductor device has two-layer wiring electrode structure in which two layers of wiring electrode material are stacked. In a region which does not overlap the pad arrangement region Re, of the active region Rb, the semiconductor device has one-layer wiring electrode structure in which the source electrode 113 functioning as the surface electrode is constituted of a one layer of the wiring electrode material.SELECTED DRAWING: Figure 2B

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device in which pads are provided on the surface of a chip. [Background technology]

[0002] Conventionally, there are semiconductor devices that incorporate semiconductor elements such as switching elements into a semiconductor chip (see, for example, Patent Document 1). In such semiconductor devices, the active region, which can be operated as a semiconductor element, is arranged over a wide area including the center of the semiconductor chip. Furthermore, a region of the semiconductor chip different from the active region, specifically a region adjacent to the active region along one side of the semiconductor chip, is designated as a pad arrangement region, and pads are arranged in this pad arrangement region. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2017-204570 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] However, in the semiconductor device described above, the active region and the pad placement region are treated as separate areas, meaning the pad placement region is an area where semiconductor elements cannot be operated. As a result, the proportion of the active region to the total area of ​​the semiconductor chip is reduced due to the presence of the pad placement region, and the on-resistance of the semiconductor elements cannot be reduced significantly.

[0005] Therefore, the inventors have found a structure that expands the active area and makes the area below the pads in the pad placement area an active area. With such a configuration, the ratio of the active area to the total area of ​​the semiconductor chip can be increased, making it possible to reduce the on-resistance of the semiconductor element.

[0006] In a semiconductor device with this structure, the semiconductor element is formed below the pad placement area. Therefore, the wiring electrode material that constitutes the pad is placed on top of the wiring electrode material that constitutes the electrodes connected to the semiconductor element. In other words, the second layer of upper wiring electrodes is stacked on top of the first layer of lower wiring electrodes that are connected to the semiconductor element. In the pad placement area, it is necessary to insulate the lower and upper wiring electrodes, so an insulating film is placed between them, and in the active area that does not overlap with the pad placement area, the lower and upper wiring electrodes are connected.

[0007] However, after diligent research by the inventors, it was discovered that stacking the wiring electrode materials resulted in excessive thickness, increasing the warping that occurs in the semiconductor chip at high temperatures.

[0008] In view of the above points, the present invention aims to provide a semiconductor device that can reduce on-resistance while suppressing an increase in the warping of the semiconductor chip. [Means for solving the problem]

[0009] To achieve the above objective, the invention described in claim 1 is a semiconductor device comprising a semiconductor chip (10), comprising: an active region (Ra) on which a semiconductor element is formed and which is connected to the semiconductor element on one side of the semiconductor chip and on which a surface electrode (113) made of a wiring electrode material is arranged; and a pad arrangement region (Re) which is provided overlapping the active region in the direction normal to one side of the semiconductor chip and on which pads (12a to 12e) made of a wiring electrode material are arranged. In the region where the pad arrangement region and the active region overlap, pads are arranged on the surface electrode via an insulating film (116), thereby forming a two-layer wiring electrode structure in which two layers of wiring electrode material are stacked. Outside the two-layer wiring electrode structure, a wiring layer (130) is provided which is electrically connected to a contact region (108) included in the semiconductor element, and the wiring layer is a one-layer electrode structure composed of one layer of the wiring electrode material.

[0010] In this way, by forming the wiring layer disposed outside the two-layer wiring structure into a single-layer electrode structure, the wiring layer can also be made thin, so that an increase in warpage at high temperatures can be suppressed.

[0011] In the invention according to claim 2, outside the active region, there is provided a wiring layer (130) electrically connected to a contact region (108) included in the semiconductor element, and the wiring layer has a single-layer electrode structure formed of a single-layer wiring electrode material.

[0012] In this way, by forming the wiring layer disposed outside the active region into a single-layer electrode structure, the wiring layer can also be made thin, so that an increase in warpage at high temperatures can be suppressed.

[0013] Note that the reference numerals with parentheses attached to each component etc. indicate an example of the correspondence relationship between the component etc. and the specific components etc. described in the embodiments described later.

Brief Description of the Drawings

[0014] [Figure 1] It is a cross-sectional view of a power module according to the first embodiment. [Figure 2A] It is a top layout view of a semiconductor chip provided in the power module shown in FIG. 1. [Figure 2B] It is a diagram showing a region having a two-layer wiring electrode structure in the semiconductor chip by hatching. [Figure 3] It is a cross-sectional view taken along line III-III in FIG. 2A when a vertical MOSFET is formed in the semiconductor chip. [Figure 4] It is a cross-sectional view taken along line IV-IV in FIG. 2A when a vertical MOSFET is formed in the semiconductor chip. [Figure 5] It is a cross-sectional view of a semiconductor chip used as a comparative example, which corresponds to the cross-section taken along line III-III in FIG. 2A. [Figure 6]This is a cross-sectional view of a semiconductor chip used as a comparative example, and corresponds to the IV-IV section in Figure 2A. [Figure 7] This figure shows the simulation results for the on-resistance of the semiconductor chip of the first embodiment and the comparative example. [Figure 8] This is a flowchart illustrating the manufacturing method of a semiconductor device. [Figure 9] This figure shows, with hatching, the region in the semiconductor chip according to the second embodiment that has a two-layer wiring electrode structure. [Figure 10] This is a cross-sectional view of a semiconductor chip according to the second embodiment, and corresponds to the III-III cross-section in Figure 2A. [Figure 11] This is a top view layout diagram of a semiconductor chip according to the fourth embodiment. [Figure 12] This is a top view layout diagram of a semiconductor chip according to the fifth embodiment. [Modes for carrying out the invention]

[0015] The embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0016] (First Embodiment) The first embodiment will now be described. First, referring to Figure 1, an example will be given of the semiconductor device according to this embodiment being applied to a power module.

[0017] The power module shown in Figure 1 incorporates a semiconductor chip 10 corresponding to the semiconductor device of this embodiment, and is used, for example, as a switching device for motor driving. Specifically, the power module includes the semiconductor chip 10, a heat sink 20, a heat sink 30, etc. The semiconductor chip 10, the heat sink 20, and the heat sink 30 are joined together by a bonding material 50 including first to third bonding materials 50a to 50c. These components are then sealed with a molding resin 60.

[0018] Specifically, the semiconductor chip 10 has a bottom surface on one side located below the plane of the paper, and a top surface on the opposite side located above the plane of the paper. The bottom surface of the semiconductor chip 10 and the top surface of the heat sink 20 are joined by a first bonding material 50a. The heat sink 20 is composed of a laminate in which a metal layer 21, an insulating layer 22, and a metal layer 23 are stacked in order, and the metal layer 23 side is joined to the bottom surface of the semiconductor chip 10 via the first bonding material 50a. In addition, the top surface of the semiconductor chip 10 and the heat sink 30 are joined by a second bonding material 50b and a third bonding material 50c. The heat sink 30 is composed of a laminate in which a metal layer 31, an insulating layer 32, and a metal layer 33 are stacked in order, and the metal layer 33 is divided into multiple connection parts 33a and 33b. The divided connection parts 33a and 33b sides are joined to the top surface of the semiconductor chip 10 via the second bonding material 50b and the third bonding material 50c.

[0019] As will be described later, connection portion 33a is connected to the source electrode 113, which corresponds to the surface electrode of the active region Rb of the semiconductor chip 10 shown in Figure 2A, and connection portion 33b is connected to each pad 12a to 12e of the pad arrangement region Re of the semiconductor chip 10. In Figure 1, only one connection portion 33b is shown, but there are as many connection portions as there are pads 12a to 12e. In addition, connection portion 33a has a lead-out portion (not shown), and by pulling out the lead-out portion from the molded resin 60 it can be electrically connected to the outside. Similarly, each connection portion 33b also has a lead-out portion (not shown), and by pulling out the lead-out portion from the molded resin 60 it can be electrically connected to the outside. The metal layer 23 also has a lead-out portion (not shown), and by pulling out the lead-out portion from the molded resin 60 it can be electrically connected to the outside.

[0020] In this embodiment, the bonding material 50, including the first to third bonding materials 50a to 50c, is composed of a bonding metal such as lead-free solder, which is a conductive material, or a conductive adhesive. The bonding material 50 then connects the semiconductor chip 10, the heat sink 20, and the heat sink 30 both physically and electrically.

[0021] With this configuration, the upper surface of the semiconductor chip 10 is electrically connected to the outside and dissipates heat via the second bonding material 50b, the third bonding material 50c, and the heat sink 30. On the lower surface of the semiconductor chip 10, the first bonding material 50a is electrically connected to the outside and dissipates heat via the heat sink 20.

[0022] The semiconductor chip 10 is a semiconductor device in which semiconductor elements are formed on a semiconductor substrate such as silicon carbide (SiC), and is, for example, in the shape of a rectangular thin plate. The semiconductor chip 10 may be made of a material other than SiC. However, in the case of SiC, since high-voltage semiconductor elements are used, the semiconductor chip 10 may become hotter than when made of other materials, and the effect of warping may become greater. For this reason, it is preferable to apply this disclosure when the semiconductor chip 10 is made of SiC.

[0023] Examples of semiconductor elements formed on the semiconductor chip 10 include vertical MOSFETs and vertical IGBTs (insulated-gate bipolar transistors). In this embodiment, although the detailed structure will be described later, a vertical MOSFET is formed on the semiconductor chip 10.

[0024] A connection portion 33a is bonded to a part of the upper surface of the semiconductor chip 10, and multiple connection portions 33b are connected to the part of the semiconductor chip 10 that is outside the portion connected to the connection portion 33a. The surface electrode provided in the active region Rb of the semiconductor chip 10, i.e., the source electrode 113 in the vertical MOSFET, is connected to the connection portion 33a. In addition, each pad 12a to 12e provided in the pad placement region Re of the semiconductor chip 10 is connected to the connection portion 33b. In Figure 1, only one connection portion 33b is shown, but there are as many connection portions 33b as there are pads 12a to 12e. On the other hand, a back electrode, i.e., the drain electrode 114 in the case of a vertical MOSFET, is formed on the back surface of the semiconductor chip 10, and the entire surface of the back electrode is connected to the metal layer 23 of the heat sink 20.

[0025] The heat sink 20 achieves high heat dissipation by insulating the metal layers 21 and 23, which are positioned on both sides of the insulating layer 22, with an insulating layer 22, while constructing the metal layers 21 and 23 from metals with high thermal conductivity, such as copper. Because the metal layers 21 and 23 are insulated from each other, the metal layer 21 side is exposed from the molded resin 60 to create a heat dissipation surface that facilitates heat dissipation, while the metal layer 23 is insulated from the outside.

[0026] The heat sink 30 achieves high heat dissipation by insulating the metal layers 31 and 33, which are arranged on both sides of the insulating layer 32, with an insulating layer 32, and by constructing the metal layers 31 and 33 from metals with high thermal conductivity, such as copper. Because the metal layers 31 and 33 are insulated from each other, the metal layer 31 side is exposed from the molded resin 60 to create a heat dissipation surface that facilitates heat dissipation, while the metal layer 33 is insulated from the outside. In addition, the metal layer 33 is divided into multiple parts to form connection parts 33a and 33b. Conventionally, the connection part 33b is made up of bonding wire, but by making this part also from a part of the metal layer 33 included in the heat sink 30, high heat dissipation is achieved.

[0027] The molded resin 60 encloses the semiconductor chip 10, heat sink 20, heat sink 30, etc. One side of the heat sink 20 and heat sink 30, and one end of the lead-out portion of the metal layer 23 and metal layer 33 (not shown) are exposed from the molded resin 60. Each of the exposed lead-out portions is electrically connectable to the outside.

[0028] Next, the detailed structure of the semiconductor chip 10 in the semiconductor device configured in this way will be described.

[0029] As shown in Figures 2A and 2B, the semiconductor chip 10 is constructed as a rectangular plate with a square top surface. The semiconductor chip 10 is provided with an internal region Ra, an active region Rb, a connecting region Rc, an outer peripheral region Rd, and a pad placement region Re.

[0030] The internal region Ra is the area of ​​the semiconductor chip 10 that includes the central part, and is the portion where the source electrode 113, which corresponds to the surface electrode described later, is exposed. This portion is referred to as the source pad 11.

[0031] The active region Rb is the region of the semiconductor chip 10 in which semiconductor elements can be operated. In this embodiment, a vertical MOSFET is formed as a semiconductor element in the active region Rb. The active region Rb is formed in a position that surrounds the internal region Ra and is located a predetermined distance inward from the outer edge of the semiconductor chip 10, and in this embodiment it is a rectangular region.

[0032] The connecting region Rc is a region provided between the active region Rb and the outer peripheral region Rd, and is, for example, in the shape of a rectangular frame, and is equipped with a gate wiring layer 120 that constitutes the gate liner, which will be described later.

[0033] The outer peripheral region Rd is positioned around the entire outer edge of the semiconductor chip 10, surrounding the active region Rb and the connecting region Rc, and is a region equipped with an outer peripheral voltage withstand structure, etc. In this embodiment, it has a rectangular frame shape.

[0034] The pad placement area Re is the area where the various pads 12a to 12e are placed. The pad placement area Re is a part of the active area Rb, in this case it is the area along one side of the rectangular active area Rb, and in Figure 2A it is the area along the side on the lower side of the paper. Furthermore, the pad placement area Re is formed so as to overlap with the active area Rb when viewed from above, with the semiconductor chip 10 viewed from the normal direction.

[0035] In this embodiment, the area represented by the dashed-dot line in the figure is the connecting region Rc, with the area inside the connecting region Rc being the active region Rb and the area outside being the outer peripheral region Rd. Furthermore, the area enclosed by the single-dash line in the figure is the pad placement region Re.

[0036] Furthermore, a temperature-sensing element region 13 is provided within the pad arrangement region Re, which overlaps with the active region Rb of the semiconductor chip 10, and a temperature-sensing element is formed therein, so that the temperature rise caused by the semiconductor element can be determined based on the temperature detection by the temperature-sensing element.

[0037] The pad placement area Re is provided with multiple pads 12a to 12e. In this embodiment, the pad placement area Re is provided with a cathode pad 12a, an anode pad 12b, a gate pad 12c, a first sense pad 12d, and a second sense pad 12e, from left to right on the page. These are electrically connected to the various parts of the vertical MOSFET provided in the active area Rb and the various parts of the temperature sensing element provided in the temperature sensing element area 13. Each of these pads 12a to 12e is connected to the connection part 33b, enabling electrical connection to the outside via the lead-out part provided in the connection part 33b.

[0038] Furthermore, the semiconductor chip 10 has the cross-sectional configuration shown in Figures 3 and 4, and a vertical MOSFET is formed in the active region Rb.

[0039] The semiconductor chip 10 is made of n, which is composed of semiconductor materials such as Si or SiC. + A type substrate 101 is used, n +On the main surface of the n-type substrate 101, an n- + type low-concentration layer 102 having a lower impurity concentration than the n-type substrate 101 is epitaxially grown. -

[0040] 〔Configuration of Active Region Rb〕 As shown in FIGS. 3 and 4, in the active region Rb, in the n- - type low-concentration layer 102, JFET portions 102a arranged in a stripe shape with one direction as the longitudinal direction are formed at positions away from the n-type substrate 101. Including the JFET portions 102a, the n- + type low-concentration layer 102 may have the same impurity concentration, but here, by making the impurity concentration of the JFET portions 102a higher than that of the other portions of the n- - type low-concentration layer 102, a lower on-resistance can be achieved. -

[0041] A p-type first deep layer 103 is formed between the JFET portions 102a, and the first deep layer 103 is also arranged in a stripe shape with one direction as the longitudinal direction. These JFET portions 102a and the first deep layer 103 are configured to have the same thickness.

[0042] Also, on the JFET portions 102a and the first deep layer 103, a current diffusion layer 104 formed wide with a direction intersecting the longitudinal direction thereof as the longitudinal direction and a second deep layer 105 formed narrower than the current diffusion layer 104 are alternately and repeatedly arranged. And the second deep layer 105 is connected to the first deep layer 103. Further, on the current diffusion layer 104 and the second deep layer 105, a p-type base region 106 is formed, and on the p-type base region 106, an n- + type source region 107 and a p- + type contact region 108 are formed. The n- + type source region 107 is formed on a portion of the p-type base region 106 corresponding to the current diffusion layer 104, and the p- + type contact region 108 is formed on a portion of the p-type base region 106 corresponding to the second deep layer 105.

[0043] p-type base region 106 and n + A gate trench 109 is formed that penetrates the type source region 107 and reaches the current diffusion layer 104. The p-type base region 106 and n-type base region described above are in contact with the side surface of this gate trench 109. + A type source region 107 is positioned. The gate trenches 109 are formed in a linear layout where the width direction is in the left-right direction of the paper in Figure 3, the longitudinal direction is in the direction of the paper normal, and the depth direction is in the up-down direction of the paper. Although only two are shown in Figure 3, multiple gate trenches 109 are arranged at equal intervals in the left-right direction of the paper, and each is positioned between the second deep layers 105, forming a striped pattern.

[0044] Furthermore, the portion of the p-type base region 106 located on the side of the gate trench 109 is n during operation of the vertical MOSFET. + This is a channel region connecting the type source region 107 and the current diffusion layer 104. A gate insulating film 110 is formed on the inner wall surface of the gate trench 109, which includes this channel region. A gate electrode 111 made of doped poly-Si is formed on the surface of the gate insulating film 110, and these gate insulating film 110 and gate electrode 111 are embedded in the gate trench 109. This constitutes a trench gate structure.

[0045] As shown in Figure 4, the trench gate structure extends along the left-right direction of the paper in Figure 2, and as shown in Figure 3, multiple trench gate structures are arranged in the up-down direction of the paper in Figure 2. Although not shown, the trench gate structure is formed to extend beyond the active region Rb in the left-right direction of the paper in Figure 2. Also, on the side of the gate trench 109, n + A type source region 107 will be formed, n +The type source region 107 is formed in the active region Rb and not outside of it. Therefore, the channel region is formed only within the active region Rb.

[0046] n + Type source area 107 and p + An interlayer insulating film 112 is formed on the surface of the type contact region 108 and the trench gate structure. In the active region Rb, a source electrode 113, which corresponds to a surface electrode, is formed on the interlayer insulating film 112. The source electrode 113 is formed by patterning the lower wiring electrode, which is made of the first layer wiring electrode material, and the upper wiring electrode, which is made of the second layer wiring electrode material, has been removed, resulting in a single-layer wiring structure.

[0047] Among the interlayer insulating film 112, n + Type source area 107 and p + A contact hole 112a is formed at a position corresponding to the type contact region 108. As a result, as shown in Figure 3, the source electrode 113 passes through the contact hole 112a. + Type source area 107 and p + It is electrically in contact with the type contact area 108.

[0048] Also, n + On the back side of the mold substrate 101, that is, on the side opposite to the side where the source electrode 113 is formed, n + A drain electrode 114, corresponding to the back electrode electrically connected to the substrate 101, is formed. This structure constitutes a vertical MOSFET with an n-channel inverted trench gate structure, and the active region Rb is formed by arranging multiple vertical MOSFETs in cells. As shown in Figure 3, the surface of the semiconductor chip 10 is covered with a passivation film 115, and the portion of the passivation film 115 corresponding to the source electrode 113 is removed and opened. The portion of the passivation film 115 that is opened in the portion corresponding to the source electrode 113 is the internal region Ra, and the exposed portion of the source electrode 113 becomes the source pad 11.

[0049] Furthermore, the portion of the active region Rb that overlaps with the pad placement region Re has a configuration similar to that of the portion of the active region Rb that does not overlap with the pad placement region Re, as shown in Figure 4. However, in the portion of the active region Rb that overlaps with the pad placement region Re, a separation insulating film 116 is placed on the surface of the source electrode 113, and pads 12a to 12e are formed on this separation insulating film 116. Figure 4 shows a cross-section of the portion where the gate pad 12c is placed, but the other pads 12a, 12b, 12d, and 12e are also formed on the source electrode 113 via the separation insulating film 116. Pads 12a to 12e are formed by patterning the upper wiring electrode, which is the second layer of wiring electrodes. Therefore, as shown in Figure 2B, in the portion of the active region Rb that overlaps with the pad placement region Re, there is a two-layer wiring electrode structure in which the source electrode 113 and pads 12a to 12e are stacked.

[0050] Furthermore, the portions of the passivation film 115 corresponding to each of the pads 12a to 12e located in the pad placement region Re are also removed and opened up. As a result, the connection portion 33b can be connected to each of the pads 12a to 12e.

[0051] Furthermore, in the temperature-sensing element region 13, which is superimposed on the active region Rb, a temperature-sensing element, such as a temperature-sensing diode, is formed. The temperature-sensing diode is constructed, for example, by ion implanting p-type and n-type impurities into polysilicon to form multiple stages of PN diodes. The cathode of the temperature-sensing diode is connected to the cathode pad 12a, and the anode is connected to the anode pad 12b, so that an electrical signal corresponding to the temperature of the semiconductor chip 10 is output.

[0052] The other pads 12c to 12e located in the pad placement region Re are electrically connected to various parts of the vertical MOSFET. The gate pad 12c is electrically connected to the gate electrode 111 via the gate wiring layer 120, which will be described later and constitutes the gate liner. This allows the gate voltage to be applied to the gate electrode 111 through the gate pad 12c. The gate wiring layer 120 is formed, for example, in a rectangular frame shape surrounding the active region Rb within the junction region Rc, that is, near the outer edge of the semiconductor chip 10, and is routed to the vicinity of the gate pad 12c. The first sense pad 12d and the second sense pad 12e are connected to the source electrode 113 of the vertical MOSFET. Specifically, most of the vertical MOSFETs formed in multiple cells in the active region Rb are main cells that supply current to loads such as motors via source-drain, but some are sense cells for measuring the current flowing through the main cells. The first sense pad 12d is connected to the source electrode 113 on the sense cell side and outputs the current flowing between the source and drain of the vertical MOSFET on the sense cell side to the outside, thereby enabling measurement of the current flowing to the main cell. The second sense pad 12e is connected to the source electrode 113 on the main cell side and outputs the source potential to the outside through the second sense pad 12e.

[0053] [Configuration of the connecting region Rc] As shown in Figure 3, even in the connecting region Rc, the position extends to the vicinity of the outer peripheral region Rd, n - The configuration consists of a JFET section 102a and a first deep layer 103 formed on a low-concentration layer 102. However, the current diffusion layer 104 is omitted on top of these, and only the second deep layer 105 is formed. Furthermore, no trench gate structure is formed, and on top of the second deep layer 105, there is a p-type base region 106 and p + Only the type contact region 108 is formed.

[0054] Also, p-type base region 106 and p +A gate lead-out portion 111a, made of doped Poly-Si and drawn out from the gate electrode 111, is formed on a gate insulating film 110 formed on the type contact region 108. An interlayer insulating film 112 is formed to cover the gate lead-out portion 111a, and a gate wiring layer 120 is further formed on the interlayer insulating film 112. This gate wiring layer 120 constitutes a gate liner and is routed in a rectangular frame shape, for example, surrounding the active region Rb, and connected to the gate pad 12c. In addition, contact holes 112b are formed in the interlayer insulating film 112 at positions corresponding to the gate wiring layer 120, and the gate wiring layer 120 and the gate lead-out portion 111a are electrically connected through the contact holes 112b.

[0055] Furthermore, a hole-drawn layer 130 is formed on the interlayer insulating film 112 in the outer peripheral region Rd side of the gate wiring layer 120. Contact holes 112c are formed in the interlayer insulating film 112 at positions corresponding to the hole-drawn layer 130, and the hole-drawn layer 130 passes through the contact holes 112c to p + It is electrically connected to the type contact area 108.

[0056] The gate wiring layer 120 and hole extraction layer 130 formed in the connecting region Rc are also constructed by patterning the lower wiring electrode, which is the first layer of wiring electrodes, and the upper wiring electrode, which is the second layer of wiring electrodes, as shown in Figures 2B and 3. In this embodiment, the gate wiring layer 120 and hole extraction layer 130 have a two-layer wiring electrode structure consisting of a lower wiring electrode and an upper wiring electrode.

[0057] Furthermore, in order to electrically isolate pads 12a to 12e from the source electrode 113, the aforementioned isolation insulating film 116 is formed between the lower wiring electrode and the upper wiring electrode. For this reason, in the gate wiring layer 120 and the hole extraction layer 130, the isolation insulating film 116 formed between the lower wiring electrode and the upper wiring electrode is removed so that the lower wiring electrode and the upper wiring electrode are electrically connected. In this way, by making the gate wiring layer 120 and the hole extraction layer 130 a two-layer wiring electrode structure, it becomes possible to reduce wiring resistance.

[0058] In a cross-section different from that shown in Figures 3 and 4, the gate wiring layer 120 is connected to the gate pad 12c, and the hole extraction layer 130 is connected to a part that is at ground potential, for example, the second sense pad 12e.

[0059] [Configuration of the outer region Rd] In the outer region Rd, the p-type base region 106 and the second deep layer 105 are removed, forming a recess 140. Multiple p-type guard rings 150 are positioned at the bottom of this recess 140, surrounding the active region Rb. The presence of the p-type guard rings 150 allows equipotential lines to extend further outside the active region Rb and be terminated thereafter, mitigating electric field concentration and ensuring sufficient breakdown voltage in the outer region Rd.

[0060] Furthermore, the outer peripheral region Rd is entirely covered with a passivation film 115, protecting the surface. In this manner, a power module equipped with a semiconductor chip 10 corresponding to the semiconductor device of this embodiment is configured.

[0061] This power module operates, for example, by applying a voltage of about 10V to the drain electrode 114 via the metal layer 23, setting the source electrode 113 to ground potential via the connection part 33a, and applying a predetermined voltage to the gate electrode 111 via the connection part 33b. That is, when a gate voltage is applied to the gate electrode 111, a channel region is formed in the portion of the p-type base region 106 that is in contact with the trench gate structure. As a result, the vertical MOSFET turns on and performs the operation of flowing current between the source and drain.

[0062] Furthermore, even when a high voltage is applied to the drain electrode 114, the first deep layer 103 is fixed at the source potential through the second deep layer 105 and the p-type base region 106, thus suppressing the rise of equipotential lines to the trench gate structure. In addition, in the outer peripheral region Rd, an outer peripheral breakdown voltage structure such as a p-type guard ring 150 is provided, which guides the equipotential lines further to the outer peripheral side, mitigating electric field concentration. This makes it possible to realize a vertical MOSFET with high breakdown voltage.

[0063] When the vertical MOSFET is operated as described above, the semiconductor chip 10 becomes hot. If the thickness of each part of the semiconductor chip 10, which is composed of wiring electrodes, is thick, it will increase warping at high temperatures. However, in this embodiment, the thickness of the source pad 11, that is, the source electrode 113, which is a pad formed by opening the passivation film 115 over the largest area, is made thin. Therefore, it is possible to suppress the increase in warping at high temperatures.

[0064] Specifically, the source electrode 113, gate wiring layer 120, hole extraction layer 130, and pads 12a to 12e described above are constructed by patterning the lower wiring electrode, which is the first layer of wiring electrodes, and the upper wiring electrode, which is the second layer of wiring electrodes. In this embodiment, the gate wiring layer 120 and the hole extraction layer 130 have a two-layer wiring electrode structure consisting of a lower wiring electrode and an upper wiring electrode, while the source electrode 113 has a one-layer wiring electrode structure in which the upper wiring electrode is removed and the lower wiring electrode remains. The pads 12a to 12e also have a one-layer wiring electrode structure consisting of the upper wiring electrode.

[0065] Thus, on the surface side of the semiconductor chip 10, the source electrode 113, which has the largest surface area among the parts made of wiring electrode material, is a single-layer wiring structure. In other words, even if the positions where pads 12a to 12e are placed are arranged as a two-layer wiring electrode structure with each pad 12a to 12e stacked on top of the source electrode 113, the positions where only the source electrode 113 is placed are arranged as a single-layer wiring electrode structure without a stacked structure. This makes it possible to suppress the increase in warping of the semiconductor chip 10 at high temperatures.

[0066] Therefore, by forming the semiconductor element below the pad placement area Re, it is possible to reduce on-resistance by making a wide area of ​​the semiconductor chip 10 an active area Rb, while suppressing an increase in the warping of the semiconductor chip 10. Furthermore, by suppressing the increase in the warping of the semiconductor chip 10, it is possible to suppress the deterioration of semiconductor element characteristics caused by warping and to further reduce on-resistance. In addition, since heat can be dissipated through the connection part 33b, even if the active area Rb is laid out to overlap with the pad placement area Re, the heat generated in that area can also be dissipated through the connection part 33b.

[0067] The structure of this embodiment was actually fabricated, and the change in on-resistance was investigated for both the structure of this embodiment and a comparative example in which the source electrode 113 also has a two-layer wiring electrode structure. The fabricated structure of this embodiment is shown in Figures 3 and 4. The comparative example has the structure shown in Figures 5 and 6. That is, as shown in Figures 5 and 6, not only the pads 12a to 12e, but also the source electrode 113, the gate wiring layer 120, and the hole extraction layer 130 all have a two-layer wiring electrode structure.

[0068] Figure 7 shows the evaluation results of the on-resistance. Specifically, with 10V applied to the drain electrode 114 and the source electrode 113 at ground potential, the gate voltage was adjusted so that a predetermined current value flowed between the source and drain, and the on-resistance was measured in each case. Here, vertical MOSFETs with four different characteristics were fabricated for each case. As a result, in all cases of the vertical MOSFET characteristics, the on-resistance was reduced by about 5% when using the structure of this embodiment compared to when the source electrode 113 also had a two-layer wiring electrode structure. This evaluation result also shows that the on-resistance can be further reduced by using the structure of this embodiment. This is presumed to be due to the following reason. That is, when a two-layer wiring electrode structure is used, an oxide layer is formed on the surface of the lower wiring electrode, increasing the contact resistance between the lower and upper wiring electrodes and thus increasing the on-resistance. In contrast, in the structure of this embodiment, even if an oxide layer is formed on the source electrode 113 when the isolation insulating film 116 is deposited, as will be described later, the oxide layer can be removed when the upper wiring electrode formed on it is removed. Therefore, it is thought that the contact resistance of the source electrode 113 was reduced, and the on-resistance was decreased.

[0069] Next, we will explain how to manufacture the semiconductor chip 10, that is, the semiconductor device, which is configured in this way. However, for the semiconductor device manufacturing process, known methods may be used for the formation of semiconductor elements, the formation of the interlayer insulating film 112, and the formation of contact holes 112a to 112c, and any method may be used. For this reason, we will only explain the process after the formation of contact holes 112a to 112c.

[0070] First, as shown in the flowchart of Figure 8, after forming the semiconductor element, the interlayer insulating film 112 and the contact holes 112a to 112c in the interlayer insulating film 112 are formed. Then, the source electrode 113, gate wiring layer 120, gate lead-out portion 111a, and pads 12a to 12e are formed by performing the steps shown thereafter.

[0071] Specifically, a lower wiring electrode is deposited on the interlayer insulating film 112, including within the contact holes 112a to 112e. For example, a wiring electrode material whose main material is AlSi is deposited as the lower wiring electrode by sputtering. In this case, it is preferable to deposit a barrier metal layer as an underlayer, such as a Ti / TiN laminated structure, by sputtering, rather than directly forming the wiring electrode material on the semiconductor layer, before forming the lower wiring electrode. Next, a resist is applied to the lower wiring electrode, and then an exposure and development process is performed to form a resist mask. Then, the lower wiring electrode is wet-etched using the resist mask, and if an underlayer has been formed, the underlayer is dry-etched. After that, the resist mask is peeled off and cleaned, and then sintering is performed. This completes the patterning of the lower wiring electrode, forming the source electrode 113, and also forming the portion of the gate wiring layer 120 and the hole extraction layer 130 that is composed of the lower wiring electrode.

[0072] Next, the separation insulating film 116 is deposited. For example, a silicon oxide film or silicon nitride film such as USG (Undoped Silicate Glass) is deposited as the insulating material constituting the separation insulating film 116. By using a silicon oxide film or silicon nitride film, the lower wiring electrode and the upper wiring electrode can be accurately insulated. In addition, using a silicon nitride film has the effect of suppressing oxidation of the portion of the lower wiring electrode covered by the silicon nitride film. After applying a resist to the separation insulating film 116, an exposure and development process is performed to form a resist mask. Then, the separation insulating film 116 is patterned by dry etching using the resist mask. At this time, the separation insulating film 116 is left in the planned formation areas of pads 12a to 12e, and the separation insulating film 116 is not left on the surface of the other source electrode 113 or on the surface of the gate wiring layer 120 and the portion of the hole extraction layer 130 composed of the lower wiring electrode. After that, the resist mask is peeled off and cleaned to form the separation insulating film 116 with the desired pattern.

[0073] Furthermore, an upper wiring electrode is deposited so as to cover the portion composed of the lower wiring electrode, such as the source electrode 113, including the separation insulating film 116. For example, a wiring electrode material such as AlSi is deposited as the upper wiring electrode by sputtering. In this case, rather than directly forming the wiring electrode material, it is preferable to deposit a barrier metal layer as an underlayer, such as a Ti / TiN laminated structure, by sputtering before forming the upper wiring electrode. Next, a resist is applied to the upper wiring electrode, and then an exposure and development process is performed to form a resist mask. Then, the upper wiring electrode is wet-etched using the resist mask, and if an underlayer has been formed, the underlayer is dry-etched. After that, the resist mask is peeled off and cleaned, and then sintering is performed. As a result, the patterning of the upper wiring electrode is completed, and the portion of the gate wiring layer 120 and hole extraction layer 130 composed of the upper wiring electrode is formed, as well as the pads 12a to 12e are formed.

[0074] Regarding the patterning of the upper wiring electrodes, the removal of the lower wiring electrodes can be prevented by controlling the etching time when removing the upper wiring electrodes. However, if a barrier metal layer is formed as the underlying layer, it can be used as an etching stopper. Also, when forming the separation insulating film 116, an oxide layer may form on the surface of the source electrode 113, but this oxide layer can be removed simultaneously when removing the upper wiring electrodes. As a result, the contact resistance of the source electrode 113 can be reduced, and the on-resistance can be reduced.

[0075] After this, the semiconductor chip 10 can be manufactured through processes such as forming a passivation film 115 composed of PIQ (Polyimideisoindoloquinazolinedione), forming a drain electrode 114 as a back electrode, and dicing to form a chip.

[0076] (Second Embodiment) A second embodiment will now be described. This embodiment is the same as the first embodiment except that the region where the two-layer wiring electrode structure is used has been changed. Therefore, only the parts that differ from the first embodiment will be described.

[0077] As shown in Figure 9, in this embodiment, only the positions of pads 12a to 12e in the pad placement region Re are configured as a two-layer wiring electrode structure, while all other regions are configured as a single-layer wiring electrode structure. Specifically, as shown in Figure 10, in this embodiment, not only the source electrodes 113 in the active region Rb that do not overlap with the pad placement region Re, but also the gate wiring layer 120 and the hole extraction layer 130 are configured as a single-layer wiring electrode structure.

[0078] With this structure, the gate wiring layer 120 and the hole extraction layer 130 can also be made thinner, which makes it possible to suppress the increase in warping at high temperatures. Furthermore, as in the first embodiment, when the gate wiring layer 120 and the hole extraction layer 130 are made into a two-layer wiring electrode structure, it is necessary to remove the separation insulating film 116 formed between the lower wiring electrode and the upper wiring electrode. However, when the structure is made up of only the lower wiring electrode, it is not necessary to remove the separation insulating film 116 in parts of the gate wiring layer 120 other than the part connected to the gate pad 12c and the hole extraction layer 130 other than the part connected to the second sense pad 12e. For this reason, if the separation insulating film 116 is made of a silicon nitride film, oxidation of the gate wiring layer 120 and the hole extraction layer 130 can be further suppressed.

[0079] (Third embodiment) A third embodiment will now be described. This embodiment sets the proportion of the region that has a two-layer wiring electrode structure compared to the first and second embodiments, and is otherwise the same as the first and second embodiments, so only the parts that differ from the first and second embodiments will be described.

[0080] As described above, in the first embodiment, the region where the pads 12a to 12e are located and the gate wiring layer 120 and hole extraction layer 130 form a two-layer wiring electrode structure. In the second embodiment, the region where the pads 12a to 12e are located forms a two-layer wiring electrode structure. The area of ​​this two-layer wiring electrode structure is preferably 30% or less of the area of ​​the active region Rb. Specifically, the warping of the semiconductor chip 10 at high temperatures increases as the area of ​​the two-layer wiring electrode structure increases. Also, the area of ​​the active region Rb is the area of ​​the heat-generating portion. There is a correlation between the area of ​​the active region Rb and the area of ​​the two-layer wiring electrode structure, and when the ratio of the area of ​​the two-layer wiring electrode structure to the area of ​​the active region Rb is 30% or less, the increase in warping of the semiconductor chip 10 can be kept within a more preferable range.

[0081] Therefore, by setting the layout so that the ratio of the area of ​​the two-layer wiring electrode structure to the area of ​​the active region Rb is 30% or less, it becomes possible to further suppress the increase in warping of the semiconductor chip 10.

[0082] (Fourth Embodiment) The fourth embodiment will now be described. This embodiment defines the pad layout in the semiconductor chip 10 compared to the first to third embodiments, and is otherwise the same as the first to third embodiments. Therefore, only the parts that differ from the first to third embodiments will be described.

[0083] As shown in Figure 11, in this embodiment, the layout of the pads 12a to 12e and the internal region Ra constituting the source pad 11 formed on the semiconductor chip 10 is made symmetrical with respect to a line L. The line L is the center line of the semiconductor chip 10, passing through the center of the internal region Ra constituting the rectangular source pad 11. With respect to this line L, the source pad 11 itself is symmetrical, and the pads 12a to 12e are also symmetrical.

[0084] With this configuration, the warpage of the semiconductor chip 10 becomes uniform around the straight line L. This makes it easier to predict the warpage and facilitates design that takes warpage into account.

[0085] (Fifth embodiment) The fifth embodiment will now be described. This embodiment specifies the number of pads in the semiconductor chip 10 compared to the first to fourth embodiments, and is otherwise the same as the first to fourth embodiments. Therefore, only the parts that differ from the first to fourth embodiments will be described.

[0086] As shown in Figure 12, in this embodiment, in addition to the internal region Ra that constitutes the source pad 11, a gate pad 12c is provided, but the other pads 12a, 12b, 12d, and 12e are not provided, and the number of pads in the two-layer wiring electrode structure is only one.

[0087] The warpage of the semiconductor chip 10 increases in proportion to the area of ​​the region with the two-layer wiring electrode structure. For this reason, it is preferable to reduce the number of pads in the two-layer wiring electrode structure, and it is desirable to have five or fewer pads. Furthermore, although the number of pads in the two-layer wiring electrode structure is five in the first to fourth embodiments, it is even more preferable to have fewer pads. For this reason, as in this embodiment, by using fewer than five pads, especially just one, it is possible to further suppress the increase in warpage of the semiconductor chip 10.

[0088] In this embodiment, the gate pad 12c is positioned along the center of one side of the rectangular semiconductor chip 10, and the internal region Ra constituting the source pad 11 surrounding it is configured as a concave shape with an opening at the bottom of the paper. Also, similar to the fourth embodiment, the source pad 11 itself is symmetrical with respect to a line, and pads 12a to 12e are symmetrical with respect to a line L. However, this is merely one example of a layout for the semiconductor chip 10 when the number of pads in the two-layer wiring electrode structure is five or less, and other layouts are acceptable as long as the number of pads meets the conditions.

[0089] (Other embodiments) This disclosure is written in accordance with the embodiments described above, but is not limited to those embodiments and includes various modifications and variations within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms that include only one, more, or fewer of those elements, fall within the scope and concept of this disclosure.

[0090] For example, in each of the above embodiments, a vertical MOSFET is given as an example of a semiconductor element provided in the active region Rb, but other elements such as vertical IGBTs or diodes may be used, or a combination of multiple types of elements may be provided.

[0091] Furthermore, although an example of a semiconductor chip 10 constituting a semiconductor device has been given, other semiconductor devices with structures different from those shown in Figure 3A may also be used. That is, in addition to surface electrodes such as the source electrode 113 provided in the active region Rb, the device may have pads 12a to 12e placed in the pad placement region Re, with pads 12a to 12e having a two-layer wiring electrode structure and the surface electrodes having a single-layer wiring electrode structure.

[0092] Furthermore, although the above embodiments described a case in which the entire pad placement area Re overlaps with the active area Rb, it is also possible for the structure to be such that at least a part of the pad placement area Re overlaps with the active area Rb, rather than the entire area.

[0093] Furthermore, in each of the above embodiments, the single-layer wiring electrode structure and the double-layer wiring electrode structure refer to the number of layers of wiring electrode material such as AlSi. The number of layers referred to here does not include metal layers that are not wiring electrode material, such as barrier metal layers. [Explanation of symbols]

[0094] 10...Semiconductor chip, 11...Source pad, 12a~12e...Pads, 112...Interlayer insulating film, 113...Source electrode, 116...Separation insulating film, 120...Gate wiring layer, Ra...Internal region, Rb...Active region, Rc...Connecting region, Rd...Peripheral region, Re...Pad placement region

Claims

1. A semiconductor device comprising a semiconductor chip (10), A semiconductor element is formed in an active region (Ra) on one side of the semiconductor chip, where a surface electrode (113) made of wiring electrode material is arranged and connected to the semiconductor element. The semiconductor chip has a pad placement region (Re) which is provided overlapping with the active region in the direction normal to one surface of the semiconductor chip, and on which pads (12a to 12e) made of the wiring electrode material are arranged, In the region where the pad placement region and the active region overlap, the pad is placed on the surface electrode via a separating insulating film (116), thereby forming a two-layer wiring electrode structure in which two layers of the wiring electrode material are stacked. Outside the two-layer wiring electrode structure, there is a wiring layer (130) electrically connected to the contact region (108) included in the semiconductor element. A semiconductor device in which the wiring layer has a single-layer electrode structure composed of one layer of the wiring electrode material.

2. A semiconductor device comprising a semiconductor chip (10), A semiconductor element is formed in an active region (Ra) on one side of the semiconductor chip, where a surface electrode (113) made of wiring electrode material is arranged and connected to the semiconductor element. The semiconductor chip has a pad placement region (Re) which is provided overlapping with the active region in the direction normal to one surface of the semiconductor chip, and on which pads (12a to 12e) made of the wiring electrode material are arranged, In the region where the pad placement region and the active region overlap, the pad is placed on the surface electrode via a separating insulating film (116), thereby forming a two-layer wiring electrode structure in which two layers of the wiring electrode material are stacked. Outside the active region, there is a wiring layer (130) electrically connected to the contact region (108) included in the semiconductor element. A semiconductor device in which the wiring layer has a single-layer electrode structure composed of one layer of the wiring electrode material.

3. The semiconductor device according to claim 1 or 2, wherein the area of ​​the region having the two-layer wiring electrode structure is 30% or less of the area of ​​the active region.

4. The semiconductor device according to any one of claims 1 to 3, wherein the surface electrode and the pad are arranged symmetrically with respect to a straight line (L) which is the center line of the semiconductor chip passing through the center of the surface electrode.

5. The semiconductor device according to any one of claims 1 to 4, wherein the number of pads is five or less.

6. The semiconductor device according to any one of claims 1 to 5, wherein the isolation insulating film is composed of a silicon oxide film.

7. The semiconductor device according to any one of claims 1 to 5, wherein the isolation insulating film is composed of a silicon nitride film.

8. The semiconductor device according to any one of claims 1 to 7, wherein the wiring electrode material is made of AlSi.

9. The semiconductor device according to any one of claims 1 to 8, wherein the semiconductor chip is formed by forming the semiconductor element on a semiconductor substrate made of silicon carbide.

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