Silicon wafers and epitaxial silicon wafers

Abstract

To reduce the dislocation loop defect density that causes stacking faults in a silicon wafer.SOLUTION: The silicon wafer is 200 mm in diameter. The dopant is phosphorus. The resistivity is 0.5 mΩ cm or more and 1.2 mΩ cm or less. The carbon concentration is 3.5×1015atoms / cm3 or more and 2.8×1016atoms / cm3 or less.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to silicon wafers and epitaxial silicon wafers.

Background Art

[0002] For example, for an epitaxial silicon wafer for a power MOS transistor, it is required that the resistivity of the silicon wafer before forming the silicon epitaxial layer is very low. For this reason, an epitaxial silicon wafer is provided in which a silicon epitaxial layer is formed on the surface of a silicon wafer doped with phosphorus (P) at a high concentration so that the resistivity becomes 1.2 mΩ·cm or less.

[0003] In recent years, there has been a demand for providing an n-type silicon wafer having a very low resistivity of 0.9 mΩ·cm or less. However, when the resistivity of the silicon wafer is very low, there is a problem that stacking faults (SF) occur in the silicon epitaxial layer when an epitaxial growth process is performed, and there is a situation where a reduction in the SF density occurring in the silicon epitaxial layer is desired.

[0004] The present applicant has found a technique for suppressing the generation of SF in a silicon epitaxial layer by using a method of adjusting the residence time (thermal history) of a single crystal ingot at 570 °C ± 70 °C during single crystal growth (shortening the time of staying in the temperature range where SF nuclei are formed) as described in Patent Document 1. In addition, as described in Patent Document 2, it has been found that the generation of SF in a silicon epitaxial layer can be suppressed by using a method of performing high-temperature heat treatment (argon annealing) before the growth of the silicon epitaxial layer.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

[0006] As described in Patent Document 1, if a silicon wafer is cut from a crystalline region in which the time spent in the temperature range where SF nuclei are formed is shortened (a silicon wafer with fewer SF nuclei), the SF density in the epitaxial layer after silicon epitaxial layer growth can be reduced.

[0007] Furthermore, as described in Patent Document 2, by subjecting a silicon wafer cut from a crystalline region where the residence time in the temperature range where SF nuclei are formed is long (a silicon wafer with many SF nuclei) to argon annealing, the SF density in the epitaxial layer after silicon epitaxial layer growth can be reduced. While the technologies described in Patent Documents 1 and 2 are effective in suppressing SF generation in silicon epitaxial layers, users are demanding further reductions in SF density.

[0008] The present invention aims to provide a silicon wafer with a low density of dislocation loop defects that cause SF, and an epitaxial silicon wafer with low occurrence of SF in the silicon epitaxial layer. [Means for solving the problem]

[0009] The inventors of this invention have diligently researched the causes of SF (Spheroidal Fractional Dislocation) occurring in silicon epitaxial layers and have discovered that silicon wafers doped with a high concentration of phosphorus have two main types of dislocation loop-shaped defects (defects in which disordered crystal arrangements are linked in a loop shape), depending on the thermal history the crystals undergo during the growth process of the single-crystal ingot.

[0010] The following explains how we arrived at our understanding of dislocation loop-shaped defects. First, a 200 mm diameter silicon single crystal ingot was grown with a high concentration of phosphorus added as a dopant. Silicon wafers were then produced by cutting from crystal regions where the time spent in the temperature range where SF nuclei are formed (hereinafter referred to as the SF nucleation temperature range residence time) was long, and by cutting from crystal regions where the SF nucleation temperature range residence time was short.

[0011] Specifically, we manufactured silicon wafers with a long residence time in the SF nucleation temperature range, specifically silicon wafers with a resistivity of 0.75 mΩ·cm cut from the top side of a straight single-crystal ingot with a residence time of 350 minutes or more at 570°C ± 70°C, and silicon wafers with a short residence time in the SF nucleation temperature range, specifically silicon wafers with a resistivity of 0.7 mΩ·cm cut from the bottom side of a straight single-crystal ingot with a residence time of 50 minutes or less at 570°C ± 70°C. Each silicon wafer was cleaved in the thickness direction, and the cleaved cross-section was observed using a transmission electron microscope (TEM). The results are shown in Figure 1.

[0012] As a result, silicon wafers cut from the crystalline region (the upper crystalline region) with a long residence time in the SF nucleation temperature range showed large composite dislocation loop defects 2, where dislocation loops overlap, as shown in Figure 1(a), confirming a high density of large defects exceeding 60 nm in size. Figure 1(b) is a photograph of the composite dislocation loop defect 2 shown in Figure 1(a) taken from a different angle, showing that this composite dislocation loop defect 2 has a planar shape. On the other hand, silicon wafers cut from crystalline regions with short SF nucleation temperature zone residence times (bottom-side crystalline regions) showed small dislocation loop defects 4 as shown in Figure 2, confirming that the density of large composite dislocation loop defects exceeding 60 nm was low.

[0013] Furthermore, it was confirmed that SF (Surface Fractionation) occurs in the silicon epitaxial layer starting from large-sized composite dislocation loop defects. This suggests that the occurrence of SF in the silicon epitaxial layer differs depending on the presence or absence of composite dislocation loop defects. Therefore, the inventors investigated the mechanism of dislocation loop generation and reached the following conclusion.

[0014] The inventors of this invention made the following assumptions regarding the generation of dislocation loop defects. First, as a silicon single crystal ingot cools, interstitial phosphorus present between the lattice layers kicks out (repels) the lattice silicon present in the lattice positions, generating interstitial silicon. This excess interstitial silicon aggregates to form dislocation loops, and interstitial phosphorus segregates into these dislocation loops, generating dislocation loop defects.

[0015] Furthermore, to suppress the occurrence of dislocation loop defects, it is effective to suppress the aggregation of interstitial silicon. We considered that by intentionally adding impurity elements that can pair with interstitial silicon, we could suppress the aggregation of interstitial silicon, and thus conceived the idea of ​​incorporating carbon into the crystal during the single crystal growth stage. By doping (adding) carbon to a silicon melt to grow a silicon single crystal ingot and evaluating the defects formed in the carbon-doped silicon wafer, we obtained the finding that the defect density of large dislocation loops formed in the silicon wafer can be reduced, thus completing the present invention.

[0016] On the other hand, Patent Document 3 describes a method for increasing the density of bulk microdefects (BMDs) formed within a silicon wafer by adding carbon to the wafer, thereby improving the gettering ability of an epitaxial silicon wafer. Specifically, the invention described in Patent Document 3 is a technology that attempts to overcome the decrease in gettering ability caused by a decrease in oxygen concentration during the latter half of single-crystal ingot growth by adding carbon. It is a well-known fact that, not limited to Patent Document 3, the BMD density is increased by adding carbon to silicon crystals in order to provide epitaxial wafers with superior gettering ability.

[0017] [Patent Document 3] Special Publication No. 2003-505324

[0018] Generally, regions in a silicon wafer with a high concentration of phosphorus, achieved through methods such as phosphorus thermal diffusion treatment, phosphorus ion implantation, or the formation of a phosphorus-containing epitaxial layer, are known to function as gettering layers (also known as the phosphorus-getting method). In other words, the silicon wafer targeted by this invention, which is highly phosphorus-doped to have a resistivity of 1.2 mΩ·cm or less, possesses sufficient gettering properties simply by the presence of a high concentration of phosphorus. Therefore, there is no requirement to increase the BMD density in the epitaxial wafer targeted by this invention. Consequently, there is no motivation to increase the BMD density and thus enhance the gettering capability of a highly phosphorus-doped silicon wafer like the one targeted by this invention by adding carbon. Furthermore, Patent Document 3 does not address the issue of frequent SF (spheroidal fission) occurrence, which is a unique problem in silicon wafers doped with high concentrations of phosphorus so that the substrate resistivity is 1.2 mΩ·cm or less.

[0019] The silicon wafer of the present invention has a diameter of 200 mm, a dopant of phosphorus, a resistivity of 0.5 mΩ·cm to 1.2 mΩ·cm, and a carbon concentration of 3.5 × 10⁻¹⁶ 15 atoms / cm 3 The above 2.8 × 10 16 atoms / cm 3 The following applies:

[0020] The resistivity of the silicon wafer as defined in this invention is the value obtained by measuring the silicon wafer surface using the four-probe method. The carbon concentration of the silicon wafer as defined in this invention is a value obtained by thinning the silicon wafer by polishing and measuring the carbon concentration at the center of the silicon wafer thickness using secondary ion mass spectrometry (SIMS).

[0021] In the above silicon wafer, the oxygen concentration of the silicon wafer is 4 × 10 17 atoms / cm 3 The above 10 x 10 17 atoms / cm 3 The following is acceptable: The oxygen concentration of the silicon wafer as defined in this invention is the value obtained by thinning the silicon wafer by polishing and measuring the oxygen concentration at the center of the silicon wafer thickness using SIMS. Because the outermost surface of a silicon wafer contains many noise components, it is difficult to accurately measure the carbon concentration there. Therefore, accurate measurement of the carbon concentration is possible by measuring at a depth of 1 μm or more from the wafer surface, excluding the outermost surface. In this invention, to obtain a more accurate value, the concentration is defined as that at the center of the silicon wafer thickness.

[0022] In the silicon wafer described above, it is preferable that no COP (Critical Point Occlusion) is present in the silicon wafer. In the present invention, "absence of COP" means a silicon wafer on which no COP is detected by the observation and evaluation described below. That is, first, a silicon wafer cut from a single crystal silicon ingot grown by the CZ method is subjected to SC-1 cleaning (i.e., cleaning with a mixed solution of ammonia water, hydrogen peroxide water, and ultrapure water mixed at 1:1:15), and the surface of the silicon wafer after cleaning is observed and evaluated using a Surfscan SP-1 manufactured by KLA-Tencor as a surface defect inspection device to identify bright point defects (LPD: Light Point Defect) presumed to be surface pits. At that time, the observation mode is the Oblique mode (oblique incidence mode), and the presumption of surface pits is based on the detection size ratio of the Wide / Narrow channels. For the LPD thus identified, it is evaluated whether it is COP using an atomic force microscope (AFM: Atomic Force Microscope). By this observation and evaluation, a silicon wafer on which no COP is observed is defined as a "silicon wafer without COP".

[0023] The epitaxial silicon wafer of the present invention has a diameter of 200 mm, a dopant of phosphorus, a resistivity of 0.5 mΩ·cm or more and 1.2 mΩ·cm or less, and a carbon concentration of 3.5×10 15 atoms / cm 3 or more and 2.8×10 16 atoms / cm 3 or less, and a silicon epitaxial layer on the surface of the silicon wafer.

[0024] The resistivity of the silicon wafer of the epitaxial silicon wafer defined in the present invention is a value measured by the four-probe method on the back surface of the silicon wafer. When an oxide film is provided on the back surface of the epitaxial silicon wafer, it is a value measured by the four-probe method on the back surface of the silicon wafer after removing the back surface oxide film. The carbon concentration of the silicon wafer in the epitaxial silicon wafer defined in this invention is the value obtained by thinning the silicon wafer by polishing and measuring the carbon concentration at the center of the silicon wafer thickness using SIMS.

[0025] During the manufacturing of epitaxial silicon wafers, the silicon wafers undergo high-temperature heat treatment during epitaxial growth and high-temperature heat treatment before epitaxial growth, causing carbon to diffuse outward and reducing the carbon concentration on the surface layer of the silicon wafer. Therefore, to measure the carbon concentration of an epitaxial silicon wafer, it is necessary to measure at a depth where outward diffusion of carbon has not occurred. By measuring at a depth of 40 μm or more from the wafer surface in the direction of wafer thickness, accurate measurement of the carbon concentration is possible. In this invention, to obtain a more accurate value, the concentration is defined as the concentration at the center of the silicon wafer thickness.

[0026] The epitaxial silicon wafer of the present invention has a diameter of 200 mm, a dopant of phosphorus, a resistivity of 0.5 mΩ·cm to 1.2 mΩ·cm, and a carbon concentration of 3.5 × 10⁻¹⁶ 15 atoms / cm 3 The above 2.8 × 10 16 atoms / cm 3 The silicon wafer comprises the following, and a silicon epitaxial layer on the surface of the silicon wafer, wherein the silicon wafer has a low carbon concentration layer on the surface side in contact with the silicon epitaxial layer, the carbon concentration of the low carbon concentration layer is 0.9 times or less the carbon concentration at the center of the thickness of the silicon wafer, and the depth of the low carbon concentration layer is 5 μm or more and 15 μm or less from the boundary between the silicon wafer and the silicon epitaxial layer. The depth of the low-carbon concentration layer is a value based on the carbon concentration profile in the depth direction obtained by SIMS measurement, and represents the depth position (width) in the thickness direction of the silicon wafer from the boundary between the epitaxial layer and the silicon wafer.

[0027] In the above epitaxial silicon wafer, the carbon concentration of the epitaxial layer is 2.0 × 10⁻⁶ 15 atoms / cm 3 It is preferable that it be less than [a certain value]. The carbon concentration of the epitaxial layer of the epitaxial silicon wafer as defined in this invention is the value obtained by measuring the epitaxial layer using SIMS.

[0028] In the epitaxial silicon wafer described above, it is desirable that the resistivity of the silicon wafer be 0.9 mΩcm or less.

[0029] In the above epitaxial silicon wafer, the oxygen concentration of the silicon wafer is 4 × 10 17 atoms / cm 3 The above 10 x 10 17 atoms / cm 3 The following is preferable.

[0030] The oxygen concentration of the silicon wafer in the epitaxial silicon wafer defined in this invention is the value obtained by measuring the oxygen concentration at the center of the silicon wafer thickness using SIMS after thinning the silicon wafer by polishing. To measure the oxygen concentration of an epitaxial silicon wafer, it is necessary to measure at a depth where outward diffusion of oxygen is not occurring. Accurate measurement of the oxygen concentration is possible by measuring at a depth of approximately 150 μm or more from the wafer surface in the direction of wafer thickness. In this invention, to obtain a more accurate value, the concentration is defined as the concentration at the center of the silicon wafer thickness.

[0031] In the epitaxial silicon wafer described above, it is desirable that no COPs (Critical Occlusions) are present in the silicon wafer.

[0032] In the epitaxial silicon wafer described above, it is desirable that an oxide film be provided on the back surface of the silicon wafer.

[0033] In the epitaxial silicon wafer described above, it is desirable that there is no oxide film on the edges and the outer periphery of the back surface of the silicon wafer.

[0034] In the epitaxial silicon wafer described above, it is desirable that the LPD density of 0.09 μm size or larger observed on the surface of the silicon epitaxial layer be 100 particles / wafer or less.

[0035] In the epitaxial silicon wafer described above, it is desirable that the LPD density of 0.09 μm size or larger observed on the surface of the silicon epitaxial layer be 30 particles / wafer or less.

[0036] The silicon wafer of the present invention has a diameter of 200 mm, a dopant of phosphorus, a resistivity of 0.5 mΩ·cm to 1.2 mΩ·cm, and a carbon concentration of 3.5 × 10⁻¹⁶ 15 atoms / cm 3 The above 2.8 × 10 16 atoms / cm 3 A silicon wafer having a low carbon concentration layer on its surface, wherein the carbon concentration of the low carbon concentration layer is 0.9 times or less the carbon concentration at the center of the silicon wafer's thickness, and the depth of the low carbon concentration layer is 5 μm or more and 15 μm or less in the thickness direction of the silicon wafer from the surface.

[0037] In the above silicon wafer, the oxygen concentration of the silicon wafer is 4 × 10 17 atoms / cm 3 The above 10 x 10 17 atoms / cm 3 The following is preferable:

[0038] In the silicon wafer described above, it is preferable that no COP (Critical Point Occlusion) is present in the silicon wafer. [Brief explanation of the drawing]

[0039] [Figure 1]This is a photograph of a complex dislocation loop observed in a silicon wafer cut from a crystalline region with a long residence time in the SF nucleation temperature range. [Figure 2] This is a photograph of dislocation loops observed in a silicon wafer cut from a crystalline region with a short residence time in the SF nucleation temperature range. [Figure 3] This is a flowchart showing one embodiment of the method for manufacturing an epitaxial silicon wafer according to the present invention. [Figure 4] This is a cross-sectional view of one embodiment of an epitaxial silicon wafer according to the present invention. [Figure 5] This graph shows the evaluation results of dislocation loops in epitaxial silicon wafers for Example 1 and Comparative Example 1. [Figure 6] This graph shows the results of the investigation into the carbon concentration profiles of the epitaxial silicon wafers in Examples 4 and 5. [Figure 7] These are X-ray topographic images of the silicon wafer surface for Examples 6 and 7 and Comparative Examples 4 and 5. [Figure 8] This graph shows the relationship between LPD density and resistivity when epitaxial layers are formed on the silicon wafer surfaces of Examples 8 and 9 and Comparative Examples 6 and 7. [Modes for carrying out the invention]

[0040] Embodiments of the present invention will be described below with reference to the drawings. The silicon wafer according to the present invention is a silicon wafer with a diameter of 200 mm, doped with phosphorus (P) as a dopant for resistivity adjustment, so that the resistivity is between 0.5 mΩ·cm and 1.2 mΩ·cm, and the carbon concentration is 3.5 × 10⁻¹⁶ 15 atoms / cm 3 The above 2.8 × 10 16 atoms / cm 3 The silicon wafer is as follows: In this invention, a silicon wafer with a diameter of 200 mm refers to a silicon wafer with a diameter of 200 ± 0.5 mm, taking into account processing tolerances and other factors. Furthermore, the epitaxial silicon wafer according to the present invention is provided with a silicon epitaxial layer on the silicon wafer described above.

[0041] A preferred manufacturing flow for obtaining an epitaxial silicon wafer according to the present invention is shown in Figure 3. The manufacturing flow preferably includes a single crystal ingot manufacturing step S1, a backside oxide film formation step S2, an outer peripheral oxide film removal step S3, an argon annealing step S4, a pre-bake step S5, and an epitaxial layer formation step S6.

[0042] In single-crystal ingot manufacturing process S1, a 200 mm diameter single-crystal silicon ingot doped with phosphorus as an n-type dopant is manufactured using the CZ method (Czochralski method) with a single-crystal ingot pulling device (not shown) to satisfy the following conditions.

[0043] (Phosphorus concentration) The phosphorus concentration in the single crystal ingot is 6 × 10 19 atoms / cm 3 The above is 1.64 × 10 20 atoms / cm 3 By doping with red phosphorus as follows, a single crystal ingot with a resistivity of 0.5 mΩ·cm to 1.2 mΩ·cm can be obtained. Also, the phosphorus concentration is 8.3 × 10 19 atoms / cm 3 By following these steps, a single-crystal ingot with a resistivity of 0.9 mΩ·cm or less can be obtained. The phosphorus concentration of the silicon wafer is the value measured using secondary ion mass spectrometry (SIMS) at the center of the silicon wafer thickness. The phosphorus concentration can also be determined from the resistivity measured by the four-probe method using the formula or graph specified in SEMI MF723-0307. Furthermore, if phosphorus is doped into the silicon molten material after the silicon raw material has been dissolved, the phosphorus will evaporate during the dissolution process, making it impossible to obtain the desired resistivity. Therefore, it is preferable to dope the silicon molten material with red phosphorus after the silicon raw material has been dissolved.

[0044] (Carbon concentration) The carbon concentration in the single crystal ingot is 3.5 × 10⁻⁶ 15 atoms / cm 3 The above 2.8 × 10 16 atoms / cm 3 As described below, by adding carbon powder to a crucible along with the silicon raw material and dissolving them, a single crystal ingot having a predetermined carbon concentration can be grown. Carbon concentration 3.5 × 10 15 atoms / cm 3 By doing so, the size and density of dislocation loop defects formed in the silicon wafer can be reduced, and the SF density generated in the epitaxial layer after the epitaxial growth process can be reduced.

[0045] The higher the carbon concentration in the silicon wafer, the greater the effect of reducing the LPD density (SF density) generated in the epitaxial layer, but the carbon concentration of 2.8 × 10⁻⁶ 16 atoms / cm 3 If the carbon content exceeds a certain limit, even if argon annealing is performed before epitaxial growth, carbon in the silicon wafer may diffuse into the epitaxial layer. If carbon is present in the epitaxial layer, depending on the type of device processing, electrically active carbon-induced defects called killer defects may occur during the device heat treatment process. Therefore, the carbon concentration in the silicon wafer is set to 2.8 × 10⁻⁶ 16 atoms / cm 3By using the following low carbon concentration, carbon diffusion into the epitaxial layer can be suppressed. In addition, by performing argon annealing on the silicon wafer before epitaxial growth to form a low-carbon concentration layer on the surface, carbon diffusion into the epitaxial layer can be reliably prevented, and the carbon concentration throughout the entire epitaxial layer can be reduced to 2 × 10⁻⁶. 15 atoms / cm 3 It can be kept below the detection limit of carbon concentration measured by SIMS.

[0046] (Oxygen concentration) As described later, a high oxygen concentration in silicon wafers tends to worsen the device's breakdown voltage characteristics. Therefore, it is desirable to lower the oxygen concentration in the single-crystal ingot, aiming for an oxygen concentration of 4 × 10⁻⁶. 17 atoms / cm 3 The above 10 x 10 17 atoms / cm 3 It is desirable to keep it within the following range.

[0047] To grow single-crystal ingots with low oxygen concentrations, it is desirable to apply a magnetic field to the silicon melt. Applying a well-known horizontal magnetic field or cusp magnetic field is sufficient. By slowing down the rotation speed of the crucible containing the silicon melt and lowering the pressure inside the pulling device furnace, the oxygen concentration incorporated into the single crystal can be reduced to the desired concentration. Note that the oxygen concentration is 4 × 10 17 atoms / cm 3 Below this level, the strength of the silicon wafer is low, and there is a risk of slip dislocations occurring when subjected to high-temperature heat treatment, therefore the oxygen concentration should be 4 × 10⁻⁶. 17 atoms / cm 3 It is desirable to keep it as above.

[0048] After this, silicon wafers are cut from the single crystal ingots manufactured in the single crystal ingot manufacturing process S1, and subjected to predetermined processing (grinding, etching, polishing, etc.) to produce mirror-finish silicon wafers with excellent surface roughness and flatness.

[0049] In the back surface oxide film formation process S2, it is desirable to form an oxide film (hereinafter referred to as the back surface oxide film) on the back surface of the silicon wafer using a CVD apparatus within the following condition range. Raw material gas: Mixture of monosilane (SiH4) and oxygen (O2) Thickness of the oxide film on the back surface: 100 nm to 1500 nm Film forming temperature: 400℃ or higher and 450℃ or lower By providing such a backside oxide film, the autodoping phenomenon can be suppressed, and the resistance fluctuations of the epitaxial layer can be reduced.

[0050] In the backside oxide film formation process S2, it is difficult to form an oxide film only on the backside of the silicon wafer, and an oxide film inevitably forms on the edges (chamfered parts) of the silicon wafer after the backside oxide film formation process S2. If an epitaxial layer is formed on the surface of the oxide film, there is a risk of nodules (granular silicon) being generated in that area, so it is desirable to remove the oxide film formed on the edges of the silicon wafer and on the outer periphery of the backside of the wafer.

[0051] Therefore, in the peripheral oxide film removal step S3, the oxide film present on the edges (chamfered portion) and the peripheral back surface of the silicon wafer can be removed using various methods such as polishing and etching. Preferably, the width of the oxide film removed from the peripheral back surface of the wafer is less than 5 mm from the outer edge of the silicon wafer. By removing the edges of the silicon wafer and the outer periphery of the backside oxide film in this way, it is possible to prevent the generation of nodules during the growth of the silicon epitaxial layer and to prevent particle generation from the wafer edge.

[0052] In the argon annealing process S4, it is desirable to perform the heat treatment within the following condition range. Gas atmosphere: Argon gas Heat treatment temperature: 1150°C to 1250°C Heat treatment time: 30 minutes to 120 minutes For heat treatment, it is preferable to use a batch furnace (vertical heat treatment apparatus) that can heat-treat multiple silicon wafers at once.

[0053] Carbon doping suppresses the generation of large dislocation loop defects in silicon wafers, and small dislocation loop defects present in silicon wafers can be eliminated by argon annealing, thereby minimizing the generation of SF in the epitaxial layer.

[0054] Furthermore, by performing argon annealing on the silicon wafer before the epitaxial growth process, it is possible to prevent the diffusion of carbon from the silicon wafer to the silicon epitaxial layer during the epitaxial layer formation process S6. This point will be explained below. Figure 4(a) is a schematic diagram showing the low-carbon concentration layer formed on the surface of a silicon wafer by argon annealing. As shown in Figure 4(a), by subjecting the silicon wafer 11 to high-temperature argon annealing, the carbon in the surface layer of the silicon wafer 11 diffuses outward, and the carbon concentration in the surface layer decreases. As a result, a low-carbon concentration layer 12 is formed on the front and back sides of the silicon wafer 11, with a carbon concentration lower than that of the center C of the silicon wafer 11 where outward diffusion of carbon has not occurred.

[0055] Figure 4(b) is a schematic diagram showing the carbon concentration profile when an argon-annealed silicon wafer is subjected to epitaxial growth treatment. As shown in Figure 4(b), the carbon concentration after the epitaxial layer formation process S6 will show a concentration profile in which the carbon concentration in the surface layer of the silicon wafer is reduced. Here, if we define the region where the carbon concentration is 0.9 times or less of the carbon concentration in the center C of the thickness of the silicon wafer 11 where outward diffusion of carbon has not occurred as the low carbon concentration layer 12, then the depth D of the low carbon concentration layer 12 formed on the surface side of the silicon wafer 11 that is in contact with the silicon epitaxial layer 13 after the epitaxial growth process can be set to 5 μm to 15 μm in the thickness direction of the silicon wafer 11 from the boundary between the silicon wafer 11 and the silicon epitaxial layer 13. The formation of this low-carbon concentration layer 12 and the application of a low-carbon concentration silicon wafer reliably prevent the diffusion of carbon from the silicon wafer 11 to the silicon epitaxial layer 13 during the epitaxial layer formation process S6. The thickness of the low-carbon concentration layer 12 can be arbitrarily adjusted by adjusting the heat treatment temperature and time of the argon annealing.

[0056] In the pre-baking process S5 under a gas atmosphere containing hydrogen and hydrogen chloride, it is desirable to perform heat treatment on the silicon wafer within the following conditions range in an epitaxial apparatus (Applied Materials Corporation: Centura®). Atmosphere: Hydrogen gas, hydrogen chloride gas Hydrogen gas flow rate: 40 L / min Hydrogen chloride gas flow rate: 1 L / min Heat treatment temperature: 1050°C to 1250°C Heat treatment time: 30 seconds to 300 seconds

[0057] The amount of material removed from the surface layer of the silicon wafer by the pre-baking process S5 is preferably 100 nm or more and 300 nm, and more preferably 150 nm ± 10 nm.

[0058] In the epitaxial layer formation process S6, it is desirable to grow the epitaxial layer on the silicon wafer that has undergone the pre-baking process S5 under the following conditions. Dopant gas: Phosphine (PH3) gas Raw material source gas: Trichlorosilane (SiHCl3) gas Carrier gas: Hydrogen gas Growth temperature: 1050℃ or higher and 1150℃ or lower Epitaxial layer thickness: 1 μm to 10 μm Resistivity of the epitaxial layer: 0.01 Ω·cm to 10 Ω·cm Phosphorus concentration: 4.44 × 10 14 atoms / cm 3 The above 4.53 × 10 18 atoms / cm 3 below By performing the epitaxial layer formation process S6, an epitaxial silicon wafer is manufactured in which a silicon epitaxial layer is formed on the surface of the silicon wafer.

[0059] By implementing the above process flow, it is possible to provide silicon wafers that can reduce the generation of SF in the epitaxial layer, and epitaxial silicon wafers with a reduced SF density in the epitaxial layer. Specifically, the diameter is 200 mm, phosphorus is added so that the resistivity is between 0.5 mΩ·cm and 1.2 mΩ·cm, and the carbon concentration is 3.5 × 10⁻⁶ 15 atoms / cm 3 The above 2.8 × 10 16 atoms / cm 3 This invention provides a silicon wafer doped with a low concentration of carbon, as described below, and represents a novel silicon wafer that has not existed before.

[0060] Carbon doping reduces the defect density of large dislocation loops in the silicon wafer. This silicon wafer can effectively function as a bulk wafer for epitaxial growth, as it can reduce the occurrence of epitaxial defects (LPDs / SFs observed on the surface of the epitaxial layer). Furthermore, by setting a low carbon doping amount, the amount of carbon diffusion from the silicon wafer to the epitaxial layer can be reduced.

[0061] Furthermore, the oxygen concentration of the silicon wafer was set to 4 × 10⁻⁶. 17 atoms / cm 3 The above 10 x 10 17 atoms / cm 3 By doing the following, it is possible to prevent device voltage breakdown failures even when carbon is used.

[0062] Furthermore, by performing argon annealing on the silicon wafer before forming the silicon epitaxial layer, the carbon concentration in the surface layer of the silicon wafer is reduced, thereby reducing the amount of carbon diffusion into the silicon epitaxial layer during its formation. By reducing the amount of carbon diffusion into the silicon epitaxial layer, it is possible to suppress the deterioration of electrical properties caused by defects resulting from incorporated carbon in the silicon epitaxial layer during heat treatment in the device manufacturing process for creating devices on epitaxial silicon wafers.

[0063] In the above embodiment, the resistivity of the silicon wafer was set to 0.5 mΩ·cm or more and 1.2 mΩ·cm or less. However, for a silicon wafer with even lower resistivity, it is preferable to set the resistivity to 0.5 mΩ·cm or more and 0.9 mΩ·cm or less. As the resistivity decreases, the generation of SF in the epitaxial layer becomes more pronounced, and the effect of carbon doping in the present invention is more fully exhibited.

[0064] Furthermore, the silicon wafer of this embodiment is manufactured from a single-crystal ingot using a silicon melt doped with phosphorus to a resistivity of 1.2 mΩ·cm or less. Due to the high concentration of phosphorus added, the OSF ring region where oxidation-induced stacking faults (OSF) occur during the single-crystal ingot manufacturing process disappears at the center of the ingot, resulting in a crystal region where COPs (Critical Oxide Faults) are absent. In other words, the silicon wafer of this embodiment can be made into a COP-free wafer by adding a high concentration of phosphorus, and the occurrence of defects caused by COPs in the epitaxial layer can be prevented. [Examples]

[0065] The experimental conditions and evaluation results of the embodiments and comparative examples of the present invention will be described below. <Dislocation Loop Evaluation> The following evaluations were performed regarding the dislocation loops in Example 1 and Comparative Example 2. <Example 1> In Example 1, an epitaxial silicon wafer was manufactured within the conditions of the manufacturing flow for epitaxial silicon wafers described with reference to Figure 3. The conditions for growing the single crystal ingot were as follows: carbon powder was added before melting the silicon raw material, and phosphorus was added to the silicon melt after the raw material was melted so that the resistivity at the upper end of the straight body of the single crystal ingot was 0.9 mΩ·cm. A sample wafer was cut from the top ingot position of a carbon-doped single-crystal ingot, and a mirror-finish silicon wafer was fabricated by performing a predetermined processing treatment. The resistivity of this silicon wafer was measured using the four-probe method and found to be 0.75 mΩ·cm, indicating that the carbon concentration of the silicon wafer was 1.2 × 10⁻⁶. 16 atoms / cm 3 That was the case.

[0066] <Comparative Example 1> In comparison to Example 1, a silicon wafer was manufactured under the same manufacturing conditions as in Example 1, except that carbon doping was not performed during the single-crystal ingot growth stage. Similar to Example 1, a sample wafer was cut from the ingot position where the resistivity was 0.75 mΩ·cm, and a mirror-finish silicon wafer was produced by performing a predetermined processing treatment.

[0067] The silicon wafers of Example 1 and Comparative Example 1 were cleaved in the thickness direction, and the cleaved cross-sections were observed using a transmission electron microscope (TEM). Figure 5 is a graph showing the evaluation results of dislocation loops in the silicon wafers of Example 1 and Comparative Example 1. In Figure 5, the horizontal axis represents the dislocation loop size, and the vertical axis represents the dislocation loop density. Figure 5(a) shows the results for Comparative Example 1, a silicon wafer that was not carbon-doped. Because this sample wafer was cut from the crystal top side, where the residence time in the SF nucleation temperature range is longer, many large dislocation loop defects exceeding 60 nm were observed. On the other hand, Figure 5(b) shows the results for the silicon wafer of Example 1, which was doped with a low concentration of carbon. Since this sample wafer was cut from the crystal top side, where the residence time in the SF nucleation temperature range is longer, many small dislocation loops were observed, but it was confirmed that the density of large dislocation loops exceeding 60 nm decreased. In other words, it was confirmed that carbon doping reduces the density of large dislocation loops formed on silicon wafers.

[0068] [LPD density assessment] When an epitaxial layer is formed using a sample silicon wafer cut from the top side of the straight ingot body, where the residence time in the temperature range where SF nuclei are formed is longer, SF occurs frequently in the epitaxial layer and the LPD density increases. Therefore, in this experiment, sample silicon wafers for Examples 2 and 3 and Comparative Examples 2 and 3 were prepared by cutting from the top side of the straight ingot body, and the LPD density observed on the epitaxial layer surface after epitaxial layer formation was measured.

[0069] [Conditions for oxide film formation on the back surface] A backside oxide film was formed on the back surface of each silicon wafer (the side opposite to the surface on which the epitaxial film was formed) under the following conditions. Raw material gas: Mixture of monosilane (SiH4) and oxygen (O2) Film formation method: CVD method Film forming temperature: 400℃ Thickness of the oxide film on the back surface: 550nm The oxide film present on the chamfered edges and the outer periphery of the back surface of each silicon wafer was removed by etching. [Hydrogen bake treatment conditions] Atmosphere: Hydrogen gas Heat treatment temperature: 1200℃ Heat treatment time: 30 seconds [Epitaxial film growth conditions] Dopant gas: Phosphine (PH3) gas Raw material source gas: Trichlorosilane (SiHCl3) gas Carrier gas: Hydrogen gas Growth temperature: 1080℃ Epitaxial film thickness: 4 μm Resistivity (epitaxial film resistivity): 0.3 Ω·cm

[0070] <Comparative Example 2> An epitaxial silicon wafer was manufactured by forming a 4 μm thick silicon epitaxial layer on the surface of a silicon wafer of Comparative Example 1, in which numerous dislocation loops were observed without carbon doping.

[0071] <Comparative Example 3> After subjecting the silicon wafer of Comparative Example 1 to argon annealing (heat treatment at 1200°C for 30 minutes in an argon gas atmosphere), an epitaxial silicon wafer was manufactured by forming a 4 μm thick silicon epitaxial layer on the surface of the silicon wafer.

[0072] <Example 2> An epitaxial silicon wafer was manufactured by forming a 4 μm thick silicon epitaxial layer on the surface of the carbon-doped silicon wafer of Example 1 without argon annealing.

[0073] <Example 3> After carbon-doping the silicon wafer of Example 1, argon annealing (heat treatment at 1200°C for 30 minutes in an argon gas atmosphere) was performed, a 4 μm thick silicon epitaxial layer was formed on the surface of the silicon wafer to produce an epitaxial silicon wafer. The epitaxial growth treatment conditions were the same for Examples 2 and 3, and Comparative Examples 2 and 3.

[0074] The LPD density on the surface of the silicon epitaxial layer of the epitaxial silicon wafer in Comparative Example 2 was measured using a surface defect inspection system (Surfscan SP-1, manufactured by KLA-Tencor). Specifically, measurements were taken in Normal mode (DCN mode), and the LPD density of 90 nm or larger observed on the epitaxial film surface was measured. The measurement area was the epitaxial layer surface, excluding the annular region extending 3 mm radially inward from the outermost edge of the epitaxial silicon wafer. The number of counted LPDs can be considered as the number of SFs. As a result, the number of detected LPDs was too high, causing an overflow (more than 100,000 per wafer), and the LPD measurement itself could not be performed. In Comparative Example 3, where the silicon wafer was subjected to argon annealing, the LPD density was reduced compared to Comparative Example 2, but 235 LPDs per wafer were still observed. Below, the LPD density of each example and comparative example was measured under the same conditions as for Comparative Example 2.

[0075] When the LPD density on the surface of the silicon epitaxial layer of the epitaxial silicon wafer in Example 2 was measured, more than 90,000 LPDs per wafer were observed. This is presumed to be because, although the density of large-sized composite dislocation loops in the silicon wafer decreased due to carbon doping, a large number of small dislocation loops smaller than 60 nm in size remained.

[0076] In Example 3, where the silicon wafer was subjected to argon annealing before epitaxial growth, the LPD density on the epitaxial layer surface decreased significantly to 64 LPDs / wafer. This is thought to be due to the disappearance of small dislocation loops smaller than 60 nm in size present in the surface layer of the silicon wafer due to argon annealing.

[0077] From the above, it was found that when carbon is doped and argon annealing is performed on the silicon wafer, the effect of reducing SF generation in the silicon epitaxial layer is enhanced, and the LPD density after epitaxial layer formation can be reduced to about 1 / 4 compared to Comparative Example 3.

[0078] [Carbon concentration profile evaluation] High-concentration carbon doping can lead to carbon diffusion into the silicon epitaxial layer due to heat treatment during silicon epitaxial layer formation, etc. Therefore, we evaluated the behavior of carbon diffusion into the silicon epitaxial layer. <Example 4> High carbon concentration silicon wafer (carbon concentration at the center of wafer thickness: 2.8 × 10⁻⁶) 16 atoms / cm 3 A silicon wafer was manufactured by preparing the same silicon epitaxial layer as in Example 2 without performing argon annealing. <Example 5> An epitaxial silicon wafer was manufactured by subjecting a silicon wafer similar to that in Example 4 to the same argon annealing procedure as in Example 3, and then forming a silicon epitaxial layer on top of it.

[0079] Figure 6 is a graph showing the results of a carbon concentration profile investigation using secondary ion mass spectrometry for the epitaxial silicon wafers of Examples 4 and 5. In Figure 6, the horizontal axis represents the depth from the epitaxial silicon wafer surface, and the vertical axis represents the carbon concentration. It can be seen that the interface between the silicon epitaxial layer and the silicon wafer is located at a depth of 4 μm from the epitaxial silicon wafer surface.

[0080] In Example 4, where the silicon wafer was not subjected to argon annealing, trace amounts of carbon diffusion were observed in the epitaxial layer. On the other hand, in Example 5, where argon annealing was performed before the formation of the silicon epitaxial layer, no carbon was detected throughout the epitaxial layer in carbon concentration measurements by SIMS analysis. The detection limit of carbon concentration of the SIMS analyzer used was 2 × 10⁻⁶. 15 atoms / cm 3 Therefore, the carbon concentration is 2 × 10⁻⁶ throughout the entire epitaxial layer. 15 atoms / cm 3 It can be concluded that the reading was below the detection limit of the SIMS measurement.

[0081] Furthermore, in Example 4, where the silicon wafer was not subjected to argon annealing, the width of the low-carbon concentration layer was less than 1 μm. On the other hand, in Example 5, where argon annealing was performed before the formation of the silicon epitaxial layer, a low-carbon concentration layer with a thickness of 8 μm was formed in the depth direction of the wafer from the interface between the silicon epitaxial layer and the silicon wafer. By forming a low-carbon concentration layer on the surface of the silicon wafer, the diffusion of carbon from the silicon wafer to the epitaxial layer can be reliably prevented. The thickness of the low-carbon concentration layer depends on the argon annealing conditions. For example, if all other conditions were the same as in Example 5, the thickness was 5.6 μm when the heat treatment condition was changed to 1150°C × 10 min, 7.3 μm when it was 1200°C × 10 min, 7.3 μm when it was 1150°C × 60 min, 9.4 μm when it was 1200°C × 60 min, and 15 μm when it was 1300°C × 60 min. In other words, the thickness of the low-carbon concentration layer can be arbitrarily adjusted by controlling the heat treatment temperature and time in argon annealing. By forming a low-carbon concentration layer of a predetermined thickness on the surface of the silicon wafer, the diffusion of carbon from the silicon wafer to the epitaxial layer can be prevented.

[0082] [Slip Dislocation Assessment] The presence or absence of slip dislocations (defects along the silicon crystal plane) was investigated for the following Comparative Examples 4 and 5, and Examples 6 and 7, depending on the presence or absence of carbon doping and argon annealing. The specifications and conditions common to the silicon wafers of Comparative Examples 4 and 5, and Examples 6 and 7 are listed below. Resistivity: 0.82mΩ·cm Carbon concentration: 5 × 10 15 atoms / cm 3 Furthermore, in Comparative Example 5 and Example 7, where argon annealing was performed, the argon annealing was a heat treatment at 1200°C for 30 minutes in an argon gas atmosphere. Furthermore, in the following explanation, "heat treatment corresponding to epitaxial layer growth conditions" refers to heat treatment performed without introducing the raw material source gas into the epitaxial apparatus (Applied Materials Corporation: Centura®), and means heat treatment at 1150°C for 1 minute in a hydrogen gas atmosphere. <Comparative Example 4> A silicon wafer that had not undergone carbon doping was subjected to heat treatment corresponding to the conditions for epitaxial layer growth without argon annealing (the silicon epitaxial layer was not grown by heat treatment alone). <Comparative Example 5> Silicon wafers that were not carbon-doped were subjected to argon annealing, followed by heat treatment corresponding to the epitaxial layer growth conditions. <Example 6> A carbon-doped silicon wafer was subjected to heat treatment corresponding to epitaxial layer growth conditions without argon annealing. <Example 7> A carbon-doped silicon wafer was subjected to argon annealing, followed by heat treatment corresponding to the epitaxial layer growth conditions.

[0083] For each silicon wafer, the presence or absence of slip dislocations observed on the wafer surface was checked using X-ray topography. As a result, as shown in Figure 7, no slip dislocations were observed in any of the silicon wafers, and it was confirmed that slip dislocations do not occur even when carbon doping is performed.

[0084] [Verification of resistivity, carbon concentration, and LPD density] For Comparative Examples 6 and 7, and Examples 8 and 9, silicon wafers were manufactured under multiple conditions to verify the correlation between resistivity, carbon concentration, and LPD density. An epitaxial layer was formed on the surface of each silicon wafer, and the LPD density observed on the surface of the epitaxial layer was measured. In Comparative Example 7 and Example 9 below, the argon annealing was performed as a heat treatment at 1200°C for 30 minutes in an argon gas atmosphere. <Comparative Example 6> Without carbon doping, phosphorus was doped to the upper end of the straight body of the single-crystal ingot so that the resistivity of the ingot was 1.2 mΩ·cm, thereby growing a single-crystal ingot with a resistivity range of 0.5 mΩ·cm to 1.2 mΩ·cm. Multiple silicon wafers with different resistivities were then manufactured from the single-crystal ingot. An epitaxial layer with a thickness of 4 μm was formed on each silicon wafer without argon annealing. <Comparative Example 7> Similar to Comparative Example 6, carbon doping was not performed, and a single crystal ingot with a resistivity range of 0.5 mΩ·cm to 1.2 mΩ·cm was grown. Multiple silicon wafers with different resistivity values ​​were then manufactured from the single crystal ingot. Carbon doping was not performed, and after argon annealing, an epitaxial layer with a thickness of 4 μm was formed on each silicon wafer.

[0085] <Example 8> Similar to Comparative Example 6, a single crystal ingot with a resistivity range of 0.5 mΩ·cm to 1.2 mΩ·cm was grown, and multiple silicon wafers with different resistivity values ​​were manufactured from the single crystal ingot. The carbon concentration at the upper end of the straight body of the single crystal ingot was 3.5 × 10⁻⁶. 15 atoms / cm 3 Carbon doping was performed to achieve this result, but an epitaxial layer with a thickness of 4 μm was formed on each silicon wafer without argon annealing. <Example 9> Similar to Comparative Example 6, a single crystal ingot with a resistivity range of 0.5 mΩ·cm to 1.2 mΩ·cm was grown, and multiple silicon wafers with different resistivity values ​​were manufactured from the single crystal ingot. The carbon concentration at the upper end of the straight body of the single crystal ingot was 3.5 × 10⁻⁶. 15 atoms / cm 3 Carbon doping was performed to achieve the desired result, and after argon annealing, an epitaxial layer with a thickness of 4 μm was formed on each silicon wafer.

[0086] Figure 8 is a graph showing the relationship between the resistivity of the silicon wafer and the LPD density observed on the epitaxial layer surface for each of the epitaxial silicon wafers in Example 8, Example 9, Comparative Example 6, and Comparative Example 7. The horizontal axis of Figure 8 represents the position from which the silicon wafer was cut, as the solidification rate of the ingot's straight body, with the solidification amount of the entire length of the grown ingot's straight body set to 1.

[0087] As shown in Figure 8, in Example 8, where carbon doping was performed and argon annealing was not performed before epitaxial growth, an LPD density of approximately 16,000 particles / wafer was observed in silicon wafers cut from the ingot's straight body position near solidification rate 0.1, which is the top-side crystalline region. This confirmed the effect of reducing LPD density, but the LPD density overflowed in silicon wafers cut from the ingot's straight body position near solidification rate 0.3. Furthermore, when using silicon wafers cut from the bottom-side crystalline region, it was possible to reduce the LPD density to 150 particles / wafer or less, even with silicon wafers with an extremely low resistivity of 0.5 mΩ·cm.

[0088] In Example 9, where carbon doping was performed and the silicon wafer was argon annealed before epitaxial growth, the LPD density could be reduced to 95 particles / wafer or less, even when using a silicon wafer cut from the top crystalline region. This is because This was achieved by miniaturizing dislocation loop defects through carbon doping and then eliminating the miniaturized dislocation loop defects by argon annealing of the silicon wafer. It became clear that the synergistic effect of carbon doping and argon annealing had a very large effect in reducing SF (Singular Fault) levels. On the other hand, when silicon wafers cut from the bottom-side crystalline region (crystalline region with a solidification rate of 0.6 or higher), where the residence time in the SF nucleation temperature range is shorter, the LPD density could be reduced to 30 particles / wafer or less in all cases.

[0089] On the other hand, in Comparative Example 6 where no carbon doping was performed and no argon annealing was applied to the silicon wafer, when a silicon wafer cut from the top crystal region was used, the LPD density overflowed, and when a silicon wafer cut from the bottom crystal region was used, although the LPD density decreased significantly, the LPD density on the silicon wafer with a resistivity of 0.5 mΩ·cm was 200 pieces per wafer or more. Also, in Comparative Example 7 where no carbon doping was performed and argon annealing was applied to the silicon wafer before the epitaxial growth process, the LPD density could be decreased compared to Comparative Example 6. However, when a silicon wafer cut from the top crystal region was used, the LPD density was 100 to 300 pieces per wafer.

[0090] From the above results, 3.5×10 15 atoms / cm 3 By performing the above carbon doping and applying argon annealing to the silicon wafer before the epitaxial growth process, it was found that the LPD density observed on the epitaxial layer surface in all crystal regions of the single crystal ingot could be made 100 pieces per wafer or less. Also, even without applying argon annealing to the silicon wafer, by performing carbon doping, the LPD density in the bottom crystal region could be made 150 pieces per wafer or less. Although this example does not disclose all examples, the inventor confirmed that if the carbon addition is at least 3.5×10 15 atoms / cm 3 or more, the LPD density after the epitaxial growth process can be reduced for silicon wafers with a resistivity of 0.5 mΩ·cm or more and 1.2 mΩ·cm or less compared to the case where no carbon is added.

[0091] 〔Evaluation of Device Breakdown Voltage Characteristics〕 The device breakdown voltage characteristics were evaluated. Here, device breakdown voltage is one of the quality characteristics of a semiconductor device. It refers to the voltage at which the device breaks down when the voltage between the drain and source is gradually increased while the gate and source of the semiconductor device are short-circuited.

[0092] There are concerns that if oxygen from the silicon wafer diffuses into the epitaxial layer where semiconductor devices are fabricated, it may affect the device's breakdown voltage characteristics. Therefore, the inventors prepared silicon wafers with six different oxygen concentrations, formed a silicon epitaxial layer on each wafer, and investigated whether there were differences in device breakdown voltage characteristics due to the difference in oxygen concentration. Furthermore, they investigated whether there were differences in device breakdown voltage characteristics depending on whether or not carbon doping was applied to the silicon wafer.

[0093] Specifically, semiconductor devices were fabricated from each of the epitaxial silicon wafers shown in Table 1 (Samples 1-12). With the gate and source constituting the semiconductor device short-circuited, a predetermined voltage was applied between the drain and source. If breakdown occurred, the breakdown characteristic was determined to be "poor," and if no breakdown occurred, the breakdown characteristic was determined to be "good."

[0094] Samples 1-6 are epitaxial silicon wafers with a diameter of 200 mm, on which a 4 μm thick silicon epitaxial layer has been formed. These wafers were created by forming epitaxial layers on six different silicon wafers with varying oxygen concentrations, without the addition of carbon. The epitaxial silicon wafers of Samples 7-12, like Samples 1-6, are 200 mm in diameter, phosphorus-doped silicon wafers with a resistivity of 0.75 mΩcm, on which a 4 μm thick silicon epitaxial layer is formed, with a carbon concentration of 2.8 × 10⁻¹⁶. 16 atoms / cm 3 These are sample wafers in which an epitaxial layer was formed on each of six silicon wafers with different oxygen concentrations. The carbon and oxygen concentrations were measured using SIMS (Simulation-Induced Mass Spectroscopy) at the center of the silicon wafer thickness after thinning the silicon wafer through polishing.

[0095] [Table 1]

[0096] As shown in Table 1, it was confirmed that in samples 7-9, carbon doping was likely to result in device breakdown voltage failure. However, even with carbon doping, when the oxygen concentration was 10 × 10⁻¹⁰, 17 atoms / cm 3 It was confirmed that the following measures can prevent device voltage failure. [Explanation of Symbols]

[0097] 11...Silicon wafer, 12...Low carbon concentration layer, 13...Epitaxial layer, C...Center, D...Depth.

Claims

1. The diameter is 200 mm. The dopant is phosphorus, the resistivity is between 0.5 mΩ·cm and 0.9 mΩ·cm, and the carbon concentration is 3.5 × 10⁻¹⁰ １５ atoms / cm ３ The above 2.8 x 10 １６ atoms / cm ３ The silicon wafer is as follows:

2. In the silicon wafer according to claim 1, The oxygen concentration of the silicon wafer is 4 × 10 １７ atoms / cm ３ The above 10 x 10 １７ atoms / cm ３ The silicon wafer is as follows:

3. In the silicon wafer according to claim 1 or claim 2, A silicon wafer in which no COP exists.

4. A silicon wafer having a diameter of 200 mm, a dopant of phosphorus, a resistivity of 0.5 mΩ·cm or more and 0.9 mΩ·cm or less, and a carbon concentration of 3.5×10 １５ atoms / cm ３ or more and 2.8×10 １６ atoms / cm ３ or less, and An epitaxial silicon wafer comprising a silicon epitaxial layer on the surface of the silicon wafer.

5. In the epitaxial silicon wafer according to claim 4, The carbon concentration of the silicon epitaxial layer is 2.0 × 10 １５ atoms / cm ３ Epitaxial silicon wafers that are less than [a certain value].

6. In the epitaxial silicon wafer according to claim 4, The oxygen concentration of the silicon wafer is 4 × 10 １７ atoms / cm ３ The above 10 x 10 １７ atoms / cm ３ The following are epitaxial silicon wafers.

7. In the epitaxial silicon wafer according to claim 4, An epitaxial silicon wafer in which no COP exists.

8. In the epitaxial silicon wafer according to claim 4, An epitaxial silicon wafer having an oxide film on the back surface of the silicon wafer.

9. In the epitaxial silicon wafer according to claim 8, An epitaxial silicon wafer having no oxide film on the edges and outer periphery of the back surface of the silicon wafer.

10. In the epitaxial silicon wafer according to claim 4, An epitaxial silicon wafer having an LPD density of 0.09 μm size or larger observed on the surface of the silicon epitaxial layer of 100 particles / wafer or less.

11. In the epitaxial silicon wafer according to claim 4, An epitaxial silicon wafer having an LPD density of 0.09 μm size or larger observed on the surface of the silicon epitaxial layer of 30 or fewer per wafer.

Images