Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor having further improved mechanical strength. A multilayer ceramic capacitor 1 includes: a plurality of laminated dielectric layers; and a plurality of laminated internal electrode layers. The multilayer ceramic capacitor 1 comprises: a laminate 2 that includes a first main surface M1 and a second main surface M2 facing each other in the height direction T, a first side surface S1 and a second side surface S2 facing each other in a width direction W orthogonal to the height direction T, and a first end surface E1 and a second end surface E2 facing each other in a length direction L orthogonal to the height direction T and the width direction W; and an external electrode layer provided on the laminate 2 and connected to a portion of the internal electrode layers. If a crystal orientation of crystal particles C of the dielectric layers is measured by an electron beam backscatter diffraction method, two or more sets of crystal particles are found in which a difference between crystal orientations of two adjacent crystal particles C in an observation range of 2μ square is within 5 degrees on the basis of a given direction.

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic capacitor.

Background Art

[0002] In recent years, multilayer ceramic capacitors have been increasingly applied to electronic devices such as small in-vehicle devices that require high dielectric constant and high reliability. Patent Document 1 describes a technique for improving the performance of a multilayer ceramic capacitor by adjusting the distribution of nickel near the grain boundaries.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the technique described in Patent Document 1, the improvement of electrical characteristics or reliability may not be sufficient. Therefore, an object of the present invention is to provide a multilayer ceramic capacitor with improved mechanical strength.

[0005] The multilayer ceramic capacitor of the present invention includes a plurality of stacked dielectric layers and a plurality of stacked internal electrode layers, and has a laminate having a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction orthogonal to the height direction, and a first end surface and a second end surface facing each other in the length direction orthogonal to the height direction and the width direction, and an external electrode layer provided on the laminate and connected to a part of the internal electrode layers. When the crystal orientation of the crystal particles of the dielectric layer is measured by the electron backscatter diffraction method, in an observation range of 2 μm square, there are two or more sets of crystal particles in which the difference in crystal orientation between two adjacent crystal particles is within 5 degrees with respect to an arbitrary direction. [Effects of the Invention]

[0006] According to the present invention, it is possible to provide a multilayer ceramic capacitor with improved mechanical strength. [Brief explanation of the drawing]

[0007] [Figure 1] This is a perspective view of the multilayer ceramic capacitor of Embodiment 1. [Figure 2] This is a cross-sectional view taken along line II in Figure 1. [Figure 3] This is a cross-sectional view taken along line II-II in Figure 1. [Figure 4A] This is an image quality map showing the crystal grains observed in the embodiment of Embodiment 1. [Figure 4B] This is a crystal orientation map created based on Figure 4A. [Figure 5A] This is an image quality map showing the crystal grains observed in a comparative example of Embodiment 1. [Figure 5B] This is a crystal orientation map created based on Figure 5A. [Figure 6A] This figure shows the peak diffraction angle of the embodiment of Embodiment 2. [Figure 6B] This figure shows the peak diffraction angle of a comparative example of Embodiment 2. [Figure 7A] This figure shows the case where the (100) crystal orientation plane is observed using high-angle scattering dark-field scanning transmission electron microscopy. [Figure 7B] This figure shows the case where the (100) crystal orientation plane is observed using high-angle scattering dark-field scanning transmission electron microscopy. [Figure 7C] This figure shows the case where the (100) crystal orientation plane is observed using high-angle scattering dark-field scanning transmission electron microscopy. [Figure 7D] This figure shows the case where the (100) crystal orientation plane is observed using high-angle scattering dark-field scanning transmission electron microscopy. [Figure 7E]This is a diagram showing the case where the crystal orientation (100) plane is observed in observation by high-angle scattering dark-field scanning transmission electron microscopy. [Figure 7F] This is a diagram showing the case where the crystal orientation (100) plane is observed in observation by high-angle scattering dark-field scanning transmission electron microscopy. [Figure 7G] This is a diagram showing the case where the crystal orientation (100) plane is observed in observation by high-angle scattering dark-field scanning transmission electron microscopy. [Figure 7H] This is a diagram showing the case where the crystal orientation (100) plane is not observed in observation by high-angle scattering dark-field scanning transmission electron microscopy. [Figure 8] This is a diagram showing the state of observation by high-angle scattering dark-field scanning transmission electron microscopy.

Mode for Carrying Out the Invention

[0008] <00​​​​​​​​​​​​​​​​In the laminate 2, of the two surfaces facing each other in the height direction T, one surface is defined as the first main surface M1, and the remaining one surface is defined as the second main surface M2. In the laminate 2, of the two surfaces facing each other in the width direction W, one surface is defined as the first side surface S1, and the remaining one surface is defined as the second side surface S2. In the laminate 2, of the two surfaces facing each other in the length direction L, one surface is defined as the first end surface E1, and the remaining one surface is defined as the second end surface E2.

[0012] Regarding the cross-section of the laminate 2, the cross-section taken along the line I-I in FIG. 1 is defined as the LT cross-section. Regarding the cross-section of the laminate 2, the cross-section taken along the line II-II in FIG. 1 is defined as the WT cross-section.

[0013] The portion where three surfaces of the laminate 2 intersect is defined as the corner portion of the laminate 2, and the portion where two surfaces of the laminate 2 intersect is defined as the ridge line portion of the laminate 2. It is preferable that the corner portion and the ridge line portion are rounded.

[0014] (Dielectric layer) The total number of dielectric layers laminated on the laminate 2 is preferably 15 or more and 2000 or less. The main material of the dielectric layer is a ceramic material. Examples of the ceramic material are dielectric ceramics mainly composed of barium titanate, calcium titanate, strontium titanate, calcium zirconate, etc. The ceramic material may be a dielectric ceramic in which sub-components such as manganese compounds, iron compounds, chromium compounds, cobalt compounds, nickel compounds, etc. are added to these main components.

[0015] The dielectric layer contains crystalline particles. These crystalline particles are the main components of the dielectric layer and are composed of a perovskite-type oxide containing A-site elements and B-site elements. The perovskite-type oxide has a composition represented by the general formula: ABO3. Each atom of the A-site element and each atom of the B-site element are ionized to occupy the A-site and B-site of the perovskite structure. Examples of A-site elements include elements with relatively large ionic sizes, such as barium, calcium, and strontium. Examples of B-site elements include elements with relatively small ionic sizes, such as titanium, zirconium, and hafnium.

[0016] The combination of A-site elements and B-site elements is not particularly limited, as long as the perovskite structure is maintained. Furthermore, each of the A-site and B-site elements may consist of only one type of element, or a combination of multiple elements.

[0017] Preferably, the A-site element contains barium, and the B-site element contains titanium. In other words, the perovskite-type oxide is preferably a barium titanate-based compound.

[0018] The thickness of each dielectric layer is preferably 0.3 μm or more and 10 μm or less.

[0019] (Classification of laminates) The division of the laminate 2 in the longitudinal direction L will be explained based on Figure 2. Figure 2 is a cross-sectional view taken along line II of Figure 1. The laminate 2 can be divided in the height direction T into a first main surface-side outer layer OL1, an inner layer range IL, and a second main surface-side outer layer OL2. The first main surface-side outer layer OL1, the inner layer range IL, and the second main surface-side outer layer OL2 are arranged in this order from the first main surface M1 to the second main surface M2 in the height direction T.

[0020] The first main surface-side outer layer portion OL1 is the portion between the internal electrode layer closest to the first main surface M1 and the first main surface M1. The inner layer range IL is the range where two internal electrode layers face each other. The second main surface-side outer layer portion OL2 is the portion between the internal electrode layer closest to the second main surface M2 and the second main surface M2.

[0021] The first main surface-side outer layer OL1 is located on the first main surface M1 side of the laminate 2. The first main surface-side outer layer OL1 is formed by an assembly of multiple dielectric layers located between the first main surface M1 and the internal electrode layer closest to the first main surface M1. The first main surface-side outer layer OL1 is formed by multiple dielectric layers located between the first main surface M1 and the outermost surface of the inner layer range IL on the first main surface M1 side and the extension of that outermost surface.

[0022] The second main surface-side outer layer OL2 is located on the second main surface M2 side of the laminate 2. The second main surface-side outer layer OL2 is formed by an assembly of multiple dielectric layers located between the second main surface M2 and the internal electrode layer closest to the second main surface M2. The second main surface-side outer layer OL2 is formed by multiple dielectric layers located between the second main surface M2 and the outermost surface of the inner layer range IL on the second main surface M2 side and the extension of that outermost surface.

[0023] The inner layer area IL is the area sandwiched between the first main surface-side outer layer OL1 and the second main surface-side outer layer OL2.

[0024] Of the dielectric layers, the dielectric layers located in the first main surface-side outer layer portion OL1 and the second main surface-side outer layer portion OL2 are designated as the outer dielectric layer 3. Of the dielectric layers, the dielectric layers located in the inner layer region IL are designated as the inner dielectric layer 4.

[0025] The following terms may be used in describing length and position.

[0026] The length in the length direction L is defined as the length direction length. The length in the width direction W is defined as the width direction length. The length in the height direction T is defined as the height direction length.

[0027] The position at half the length in the longitudinal direction is defined as the center position in the longitudinal direction L. The center position in the longitudinal direction L is defined as the longitudinal center position.

[0028] The position at half the length in the width direction is defined as the center position in the width direction W. The center position in the width direction W is defined as the width direction center position.

[0029] The position at half the length in the height direction is defined as the center position in the height direction T. The center position in the height direction T is defined as the height direction center position.

[0030] The end in the length direction L is defined as the lengthwise end. The end in the width direction W is defined as the widthwise end. The end in the height direction T is defined as the heightwise end.

[0031] The size of the laminate 2 is not particularly limited. The length of the laminate is preferably 0.2 mm or more and 10 mm or less. The width of the laminate 2 is preferably 0.1 mm or more and 5 mm or less. The height of the laminate 2 is preferably 0.1 mm or more and 5 mm or less.

[0032] (L gap) The division of the laminate 2 in the longitudinal direction L will now be explained. The laminate 2 can be divided in the longitudinal direction L into a first end face side outer layer LG1, a longitudinally opposing part LF, and a second end face side outer layer LG2. The first end face side outer layer LG1, the longitudinally opposing part LF, and the second end face side outer layer LG2 are arranged in this order in the longitudinal direction L, from the first end face E1 to the second end face E2.

[0033] The longitudinal opposing portion LF is the portion where two internal electrode layers face each other in the height direction T. The first end face side outer layer portion LG1 is the portion between the longitudinal opposing portion LF and the first end face E1. The second end face side outer layer portion LG2 is the portion between the longitudinal opposing portion LF and the second end face E2. The longitudinal opposing portion LF corresponds to the opposing electrode portion of the internal electrode layer. The first end face side outer layer portion LG1 and the second end face side outer layer portion LG2 correspond to the lead-out electrode portion of the internal electrode layer. The first end face side outer layer portion LG1 and the second end face side outer layer portion LG2 are also called the L gap.

[0034] The counter electrode section includes a first counter electrode section 7a and a second counter electrode section 7b. The lead-out electrode section includes a first lead-out electrode section 8a and a second lead-out electrode section 8b. The counter electrode section and the lead-out electrode section will be described later.

[0035] The first end-face side outer layer LG1 is located on the first end face E1 side. The first end-face side outer layer LG1 is located between the first end face E1 and the end of the second internal electrode layer 6b on the first end face E1 side.

[0036] The second end-face side outer layer LG2 is located on the second end face E2 side. The second end-face side outer layer LG2 is located between the second end face E2 and the end of the first internal electrode layer 6a on the second end face E2 side.

[0037] (W gap) The division of the laminate 2 in the width direction W will be explained based on Figure 3. Figure 3 is a cross-sectional view taken along line II-II in Figure 1. The laminate 2 can be divided in the width direction W into a first side outer layer WG1, a width-direction opposing layer WF, and a second side outer layer WG2. The first side outer layer WG1, the width-direction opposing layer WF, and the second side outer layer WG2 are arranged in this order from the first side S1 to the second side S2 in the width direction W.

[0038] The widthwise opposing portion WF is the portion where two internal electrode layers face each other in the height direction T. The first side outer layer portion WG1 is the portion between the widthwise opposing portion WF and the first side surface S1. The second side outer layer portion WG2 is the portion between the widthwise opposing portion WF and the second side surface S2. The first side outer layer portion WG1 and the second side outer layer portion WG2 are also called the W gap.

[0039] The first side outer layer WG1 and the second side outer layer WG2 are portions in which there is no internal electrode layer in the height direction T. The first side outer layer WG1 is located on the first side S1 side.

[0040] The second side outer layer WG2 is located on the second side S2 side. The second side outer layer WG2 is formed by a plurality of dielectric layers located between the second side S2 and the outermost surface of the widthwise opposing portion WF on the second side S2 side.

[0041] (Internal electrode layer) The internal electrode layer includes a plurality of first internal electrode layers 6a and a plurality of second internal electrode layers 6b. The first internal electrode layers 6a are internal electrode layers exposed on the first end face E1. The second internal electrode layers 6b are internal electrode layers exposed on the second end face E2.

[0042] The first internal electrode layer 6a can be divided into a first opposing electrode portion 7a and a first extension electrode portion 8a. The first opposing electrode portion 7a is the portion facing the second internal electrode layer 6b. The first extension electrode portion 8a is the portion that is drawn out from the first opposing electrode portion 7a to the first end face E1 of the laminate 2.

[0043] The first extraction electrode portion 8a has its end facing the first end face E1 that is drawn out onto the surface of the first end face E1 of the laminate 2. The end of the first extraction electrode portion 8a that is drawn out onto the first end face E1 is exposed to the first end face E1.

[0044] The second internal electrode layer 6b can be divided into a second opposing electrode portion 7b and a second drawn-out electrode portion 8b. The second opposing electrode portion 7b is the portion facing the first internal electrode layer 6a. The second drawn-out electrode portion 8b is the portion drawn out from the second opposing electrode portion 7b to the second end face E2 of the laminate 2.

[0045] The end of the second extraction electrode portion 8b on the side of the second end face E2 is drawn out to the surface of the second end face E2 of the laminate 2. The end of the second extraction electrode portion 8b that is drawn out to the second end face E2 is exposed to the second end face E2.

[0046] The materials for the first internal electrode layer 6a and the second internal electrode layer 6b can be metals such as nickel, copper, silver, palladium, and gold. The materials for the first internal electrode layer 6a and the second internal electrode layer 6b can be alloys containing at least one of the aforementioned metals, such as a silver-palladium alloy.

[0047] In the multilayer ceramic capacitor 1, capacitance is formed when the first counter electrode portion 7a and the second counter electrode portion 7b face each other via the inner dielectric layer 4. As a result, the multilayer ceramic capacitor 1 exhibits the characteristics of a capacitor.

[0048] The thickness of the first internal electrode layer 6a and the thickness of the second internal electrode layer 6b are preferably, for example, 0.2 μm or more and 2.0 μm or less. The total number of layers, including the first internal electrode layer 6a and the second internal electrode layer 6b, is preferably 15 to 2000 layers.

[0049] (Inner layer) The portion where the first internal electrode layer 6a and the second internal electrode layer 6b face each other is defined as the inner layer portion 10. The inner layer portion 10 is the portion where the longitudinally opposing portion LF shown in Figure 2 and the widthwise opposing portion WF shown in Figure 3 intersect with the inner layer range IL. The shape of the inner layer portion 10 is approximately a rectangular parallelepiped. Figure 2 shows the portion where the longitudinally opposing portion LF and the inner layer range IL intersect as the inner layer portion 10. Also, Figure 3 shows the portion where the widthwise opposing portion WF and the inner layer range IL intersect as the inner layer portion 10.

[0050] (external electrode) The external electrodes will now be described. The external electrodes include a first external electrode 20a and a second external electrode 20b. The first external electrode 20a is an external electrode connected to the first internal electrode layer 6a. The second external electrode 20b is an external electrode connected to the second internal electrode layer 6b.

[0051] The first external electrode 20a is positioned on the first end face E1, a portion of the first main surface M1, a portion of the second main surface M2, a portion of the first side surface S1, and a portion of the second side surface S2. The second external electrode 20b is positioned on the second end face E2, a portion of the first main surface M1, a portion of the second main surface M2, a portion of the first side surface S1, and a portion of the second side surface S2.

[0052] The external electrode includes a base electrode layer and a plating layer. The plating layer includes a Ni plating layer and a Sn plating layer. These layers are arranged in the order of base electrode layer, Ni plating layer, and Sn plating layer from the end face of the laminate 2.

[0053] The first external electrode 20a includes a first base electrode layer 22a, a first Ni plating layer 23a, and a first Sn plating layer 24a. The second external electrode 20b includes a second base electrode layer 22b, a second Ni plating layer 23b, and a second Sn plating layer 24b.

[0054] (base electrode layer) The first base electrode layer 22a is positioned on the first end face E1 of the laminate 2 and covers the first end face E1. The first base electrode layer 22a extends from the first end face E1 to a portion of the first main surface M1, a portion of the second main surface M2, a portion of the first side surface S1, and a portion of the second side surface S2.

[0055] The second base electrode layer 22b is positioned on the second end face E2 of the laminate 2 and covers the second end face E2. The second base electrode layer 22b extends from the second end face E2 to a portion of the first main surface M1, a portion of the second main surface M2, a portion of the first side surface S1, and a portion of the second side surface S2.

[0056] The underlying electrode layer contains a glass component and a metal. The glass component includes at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal includes at least one selected from, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc.

[0057] (Ni plating layer and Sn plating layer) The first Ni plating layer 23a is positioned to cover the first underlay electrode layer 22a. The first Sn plating layer 24a is positioned to cover the first Ni plating layer 23a.

[0058] The second Ni plating layer 23b is positioned to cover the second under electrode layer 22b. The second Sn plating layer 24b is positioned to cover the second Ni plating layer 23b.

[0059] The Ni plating layer prevents the underlying electrode layer from being corroded by the solder used when mounting the multilayer ceramic capacitor 1. The Sn plating layer improves the wettability of the solder used when mounting the multilayer ceramic capacitor 1, making mounting easier.

[0060] Furthermore, a conductive resin layer can be placed between the base electrode layer and the Ni plating layer. The conductive resin layer may include epoxy resin and metal fillers.

[0061] The size of the multilayer ceramic capacitor 1 is not particularly limited. The preferred length of the multilayer ceramic capacitor 1, including the laminate 2 and external electrodes, is 0.2 mm to 10 mm. The preferred height of the multilayer ceramic capacitor 1, including the laminate 2 and external electrodes, is 0.1 mm to 5 mm. The preferred width of the multilayer ceramic capacitor 1, including the laminate 2 and external electrodes, is 0.1 mm to 10 mm.

[0062] (Manufacturing method for multilayer ceramic capacitors) The manufacturing method for the multilayer ceramic capacitor 1 will be explained. (1) Prepare a conductive paste for the dielectric sheet and the internal electrode layer. The conductive paste for the dielectric sheet and the internal electrode layer includes a binder and a solvent. The binder and solvent may be known organic binders and organic solvents, etc.

[0063] (2) A conductive paste for the internal electrode layer is printed on the dielectric sheet in a predetermined pattern. The internal electrode layer pattern is formed by printing the conductive paste. Printing can be done by, for example, screen printing or gravure printing.

[0064] (3) A predetermined number of dielectric sheets for the outer layer are stacked. The dielectric sheets for the outer layer do not have the internal electrode layer pattern printed on them. Dielectric sheets with the internal electrode layer pattern printed on them are stacked sequentially on top of the stacked dielectric sheets. Furthermore, a predetermined number of dielectric sheets for the outer layer are stacked on top of that. A laminated sheet is produced by these stacking processes.

[0065] (4) A laminated block is produced by pressing the laminated sheets in the height direction. The pressing method can be hydrostatic pressing.

[0066] (5) Cut the laminated block to the specified size. This cut will produce the laminated chips. The corners and edges of the laminated chips may be rounded during the cutting process. Barrel polishing can be used to round the edges.

[0067] (6) The laminated chips are fired. This firing process produces the laminate. The preferred firing temperature is 900°C to 1200°C. The firing temperature can be changed depending on the materials of the dielectric and internal electrode layers.

[0068] Cooling after heating to the firing temperature should be faster than natural cooling. For example, cooling from the firing temperature of 900°C to 1200°C to a temperature of 100°C to 300°C should be done within 10 minutes. Preferably, cooling from 1000°C to 200°C should be done within 7 minutes. More preferably, cooling from 1000°C to 200°C should be done within 5 minutes. Even more preferably, cooling from 1000°C to 200°C should be done within 1 minute.

[0069] By cooling in this way, productivity can be improved compared to simply leaving it to cool naturally.

[0070] Here, cooling does not simply mean placing the stacked chip in a gas at a predetermined temperature. More actively, cooling means cooling the stacked chip. For example, a gas at a predetermined temperature can be blown onto the stacked chip. Alternatively, a solid or liquid at a predetermined temperature can be brought into contact with the stacked chip.

[0071] (external electrode) Next, the external electrodes are formed. First, a conductive paste, which will serve as the base electrode layer, is applied to the two end faces of the laminate 2. The conductive paste contains glass components and metal components, etc. The conductive paste can be applied by methods such as dipping. After application, a baking treatment is performed to form the base electrode layer. The baking treatment temperature is preferably between 500°C and 900°C. The baking treatment time is preferably between 30 minutes and 2 hours.

[0072] Next, a Ni plating layer is formed on the surface of the base electrode layer. Furthermore, a Sn plating layer is formed on the surface of the Ni plating layer. The Ni plating layer and the Sn plating layer can be formed by methods such as barrel plating. In this way, a multilayer ceramic capacitor 1 is obtained.

[0073] The crystal orientation of the crystal grains in the dielectric layer of the multilayer ceramic capacitor 1 of Embodiment 1 will be described below. (Crystal orientation) In the dielectric layer of the multilayer ceramic capacitor 1 of Embodiment 1, there are many pairs of adjacent crystal grains whose crystal orientations are close to each other. The crystal orientations determined by electron backscatter diffraction (EBSD) will be explained below.

[0074] Figures 4A and 4B show an example of Embodiment 1, and Figures 5A and 5B show a comparative example of Embodiment 1. Figures 4A and 5B are image quality maps showing the appearance of crystal grains C observed in the ND direction by electron backscatter diffraction.

[0075] Figure 4B is a crystal orientation map created based on the image quality map shown in Figure 4A. Similarly, Figure 5B is a crystal orientation map created based on the image quality map shown in Figure 5A. Crystal orientation maps are also called inverse pole figure (IPF) maps.

[0076] For the examples of Embodiment 1 and comparative examples of Embodiment 1 shown in Figures 4A and 4B, and Figures 5A and 5B, measurements were performed by electron beam backscatter diffraction on the following samples. A multilayer ceramic capacitor was polished to expose the surface of the sample. Polishing was performed by grinding along planes parallel to the width direction W and the height direction T. The surface of the sample was defined as the WT cross-section at the center position in the length direction T.

[0077] For the crystal orientation measurement, the outer layer was measured. This is because crystal orientation has a high correlation with cracks that occur in the outer layer.

[0078] Furthermore, electron beam backscatter diffraction measurements were performed using thin section samples. The WT cross-section at the midpoint of the length T of the multilayer ceramic capacitor, as described above, was measured after processing the sample into a thin section. Specifically, the surface opposite to the measurement surface was polished to a thickness of 100 nm, and then the WT cross-section was measured.

[0079] The area for measuring crystal orientation in the outer layer is 2 μm square. Typically, between 50 and 250 crystal grains are observed within this observation area.

[0080] In the crystal orientation maps shown in Figures 4B and 5B, a dashed line A is drawn at the grain boundary between two adjacent crystal grains where the difference in their crystal orientations is within 5 degrees relative to any given direction.

[0081] As shown in Figure 4B, in the embodiment of Embodiment 1, there are 24 sets of crystal grains within the measurement range shown in Figure 4B, where the difference in crystal orientation between two adjacent crystal grains is within 5 degrees with respect to an arbitrary direction.

[0082] In contrast, in the comparative example of Embodiment 1, there is one set, as shown in Figure 5B.

[0083] Furthermore, in the embodiment of Embodiment 1, there are four sets of three crystal grains, each set consisting of one crystal grain and two crystal grains adjacent to it, with a crystal orientation misalignment angle of 5 degrees or less between them. In contrast, the comparative example of Embodiment 1 has zero such sets.

[0084] Thus, in the dielectric layer of the multilayer ceramic capacitor 1 of Embodiment 1, there are many pairs of crystal grains whose crystal orientations are close to each other.

[0085] Furthermore, the ratio of crystal particles in contact with other crystal particles whose crystal orientation difference is within 5 degrees relative to any given direction, relative to the total number of crystal particles, is higher in the multilayer ceramic capacitor 1 of Embodiment 1 than in conventional multilayer ceramic capacitors. In the multilayer ceramic capacitor 1 of Embodiment 1 shown in Figure 4B, 45 out of 166 total crystal particles were in contact with other crystal particles whose crystal orientation difference was within 5 degrees relative to any given direction. This ratio was 27.1%. In contrast, in the comparative example of Embodiment 1 shown in Figure 5B, 2 out of 113 total crystal particles were in contact with other crystal particles whose crystal orientation difference was within 5 degrees relative to any given direction. This ratio was 1.8%.

[0086] The occurrence of cracks in the outer layer of the multilayer ceramic capacitors of the embodiment 1 and the comparative example of embodiment 1 was evaluated.

[0087] The evaluation method and criteria for crack occurrence are as follows. Ten multilayer ceramic capacitors were subjected to deflection tests according to the JIS C 6484 method, and the presence or absence of cracks in the dielectric layer was evaluated when the deflection amount was fixed at 5 mm.

[0088] In the multilayer ceramic capacitor of Embodiment 1, no cracks occurred, whereas in the comparative example of Embodiment 1, cracks occurred in the multilayer ceramic capacitor.

[0089] (Measurement method) The length and thickness of each part can be measured as follows: Polish the multilayer ceramic capacitor 1 to the center in the width direction. Then, observe the cross-section exposed by polishing using an optical microscope or similar device. The measurements can then be taken from the observed cross-section.

[0090] (Embodiment 2) The multilayer ceramic capacitor 1 of Embodiment 2 will now be described. The following description will mainly focus on aspects that differ from Embodiment 1. Matters not specifically described can be the same as in Embodiment 1.

[0091] The technology described in Patent Document 1 may not provide sufficient improvement in electrical characteristics or reliability. Therefore, Embodiment 2 aims to provide a multilayer ceramic capacitor with a higher relative permittivity.

[0092] The multilayer ceramic capacitor of Embodiment 2 comprises a laminate having a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and width direction, and an external electrode layer provided on the laminate and connected to a part of the internal electrode layer, wherein the X-ray diffraction intensity of the dielectric layer is measured in the width direction and the height direction. When measured by X-ray stress measurement in the cross-section of the parallel laminate, with the width direction as the azimuth angle of 0 degrees and the counterclockwise direction as the positive azimuth direction, and with an azimuth angle of 30 degrees, the diffraction angle at which the X-ray diffraction intensity is maximized when the incident angle of X-rays is changed from the sample in the direction of the normal to the sample is defined as the first peak diffraction angle, and with an azimuth angle of 90 degrees, the diffraction angle at which the X-ray diffraction intensity is maximized when the incident angle of X-rays is changed from the sample in the direction of the normal to the sample is defined as the second peak diffraction angle, the difference between the first peak diffraction angle and the second peak diffraction angle is 0.023 degrees or more.

[0093] According to the multilayer ceramic capacitor of Embodiment 2, it is possible to provide a multilayer ceramic capacitor with a higher relative permittivity.

[0094] The characteristics of the dielectric layer in the multilayer ceramic capacitor 1 of Embodiment 2 will be described. (Peak diffraction angle) The peak diffraction angle will now be explained. In the dielectric layer of the multilayer ceramic capacitor 1 of Embodiment 2, the peak diffraction angle differs depending on the azimuth angle being measured. The peak diffraction angle is the diffraction angle at which the X-ray diffraction intensity is maximum.

[0095] The peak diffraction angle can be measured by X-ray stress measurement. The X-ray stress measurement method is described in the journal "Materials" (J.Soc.Mat.Sci.,Japan), Vol. 47, No. 11, pp. 1188-1194, Nov. 1998, etc.

[0096] In X-ray stress measurement, a sample is irradiated with X-rays, and the diffracted X-rays from the sample are detected. The diffraction angle is the angular difference between the direction of X-ray irradiation onto the sample and the direction of emission of the diffracted X-rays from the sample. The diffraction angle is equivalent to twice the size of the Bragg angle.

[0097] Diffraction X-rays are detected by changing the X-ray irradiation angle onto the sample. The X-ray irradiation angle onto the sample can be changed by shifting the irradiation direction from the direction normal to the sample surface to the direction parallel to the sample surface. Alternatively, the X-ray irradiation angle onto the sample can be changed by shifting the irradiation direction from the direction parallel to the sample surface to the direction normal to the sample surface.

[0098] By varying the X-ray irradiation angle onto the sample, the irradiation angle that maximizes the intensity of diffracted X-rays from the (222) crystal plane of BaTiO3 is determined. This irradiation angle is the peak diffraction angle.

[0099] The peak diffraction angle can be measured by changing the azimuth angle. The azimuth angle is the direction in which the angle is changed when the X-ray irradiation angle is altered. In other words, the azimuth angle is the direction in which the irradiation direction is tilted when changing the irradiation direction from the direction normal to the sample surface to a direction parallel to the sample surface.

[0100] The sample used for measuring the peak diffraction angle is described below. A multilayer ceramic capacitor is polished to expose the surface of the sample. Polishing is performed by removing material from surfaces parallel to the width direction W and the height direction T. The surface of the sample is defined as the WT cross-section at the center position in the length direction T.

[0101] The circular area with a diameter of 500 μm in the central part of the WT cross-section is defined as the X-ray irradiation area. The inner layer area IL of laminate 2 is defined as the measurement area.

[0102] The width direction W in the WT cross section is defined as having an azimuth of 0 degrees. The counterclockwise direction from the width direction W is defined as the positive direction of the azimuth.

[0103] At an azimuth angle of 30 degrees, the diffraction angle at which the X-ray diffraction intensity is maximized when the angle of incidence of X-rays is changed from the sample surface in the direction of the normal to the sample surface is defined as the first peak diffraction angle. Furthermore, at an azimuth angle of 90 degrees, the diffraction angle at which the X-ray diffraction intensity is maximized when the angle of incidence of X-rays is changed from the sample surface in the direction of the normal to the sample surface is defined as the second peak diffraction angle.

[0104] Figures 6A and 6B show the peak diffraction angles of an example of Embodiment 2 and a comparative example of Embodiment 2. Figure 6A shows the peak diffraction angle of an example of Embodiment 2, and Figure 6B shows the peak diffraction angle of a comparative example of Embodiment 2. Figures 6A and 6B show the peak diffraction angle when the azimuth angle is 30 degrees and when the azimuth angle is 90 degrees, respectively.

[0105] As shown in Figures 6A and 6B, in the embodiment of Embodiment 2, the difference between the first peak diffraction angle and the second peak diffraction angle is 0.023 degrees or more. In contrast, in the comparative example of Embodiment 2, the difference between the first peak diffraction angle and the second peak diffraction angle is less than 0.023 degrees. [Table 1] [Table 2]

[0106] Tables 1 and 2 show the relative permittivity of the examples and comparative examples of Embodiment 2. Table 1 shows the case with 300 layers and a dielectric layer thickness of 1.0 μm, while Table 2 shows the case with 410 layers and a dielectric layer thickness of 0.6 μm. In both cases, the examples of Embodiment 2 show a high relative permittivity exceeding 3800. On the other hand, the comparative examples of Embodiment 2 do not exceed 3800.

[0107] In this way, a high relative permittivity can be achieved by making the difference between the first peak diffraction angle and the second peak diffraction angle 0.023 degrees or more.

[0108] The dimensions of the multilayer ceramic capacitors in the embodiment 2 and the comparative example 2 are 1.0 mm in length (L) and 0.5 mm in width (W) and height (T). The number of internal electrode layers is 300 or 410, and the thickness of the dielectric layer is 0.60 μm or 1 μm. The thickness of the internal electrode layer is 0.5 μm.

[0109] (Measurement method) The length and thickness of each part can be measured as follows: Polish the multilayer ceramic capacitor 1 to the center in the width direction. Then, observe the cross-section exposed by polishing using an optical microscope or similar device. The measurements can then be taken from the observed cross-section.

[0110] (1) A laminate comprising a plurality of stacked dielectric layers and a plurality of stacked internal electrode layers, having a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and width direction, A multilayer ceramic capacitor comprising an external electrode layer provided on the laminate and connected to a part of the internal electrode layer, When the X-ray diffraction intensity of the dielectric layer is measured by an X-ray stress measurement method in a cross-section of the laminate parallel to the width direction and the height direction, The width direction is set to an azimuth angle of 0 degrees, The counterclockwise direction is considered the positive direction of the azimuth angle. At an azimuth angle of 30 degrees, when the incident angle of X-rays is changed from the sample in the direction of the normal to the sample, the diffraction angle at which the X-ray diffraction intensity is maximum is defined as the first peak diffraction angle. When the incident angle of X-rays is changed from the sample in the direction of the normal to the sample at an azimuth angle of 90 degrees, the diffraction angle at which the X-ray diffraction intensity is maximum is defined as the second peak diffraction angle. A multilayer ceramic capacitor in which the difference between the first peak diffraction angle and the second peak diffraction angle is 0.023 degrees or more.

[0111] (Embodiment 3) The multilayer ceramic capacitor 1 of Embodiment 3 will now be described. The following description will mainly focus on aspects that differ from Embodiment 1. Matters not specifically described can be the same as in Embodiment 1.

[0112] The technology described in Patent Document 1 may not provide sufficient improvement in electrical characteristics or reliability. Therefore, Embodiment 3 aims to provide a multilayer ceramic capacitor with a higher relative permittivity.

[0113] The multilayer ceramic capacitor of Embodiment 3 includes a plurality of stacked dielectric layers and a plurality of stacked internal electrode layers, comprising a laminate having a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and width direction, and an external electrode layer provided on the laminate and connected to a part of the internal electrode layers, wherein when the dielectric layers are observed by high-angle scattering dark-field scanning transmission electron microscopy, by positioning the optical axis of the microscope perpendicular to the observation surface and tilting the observation surface by -20 degrees to +20 degrees from a surface perpendicular to the optical axis, a plurality of 100 crystal orientation planes can be observed.

[0114] According to the multilayer ceramic capacitor of Embodiment 3, it is possible to provide a multilayer ceramic capacitor with a higher relative permittivity.

[0115] The detection of the (100) crystal orientation plane of the crystal grains in the dielectric layer of the multilayer ceramic capacitor 1 of Embodiment 3 will be described. (Crystal orientation (100) plane) In the dielectric layer of the multilayer ceramic capacitor 1 of Embodiment 3, the probability of the crystal orientation (100) plane being present is high. The following explanation is based on observations made by high-angle scatter dark-field scanning transmission electron microscopy (HAADF-STEM).

[0116] Figures 7A to 7G show the case where the crystal orientation (100) plane was observed using high-angle scattering dark-field scanning transmission electron microscopy, while Figure 7H shows the case where the crystal orientation (100) plane was not observed. Observation of the observation surface using high-angle scattering dark-field scanning transmission electron microscopy is performed while tilting the observation surface.

[0117] Figure 8 shows the observation of an observation surface using high-angle scattering dark-field scanning transmission electron microscopy. In the XYZ Cartesian coordinate system shown in Figure 8, when the observation surface is positioned in the YZ plane, the electron beam in high-angle scattering dark-field scanning transmission electron microscopy is irradiated from the positive side of the X-axis toward the negative side of the X-axis, as indicated by arrow EB.

[0118] An observation plane positioned in the YZ plane can rotate around the Z axis and around the Y axis. In Figure 8, rotation around the Z axis is indicated by arrow A, and rotation around the Y axis is indicated by arrow B.

[0119] In rotation around the Z-axis, let the angle of rotation be angle α. Rotation in the positive direction of the X-axis is defined as the positive direction at angle α. In rotation around the Y-axis, let the angle of rotation be angle β. Rotation in the positive direction of the X-axis is defined as the positive direction at angle β.

[0120] High-angle scattering dark-field scanning transmission electron microscopy observations were performed on the WT cross-section at an intermediate position along the length T of the multilayer ceramic capacitor. The multilayer ceramic capacitor was polished to expose the WT cross-section. Polishing was performed by grinding surfaces parallel to the width W and height T.

[0121] Furthermore, observations using high-angle scattering dark-field scanning transmission electron microscopy were performed using thin section samples. Specifically, thin section samples containing the WT cross-section at an intermediate position in the longitudinal direction T of the multilayer ceramic capacitor were prepared, and the WT cross-section in the thin section sample was observed. The thin section sample was prepared by polishing the surface opposite to the WT cross-section to be observed, so that the sample thickness was 70 μm.

[0122] The observation focused on the central part of the crystal grain. In barium titanate, which has a core-shell structure, the core portion was the target of observation.

[0123] Figure 7A shows the crystal orientation (100) plane observed by tilting the observation plane by α = 1.95 degrees and β = 0.27 degrees. Similarly, Figure 7B shows the crystal orientation (100) plane observed by tilting the observation plane by α = 9.84 degrees and β = 1.87 degrees, Figure 7C shows α = 9.06 degrees and β = 2.35 degrees, Figure 7D shows α = 0.96 degrees and β = -13.75 degrees, Figure 7E shows α = 9.21 degrees and β = 11.38 degrees, Figure 7F shows α = 17.59 degrees and β = 10.94 degrees, and Figure 7G shows the crystal orientation (100) plane observed by tilting the observation plane by α = 17.59 degrees and β = 6.38 degrees.

[0124] In the dielectric layer of the multilayer ceramic capacitor 1 of Embodiment 3, multiple crystal orientation (100) planes can be observed by tilting the observation surface at an angle α of -20 degrees or more and within +20 degrees and at an angle β of -20 degrees or more and within +20 degrees.

[0125] On the other hand, in conventional multilayer ceramic capacitors, the crystal orientation (100) plane cannot be observed by tilting the observation surface between -20 and +20 degrees with respect to angle α, and between -20 and +20 degrees with respect to angle β. The observation results when the crystal orientation (100) plane is not observed are shown in Figure 7H.

[0126] In the multilayer ceramic capacitor 1 of Embodiment 3, the crystal orientation (100) plane can be observed by tilting the observation surface at an angle α of -20 degrees to +20 degrees and at an angle β of -20 degrees to +20 degrees. This embodiment achieved a higher dielectric constant compared to conventional multilayer ceramic capacitors.

[0127] Furthermore, Figures 7A to 7G show the observation results of the central part of the crystal grain. In the multilayer ceramic capacitor 1 of Embodiment 3, the (100) crystal orientation plane was observed in the central part of the crystal grain, where the (100) crystal orientation plane is usually difficult to observe.

[0128] Furthermore, in the multilayer ceramic capacitor 1 of Embodiment 3, the (100) crystal orientation plane described above is observed in both adjacent crystal grains. As described above, in the multilayer ceramic capacitor 1 of Embodiment 3, the crystal orientation (100) plane exists accurately and with high probability without distortion.

[0129] (Measurement method) The length and thickness of each part can be measured as follows: Polish the multilayer ceramic capacitor 1 to the center in the width direction. Then, observe the cross-section exposed by polishing using an optical microscope or similar device. The measurements can then be taken from the observed cross-section.

[0130] (1) A laminate comprising a plurality of stacked dielectric layers and a plurality of stacked internal electrode layers, having a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and width direction, A multilayer ceramic capacitor comprising an external electrode layer provided on the laminate and connected to a part of the internal electrode layer, When the dielectric layer is observed by high-angle scattering dark-field scanning transmission electron microscopy, Position the optical axis of the microscope perpendicular to the observation surface. A multilayer ceramic capacitor in which multiple 100 crystal orientation planes can be observed by tilting the observation surface at an angle of -20 degrees to +20 degrees from a plane perpendicular to the optical axis.

[0131] (2) The observation described above is an observation of the central part of the crystal grains contained in the dielectric layer, as described in (1) for the multilayer ceramic capacitor.

[0132] (3) The multilayer ceramic capacitor according to (2), wherein the 100 plane is observed in adjacent crystal grains.

[0133] (Embodiment 4) The multilayer ceramic capacitor 1 of Embodiment 4 will now be described. The following description will mainly focus on aspects that differ from Embodiment 1. Matters not specifically described can be the same as in Embodiment 1.

[0134] The technology described in Patent Document 1 may not provide sufficient improvement in electrical characteristics or reliability. Therefore, Embodiment 4 aims to provide a multilayer ceramic capacitor with a higher relative permittivity.

[0135] The multilayer ceramic capacitor of Embodiment 4 includes a laminate comprising a plurality of stacked dielectric layers and a plurality of stacked internal electrode layers, the laminate having a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and width direction, and an external electrode layer provided on the laminate and connected to a part of the internal electrode layers, wherein the median diameter of the crystal grains of the dielectric layer determined by observation with a scanning transmission electron microscope is defined as the first average particle size, the crystal orientation of the crystal grains of the dielectric layer is measured by electron backscatter diffraction, and the median diameter of the crystal grains when two adjacent crystal grains whose crystal orientation misalignment angle is within 5 degrees with respect to an arbitrary direction is considered as one crystal grain is defined as the second average particle size, and the value of the second average particle size / the first average particle size is 1.0 or more.

[0136] According to the multilayer ceramic capacitor of Embodiment 4, it is possible to provide a multilayer ceramic capacitor with a higher relative permittivity.

[0137] (particle size) The particle size of the crystalline grains in the dielectric layer of the multilayer ceramic capacitor 1 of Embodiment 4 will now be described. In the dielectric layer of the multilayer ceramic capacitor 1 of Embodiment 4, when comparing the particle size determined based on observation with a scanning transmission electron microscope with the particle size determined based on the crystal orientation map of transmitted EBSD, they are either the same or the latter is larger.

[0138] Here, the particle size of a crystal grain refers to the median diameter in the area particle size distribution. The median diameter is also called d50.

[0139] When determining particle size based on the crystal orientation map obtained from transmitted EBSD, the crystal orientation of the crystalline particles in the dielectric layer is first measured by electron backscatter diffraction. Then, if the difference between the crystal orientations of two adjacent crystalline particles is within 5 degrees relative to any given direction, those particles are treated as a single particle. Therefore, if there are many crystalline particles where the difference between the crystal orientations of two adjacent crystalline particles is within 5 degrees relative to any given direction, the particle size determined based on the crystal orientation map obtained from transmitted EBSD will be larger. [Table 3]

[0140] Table 3 shows the cooling time, particle size, and relative permittivity values ​​after firing of multilayer ceramic capacitors. The median diameter of the crystalline particles in the dielectric layer, determined based on observations using a scanning transmission electron microscope, is defined as the first average particle size. The second average particle size is defined as the median diameter of the crystalline particles when the crystal orientation is measured by electron backscatter diffraction and two adjacent particles whose crystal orientation misalignment angle is within 5 degrees relative to any direction are considered as a single crystalline particle.

[0141] Table 3 shows the values ​​of the relative permittivity / first average particle size, in addition to the first and second average particle sizes. The relative permittivity / first average particle size value indicates the relative permittivity per particle size, and a larger value indicates more favorable electrical properties. For samples where the second average particle size / first average particle size is 1 or greater, the relative permittivity / first average particle size value is 13 or greater. In other words, these samples showed favorable electrical properties.

[0142] The measurements shown in Table 3 were performed on the WT cross-section at the midpoint of the length T of the multilayer ceramic capacitor. The multilayer ceramic capacitor was polished to expose the WT cross-section. Polishing was performed by grinding along surfaces parallel to the width W and height T.

[0143] Measurements using electron backscatter diffraction to obtain a crystal orientation map from transmitted EBSD were performed using thin sections. The WT cross-section at the midpoint of the length T of the multilayer ceramic capacitor, as described above, was measured after processing the thin section. Specifically, the surface opposite to the measurement surface was polished to a thickness of 100 nm, and then the WT cross-section was measured.

[0144] The particle size was evaluated from the central portion of the WT cross-section. The size of the evaluation area was set to 2 μm square. In electron beam backscatter diffraction, accurate values ​​may not be obtained in areas where multiple crystal grains overlap in a direction perpendicular to the measurement surface. If such areas where accurate values ​​cannot be obtained are included in a high proportion within the evaluation area, accurate evaluation becomes difficult. Therefore, the size of the evaluation area was set to 2 μm square.

[0145] (Measurement method) The length and thickness of each part can be measured as follows: Polish the multilayer ceramic capacitor 1 to the center in the width direction. Then, observe the cross-section exposed by polishing using an optical microscope or similar device. The measurements can then be taken from the observed cross-section.

[0146] (1) A laminate comprising a plurality of stacked dielectric layers and a plurality of stacked internal electrode layers, having a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and width direction, A multilayer ceramic capacitor comprising an external electrode layer provided on the laminate and connected to a part of the internal electrode layer, The median diameter of the crystal grains in the dielectric layer, determined by observation with a scanning transmission electron microscope, is defined as the first average grain size. When the crystal orientation of the crystal grains in the dielectric layer is measured by electron beam backscatter diffraction, and a crystal grain whose crystal orientation misalignment angle with two adjacent crystal grains is within 5 degrees relative to any direction is considered as a single crystal grain, the median diameter of the crystal grain is taken as the second average grain size, A multilayer ceramic capacitor in which the ratio of the second average particle size to the first average particle size is 1.0 or greater.

[0147] Although various embodiments of the present invention have been described above, the present invention is not limited to the embodiments described above, and various modifications and variations are possible. [Explanation of symbols]

[0148] 1. Multilayer ceramic capacitor 2 Laminate 3. Outer dielectric layer 4. Inner Dielectric Layer 5a First dielectric layer 5b Second dielectric layer 6a First internal electrode layer 6b Second internal electrode layer 20a First external electrode 20b Second external electrode C crystal particles

Claims

1. A laminate comprising a plurality of stacked dielectric layers and a plurality of stacked internal electrode layers, having a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and width direction, A multilayer ceramic capacitor comprising an external electrode layer provided on the laminate and connected to a part of the internal electrode layer, When the crystal orientation of the crystalline particles of the dielectric layer is measured by electron beam backscatter diffraction, In an observation area of ​​2 μm square, A multilayer ceramic capacitor having two or more pairs of crystal grains, each pair having a crystal orientation difference of 5 degrees or less relative to any given direction.

2. The multilayer ceramic capacitor according to claim 1, wherein there are 20 or more sets of crystal grains, each set having a crystal orientation difference of 5 degrees or less with respect to any direction.

3. One crystal grain, The multilayer ceramic capacitor according to claim 1 or 2, wherein there is one or more sets of three crystal particles, each set including two crystal particles adjacent to the crystal particle and having a crystal orientation misalignment angle of 5 degrees or less with respect to the crystal particle.

4. The multilayer ceramic capacitor according to claim 1 or 2, wherein 50 to 250 crystal particles are observed within the observation area.

5. A laminate comprising a plurality of stacked dielectric layers and a plurality of stacked internal electrode layers, having a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and width direction, A multilayer ceramic capacitor comprising an external electrode layer provided on the laminate and connected to a part of the internal electrode layer, When the crystal orientation of the crystalline particles of the dielectric layer is measured by electron beam backscatter diffraction, A multilayer ceramic capacitor in which 2% or more of the total crystal particles are in contact with other crystal particles whose crystal orientation difference is within 5 degrees relative to any given direction.

6. The multilayer ceramic capacitor according to claim 5, wherein 20% or more of the total crystal particles are in contact with other crystal particles whose crystal orientation difference is within 5 degrees with respect to any direction.

7. A laminate comprising a plurality of stacked dielectric layers and a plurality of stacked internal electrode layers, having a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and width direction, A multilayer ceramic capacitor comprising an external electrode layer provided on the laminate and connected to a part of the internal electrode layer, The median diameter of the crystalline particles of the dielectric layer, determined by observation with a scanning transmission electron microscope, is defined as the first average particle size. When the crystal orientation of the crystal grains in the dielectric layer is measured by electron beam backscatter diffraction, and a crystal grain whose crystal orientation misalignment angle with two adjacent crystal grains is within 5 degrees with respect to an arbitrary direction is considered as a single crystal grain, the median diameter of the crystal grain is taken as the second average grain size, A multilayer ceramic capacitor in which the value of the second average particle size / the first average particle size is 1.0 or greater.

Images