Semiconductor equipment

Abstract

Provided is a semiconductor device capable of achieving a high-integrated or minute arrangement. In the present invention, a first transistor and a second transistor both have, in a shared manner, a first metal oxide disposed on a first insulator, and a first conductor disposed on the first metal oxide. The first transistor has: a second insulator and a second conductor disposed on the first metal oxide; and a third conductor disposed on the second insulator. The second transistor has: a third insulator and a fourth conductor disposed on the first metal oxide; and a fifth conductor disposed on the third insulator. A lateral surface of the first insulator has a portion in contact with the fourth conductor. An end portion of the fourth conductor has a portion located more outward than an end portion of the first insulator. The second insulator is located between the first conductor and the second conductor. The metal oxide and the third conductor overlap each other with the second insulator therebetween. The third insulator is located between the first conductor and the fourth conductor. The metal oxide and the fifth conductor overlap each other with the third insulator therebetween.

Description

[Technical Field]

[0001] One aspect of the present invention relates to a semiconductor device, a memory device, and an electronic device. Another aspect of the present invention relates to a method for manufacturing a semiconductor device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), methods for driving them, or methods for manufacturing them.

[0003] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Semiconductor elements such as transistors, as well as semiconductor circuits, computing devices, and memory devices, are all forms of semiconductor devices. Display devices (such as liquid crystal displays and light-emitting displays), projection devices, lighting devices, electro-optical devices, energy storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices may also be considered to have semiconductor devices. [Background technology]

[0004] In recent years, development of semiconductor devices such as LSIs (Large Scale Integrations), CPUs (Central Processing Units), GPUs (Graphics Processing Units), and memory (storage devices) has progressed. These semiconductor devices are used in various electronic devices such as computers and personal digital assistants. In addition, various types of memory have been developed depending on the application, such as temporary storage during computation execution and long-term data storage. Representative memory types include DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), and flash memory.

[0005] In addition, with the increase in the amount of data to be processed, semiconductor devices having a larger memory capacity are required. In Patent Document 1 and Non-Patent Document 1, memory cells formed by stacking transistors are disclosed.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Non-Patent Documents

[0007]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] One aspect of the present invention aims to provide a semiconductor device capable of miniaturization or high integration. One aspect of the present invention aims to provide a semiconductor device with a high operating speed. One aspect of the present invention aims to provide a semiconductor device having good electrical characteristics. One aspect of the present invention aims to provide a semiconductor device with little variation in the electrical characteristics of transistors. One aspect of the present invention aims to provide a highly reliable semiconductor device. One aspect of the present invention aims to provide a semiconductor device with a large on-current. One aspect of the present invention aims to provide a semiconductor device with low power consumption. One aspect of the present invention aims to provide a novel semiconductor device.

[0009] One aspect of the present invention aims to provide a memory device with a large storage capacity. One aspect of the present invention aims to provide a memory device with a small occupied area. One aspect of the present invention aims to provide a highly reliable memory device. One aspect of the present invention aims to provide a memory device with low power consumption. One aspect of the present invention aims to provide a novel memory device.

[0010] Note that the description of these problems does not prevent the existence of other problems. One aspect of the present invention does not necessarily need to solve all of these problems. It is possible to extract other problems from the description of the specification, drawings, and claims.

Means for Solving the Problems

[0011] One aspect of the present invention has a first transistor, a second transistor, and a first insulator on an insulating surface. The first transistor and the second transistor each share a first metal oxide on the first insulator and a first conductor on the first metal oxide. The first transistor has a second conductor and a second insulator on the first metal oxide and a third conductor on the second insulator. The second transistor has a fourth conductor and a third insulator on the first metal oxide and a fifth conductor on the third insulator. The side surface of the first insulator has a portion in contact with the fourth conductor, and the end of the fourth conductor has a portion located outside the end of the first insulator. The second insulator is located between the first conductor and the second conductor, and the metal oxide and the third conductor overlap via the second insulator. The third insulator is located between the first conductor and the fourth conductor, and the metal oxide and the fifth conductor overlap via the third insulator. It is a semiconductor device.

[0012] One aspect of the present invention comprises a first transistor, a second transistor, a third transistor, a first insulator, a second insulator, a third insulator, and a capacitive element, wherein the first and second transistors each share a first metal oxide on the first insulator and a first conductor on the first metal oxide, the first transistor has a second conductor and a fourth insulator on the first metal oxide and a third conductor on the fourth insulator, the second transistor has a fourth conductor and a fifth insulator on the first metal oxide and a fifth conductor on the fifth insulator, and the third transistor has a second metal oxide, a sixth conductor, a seventh conductor, and a sixth insulator on the second metal oxide and an eighth conductor on the sixth insulator. A semiconductor device comprising a ninth conductor, a seventh insulator on the ninth conductor, and a tenth conductor on the seventh insulator, wherein the side surface of the first insulator has a portion in contact with the fourth conductor, and the end of the fourth conductor has a portion located outside the end of the first insulator, the second insulator is located on the first transistor and the second transistor, and the second conductor and the sixth conductor are electrically connected through an opening provided in the second insulator, the third insulator is located on the third transistor, and the portion on the third insulator where the ninth conductor, the seventh insulator and the tenth conductor overlap is located, and the sixth conductor and the ninth conductor are electrically connected through an opening provided in the third insulator.

[0013] Preferably, the end of the fourth conductor has a portion that is located outside the end of the second insulator.

[0014] Preferably, the end of the second insulator has a portion that is located outside the end of the first insulator.

[0015] Preferably, the end of the seventh conductor has a portion that is located outside the end of the second insulator.

[0016] Preferably, the end of the third insulator has a portion that is located outside the end of the first insulator.

[0017] Preferably, each of the above semiconductor devices has an eleventh conductor having a portion that contacts a part of the upper surface of the fourth conductor, a portion that contacts a part of the side surface of the fourth conductor, a portion that contacts a part of the upper surface of the seventh conductor, and a portion that contacts a part of the side surface of the seventh conductor. Preferably, the eleventh conductor has a portion that contacts a part of the lower surface of the fourth conductor and a portion that contacts a part of the lower surface of the seventh conductor.

[0018] The seventh insulator preferably has one or both of zirconium oxide and aluminum oxide. [Effects of the Invention]

[0019] According to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one aspect of the present invention, a semiconductor device with a high operating speed can be provided. According to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. According to one aspect of the present invention, a semiconductor device with less variation in the electrical characteristics of transistors can be provided. According to one aspect of the present invention, a highly reliable semiconductor device can be provided. According to one aspect of the present invention, a semiconductor device with a large on-current can be provided. According to one aspect of the present invention, a semiconductor device with low power consumption can be provided. According to one aspect of the present invention, a novel semiconductor device can be provided.

[0020] According to one aspect of the present invention, a storage device with a large storage capacity can be provided. According to one aspect of the present invention, a storage device with a small footprint can be provided. According to one aspect of the present invention, a storage device with high reliability can be provided. According to one aspect of the present invention, a storage device with low power consumption can be provided. According to one aspect of the present invention, a novel storage device can be provided.

[0021] Furthermore, the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description, drawings, and claims. [Brief explanation of the drawing]

[0022] Figure 1 is a cross-sectional view showing an example of a semiconductor device. Figure 2 is a cross-sectional view showing an example of a semiconductor device. Figure 3 is a cross-sectional view showing an example of a semiconductor device. Figure 4 is a cross-sectional view showing an example of a semiconductor device. Figure 5 is a cross-sectional view showing an example of a semiconductor device. Figure 6 is a cross-sectional view showing an example of a semiconductor device. Figure 7 is a cross-sectional view showing an example of a semiconductor device. Figure 8 is a cross-sectional view showing an example of a semiconductor device. Figure 9 is a cross-sectional view showing an example of a semiconductor device. Figure 10 is a cross-sectional view showing an example of a semiconductor device. Figure 11 is a cross-sectional view showing an example of a semiconductor device. Figures 12A and 12B are top views showing an example of a semiconductor device. Figures 13A to 13D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figures 14A to 14C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figures 15A and 15B are cross-sectional views showing an example of a semiconductor device manufacturing method. Figures 16A and 16B are cross-sectional views showing an example of a semiconductor device manufacturing method. Figures 17A and 17B are cross-sectional views showing an example of a semiconductor device manufacturing method. Figures 18A and 18B are cross-sectional views showing an example of a semiconductor device fabrication method. Figures 19A and 19B show examples of storage devices. Figures 20A and 20B are circuit diagrams showing an example of a memory layer. Figure 21 is a timing chart illustrating an example of memory cell operation. Figures 22A and 22B are circuit diagrams illustrating an example of memory cell operation. Figures 23A and 23B are circuit diagrams illustrating an example of memory cell operation. Figure 24 is a circuit diagram illustrating an example of a semiconductor device configuration. Figures 25A and 25B show examples of semiconductor devices. Figures 26A and 26B show examples of electronic components. Figures 27A to 27J show examples of electronic devices. Figures 28A to 28E show examples of electronic devices. Figures 29A to 29C show examples of electronic devices. Figure 30 shows an example of space equipment. [Modes for carrying out the invention]

[0023] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Accordingly, the present invention shall not be construed as being limited to the descriptions of the embodiments shown below.

[0024] In the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the hatching patterns are the same, and reference numerals may not be assigned.

[0025] Furthermore, for the sake of ease of understanding, the position, size, and scope of each component shown in the drawings may not represent their actual position, size, and scope. Therefore, the disclosed invention is not necessarily limited to the position, size, and scope disclosed in the drawings.

[0026] In this specification, the ordinal numbers "first," "second," etc., are used for convenience only and do not limit the number of components or the order of components (for example, process order or stacking order). Furthermore, the ordinal numbers used for components in one part of this specification may not be the same as those used for the same components in other parts of this specification or in the claims.

[0027] It should be noted that the terms "film" and "layer" can be interchanged depending on the context or situation. For example, the term "conductive layer" can be changed to "conductive film." Or, for example, the term "insulating film" can be changed to "insulating layer."

[0028] (Embodiment 1) In this embodiment, a semiconductor device according to one aspect of the present invention will be described with reference to Figures 1 to 18.

[0029] A semiconductor device according to one aspect of the present invention has a first transistor, a second transistor, and a first insulator on an insulating surface, the first transistor and the second transistor each share a first metal oxide on the first insulator and a first conductor on the first metal oxide, the first transistor has a second conductor and a second insulator on the first metal oxide and a third conductor on the second insulator, and the second transistor has a fourth conductor on the first metal oxide The material comprises a third insulator and a fifth conductor on the third insulator, wherein the side surface of the first insulator has a portion in contact with the fourth conductor, the end of the fourth conductor has a portion located outside the end of the first insulator, the second insulator is located between the first conductor and the second conductor, the metal oxide and the third conductor overlap via the second insulator, the third insulator is located between the first conductor and the fourth conductor, and the metal oxide and the fifth conductor overlap via the third insulator.

[0030] The metal oxide functions as the channel-forming region of the first transistor and also as the channel-forming region of the second transistor. The first conductor functions as the source or drain of the first transistor and also as the source or drain of the second transistor.

[0031] By having the first and second transistors adjacent to each other and sharing a metal oxide and the first conductor, two transistors can be formed in an area smaller than the area of ​​two transistors combined (for example, the area of ​​1.5 transistors). This allows for high-density arrangement of transistors, enabling high integration in semiconductor devices. For example, it can be used for high integration in memory devices such as various types of memory.

[0032] A semiconductor device according to one aspect of the present invention has a transistor (OS transistor) having a metal oxide in the channel formation region. Because the OS transistor has a small off-current, it can retain stored data for a long period of time when used in a memory device. In other words, it does not require a refresh operation, or the refresh operation is performed very infrequently, so the power consumption of the memory device can be significantly reduced. Furthermore, because the OS transistor has a high frequency characteristic, reading and writing to the memory device can be performed at high speed.

[0033] A semiconductor device according to one aspect of the present invention comprises a first transistor, a second transistor, a third transistor, a first insulator, a second insulator, a third insulator, and a capacitive element, wherein the first transistor and the second transistor each share a first metal oxide on the first insulator and a first conductor on the first metal oxide, the first transistor comprises a second conductor and a fourth insulator on the first metal oxide and a third conductor on the fourth insulator, the second transistor comprises a fourth conductor and a fifth insulator on the first metal oxide and a fifth conductor on the fifth insulator, and the third transistor comprises a second metal oxide, a sixth conductor, a seventh conductor, and a sixth insulator on the second metal oxide, and a sixth insulator The capacitive element has an eighth conductor on top, and a ninth conductor, a seventh insulator on the ninth conductor, and a tenth conductor on the seventh insulator, the side surface of the first insulator has a portion in contact with the fourth conductor, the end of the fourth conductor has a portion located outside the end of the first insulator, the second insulator is located on the first transistor and the second transistor, and the second conductor and the sixth conductor are electrically connected through an opening provided in the second insulator, the third insulator is located on the third transistor, the portion on the third insulator where the ninth conductor, the seventh insulator and the tenth conductor overlap is located, and the sixth conductor and the ninth conductor are electrically connected through an opening provided in the third insulator.

[0034] An opening can include, for example, grooves and slits. Furthermore, the area in which an opening is formed may also be referred to as an opening.

[0035] Furthermore, in the drawings used in this embodiment, the side wall of the insulator at the opening of the insulator is shown to be approximately perpendicular to the substrate surface or the surface to be formed, but it may also be tapered.

[0036] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle between the inclined side surface and the substrate surface or the surface to be formed (hereinafter sometimes referred to as the taper angle) is less than 90°. The side surface of the structure and the substrate surface do not necessarily have to be perfectly flat, and may be substantially planar with fine curvature, or substantially planar with fine irregularities.

[0037] One embodiment of the present invention is not limited to a configuration in which all transistors constituting a single circuit are formed on the same plane, but can also have a two-stage structure in which the remaining transistors are placed on top of some of the transistors. This allows for a high-density arrangement of transistors, enabling high integration in semiconductor devices. For example, it can be used for high integration in memory devices such as various types of memory.

[0038] Furthermore, in a memory device to which one aspect of the present invention is applied, a configuration can be applied in which a part of the upper surface and a part of the side surface of the fourth conductor are in direct contact with the write and read bit lines. Similarly, in a semiconductor device according to one aspect of the present invention, a configuration can be applied in which a part of the upper surface and a part of the side surface of the ninth conductor are in direct contact with the write and read bit lines. With such a configuration, it is not necessary to provide separate connecting electrodes between the fourth or ninth conductor and the write and read bit lines, and the integration density of memory cells can be increased.

[0039] <Example of cross-sectional configuration of a semiconductor device 1> An example of a cross-sectional configuration of a semiconductor device according to one embodiment of the present invention will be described with reference to Figures 1 to 8.

[0040] In Figures 1 to 8, the X direction is parallel to the channel length direction of the illustrated transistor, the Y direction is perpendicular to the X direction, and the Z direction is perpendicular to both the X and Y directions.

[0041] The semiconductor device shown in Figure 1 includes an insulator 210, a conductor 209 embedded in the insulator 210, an insulator 212 on the insulator 210, an insulator 214 on the insulator 212, n layers (where n is an integer of 1 or more) of layers 11 (the first layer 11_1 to the nth layer 11_n) on the insulator 214, a conductor 240 (conductor 240a and conductor 240b) extending in the Z direction so as to penetrate the n layers 11 and electrically connected to the conductor 209, an insulator 281 on the nth layer 11_n, an insulator 283 on the insulator 281 and the conductor 240, and an insulator 285 on the insulator 283. The components of the semiconductor device in this embodiment may each have a single-layer structure or a multilayer structure.

[0042] The conductor 209 functions as part of a circuit element such as a switch, transistor, capacitive element, inductor, resistor, and diode, as well as as wiring, an electrode, or a terminal.

[0043] Figure 1 shows the n layers of the n-layer structure 11, specifically the bottommost layer 11_1, the second layer 11_2 above the first layer 11_1, and the topmost layer, the nth layer 11_n.

[0044] The semiconductor device of this embodiment can be used as a memory cell (or memory cell array) of a storage device. Each of the n layers 11 corresponds to the storage layer 60 in the storage device described in Embodiment 2. Each of the n layers 11 is provided with a memory cell array having multiple memory cells. The conductor 209 is electrically connected to a drive circuit provided below the conductor 209 for driving the memory cells. By increasing the number of stacked storage layers 60 (increasing the value of n), the storage capacity of the storage device can be increased without increasing the area occupied by the memory cells. Therefore, the area occupied per bit is reduced, and a compact storage device with a large storage capacity can be realized.

[0045] Since each layer of the n-layer structure 11 has a similar configuration, this embodiment will mainly describe the first layer 11_1 as an example.

[0046] The first layer 11_1 has transistors 201a, 201b, 202a, 202b, 203a, 203b, and capacitive elements 101a, 101b.

[0047] The first layer 11_1 is symmetrical in its configuration on the right and left sides, with respect to the conductor 240. That is, in Figure 1, transistors 201a and 201b are symmetrical, transistors 202a and 202b are symmetrical, transistors 203a and 203b are symmetrical, and capacitive elements 101a and 101b are symmetrical. In this embodiment, the configuration on the left side of the first layer 11_1 (transistors 201a, 202a, 203a, and capacitive element 101a) will be used as an example for explanation.

[0048] Transistors 202a and 203a are provided on an insulator 214 and share some layers. The gate of transistor 202a and the source or drain of transistor 201a are electrically connected via a conductor provided on transistor 202a. In addition, one electrode (lower electrode) of a capacitive element 101a is physically and electrically connected to the source or drain of transistor 201a. Furthermore, the other electrode (upper electrode) of the capacitive element 101a on the first layer 11_1 is electrically connected to the source or drain of transistor 202a on the second layer 11_2.

[0049] Thus, the first layer 11_1 can be said to have a configuration in which two layers on which transistors are provided are stacked. Specifically, the first layer 11_1 has transistors 202a and 203a in the first stage (lower stage), and transistor 201a and capacitive element 101a in the second stage (upper stage). By stacking two layers on which transistors are provided, the integration density can be increased.

[0050] The semiconductor device shown in Figure 2 is a modified version of the semiconductor device shown in Figure 1. In Figure 1, an example is shown in which the source or drain of transistor 202a is electrically connected to the conductor 265c, but as shown in Figure 2, a configuration without the conductor 265c is also possible. In this case, it is preferable to route the source or drain of transistor 202a in the Y direction, as this makes it easier to supply a desired potential (e.g., ground potential).

[0051] The semiconductor device shown in Figure 3 is a modified version of the semiconductor device shown in Figure 1. Specifically, Figure 3 uses a conductor 263 that functions as a contact plug for electrically connecting the gate of transistor 202a and the source or drain of transistor 201a. Also in Figure 3, a conductor 231 that functions as a contact plug for electrically connecting the other electrode (upper electrode) of the capacitive element 101a of the first layer 11_1 and the source or drain of transistor 202a of the second layer 11_2. The conductor 231 is embedded inside an opening provided in the insulator 232 located on the capacitive element 101a. Thus, the method of electrically connecting two conductors located above and below each other is not particularly limited, and various configurations can be applied.

[0052] Figure 3 also shows an example where the insulators 212 and 214 are in contact with the conductor 240.

[0053] Next, we will explain transistors 202a and 203a in detail using Figure 4.

[0054] The transistor 202a includes a conductor 265b (conductor 265b1 and conductor 265b2) provided on an insulator 214, an insulator 272 on the conductor 265b, an insulator 274 on the insulator 272, an oxide 220 (oxide 220a and oxide 220b) on the insulator 274, a conductor 252b (conductor 252b1 and conductor 252b2) covering a part of the side surface of the insulator 274, and a part of the top surface and part of the side surface of the oxide 220, a conductor 252c (conductor 252c1 and conductor 252c2) on the oxide 220, an insulator 243b on the oxide 220, an insulator 244b on the insulator 243b, and a conductor 270b (conductor 270b1 and conductor 270b2) on the insulator 244b.

[0055] The transistor 203a includes a conductor 265a (conductor 265a1 and conductor 265a2) provided on an insulator 214, an insulator 272 on the conductor 265a, an insulator 274 on the insulator 272, an oxide 220 on the insulator 274, a conductor 252a (conductor 252a1 and conductor 252a2) covering a part of the side surface of the insulator 274, and a part of the top surface and part of the side surface of the oxide 220, a conductor 252c on the oxide 220, an insulator 243a on the oxide 220, an insulator 244a on the insulator 243a, and a conductor 270a (conductor 270a1 and conductor 270a2) on the insulator 244a.

[0056] The conductors 265a and 265b are embedded inside openings provided in the insulator 266. An insulator 276 is provided on the conductors 252a, 252b, and 252c, and an insulator 290 is provided on the insulator 276. The insulators 243a, 243b, 244a, 244b, and the conductors 270a and 270b are embedded inside openings provided in the insulator 290 and the insulator 276.

[0057] The oxide 220 has a region that functions as a channel formation region for transistor 202a and a region that functions as a channel formation region for transistor 203a.

[0058] Conductor 252a has a region that functions as either the source electrode or the drain electrode of transistor 203a. Conductor 252b has a region that functions as either the source electrode or the drain electrode of transistor 202a. Conductor 252c has a region that functions as the other source electrode or drain electrode of transistor 202a and a region that functions as the other source electrode or drain electrode of transistor 203a. It can also be said that conductor 252c functions as the other source electrode or drain electrode of transistor 202a and as the other source electrode or drain electrode of transistor 203a.

[0059] The conductor 270a has a region that functions as the first gate electrode of transistor 203a. The insulators 243a and 244a each have a region that functions as the first gate insulator of transistor 203a.

[0060] The conductor 270b has a region that functions as the first gate electrode of transistor 202a. The insulators 243b and 244b each have a region that functions as the first gate insulator of transistor 202a.

[0061] Conductor 265a has a region that functions as the second gate electrode of transistor 203a. Conductor 265b has a region that functions as the second gate electrode of transistor 202a. Insulators 272 and 274 each have a region that functions as the second gate insulator of transistor 202a and a region that functions as the second gate insulator of transistor 203a, respectively.

[0062] Transistors 202a and 203a are adjacent to each other and share oxide 220 and conductor 252c, respectively. This allows two transistors (transistors 202a and 203a) to be formed in an area smaller than the area of ​​two transistors (for example, the area of ​​1.5 transistors). This enables high-density arrangement of transistors and achieves high integration in semiconductor devices.

[0063] Furthermore, as shown in region 250 of Figure 4, a conductor 252c is placed in the region between conductors 270a and 270b. Therefore, an n-type region (low-resistance region) can be formed in the region of oxide 220 (especially oxide 220b) that overlaps with the conductor 252c. In addition, current can be passed between transistors 202a and 203a via the conductor 252c. Thus, compared to a configuration in which two transistors using silicon in the semiconductor layer where the channel is formed (also called Si transistors) are connected in series, the resistance component between transistors 202a and 203a can be made extremely small.

[0064] The configurations of transistors 202a and 203a are the same as those of transistor 201a, except that they share oxide 220 and conductor 252c. Furthermore, the materials and manufacturing methods applicable to transistors 202a and 203a are also the same as those for transistor 201a. Therefore, the materials and manufacturing methods for the transistors in this embodiment will be described together with the description of transistor 201a later.

[0065] Figure 5 shows an enlarged view of the configuration of the left half of the first layer 11_1 in Figure 3 (the conductor 240 and the configuration shown to the left of it).

[0066] As shown in Figure 5, transistors 202a and 203a are provided on the insulator 214. The conductor 252b of transistor 202a is electrically connected to the conductor 265c (conductor 265c1 and conductor 265c2).

[0067] Furthermore, an insulator 262 is provided on the insulator 290, on the transistor 202a, and on the transistor 203a, and an insulator 264 is provided on the insulator 262. Conductors 263 (conductors 263a and 263b) are provided inside the openings provided in the insulators 262 and 264. Then, a transistor 201a and a capacitive element 101a are provided on the insulator 264.

[0068] The transistor 201a includes a conductor 205a (conductor 205a1 and conductor 205a2) provided on an insulator 264, an insulator 222 on the conductor 205a, an insulator 224 on the insulator 222, an oxide 230 (oxide 230a and oxide 230b) on the insulator 224, and conductors 242a (conductor 242a1 and conductor 242a2) and conductors 242b (conductor 242b1 and conductor 242b2) covering a part of the side surface of the insulator 224 and a part of the top surface and part of the side surface of the oxide 230, respectively, an insulator 253 on the oxide 230, an insulator 254 on the insulator 253, and a conductor 260 (conductor 260a and conductor 260b) on the insulator 254.

[0069] Conductors 205a and 205b are embedded inside openings provided in the insulator 216. An insulator 275 is provided on conductors 242a and 242b, and an insulator 280 is provided on insulator 275. Insulators 253, 254, and conductor 260 are embedded inside openings provided in insulators 280 and insulator 275. An insulator 282 is provided on insulator 280 and on conductor 260.

[0070] The oxide 230 has a region that functions as a channel formation region for transistor 201a.

[0071] Conductor 242a has a region that functions as either the source electrode or the drain electrode of transistor 201a. Conductor 242b has a region that functions as either the source electrode or the drain electrode of transistor 201a.

[0072] The conductor 260 has a region that functions as the first gate electrode of transistor 201a. The insulators 253 and 254 each have a region that functions as the first gate insulator of transistor 201a.

[0073] The conductor 205a has a region that functions as the second gate electrode of transistor 201a. The insulators 222 and 224 each have a region that functions as the second gate insulator of transistor 201a.

[0074] The conductor 242b of transistor 201a is electrically connected to the conductor 270b of transistor 202a. Specifically, the conductor 242b is electrically connected to the conductor 270b via the conductor 205b (conductors 205b1 and 205b2) and the conductor 263.

[0075] The capacitive element 101a includes a conductor 153 on the conductor 242b, an insulator 154 on the conductor 153, and a conductor 160 (conductor 160a and conductor 160b) on the insulator 154.

[0076] At least a portion of the conductor 153, the insulator 154, and the conductor 160 are arranged inside openings provided in the insulators 275, 280, and 282. The respective ends of the conductor 153, 154, and 160 are located on the insulator 282. The insulator 154 is provided so as to cover the end of the conductor 153. This allows for electrical isolation between the conductor 153 and the conductor 160. The deeper the openings provided in the insulators 275, 280, and 282 are (i.e., the thicker one or more of the insulators 275, 280, and 282 are), the larger the capacitance of the capacitive element 101a can be. By increasing the capacitance per unit area of ​​the capacitive element 101a, miniaturization or high integration of the semiconductor device can be achieved.

[0077] Conductors 231 (conductors 231a and 231b) are provided on the conductor 160, thereby enabling electrical connection between the conductor 160 and the source or drain of the transistor 202a above. As shown in Figure 1, it is also possible to electrically connect the conductor 160 and the source or drain of the transistor 202a above without using the conductor 231.

[0078] The conductor 153 has a region that functions as one electrode (lower electrode) of the capacitive element 101a. The insulator 154 has a region that functions as the dielectric of the capacitive element 101a. The conductor 160 has a region that functions as the other electrode (upper electrode) of the capacitive element 101a. The capacitive element 101a constitutes a MIM (Metal-Insulator-Metal) capacitance.

[0079] The conductor 242a, which includes a region that functions as either the source or drain electrode of transistor 201a, extends beyond the oxide 230, which functions as a semiconductor layer. Thus, the conductor 242a also functions as wiring. For example, in Figure 5, portions of the top, side, and bottom surfaces of the conductor 242a are electrically connected to the conductor 240, which extends in the Z direction.

[0080] Similarly, the conductor 252a, which includes a region that functions as either the source or drain electrode of transistor 203a, extends beyond the oxide 220, which functions as a semiconductor layer. Thus, the conductor 252a also functions as wiring. For example, in Figure 5, portions of the top, side, and bottom surfaces of the conductor 252a are electrically connected to the conductor 240, which extends in the Z direction.

[0081] Since the conductor 240 is in direct contact with at least one of the top, side, and bottom surfaces of the conductor 242a and at least one of the top, side, and bottom surfaces of the conductor 252a, there is no need to provide separate connecting electrodes, thus reducing the occupied area of ​​the memory cell array. In addition, the integration density of memory cells is improved, and the storage capacity can be increased. It is preferable that the conductor 240 is in contact with two or more of the top, side, and bottom surfaces of the conductor 242a. Similarly, it is preferable that the conductor 240 is in contact with two or more of the top, side, and bottom surfaces of the conductor 252a. By having the conductor 240 in contact with multiple surfaces of the conductor 242a or conductor 252a, the contact resistance between the conductor 240 and the conductor 242a or conductor 252a can be reduced.

[0082] Figure 6 shows an enlarged view of the region where conductor 240 and conductor 242a are in contact and its vicinity. As shown in Figure 6, conductor 240 has a region having width W1 and a region having width W2. Width W1 corresponds to the distance between conductor 242a on transistor 201a and conductor 242a on transistor 201b. Width W2 corresponds, for example, to the distance between the interface between insulator 280 and conductor 240a on transistor 201a and the interface between insulator 280 and conductor 240a on transistor 201b.

[0083] As shown in Figure 6, it is preferable that the width W2 is greater than the width W1. In this configuration, the conductor 240 is in contact with at least a portion of the upper surface and a portion of the side surface of the conductor 242a. Therefore, the area of ​​the region in contact between the conductor 240 and the conductor 242a can be increased. In this specification, the contact between the conductor 240 and the conductor 242a is sometimes referred to as top-side contact. Also, as shown in Figure 6, the conductor 240 may be in contact with a portion of the lower surface of the conductor 242a. This configuration allows for an even greater increase in the area of ​​the region in contact between the conductor 240 and the conductor 242a.

[0084] Furthermore, the same applies to the region where conductor 240 and conductor 252a are in contact, and to the vicinity thereof, as explained using Figure 6.

[0085] Furthermore, in Figure 5, the end of insulator 262 is located inward from the respective ends of insulators 266, 290, 264, 216, 280, 284, and 232. Similarly, the end of insulator 282 is located inward from the respective ends of insulators 266, 290, 264, 216, 280, 284, and 232. Thus, in a cross-sectional view, a configuration can be applied in which the ends of insulator 262 and insulator 282 are located inward from one or more ends of insulators 266, 290, 264, 216, 280, 284, and 232.

[0086] The insulators 266, 290, 264, 216, 280, 284, and 232 each function as interlayer films. For example, it is preferable that the insulators 266, 290, 264, 216, 280, 284, and 232 each have one or both of silicon oxide and silicon oxynitride.

[0087] In this specification, "oxide nitride" refers to a material in which the oxygen content is greater than the nitrogen content, and "nitride oxide" refers to a material in which the nitrogen content is greater than the oxygen content. For example, when "silicon oxynitride" is written, it refers to a material in which the oxygen content is greater than the nitrogen content, and when "silicon nitride oxide" is written, it refers to a material in which the nitrogen content is greater than the oxygen content.

[0088] On the other hand, it is preferable that insulators 262 and 282 function as barrier insulators for the transistor. For example, it is preferable that insulators 262 and 282 each contain either or both aluminum oxide and hafnium oxide.

[0089] In this specification, a barrier insulator refers to an insulator that possesses barrier properties. In this specification, barrier properties refer to the function of suppressing the diffusion of the corresponding substance (also known as low permeability), or the function of capturing and fixing the corresponding substance (also known as gettering).

[0090] In this context, aluminum oxide and hafnium oxide can be more difficult to etch than silicon oxide or silicon oxide / nitride. It can also be said that aluminum oxide and hafnium oxide are both difficult-to-etch materials.

[0091] In the manufacturing process of the semiconductor device of this embodiment, it is necessary to create openings in the laminated structure of the insulators before providing the conductor 240. At this time, it may be difficult to process insulators 262 and 282 with the same etching gas as insulators 266, 290, 264, 216, 280, and 284. Therefore, in one embodiment of the semiconductor device manufacturing method of the present invention, the manufacturing process for insulator 262 and insulator 282 each involve a film deposition process followed by a processing process, and then proceeding to the manufacturing process of the next layer (film deposition process, etc.). In the processing process for the laminated structure of the insulators immediately before providing the conductor 240, openings are provided in insulators 266, 290, 264, 216, 280, and 284, which are made of materials that are easier to etch than insulators 262 and 282. In this way, by pre-opening insulators made of difficult-to-etch materials and opening other insulators all at once before providing the conductor 240, the process margin can be increased. Furthermore, it is possible to improve the yield in forming each aperture and enhance the productivity of semiconductor devices.

[0092] Furthermore, in Figure 5, etc., recesses are provided in the region of insulator 280 that does not overlap with insulator 282, and in the region of insulator 290 that does not overlap with insulator 262. Depending on the etching conditions of insulator 282 or insulator 262, a portion of insulator 280 or insulator 290 may be removed during processing of insulator 282 or insulator 262, forming a recess. Note that insulator 280 and insulator 290 do not necessarily have recesses.

[0093] In Figure 7, the end of insulator 262 is located outside the respective ends of insulators 266, 290, 264, 216, 280, 284, and 232. Similarly, the end of insulator 282 is located outside the respective ends of insulators 266, 290, 264, 216, 280, 284, and 232. Thus, a configuration can be applied in which the ends of insulator 262 and insulator 282 are located outside one or more of the ends of insulators 266, 290, 264, 216, 280, 284, and 232.

[0094] Here, as shown in Figure 1, when an opening for the conductor 240 is provided in the insulator layer structure after stacking n layers of memory cells, it is necessary to make a deep opening, which can make it difficult to keep the width of the opening (also called the opening diameter; in Figure 1, it corresponds to the length in the X-axis direction) constant. For example, the width on the upper side of the opening (the nth layer side) tends to be wider, and the width on the lower side of the opening (the first layer side) tends to be narrower. Here, if the ends of the insulator 262 and the ends of the insulator 282 are provided to protrude into the interior of the opening, it is possible to suppress excessive etching of the opening. This can suppress variations in the opening diameter. In addition, it is possible to ensure a sufficient width at the bottom of the opening while preventing the width of the upper part of the opening from becoming too wide.

[0095] Figures 7 and 8 show examples where the ends of insulator 262 and insulator 282 are aligned with, or approximately aligned with, the ends of conductor 242a and conductor 252a. Figure 8 also shows an example where the ends of insulator 272 and insulator 222 are approximately aligned with the ends of conductor 242a and conductor 252a. The semiconductor device according to one embodiment of the present invention is not limited to these configurations. For example, the ends of insulators 272, 222, 262, and 282 may be located outside or inside one or both of the ends of conductor 242a and conductor 252a.

[0096] Furthermore, if the edges are aligned or roughly aligned in a cross-sectional view, and the top surface shapes match or roughly match, then in a top view, at least a portion of the contours overlaps between the stacked layers. Such cases include, for example, when the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and a portion of the upper layer may be located inside the lower layer, or a portion of the upper layer may be located outside the lower layer; in this case as well, the edges are said to be roughly aligned, or the top surface shapes roughly match.

[0097] In Figure 5, the ends of insulator 222 and insulator 272 are located inward from the respective ends of insulators 266, 290, 264, 216, 280, 284, and 232. The configuration of insulators 222 and 272 is not limited to this. For example, in Figure 8, the ends of insulator 222 and insulator 272 are located outward from the respective ends of insulators 266, 290, 264, 216, 280, 284, and 232.

[0098] As shown in Figure 5, when the end of the insulator 272 is located inward from the end of the conductor 252a, the conductor 240 can be configured to be in contact with the top, side, and bottom surfaces of the conductor 252a, thereby reducing the contact resistance between the conductor 240 and the conductor 252a. Similarly, when the end of the insulator 222 is located inward from the end of the conductor 242a, the conductor 240 can be configured to be in contact with the top, side, and bottom surfaces of the conductor 242a, thereby reducing the contact resistance between the conductor 240 and the conductor 242a.

[0099] Furthermore, in Figure 5, etc., recesses are provided in the region of insulator 216 that does not overlap with insulator 222, and in the region of insulator 266 that does not overlap with insulator 272. Depending on the etching conditions of insulator 222 or insulator 272, a portion of insulator 216 or insulator 266 may be removed during processing of insulator 222 or insulator 272, forming a recess. Note that insulator 216 and insulator 266 do not necessarily have recesses.

[0100] Furthermore, as shown in Figure 8, if the end of the insulator 272 is roughly aligned with the end of the conductor 252a, or is located outside the end of the conductor 252a, the insulator 266 can be configured without a recess in the completed semiconductor device. Similarly, if the end of the insulator 222 is roughly aligned with the end of the conductor 242a, or is located outside the end of the conductor 242a, the insulator 216 can be configured without a recess in the completed semiconductor device. Recesses provided in insulators are prone to shape variations. Therefore, by eliminating recesses in the insulators 266 and 216, variations in the shape of the semiconductor device can be reduced.

[0101] Furthermore, although the above examples illustrate a configuration in which the insulator 282 is pre-opened, the methods for realizing the configurations shown in Figures 5, 7, and 8 are not limited to these. For example, if the etching rates of the insulator 282 and the insulator 280 are different, even if they are opened at once, the ends of the insulator 282 and the insulator 280 may not be aligned in a cross-sectional view. For example, it may be possible to open the insulator 282 and the insulator 280 at once to form the insulator 280 and insulator 282 with the shape shown in Figure 7. A semiconductor device manufactured by such a method is also included in one aspect of the present invention.

[0102] Other materials that can be used for insulators 262, 282, 266, 290, 264, 216, 280, and 284 will be described later.

[0103] Next, the transistors in the semiconductor device of this embodiment will be described in detail.

[0104] In the following explanation, we will mainly use the components of transistor 201a as examples, but the explanations can also be applied to the components of transistors 202a and 203a. That is, for example, the explanations for conductor 205, insulator 222, insulator 224, oxide 230, conductor 242, insulator 253, insulator 254, and conductor 260 can also be applied to conductor 265, insulator 272, insulator 274, oxide 220, conductor 252, insulator 243, insulator 244, and conductor 270, respectively.

[0105] Preferably, the oxide 230 has oxide 230a on the insulator 224 and oxide 230b on oxide 230a. By having oxide 230a below oxide 230b, the diffusion of impurities from structures formed below oxide 230a to oxide 230b can be suppressed.

[0106] In this embodiment, the oxide 230 is shown as having a two-layer structure of oxide 230a and oxide 230b, but it is not limited to this. For example, oxide 230 may have a single-layer structure of oxide 230b, or it may have a laminated structure of three or more layers.

[0107] The oxide 230b has a channel-forming region in the transistor 201a, and a source region and a drain region provided so as to sandwich the channel-forming region. At least a portion of the channel-forming region overlaps with the conductor 260. Of the source region and the drain region, one overlaps with the conductor 242a, and the other overlaps with the conductor 242b.

[0108] The channel-forming region is a high-resistance region with a lower carrier concentration due to fewer oxygen vacancies or lower impurity concentrations compared to the source and drain regions. Therefore, the channel-forming region can be said to be type i (intrinsic) or substantially type i.

[0109] Further, the source region and the drain region are low-resistance regions with a high carrier concentration because they have a large amount of oxygen deficiency or a high impurity concentration such as hydrogen, nitrogen, and metal elements. That is, the source region and the drain region are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region.

[0110] Note that the carrier concentration in the channel formation region is 1×10 18 cm -3 or less, 1×10 17 cm -3 or less, 1×10 16 cm -3 or less, 1×10 15 cm -3 or less, 1×10 14 cm -3 or less, 1×10 13 cm -3 or less, 1×10 12 cm -3 or less, 1×10 11 cm -3 or less, or 1×10 10 cm -3 or less, which is preferable. Regarding the lower limit value of the carrier concentration in the channel formation region, there is no particular limitation. For example, it can be 1×10 -9 cm -3 .

[0111] Note that when reducing the carrier concentration of the oxide 230b, the impurity concentration in the oxide 230b is reduced and the defect level density is reduced. In this specification and the like, having a low impurity concentration and a low defect level density is referred to as high purity intrinsic or substantially high purity intrinsic. Note that an oxide semiconductor (or metal oxide) with a low carrier concentration may be referred to as a high purity intrinsic or substantially high purity intrinsic oxide semiconductor (or metal oxide).

[0112] To stabilize the electrical characteristics of transistor 201a, it is effective to reduce the impurity concentration in oxide 230b. Furthermore, in order to reduce the impurity concentration in oxide 230b, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that impurities in oxide 230b refer to elements other than the main components that make up oxide 230b. For example, elements with a concentration of less than 0.1 atomic percent can be considered impurities.

[0113] Furthermore, the channel-forming region, source region, and drain region may each have oxide 230a formed in addition to oxide 230b.

[0114] Furthermore, in oxide 230, it may be difficult to clearly detect the boundaries between each region. The concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen, detected within each region may not be limited to stepwise changes between regions, but may also change continuously within each region. In other words, the closer a region is to the channel formation region, the lower the concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen may be.

[0115] For oxide 230 (oxide 230a and oxide 230b), it is preferable to use a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor).

[0116] The band gap of the metal oxide that functions as a semiconductor is preferably 2 eV or more, and more preferably 2.5 eV or more. By using a metal oxide with a large band gap, the off-current of the transistor can be reduced.

[0117] As oxide 230, it is preferable to use a metal oxide such as indium oxide, gallium oxide, and zinc oxide. Alternatively, as oxide 230, it is preferable to use a metal oxide having two or three elements selected from indium, element M, and zinc. Element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. In particular, it is preferable that element M is one or more selected from aluminum, gallium, yttrium, and tin. A metal oxide having indium, element M, and zinc may be referred to as In-M-Zn oxide.

[0118] The oxide 230 preferably has a laminated structure of multiple oxide layers with different chemical compositions. For example, in the metal oxide used for oxide 230a, it is preferable that the atomic ratio of element M to the main metal element is greater than the atomic ratio of element M to the main metal element in the metal oxide used for oxide 230b. Furthermore, in the metal oxide used for oxide 230a, it is preferable that the atomic ratio of element M to In is greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b. This configuration suppresses the diffusion of impurities and oxygen from structures formed below oxide 230a to oxide 230b.

[0119] Furthermore, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 230b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a. With this configuration, transistor 201a can obtain a large on-current and high frequency characteristics.

[0120] Furthermore, because oxides 230a and 230b share a common element other than oxygen as their main component, the defect level density at the interface between oxides 230a and 230b can be reduced. As a result, the influence of interfacial scattering on carrier conduction is reduced, and transistor 201a can obtain a large on-current and high frequency characteristics.

[0121] Specifically, as oxide 230a, a metal oxide with a composition of In:M:Zn=1:3:4 [atomic ratio] or close to it, or In:M:Zn=1:1:0.5 [atomic ratio] or close to it can be used. Furthermore, as oxide 230b, a metal oxide with a composition of In:M:Zn=1:1:1 [atomic ratio] or close to it, In:M:Zn=1:1:1.2 [atomic ratio] or close to it, In:M:Zn=1:1:2 [atomic ratio] or close to it, or In:M:Zn=4:2:3 [atomic ratio] or close to it can be used. Note that "close to it" includes a range of ±30% of the desired atomic ratio. Also, it is preferable to use gallium as element M. Furthermore, when a single layer of oxide 230b is provided as oxide 230, a metal oxide that can be used for oxide 230a may be applied as oxide 230b.

[0122] Furthermore, when depositing metal oxide films by sputtering, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide film, but may also be the atomic ratio of the sputtering target used for depositing the metal oxide film.

[0123] It is preferable that oxide 230b is crystalline. In particular, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) as oxide 230b.

[0124] CAAC-OS is a metal oxide with a highly crystalline, dense structure and few impurities and defects (e.g., oxygen vacancies). In particular, by heat-treating the metal oxide after its formation at a temperature that does not cause polycrystallization of the metal oxide (e.g., between 400°C and 600°C), the CAAC-OS can be made to have an even more crystalline and dense structure. By increasing the density of CAAC-OS in this way, the diffusion of impurities or oxygen within the CAAC-OS can be further reduced.

[0125] Furthermore, because it is difficult to identify clear grain boundaries in CAAC-OS, a decrease in electron mobility due to grain boundary issues is less likely to occur. Therefore, metal oxides containing CAAC-OS have stable physical properties. Consequently, metal oxides containing CAAC-OS are highly heat-resistant and reliable.

[0126] Furthermore, by using a crystalline oxide such as CAAC-OS as oxide 230b, the extraction of oxygen from oxide 230b by the source electrode or drain electrode can be suppressed. As a result, even when heat treatment is performed, the extraction of oxygen from oxide 230b is reduced, making transistor 201a stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0127] In transistors using oxide semiconductors, the electrical properties tend to fluctuate and reliability may be poor if impurities and oxygen vacancies are present in the region where the channel is formed in the oxide semiconductor. Furthermore, hydrogen near the oxygen vacancy can fill the oxygen vacancy, creating a defect (hereinafter referred to as V). O Oxygen vacancies (sometimes called H) can form and generate electron carriers. Therefore, if the region where channels are formed in an oxide semiconductor contains oxygen vacancies, the transistor is likely to exhibit normally-on characteristics (a characteristic in which channels exist and current flows through the transistor even without applying voltage to the gate electrode). Consequently, in the region where channels are formed in an oxide semiconductor, impurities, oxygen vacancies, and V are likely to be present. OIt is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where the channel is formed has a reduced carrier concentration and is type i (intrinsed) or substantially type i.

[0128] In contrast, by placing an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen is supplied from the insulator to the oxide semiconductor, eliminating oxygen deficiencies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source or drain region, it may cause a decrease in the on-current or field-effect mobility of transistor 201a. Furthermore, variations in the amount of oxygen supplied to the source or drain region within the substrate surface will result in variations in the characteristics of the semiconductor device containing the transistor. In addition, if the oxygen supplied from the insulator to the oxide semiconductor diffuses into conductors such as the gate electrode, source electrode, and drain electrode, these conductors may oxidize, impairing their conductivity and potentially adversely affecting the electrical characteristics and reliability of the transistor.

[0129] Therefore, in oxide semiconductors, the channel formation region is preferably i-type or substantially i-type with reduced carrier concentration, while the source and drain regions are preferably n-type with high carrier concentration. In other words, oxygen vacancies in the channel formation region of oxide semiconductors, and V O It is preferable to reduce H. Also, ensure that an excessive amount of oxygen is not supplied to the source region and drain region, and that the V of the source region and drain region is not reduced. O It is preferable to prevent an excessive reduction in the amount of H. Furthermore, it is preferable to have a configuration that suppresses a decrease in the conductivity of conductors 260, 242a, and 242b. For example, it is preferable to have a configuration that suppresses oxidation of conductors 260, 242a, and 242b. Note that hydrogen in oxide semiconductors is V. O Since H can be formed, V O To reduce the amount of H, it is necessary to reduce the hydrogen concentration.

[0130] Therefore, in this embodiment, the semiconductor device is configured to reduce the hydrogen concentration in the channel formation region, suppress oxidation of the conductors 242a, 242b, and 260, and suppress the reduction of hydrogen concentration in the source region and drain region.

[0131] The insulator 253 in contact with the channel-forming region in oxide 230b preferably has the function of capturing and fixing hydrogen. This makes it possible to reduce the hydrogen concentration in the channel-forming region of oxide 230b. O By reducing H, the channel-forming region can be made i-type or substantially i-type.

[0132] Examples of insulators having the function of capturing and fixing hydrogen include metal oxides having an amorphous structure. It is preferable to use a metal oxide such as magnesium oxide, or an oxide containing one or both of aluminum and hafnium, as the insulator 253. In such amorphous metal oxides, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. In other words, amorphous metal oxides have a high ability to capture or fix hydrogen.

[0133] Furthermore, it is preferable to use a high-dielectric constant (high-k) material for the insulator 253. An example of a high-k material is an oxide containing either or both aluminum and hafnium. By using a high-k material as the insulator 253, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. Additionally, it becomes possible to thin the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator.

[0134] Based on the above, it is preferable to use an oxide containing one or both of aluminum and hafnium as the insulator 253, and it is more preferable to use an oxide containing one or both of aluminum and hafnium having an amorphous structure, and it is even more preferable to use hafnium oxide having an amorphous structure. In this embodiment, hafnium oxide is used as the insulator 253. In this case, the insulator 253 is an insulator having at least oxygen and hafnium. Furthermore, the hafnium oxide has an amorphous structure. In this case, the insulator 253 has an amorphous structure.

[0135] In addition, the insulator 253 may be an insulator with a thermally stable structure, such as silicon oxide or silicon oxide-nitride. For example, the insulator 253 may be a laminated structure having aluminum oxide and silicon oxide or silicon oxide-nitride on aluminum oxide. Alternatively, the insulator 253 may be a laminated structure having aluminum oxide, silicon oxide or silicon oxide-nitride on aluminum oxide and hafnium oxide on silicon oxide or silicon oxide-nitride.

[0136] To suppress oxidation of conductors 242a, 242b, and 260, it is preferable to provide oxygen barrier insulators near each of conductors 242a, 242b, and 260. In the semiconductor device described in this embodiment, the insulators are, for example, insulator 253, insulator 254, and insulator 275.

[0137] Examples of oxygen barrier insulators include oxides containing one or both aluminum and hafnium, magnesium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). For example, insulators 253, 254, and 275 are preferably single-layer or multi-layer structures of the above-mentioned oxygen barrier insulators.

[0138] The insulator 253 preferably has barrier properties against oxygen. It is preferable that the insulator 253 is at least less permeable to oxygen than the insulator 280. The insulator 253 has regions that are in contact with the side surfaces of the conductor 242a and the conductor 242b. The oxygen barrier properties of the insulator 253 suppress oxidation of the side surfaces of the conductors 242a and 242b, preventing the formation of an oxide film on these surfaces. This suppresses a decrease in the on-current of the transistor 201a or a decrease in the field-effect mobility.

[0139] Furthermore, the insulator 253 is provided in contact with the upper and side surfaces of oxide 230b, the side surfaces of oxide 230a, the side surfaces of insulator 224, and the upper surface of insulator 222. Because the insulator 253 has an oxygen barrier property, it can suppress the detachment of oxygen from the channel-forming region of oxide 230b when heat treatment or the like is performed. Therefore, the formation of oxygen vacancies in oxide 230a and oxide 230b can be reduced.

[0140] Conversely, even if the insulator 280 contains an excess amount of oxygen, it is possible to suppress the excessive supply of that oxygen to oxides 230a and 230b. Therefore, it is possible to suppress excessive oxidation of the source and drain regions, which can lead to a decrease in the on-current of transistor 201a or a decrease in field-effect mobility.

[0141] Oxides containing either or both aluminum and hafnium have barrier properties against oxygen and can therefore be suitably used as insulator 253.

[0142] The insulator 254 preferably has barrier properties against oxygen. The insulator 254 is provided between the channel-forming region of the oxide 230 and the conductor 260, and between the insulator 280 and the conductor 260. With this configuration, oxygen contained in the channel-forming region of the oxide 230 diffuses into the conductor 260, suppressing the formation of oxygen vacancies in the channel-forming region of the oxide 230. In addition, oxygen contained in the oxide 230 and oxygen contained in the insulator 280 diffuses into the conductor 260, suppressing oxidation of the conductor 260. The insulator 254 preferably has lower oxygen permeability than at least the insulator 280. For example, silicon nitride is preferably used as the insulator 254. In this case, the insulator 254 is an insulator having at least nitrogen and silicon.

[0143] Furthermore, it is preferable that the insulator 254 has barrier properties against hydrogen. This prevents impurities such as hydrogen contained in the conductor 260 from diffusing into the oxide 230b.

[0144] The insulator 275 preferably has barrier properties against oxygen. The insulator 275 is provided between the insulator 280 and the conductor 242a, and between the insulator 280 and the conductor 242b. This configuration suppresses the diffusion of oxygen contained in the insulator 280 to the conductors 242a and 242b. Therefore, it is possible to suppress the oxidation of the conductors 242a and 242b by the oxygen contained in the insulator 280, which increases their resistivity and reduces the on-current. The insulator 275 preferably has lower oxygen permeability than at least the insulator 280. For example, it is preferable to use silicon nitride as the insulator 275. In this case, the insulator 275 is an insulator having at least nitrogen and silicon.

[0145] To suppress the reduction of hydrogen concentration in the source and drain regions of the oxide 220, it is preferable to provide a hydrogen barrier insulator near the source and drain regions, respectively. In the semiconductor device described in this embodiment, the hydrogen barrier insulator is, for example, an insulator 275.

[0146] Examples of barrier insulators against hydrogen include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulator 275 is preferably a single-layer or multi-layer structure of the above-mentioned barrier insulator against hydrogen.

[0147] The insulator 275 preferably has hydrogen barrier properties. The hydrogen barrier properties of the insulator 275 suppress the capture and deposition of hydrogen in the source and drain regions by the insulator 253. Therefore, the source and drain regions can be of the n-type.

[0148] By adopting the above configuration, the channel formation region can be made i-type or substantially i-type, and the source and drain regions can be made n-type, thereby providing a semiconductor device with good electrical characteristics. Furthermore, by adopting the above configuration, good electrical characteristics can be maintained even when the semiconductor device is miniaturized or highly integrated. In addition, high-frequency characteristics can be improved by miniaturizing transistor 201a. Specifically, the cutoff frequency can be improved.

[0149] Insulators 253 and 254 each function as part of the gate insulator. Insulators 253 and 254 are provided together with the conductor 260 in an opening formed in the insulator 280 or the like. In order to miniaturize the transistor 201a, it is preferable that the film thickness of insulator 253 and insulator 254 be thin. The film thickness of insulator 253 is preferably 0.1 nm or more and 5.0 nm or less, more preferably 0.5 nm or more and 5.0 nm or less, more preferably 1.0 nm or more and less than 5.0 nm, and still preferably 1.0 nm or more and 3.0 nm or less. The film thickness of insulator 254 is preferably 0.1 nm or more and 5.0 nm or less, more preferably 0.5 nm or more and 3.0 nm or less, and still preferably 1.0 nm or more and 3.0 nm or less. Note that insulators 253 and 254 each only need to have a region with the above-mentioned film thickness in at least a part of it.

[0150] To achieve the thin film thickness of insulator 253 as described above, it is preferable to deposit the film using atomic layer deposition (ALD). ALD methods include thermal ALD, which uses only thermal energy for the reaction between the precursor and reactant, and plasma-enhanced ALD (PEALD), which uses plasma-excited reactants. PEALD is preferable in some cases because the use of plasma allows for film deposition at lower temperatures.

[0151] The ALD method allows for the deposition of atoms layer by layer, resulting in several advantages: the ability to deposit extremely thin films, films on structures with high aspect ratios, films with fewer defects such as pinholes, films with excellent coverage, and films at low temperatures. Therefore, the insulator 253 can be deposited with good coverage and with the thin film thickness described above on the sides of openings formed in the insulator 280 and the side edges of the conductors 242a and 242b.

[0152] Note that precursors used in the ALD method may contain carbon and other impurities. Therefore, films formed by the ALD method may contain more carbon and other impurities compared to films formed by other film deposition methods. The quantity of impurities can be quantified using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0153] For example, silicon nitride deposited by the PEALD method can be used as the insulator 254.

[0154] Furthermore, by using an insulator 253 that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, such as hafnium oxide, the insulator 253 can also perform the function of the insulator 254. In such a case, by omitting the insulator 254, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0155] Furthermore, in this embodiment, it is preferable to configure the semiconductor device to suppress the mixing of hydrogen into the transistor 201a, in addition to the above configuration. For example, it is preferable to provide an insulator having the function of suppressing hydrogen diffusion so as to cover one or both of the top and bottom of the transistor 201a. In the semiconductor device described in this embodiment, the insulator is, for example, an insulator 212.

[0156] It is preferable to use an insulator 212 that has the function of suppressing hydrogen diffusion. This suppresses the diffusion of hydrogen from below the insulator 212 to the transistor 201a. As the insulator 212, an insulator that can be used for the insulator 275 described above can be used.

[0157] It is preferable that one or more of insulators 212, 214, 262, 282, 283, 284, and 285 function as barrier insulators that suppress the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 201a into the transistor 201a. Therefore, it is preferable that one or more of insulators 212, 214, 262, 282, 283, 284, and 285 are insulating materials that have the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (the above impurities are less permeable). Alternatively, it is preferable that they are insulating materials that have the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms and oxygen molecules) (the above oxygen is less permeable).

[0158] Insulators 212, 214, 262, 282, 283, 284, and 285 preferably each have an insulator that has the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, it is preferable to use silicon nitride, which has higher hydrogen barrier properties, as insulator 212. Also, for example, it is preferable that insulators 214, 262, 282, 283, 284, and 285 each have aluminum oxide or magnesium oxide, which have high hydrogen capture and hydrogen fixation functions. This makes it possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 201a side via insulators 212 and 214. Alternatively, it is possible to suppress the diffusion of impurities such as water and hydrogen from the interlayer insulating film located outside the insulator 284 towards the transistor 201a. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 224 towards the substrate. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 280 upward from the transistor 201a via the insulator 282. Thus, it is preferable to have a structure in which the top and bottom of the transistor 201a are surrounded by insulators that have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0159] The conductor 205a is arranged so as to overlap with the oxide 230 and the conductor 260. Here, it is preferable that the conductor 205a is embedded in an opening formed in the insulator 216. In some cases, a portion of the conductor 205a may be embedded in the insulator 214.

[0160] The conductor 205a may have a single-layer structure or a multi-layer structure. In Figure 5, the conductor 205a has conductor 205a1 and conductor 205a2. Conductor 205a1 is provided in contact with the bottom surface and side wall of the opening. Conductor 205a2 is provided so as to be embedded in the recess of conductor 205a1. Here, the height of the upper surface of conductor 205a2 is approximately the same as the height of the upper surface of conductor 205a1 and the height of the upper surface of insulator 216.

[0161] Here, it is preferable that the conductor 205a1 is a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable that the conductive material has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms and oxygen molecules).

[0162] By using a conductive material that has the function of reducing hydrogen diffusion for the conductor 205a1, it is possible to prevent impurities such as hydrogen contained in the conductor 205a2 from diffusing into the oxide 230 via the insulators 216 and 224. Furthermore, by using a conductive material that has the function of suppressing oxygen diffusion for the conductor 205a1, it is possible to suppress oxidation of the conductor 205a2 and a decrease in conductivity. Examples of conductive materials that have the function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductor 205a1 can be a single-layer structure or a multi-layer structure of the above conductive material. For example, it is preferable that the conductor 205a1 has titanium nitride.

[0163] Furthermore, it is preferable that the conductor 205a2 is made of a conductive material mainly composed of tungsten, copper, or aluminum. For example, it is preferable that the conductor 205a2 contains tungsten.

[0164] The conductor 205a can function as a second gate electrode. In this case, the threshold voltage (Vth) of transistor 201a can be controlled by changing the potential applied to conductor 205a independently of the potential applied to conductor 260. In particular, by applying a negative potential to conductor 205a, it is possible to increase the Vth of transistor 201a and reduce the off-current. Therefore, applying a negative potential to conductor 205a reduces the drain current when the potential applied to conductor 260 is 0V compared to not applying a negative potential.

[0165] Furthermore, the electrical resistivity of the conductor 205a is designed considering the potential applied to the conductor 205a, and the film thickness of the conductor 205a is set to match this electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205a. Here, it is preferable to make the film thicknesses of the conductor 205a and the insulator 216 as thin as is permitted by the design of the conductor 205a. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, thereby suppressing the diffusion of these impurities into the oxide 230.

[0166] Insulators 222 and 224 function as gate insulators.

[0167] Preferably, the insulator 222 has the function of suppressing the diffusion of hydrogen (for example, at least one such as hydrogen atoms and hydrogen molecules). Furthermore, preferably, the insulator 222 has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms and oxygen molecules). For example, it is preferable that the insulator 222 has the function of suppressing the diffusion of one or both of hydrogen and oxygen more effectively than the insulator 224.

[0168] The insulator 222 preferably has an insulator containing an oxide of one or both of the insulating materials aluminum and hafnium. It is preferable to use aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) as the insulator. Alternatively, it is preferable to use an oxide containing hafnium and zirconium, such as hafnium-zirconium oxide. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 to the substrate side and the diffusion of impurities such as hydrogen from the periphery of the transistor 201a to the oxide 230. Therefore, by providing the insulator 222, the diffusion of impurities such as hydrogen into the inside of the transistor 201a can be suppressed, and the generation of oxygen vacancies in the oxide 230 can be suppressed. Furthermore, the reaction of the conductor 205a with the oxygen contained in the insulator 224 and the oxide 230 can be suppressed.

[0169] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the above insulator. Alternatively, these insulators may be subjected to nitriding treatment. Furthermore, insulator 222 may be used by laminating silicon oxide, silicon oxide nitride, or silicon nitride onto the above insulator.

[0170] Furthermore, the insulator 222 may be a single-layer or multi-layer structure of an insulator containing so-called high-k materials, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, or hafnium-zirconium oxide. As transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, materials with high dielectric constants, such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), and (Ba,Sr)TiO3 (BST), can also be used as the insulator 222.

[0171] The insulator 224 in contact with the oxide 230 is preferably, for example, silicon oxide or silicon oxide nitride.

[0172] Furthermore, the insulators 222 and 224 may each have a laminated structure of two or more layers. In that case, the laminated structure is not limited to being made of the same material, but may be made of different materials.

[0173] It is preferable to use conductive materials that are resistant to oxidation or conductive materials that have a function to suppress the diffusion of oxygen as conductors 242a, 242b, and 260. Examples of such conductive materials include conductive materials containing nitrogen and conductive materials containing oxygen. This makes it possible to suppress a decrease in the conductivity of conductors 242a, 242b, and 260. When conductive materials containing metal and nitrogen are used as conductors 242a, 242b, and 260, conductors 242a, 242b, and 260 become conductors having at least a metal and nitrogen.

[0174] Conductors 242a and 242b may have a single-layer structure or a multilayer structure. Similarly, conductor 260 may have a single-layer structure or a multilayer structure.

[0175] Figure 5 shows the conductors 242a and 242b in a two-layer structure. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the layer in contact with oxide 230b (conductor 242a1 and conductor 242b1). This can suppress a decrease in the conductivity of conductors 242a and 242b. Furthermore, it is preferable to use a material that readily absorbs (extracts) hydrogen as the layer in contact with oxide 230b (conductor 242a1 and conductor 242b1) in order to reduce the hydrogen concentration of oxide 230.

[0176] Furthermore, it is preferable that conductors 242a2 and 242b2 have higher conductivity than conductors 242a1 and 242b1. For example, it is preferable that the film thickness of conductors 242a2 and 242b2 be greater than the film thickness of conductors 242a1 and 242b1.

[0177] For example, tantalum nitride or titanium nitride can be used as conductors 242a1 and 242b1, and tungsten can be used as conductors 242a2 and 242b2.

[0178] To suppress the decrease in conductivity of conductors 242a and 242b, it is preferable to use a crystalline oxide such as CAAC-OS as the oxide 230b. In particular, it is preferable to use a metal oxide having indium, zinc, and one or more selected from gallium, aluminum, and tin. By using CAAC-OS, the abstraction of oxygen from oxide 230b by conductor 242a or conductor 242b can be suppressed. Furthermore, a decrease in conductivity of conductors 242a and conductor 242b can be suppressed.

[0179] As conductors 242a and 242b, it is preferable to use, for example, tantalum-containing nitrides, titanium-containing nitrides, molybdenum-containing nitrides, tungsten-containing nitrides, tantalum and aluminum-containing nitrides, titanium and aluminum-containing nitrides, etc. In one embodiment of the present invention, tantalum-containing nitrides are particularly preferred. Alternatively, for example, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc., may also be used. These materials are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0180] Furthermore, hydrogen contained in oxide 230b, etc., may diffuse into conductor 242a or conductor 242b. In particular, by using tantalum-containing nitrides for conductor 242a and conductor 242b, hydrogen contained in oxide 230b, etc., is more likely to diffuse into conductor 242a or conductor 242b, and the diffused hydrogen may combine with nitrogen present in conductor 242a or conductor 242b. In other words, hydrogen contained in oxide 230b, etc., may be absorbed by conductor 242a or conductor 242b.

[0181] The conductor 260 is positioned such that its upper surface is approximately the same height as the top of the insulator 254, the top of the insulator 253, and the upper surface of the insulator 280.

[0182] The conductor 260 functions as the first gate electrode of the transistor 201a. Preferably, the conductor 260 has a conductor 260a and a conductor 260b disposed on top of the conductor 260a. For example, it is preferable that the conductor 260a is arranged to enclose the bottom and sides of the conductor 260b.

[0183] Figure 5 shows the conductor 260 as a two-layer structure. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductor 260a.

[0184] It is preferable to use a conductive material for the conductor 260a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms and oxygen molecules).

[0185] Furthermore, because the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress the oxidation of the conductor 260b and the resulting decrease in conductivity due to oxygen contained in the insulator 280, etc. As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc.

[0186] Furthermore, it is preferable to use a highly conductive material for the conductor 260. For example, the conductor 260b can be a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 260b may also be in a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0187] Furthermore, in transistor 201a, the conductor 260 is formed self-aligningly to fill the openings formed in the insulator 280 and the like. By forming the conductor 260 in this way, the conductor 260 can be reliably positioned in the region between the conductors 242a and 242b without the need for alignment.

[0188] It is preferable that insulators 266, 290, 264, 216, 280, 284, 232, and 281 each have a lower dielectric constant than insulator 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wiring can be reduced.

[0189] For example, it is preferable that insulators 266, 290, 264, 216, 280, 284, 232, and 281 each contain one or more of the following: silicon oxide, silicon oxynitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide with voids.

[0190] In particular, silicon oxide and silicon oxide-nitride are preferred because they are thermally stable. Materials such as silicon oxide, silicon oxide-nitride, and silicon oxide with vacancies are especially preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0191] Furthermore, the upper surfaces of insulators 266, 290, 264, 216, 280, 284, 232, and 281 may each be flattened.

[0192] It is preferable that the concentration of impurities such as water and hydrogen in the insulator 280 is reduced. For example, it is preferable that the insulator 280 has a silicon-containing oxide such as silicon oxide or silicon oxynitride.

[0193] Furthermore, at the opening of the insulator 280, the side wall of the insulator 280 may be approximately perpendicular to the upper surface of the insulator 222, or it may be tapered. By making the side wall tapered, the covering of the insulator 253 and other materials provided at the opening of the insulator 280 is improved, and defects such as porosity can be reduced.

[0194] The conductors 153 and 160 of the capacitive element 101a can be formed using various conductors that can be used for conductor 205, conductor 242, or conductor 260, respectively. It is preferable to deposit the conductors 153 and 160 using a film deposition method that provides good coverage, such as the ALD method or the CVD method.

[0195] The upper surface of the conductor 242b is in contact with the lower surface of the conductor 153. For example, by using the same conductive material as the conductor 242b for the conductor 153, the contact resistance between the conductor 153 and the conductor 242b can be reduced. For example, titanium nitride or tantalum nitride deposited using the ALD method can be used as the conductor 153.

[0196] For example, titanium nitride deposited using the ALD method can be used as the conductor 160a, and tungsten deposited using the CVD method can be used as the conductor 160b. If the adhesion of tungsten to the insulator 154 is sufficiently high, a single-layer structure of tungsten deposited using the CVD method may be used as the conductor 160.

[0197] It is preferable to use a high-dielectric constant (high-k) material (a material with a high relative permittivity) for the insulator 154 of the capacitive element 101a. It is preferable to deposit the insulator 154 using a film deposition method with good coverage, such as the ALD method or the CVD method.

[0198] Examples of high-dielectric constant (high-k) insulators include oxides, oxidized nitrides, nitride oxides, and nitrides containing one or more metallic elements selected from aluminum, hafnium, zirconium, and gallium. Silicon may also be included in the oxides, oxidized nitrides, nitride oxides, or nitrides. Furthermore, insulators made of the above materials can be used in laminated form.

[0199] For example, examples of high-dielectric constant (high-k) insulators include aluminum oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxides containing aluminum and hafnium, oxides containing silicon and hafnium, oxides containing silicon and hafnium, oxides containing silicon and zirconium, oxides containing silicon and zirconium, oxides containing hafnium and zirconium, and oxides containing hafnium and zirconium. By using such high-k materials, the insulator 154 can be made thick enough to suppress leakage current, while ensuring sufficient capacitance of the capacitive element 101a.

[0200] Furthermore, it is preferable to use insulators made of the above materials in a laminated form, and it is preferable to use a laminated structure of a high dielectric constant (high-k) material and a material with a greater dielectric strength than the high dielectric constant (high-k) material. For example, as the insulator 154, an insulator laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used. Alternatively, for example, an insulator laminated in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used. Alternatively, for example, an insulating film laminated in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide can be used. By using laminated insulators with relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic discharge breakdown of the capacitive element 101a can be suppressed.

[0201] The conductor 240 is provided in contact with the inner walls of the openings of the insulators 212, 214, 266, 272, 290, 262, 264, 216, 275, 280, 282, 284, 232, and 281. The conductor 240 is also in contact with the upper and side surfaces of the conductor 252a, the upper and side surfaces of the conductor 242a, and the upper surface of the conductor 209.

[0202] The conductor 240 functions as a plug or wiring for electrically connecting circuit elements such as switches, transistors, capacitive elements, inductors, resistive elements, and diodes, as well as wiring, electrodes, or terminals, to transistors 201a and 203a.

[0203] For example, in the storage device described in Embodiment 2, the conductor 240 functions as a write and read bit line.

[0204] It is preferable that the conductor 240 has a laminated structure of conductor 240a and conductor 240b. For example, as shown in Figure 5, the conductor 240 can have a structure in which conductor 240a is provided in contact with the inner wall of the opening, and conductor 240b is provided further inside. In other words, conductor 240a is positioned closer to insulators 212, 214, 266, 272, 290, 262, 264, 216, 275, 280, 282, 284, 232, and 281 compared to conductor 240b. Furthermore, conductor 240a is in contact with the top and side surfaces of conductor 252a, the top and side surfaces of conductor 242a, and the top surface of conductor 209.

[0205] It is preferable to use a conductive material as the conductor 240a that has the function of suppressing the permeation of impurities such as water and hydrogen. The conductor 240a can be a single-layer structure or a multilayer structure using one or more of the following: tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, and ruthenium oxide. This suppresses the mixing of impurities such as water and hydrogen into the oxides 230 and 220 through the conductor 240.

[0206] Furthermore, since the conductor 240 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 240b can be a conductive material mainly composed of tungsten, copper, or aluminum.

[0207] For example, it is preferable to use titanium nitride as conductor 240a and tungsten as conductor 240b. In this case, conductor 240a will be a conductor containing titanium and nitrogen, and conductor 240b will be a conductor containing tungsten.

[0208] The conductor 240 may be a single-layer structure or a laminated structure of three or more layers. Also, although Figure 1 shows an example where the height of the top surface of the conductor 240 is the same as the height of the top surface of the insulator 281, the height of the top surface of the conductor 240 may be higher than the height of the top surface of the insulator 281.

[0209] <Example of cross-sectional configuration of a semiconductor device 2> An example of a cross-sectional configuration of a semiconductor device according to one embodiment of the present invention will be described using Figures 9 and 10.

[0210] In Figure 9, the X direction is parallel to the channel length direction of the illustrated transistor, the Y direction is perpendicular to the X direction, and the Z direction is perpendicular to both the X and Y directions.

[0211] Furthermore, in Figure 10, the Y direction is parallel to the channel width direction of the illustrated transistor, the X direction is perpendicular to the Y direction, and the Z direction is perpendicular to both the X and Y directions.

[0212] Figure 9 shows a modified version of the semiconductor device shown in Figure 5. Specifically, in Figure 9, the channel length of transistor 202a is longer than the channel length of transistor 203a.

[0213] Figure 5 shows an example where the channel lengths of transistor 203a and transistor 202a are equal, but this is not the only example. The channel lengths of transistor 203a and transistor 202a can be determined independently.

[0214] Furthermore, as shown in Figure 9, the transistor 202a and the capacitive element 101a may have overlapping portions. Specifically, the laminated structure of conductor 265b, oxide 220, and conductor 270b in the transistor 202a and the laminated structure of conductor 153, insulator 154, and conductor 160 in the capacitive element 101a may have overlapping portions.

[0215] Furthermore, Figure 10 shows a cross-sectional view in the Y direction between the dashed-dotted lines X1 and X2 in Figure 9. Figure 10 can also be considered a cross-sectional view in the channel width direction of transistor 202a. Additionally, Figure 9 can also be considered a cross-sectional view in the Y direction between the dashed-dotted lines X1 and X2 in Figure 10.

[0216] In Figure 10, an insulator 212 is provided on an insulator 210, an insulator 214 is provided on an insulator 212, and a conductor 265b is provided on an insulator 214. Furthermore, an insulator 272 is provided on a conductor 265b, an insulator 274 is provided on an insulator 272, and an oxide 220 is provided on an insulator 274. The sides of insulator 274, and the top and sides of oxide 220 are covered by insulators 243b, 244b, and 270b. Insulators 243b, 244b, and 270b are provided inside the opening of an insulator 290 provided on insulator 272.

[0217] Here, the oxide 220 is covered not only on its top surface but also on its sides by the conductor 270b, which has a region that functions as a first gate electrode.

[0218] In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric field of at least the first gate electrode is called a surrounded channel (S-channel) structure. Furthermore, the S-channel structure disclosed in this specification has a structure different from that of the Fin-type structure and the planar-type structure. On the other hand, the S-channel structure disclosed in this specification can also be considered as a type of Fin-type structure. In this specification, the Fin-type structure refers to a structure in which the gate electrode is arranged to surround at least two or more sides (specifically, two, three, or four sides) of the channel. By adopting the Fin-type structure and the S-channel structure, it is possible to increase resistance to short-channel effects, or in other words, to create a transistor in which short-channel effects are less likely to occur.

[0219] By making the transistor in the semiconductor device of this embodiment an S-channel structure, the channel formation region can be electrically surrounded. Since the S-channel structure electrically surrounds the channel formation region, it can be said to be substantially equivalent to a GAA (Gate All Around) structure or an LGAA (Lateral Gate All Around) structure. By making the transistor an S-channel, GAA, or LGAA structure, the channel formation region formed at or near the interface between the oxide and the gate insulator can be made the entire bulk of the oxide. Therefore, it becomes possible to improve the current density flowing through the transistor, which can be expected to improve the on-current of the transistor or increase the field-effect mobility of the transistor.

[0220] Although the transistor 202a shown in Figure 10 is an example of an S-channel structure, the semiconductor device of one aspect of the present invention is not limited to this. For example, the transistor structure that can be used in one aspect of the present invention may be one or more selected from the planar structure, fin structure, and GAA structure.

[0221] The cross-sectional shape of the oxide 220 is not limited to the configuration shown in Figure 10. For example, the oxide 220 may have a curved surface between its side and top surfaces. This can improve the coverage of the film formed on the oxide 220.

[0222] In Figure 10, an insulator 262 is provided on an insulator 272, and an insulator 216 is provided on an insulator 262. Conductors 205b are embedded in openings provided in insulators 262 and 216, and conductors 205b and 270b are electrically connected. In addition, an insulator 222 is provided on an insulator 216, a conductor 242b is provided on an insulator 222, an insulator 275 is provided on a conductor 242b, an insulator 280 is provided on an insulator 275, and an insulator 282 is provided on an insulator 280. A conductor 153 is provided on an insulator 282, an insulator 154 is provided on a conductor 153, and a conductor 160 is provided on an insulator 154. Conductors 205b and 242b are electrically connected through an opening provided in an insulator 222. Furthermore, the conductor 242b and the conductor 153 are electrically connected through openings provided in the insulators 275, 280, and 282. The conductor 160 is electrically connected to the conductor 265c provided in the upper layer (the second layer 11_2 for the first layer 11_1).

[0223] <Example of cross-sectional configuration of a semiconductor device 3> An example of a cross-sectional configuration of a semiconductor device according to one embodiment of the present invention will be described using Figure 11.

[0224] In the semiconductor device shown in Figure 11, a layer containing transistors 300, etc. (corresponding to the drive circuit layer 50 described in Embodiment 2) is provided below a stacked structure similar to the stacked structure shown in Figure 1 (corresponding to the memory layer 60 described in Embodiment 2). The configuration of the layer above the insulator 212 in Figure 11 is the same as in Figure 1, so a detailed explanation is omitted.

[0225] Figure 11 illustrates a transistor 300 in the drive circuit layer 50 described in Embodiment 2. The transistor 300 is provided on a substrate 311 and has a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that includes a part of the substrate 311, and low-resistance regions 314a and 314b that function as a source region or drain region. The transistor 300 may be either a p-channel transistor or an n-channel transistor. For example, a single-crystal silicon substrate can be used as the substrate 311.

[0226] In Figure 11, the transistor 300 has a convex shape in the semiconductor region 313 (part of the substrate 311) where the channel is formed. Furthermore, the sides and top surface of the semiconductor region 313 are covered by a conductor 316 via an insulator 315. The conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. It may also have an insulator in contact with the top of the convex portion, functioning as a mask for forming the convex portion. While this example shows the formation of the convex portion by processing a part of the semiconductor substrate, a semiconductor film with a convex shape may also be formed by processing an SOI (Silicon on Insulator) substrate.

[0227] Note that the transistor 300 shown in Figure 11 is just one example, and its structure is not limited to this example; an appropriate transistor can be used depending on the circuit configuration or driving method.

[0228] A wiring layer containing an interlayer film, wiring, and plugs may be provided between each structure. Furthermore, multiple wiring layers may be provided depending on the design. Also, in this specification, the wiring and the plugs electrically connected to the wiring may be integrated into a single unit. That is, a portion of the conductor may function as wiring, and a portion of the conductor may function as a plug.

[0229] For example, on transistor 300, insulators 320, 322, 324, and 326 are layered in sequence as interlayer films. Conductors such as 328 are embedded in insulators 320 and 322. Conductors such as 330 are embedded in insulators 324 and 326. Conductors 328 and 330 function as contact plugs or wiring.

[0230] Furthermore, the insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape beneath it. For example, the upper surface of the insulator 322 may be planarized by a planarizing treatment such as chemical mechanical polishing (CMP) to improve its flatness.

[0231] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Figure 11, insulators 350, 357, 210a, and 210b are sequentially stacked on the insulator 326 and the conductor 330. Conductors 209 are embedded in insulators 350, 357, 210a, and 210b. Conductors 209 function as contact plugs or wiring.

[0232] For example, the conductor 240 and the transistor 300 are electrically connected via conductors 209, 330, and 328, among others.

[0233] <Example of top surface configuration of a semiconductor device> An example of the top surface configuration of a semiconductor device according to one embodiment of the present invention will be described using Figures 12A and 12B.

[0234] In Figures 12A and 12B, the X direction is parallel to the channel length direction of the illustrated transistor, the Y direction is parallel to the channel width direction of the illustrated transistor, and the Z direction is perpendicular to the X and Y directions. Note that, for simplification, some components, such as insulators, are not shown in Figures 12A and 12B.

[0235] Figure 12A shows the upper layout of each layer, such as the first layer 11_1, and displays transistors 201a and 201b, and capacitive elements 101a and 101b, etc.

[0236] Figure 12B shows the lower layout of each layer, such as the first layer 11_1, and illustrates transistors 202a, 202b, 203a, 203b, etc.

[0237] The various conductors shown in Figures 12A and 12B are formed with line-and-space patterns. If these conductors are designed with a line / space ratio of 20nm / 20nm, with a 10nm margin where the two patterns overlap, and conductor 240 is designed with a 25nm × 25nm pattern (adding a 5nm margin for misalignment), the area of ​​one cell (the area enclosed by the dashed line in Figures 12A and 12B) is 60nm × 162.5nm = 0.000975μm². 2 Therefore, the cell density is 103 cells / μm 2 For example, if four layers of cells are stacked (where n=4 in Figure 1), the cell density will be 412 cells / μm 2 This is the result.

[0238] Furthermore, if the margin between the two overlapping patterns is set to 5 nm and the potential is supplied by routing the conductor 252b in the Y direction (i.e., a configuration without conductor 265c, see Figure 2), the area of ​​one cell is 50 nm × 135 nm = 0.00675 μm². 2 Therefore, the cell density is 148 cells / μm 2 For example, if four layers of cells are stacked, the cell density will be 593 cells / μm 2 This is the result.

[0239] In Figures 12A and 12B, the conductor 240 is shown as a rectangle in top view, but it is not limited to this. For example, the conductor 240 may be circular, elliptical or other approximate circular shapes, polygonal shapes such as rectangles, or polygonal shapes such as rectangles with rounded corners in top view.

[0240] <Component materials for semiconductor devices> The following describes the constituent materials that can be used in semiconductor devices. Note that each layer constituting the semiconductor device may be a single-layer structure or a multilayer structure.

[0241] <<Substrate>> As substrates for forming transistors, for example, insulating substrates, semiconductor substrates, or conductive substrates can be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates, can be used. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having metal nitrides, substrates having metal oxides, substrates on which a conductor or semiconductor is provided on an insulating substrate, substrates on which a conductor or insulator is provided on a semiconductor substrate, and substrates on which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates equipped with one or more types of elements may be used. Examples of elements provided on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0242] <<Insulator>> Examples of insulators include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0243] For example, as transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material for the insulator that functions as the gate insulator, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0244] Examples of insulators with a high dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxide nitrides having aluminum and hafnium, oxides having silicon and hafnium, oxide nitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0245] Examples of insulators with low dielectric constants include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, porous silicon oxide, and resins.

[0246] Furthermore, the electrical properties of transistors using metal oxides can be stabilized by surrounding them with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include insulators containing one or more of the following: boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, which can be used in a single layer or in a multilayer structure. Specifically, examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, as well as metal nitrides such as aluminum nitride, silicon nitride, and silicon nitride.

[0247] Furthermore, the insulator that functions as a gate insulator is preferably an insulator that has a region containing oxygen that is desorbed by heating. For example, by having silicon oxide or silicon oxynitride having a region containing oxygen that is desorbed by heating in a structure that is in contact with oxide 220 or oxide 230, the oxygen deficiency of oxide 220 or oxide 230 can be compensated for.

[0248] <<Conductive material>> As the conductor, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metallic elements, or an alloy combining the above metallic elements. Examples of conductors include tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0249] When using a laminated conductor, for example, a laminated structure combining a material containing the aforementioned metal element and a conductive material containing oxygen, a laminated structure combining a material containing the aforementioned metal element and a conductive material containing nitrogen, or a laminated structure combining a material containing the aforementioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be applied.

[0250] Furthermore, when using an oxide in the channel formation region of a transistor, it is preferable to use a laminated structure for the conductor functioning as the gate electrode, which combines a material containing the aforementioned metal element with a conductive material containing oxygen. In this case, it is preferable to place the conductive material containing oxygen on the channel formation region side. By placing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is more easily supplied to the channel formation region.

[0251] In particular, it is preferable to use a conductive material containing the metal element and oxygen contained in the metal oxide in which the channel is formed as the conductor that functions as the gate electrode. Alternatively, conductive materials containing the aforementioned metal element and nitrogen may be used. For example, conductive materials containing nitrogen such as titanium nitride and tantalum nitride may be used. Alternatively, one or more of the following may be used: indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon-doped indium tin oxide. In addition, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Alternatively, it may be possible to capture hydrogen that is mixed in from an external insulator or the like.

[0252] <<Metal Oxides>> It is preferable to use metal oxides (oxide semiconductors) that function as semiconductors for oxides 220 and 230, respectively. Below, metal oxides applicable to oxides 220 and 230 according to one aspect of the present invention will be described.

[0253] The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that it contains indium and zinc. In addition, it is preferable that it contains aluminum, gallium, yttrium, tin, etc. It may also contain one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0254] Here, we consider the case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. Element M is aluminum, gallium, yttrium, or tin. Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, it is also possible to use a combination of multiple of the aforementioned elements for element M. In particular, it is preferable that element M is one or more elements selected from gallium, aluminum, yttrium, and tin.

[0255] In particular, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also written as In-Ga-Zn oxide, or IGZO) as the semiconductor layer of the transistor. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also written as IAZO) may be used as the semiconductor layer of the transistor. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (IAGZO or IGAZO) may be used as the semiconductor layer.

[0256] In this specification, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be called metal oxynitrides.

[0257] In the following sections, we will describe In-Ga-Zn oxide as an example of a metal oxide.

[0258] Examples of crystalline structures for oxide semiconductors include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), CAC (cloud-aligned composite), single crystal, and polycrystal.

[0259] Note that when focusing on the structure, the oxide semiconductor may be classified differently from the above. For example, the oxide semiconductor can be divided into a single crystal oxide semiconductor and other non-single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include the above-mentioned CAAC-OS and nc-OS. In addition, the non-single crystal oxide semiconductor includes a polycrystalline oxide semiconductor, a pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor), an amorphous oxide semiconductor, and the like.

[0260] Here, the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.

[0261] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystal regions, and the c-axis of the plurality of crystal regions is oriented in a specific direction. Note that the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. In addition, the crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, the crystal region is also a region where the lattice arrangements are aligned. Furthermore, CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have strain. Note that the strain refers to a portion where the direction of the lattice arrangement changes between a region where the lattice arrangements are aligned and another region where the lattice arrangements are aligned in a region where a plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor in which the c-axis is oriented and there is no clear orientation in the a-b plane direction.

[0262] Note that each of the above-mentioned plurality of crystal regions is composed of one or more minute crystals (crystals having a maximum diameter of less than 10 nm). When the crystal region is composed of one minute crystal, the maximum diameter of the crystal region is less than 10 nm. In addition, when the crystal region is composed of a number of minute crystals, the maximum diameter of the crystal region may be about several tens of nm.

[0263] CAAC-OS is an oxide semiconductor with high crystallinity and no distinct grain boundaries being confirmed. Therefore, it can be said that the decrease in electron mobility due to grain boundaries hardly occurs in CAAC-OS. In addition, since the crystallinity of an oxide semiconductor may decrease due to the incorporation of impurities, the generation of defects, etc., CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the oxide semiconductor having CAAC-OS are stable. For this reason, the oxide semiconductor having CAAC-OS is heat-resistant and highly reliable. Also, CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when CAAC-OS is used for an OS transistor, it becomes possible to expand the degree of freedom in the manufacturing process.

[0264] [nc-OS] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In other words, nc-OS has minute crystals. Since the size of the minute crystals is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystals are also referred to as nanocrystals. Also, nc-OS has no regularity in the crystal orientation among different nanocrystals. Therefore, no orientation is seen in the entire film. Therefore, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or an amorphous oxide semiconductor.

[0265] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. a-like OS has loose or low-density regions. That is, a-like OS has lower crystallinity compared with nc-OS and CAAC-OS. Also, a-like OS has a higher hydrogen concentration in the film compared with nc-OS and CAAC-OS.

[0266] Next, the details of the above-mentioned CAC-OS will be described. Note that CAC-OS relates to the material composition.

[0267] [CAC-OS] CAC-OS is a material composition in which, for example, the elements constituting the metal oxide are unevenly distributed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide, and the regions containing these metal elements are mixed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size, is also referred to as a mosaic or patchy state.

[0268] Furthermore, CAC-OS is a composite metal oxide having a mosaic-like structure formed by the separation of the material into a first region and a second region, with the first region distributed within the film (hereinafter also referred to as a cloud-like structure). In other words, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0269] Furthermore, CAC-OS in In-Ga-Zn oxide refers to a material composition containing In, Ga, Zn, and O, in which regions with In as the main component (first region) and regions with Ga as the main component (second region) are present in a mosaic-like manner, and these regions exist randomly. Therefore, it is presumed that CAC-OS has a structure in which the metal elements are unevenly distributed.

[0270] CAC-OS can be formed, for example, by sputtering under conditions where the substrate is not heated. When forming CAC-OS by sputtering, one or more gases selected from inert gases (typically argon), oxygen gas, and nitrogen gas can be used as the deposition gas. Furthermore, a lower ratio of the oxygen gas flow rate to the total deposition gas flow rate during deposition is preferable. For example, the ratio of the oxygen gas flow rate to the total deposition gas flow rate during deposition should be 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0271] Here, the first region is a region with higher conductivity compared to the second region. In other words, the conductivity of the metal oxide is exhibited when carriers flow through the first region. Therefore, a high field-effect mobility (μ) can be achieved when the first region is distributed in a cloud-like manner within the metal oxide.

[0272] On the other hand, the second region is a region with higher insulating properties compared to the first region. In other words, the distribution of the second region within the metal oxide can suppress leakage current.

[0273] Therefore, when CAC-OS is used in a transistor, the conductivity due to the first region and the insulation due to the second region work complementaryly to give CAC-OS a switching function (on / off function). In other words, CAC-OS has conductive function in part of the material, insulating function in part of the material, and semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching operation can be achieved.

[0274] Furthermore, transistors using CAC-OS offer high reliability. Therefore, CAC-OS is ideal for various semiconductor devices, including display devices.

[0275] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention may include two or more of the following: amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0276] <<Other Semiconductor Materials>> The semiconductor layer of the transistor may use a semiconductor material with a bandgap (a semiconductor material that is not a zero-gap semiconductor). For example, a single-element semiconductor such as silicon or a compound semiconductor such as gallium arsenide may be used.

[0277] Furthermore, it is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor in the semiconductor layer of the transistor. Specific examples of transition metal chalcogenides applicable to the semiconductor layer of a transistor include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2). By applying the above-mentioned transition metal chalcogenides to the semiconductor layer of a transistor, a semiconductor device with a high on-current can be provided.

[0278] <Examples of semiconductor device fabrication methods> An example of a method for manufacturing a semiconductor device according to one embodiment of the present invention will be explained using Figures 13 to 18. Here, the case of manufacturing the semiconductor device shown in Figure 1 will be used as an example.

[0279] In the following, insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be deposited using methods such as sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), and ALD as appropriate.

[0280] Note that the sputtering method includes the RF sputtering method using a high-frequency power source as the sputtering power source, the DC sputtering method using a DC power source, and the pulsed DC sputtering method that changes the voltage applied to the electrodes in a pulsed manner. The RF sputtering method is mainly used when forming an insulating film, and the DC sputtering method is mainly used when forming a metal conductive film. Also, the pulsed DC sputtering method is mainly used when forming compounds such as oxides, nitrides, and carbides by the reactive sputtering method.

[0281] Note that the CVD method can be classified into the plasma CVD (PECVD) method using plasma, the thermal CVD (TCVD: Thermal CVD) method using heat, the photo CVD (Photo CVD) method using light, etc. Furthermore, it can be divided into the metal CVD (MCVD: Metal CVD) method and the metal organic CVD (MOCVD: Metal Organic CVD) method according to the raw material gas used.

[0282] The plasma CVD method can obtain a high-quality film at a relatively low temperature. Also, since the thermal CVD method does not use plasma, it is a film-forming method that can reduce plasma damage to the object to be processed. For example, wirings, electrodes, elements (such as transistors and capacitor elements) included in a semiconductor device may be charged up by receiving charges from plasma. At this time, the wirings, electrodes, elements, etc. included in the semiconductor device may be damaged by the accumulated charges. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of the semiconductor device can be increased. Also, in the thermal CVD method, since plasma damage does not occur during film formation, a film with few defects can be obtained.

[0283] Also, as the ALD method, a thermal ALD method that performs the reaction of the precursor and the reactant only with thermal energy, a PEALD method that uses a plasma-excited reactant, etc. can be used.

[0284] CVD and ALD methods differ from sputtering, where particles emitted from a target or other source are deposited. Therefore, they are less affected by the shape of the workpiece and are film deposition methods that provide good step-level coverage. In particular, the ALD method has excellent step-level coverage and excellent thickness uniformity, making it suitable for coating the surface of openings with high aspect ratios. However, since the ALD method has a relatively slow deposition rate, it is sometimes preferable to use it in combination with other film deposition methods that have a faster deposition rate, such as the CVD method.

[0285] Furthermore, the CVD method allows for the deposition of films with any desired composition by changing the flow rate ratio of the raw material gases. For example, in the CVD method, films with continuously changing compositions can be deposited by changing the flow rate ratio of the raw material gases while the film is being deposited. When depositing films while changing the flow rate ratio of the raw material gases, the time required for film deposition can be shortened compared to depositing films using multiple deposition chambers, because time spent on transport or pressure adjustment is eliminated. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0286] Furthermore, the ALD method allows for the deposition of films with any desired composition by simultaneously introducing multiple different types of precursors. Alternatively, when introducing multiple different types of precursors, films with any desired composition can be deposited by controlling the number of cycles for each precursor.

[0287] First, a substrate (not shown) is prepared, and an insulator 210 and a conductor 209 are formed on the substrate. Next, an insulator 212 is deposited on the insulator 210 and the conductor 209, an insulator 214 is deposited on the insulator 212, and an insulator 266 is deposited on the insulator 214 (Figure 13A).

[0288] It is preferable to deposit insulators 212, 214, and 266 using a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in insulator 212, insulator 214, or insulator 266 can be reduced. However, the deposition method for insulators 212, 214, and 266 is not limited to sputtering; for example, CVD, MBE, PLD, or ALD may be used.

[0289] In this embodiment, silicon nitride is deposited as the insulator 212 using a silicon target in a nitrogen gas-containing atmosphere by pulsed DC sputtering. By using pulsed DC sputtering, the generation of particles due to arcing on the target surface can be suppressed, making the film thickness distribution more uniform. Furthermore, by using a pulsed voltage, the rise and fall of the discharge can be made steeper than with a high-frequency voltage. This allows for more efficient power supply to the electrode, improving the sputtering rate and film quality.

[0290] By using an insulator that is impermeable to impurities such as water and hydrogen, such as silicon nitride, the diffusion of impurities such as water and hydrogen contained in the layer below the insulator 212 can be suppressed. Furthermore, by using an insulator that is impermeable to copper, such as silicon nitride, as the insulator 212, even if a diffusive metal such as copper is used in the conductor layer below the insulator 212 (not shown), the diffusion of that metal upward through the insulator 212 can be suppressed.

[0291] In this embodiment, aluminum oxide is deposited as the insulator 214 using a pulsed DC sputtering method with an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. Here, RF (Radio Frequency) power may be applied to the substrate. The amount of oxygen injected into the layer below the insulator 214 can be controlled by the magnitude of the RF power applied to the substrate. For example, the RF power may be 0 W / cm². 2 The above is 1.86 W / cm². 2 The following applies: In other words, the amount of oxygen injected can be varied to suit the characteristics of the transistor by changing the RF power used during the formation of the insulator 214. Therefore, an amount of oxygen suitable for improving the reliability of the transistor can be injected. Furthermore, the RF frequency is preferably 10 MHz or higher. Typically, it is 13.56 MHz. The higher the RF frequency, the less damage can be inflicted on the substrate.

[0292] It is preferable to use an amorphous metal oxide, such as aluminum oxide, as the insulator 214, which has high hydrogen capture and hydrogen fixation capabilities. This allows for the capture or fixation of hydrogen contained in the insulator 266, etc., preventing the hydrogen from diffusing into the oxide 220. In particular, it is preferable to use amorphous aluminum oxide, or aluminum oxide with an amorphous structure, as the insulator 214, as this may allow for more effective capture or fixation of hydrogen. This makes it possible to manufacture transistors and semiconductor devices with good properties and high reliability.

[0293] In this embodiment, an example is shown in which the portions of the insulator 212 and insulator 214 that overlap with the position where the conductor 240 will be installed later are opened in advance. Furthermore, the width of the opening is not particularly limited; for example, the ends of insulator 212 and insulator 214 may be aligned with one or both of the ends of insulator 272 and conductor 252, respectively.

[0294] The insulator 212 may be opened during the processing step described in Figure 17A. If the insulator 212 is opened in advance, impurities such as water and hydrogen may easily diffuse from the substrate side to the transistor during the manufacturing process. By delaying the timing of opening the insulator 212, the function of the insulator 212 as a barrier insulator can be further enhanced, which is preferable. Similarly, the insulator 214 may also be opened during the processing step described in Figure 17A. When the insulators 212 and 214 are opened during the processing step described in Figure 17A, the insulators 212 and 214 can be, for example, the shapes shown in Figure 3.

[0295] Note that insulators 212 and 214 may be opened during the processing step described in Figure 17A. If insulators 212 and 214 are opened in advance, impurities such as water and hydrogen may easily diffuse from the substrate side to the transistor during the manufacturing process. By delaying the timing of opening insulators 212 and 214, the function of insulators 212 and 214 as barrier insulators can be further enhanced, which is preferable. When insulators 212 and 214 are opened during the processing step described in Figure 17A, insulators 212 and 214 can be, for example, the shape shown in Figure 3.

[0296] Dry etching or wet etching can be used to form the openings. Dry etching is preferable because it is suitable for microfabrication. As the etching gas, an etching gas containing halogens can be used, specifically an etching gas containing one or more of fluorine, chlorine, and bromine. For example, as the etching gas, C4F6 gas, C5F6 gas, C4F8 gas, CF4 gas, SF6 gas, CHF3 gas, Cl2 gas, BCl3 gas, SiCl4 gas, or BBr3 gas can be used individually or in mixtures of two or more gases. In addition, oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas can be added to the above etching gas as appropriate. For example, when aluminum oxide is used for the insulator 214, a mixed gas of CHF3 and Ar can be used as the etching gas. Furthermore, the etching conditions can be appropriately set according to the object to be etched.

[0297] As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency voltage to one electrode of the parallel plate electrodes. Alternatively, it may be configured to apply multiple different high-frequency voltages to one electrode of the parallel plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. A dry etching apparatus having a high-density plasma source may be, for example, an inductively coupled plasma (ICP) etching apparatus.

[0298] In this embodiment, silicon oxide is deposited as the insulator 266 using a silicon target in an atmosphere containing oxygen gas by pulsed DC sputtering. By using pulsed DC sputtering, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0299] Next, an opening is formed in the insulator 266 that reaches the insulator 214. It is preferable to select an insulator 214 that functions as an etching stopper film when etching the insulator 266 to form a groove. For example, if silicon oxide or silicon oxynitride is used for the insulator 266 in which the groove is formed, silicon nitride, aluminum oxide, or hafnium oxide may be used for the insulator 214.

[0300] After the openings are formed, conductive films that will become conductors 265a1, 265b1, and 265c1 are deposited (Figure 13A). It is desirable that the conductive films that will become conductors 265a1, 265b1, and 265c1 contain a conductor that has the function of suppressing oxygen permeation. It is preferable that the conductive films contain one or more of the following, for example, tantalum nitride, tungsten nitride, and titanium nitride. Alternatively, the conductive films can be a laminate of a conductor that has the function of suppressing oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive films that will become conductors 265a1, 265b1, and 265c1 can be deposited using, for example, sputtering, CVD, MBE, PLD, or ALD.

[0301] In this embodiment, titanium nitride is deposited as a conductive film to form the conductors 265a1, 265b1, and 265c1. By using such a metal nitride as a layer beneath the conductors 265a, 265b, and 265c, oxidation of the conductors 265a2, 265b2, and 265c2 by an insulator 266 or the like can be suppressed. Furthermore, even if easily diffusible metals such as copper are used as the conductors 265a2, 265b2, and 265c2, it is possible to prevent the metal from diffusing out of the conductors 265a1, 265b1, and 265c1.

[0302] Next, conductive films that will become conductors 265a2, 265b2, and 265c2 are deposited. Preferably, the conductive films that will become conductors 265a2, 265b2, and 265c2 have one or more of the following materials: tantalum, tungsten, titanium, molybdenum, aluminum, copper, and molybdenum-tungsten alloy. The conductive films can be deposited using, for example, a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, tungsten is deposited as the conductive film that will become conductors 265a2, 265b2, and 265c2.

[0303] Next, by performing CMP treatment, a portion of the conductive film that will become conductors 265a1, 265b1, and 265c1, and the conductive film that will become conductors 265a2, 265b2, and 265c2, is removed, exposing the insulator 266. As a result, conductors 265a1, 265b1, 265c1 and conductors 265a2, 265b2, and 265c2 remain only in the openings of the insulator 266 (Figure 13A). Note that a portion of the insulator 266 may be removed by this CMP treatment.

[0304] Next, an insulator 272 is deposited on the insulator 266 and on the conductors 265a, 265b, and 265c (Figure 13A).

[0305] As the insulator 272, it is preferable to deposit an insulator containing an oxide of either or both aluminum and hafnium. Preferably, as the insulator containing an oxide of either or both aluminum and hafnium, it is preferable to use, for example, aluminum oxide, hafnium oxide, or an oxide containing both aluminum and hafnium (hafnium aluminate). Alternatively, it is preferable to use hafnium zirconium oxide. The insulator containing an oxide of either or both aluminum and hafnium has barrier properties against oxygen, hydrogen, and water. Because the insulator 272 has barrier properties against hydrogen and water, the diffusion of hydrogen and water contained in the structure provided around the transistor into the inside of the transistor through the insulator 272 is suppressed, thereby suppressing the generation of oxygen vacancies in the oxide 220.

[0306] Alternatively, the insulator 272 may be a laminated film of an insulator containing an oxide of either or both aluminum and hafnium, and silicon oxide, silicon oxide oxide, silicon nitride, or silicon nitride oxide.

[0307] The insulator 272 can be deposited using, for example, sputtering, CVD, MBE, PLD, or ALD. In this embodiment, hafnium oxide is deposited as the insulator 272 using the ALD method. Alternatively, a laminate of silicon nitride deposited using the PEALD method and hafnium oxide deposited using the ALD method may be used as the insulator 272.

[0308] Next, it is preferable to perform a heat treatment. The heat treatment temperature is preferably 250°C to 650°C, more preferably 300°C to 500°C, and even more preferably 320°C to 450°C. The heat treatment is carried out in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, it is preferable to have about 20% oxygen gas. The heat treatment may also be carried out under reduced pressure. Alternatively, after heat treatment in an atmosphere of nitrogen gas or an inert gas, the heat treatment may be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen.

[0309] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from moisture or other substances being incorporated into the insulator 272, etc.

[0310] In this embodiment, as a heat treatment, after the insulator 272 is formed, the insulator is treated at a temperature of 400°C for 1 hour with a flow rate ratio of nitrogen gas to oxygen gas of 4:1. This heat treatment can remove impurities such as water and hydrogen contained in the insulator 272. Furthermore, when an oxide containing hafnium is used as the insulator 272, a portion of the insulator 272 may crystallize as a result of this heat treatment. The heat treatment can also be performed at a later time, such as after the formation of the insulator 274.

[0311] Next, an insulating film 274f is deposited on the insulator 272 (Figure 13A).

[0312] The insulating film 274f can be deposited using, for example, sputtering, CVD, MBE, PLD, or ALD. In this embodiment, silicon oxide is deposited as the insulating film 274f using the sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating film 274f can be reduced. Since the insulating film 274f comes into contact with the oxide 220a in a later process, it is preferable that the hydrogen concentration is reduced in this way.

[0313] Next, an oxide film 220af is deposited on the insulating film 274f, and an oxide film 220bf is deposited on the oxide film 220af (Figure 13A). It is preferable to deposit the oxide film 220af and oxide film 220bf continuously without exposing them to the atmosphere. By depositing the films without exposure to the atmosphere, it is possible to prevent impurities or moisture from the atmosphere from adhering to the oxide film 220af and oxide film 220bf, and to keep the vicinity of the interface between the oxide film 220af and oxide film 220bf clean.

[0314] The oxide films 220af and 220bf can be deposited using, for example, sputtering, CVD, MBE, PLD, or ALD. In this embodiment, sputtering is used to deposit the oxide films 220af and 220bf.

[0315] For example, when depositing oxide films 220af and 220bf by sputtering, oxygen or a mixture of oxygen and a noble gas is used as the sputtering gas. By increasing the proportion of oxygen in the sputtering gas, the excess oxygen in the deposited oxide film can be increased. Furthermore, when depositing the above oxide films by sputtering, an In-M-Zn oxide target can be used.

[0316] In particular, during the deposition of the oxide film 220af, some of the oxygen contained in the sputtering gas may be supplied to the insulating film 274f. Therefore, the proportion of oxygen contained in the sputtering gas is preferably 70% or more, more preferably 80% or more, and even more preferably 100%.

[0317] Furthermore, when forming the oxide film 220bf by sputtering, if the proportion of oxygen in the sputtering gas is set to be more than 30% but 100% or less, preferably 70% or more but 100%, an oxygen-rich oxide semiconductor is formed. Transistors using an oxygen-rich oxide semiconductor in the channel formation region can achieve relatively high reliability. However, one aspect of the present invention is not limited to this. When forming the oxide film 220bf by sputtering, if the proportion of oxygen in the sputtering gas is set to be 1% or more but 30% or less, preferably 5% or more but 20%, an oxygen-deficient oxide semiconductor is formed. Transistors using an oxygen-deficient oxide semiconductor in the channel formation region can achieve relatively high field-effect mobility. In addition, the crystallinity of the oxide film can be improved by performing film formation while heating the substrate.

[0318] In this embodiment, oxide film 220af is deposited by sputtering using an oxide target with an In:Ga:Zn ratio of 1:3:4. Oxide film 220bf is deposited by sputtering using an oxide target with an In:Ga:Zn ratio of 4:2:4.1, an In:Ga:Zn ratio of 1:1:1, an In:Ga:Zn ratio of 1:1:1.2, or an In:Ga:Zn ratio of 1:1:2. The deposition conditions and atomic ratios of each oxide film can be appropriately selected to match the desired properties of oxide 220a and oxide 220b.

[0319] Furthermore, it is preferable to deposit the insulating film 274f, the oxide film 220af, and the oxide film 220bf by sputtering without exposure to the atmosphere. For example, it is preferable to use a multi-chamber type deposition apparatus. This reduces the incorporation of hydrogen into the films between each deposition process for the insulating film 274f, the oxide film 220af, and the oxide film 220bf.

[0320] Furthermore, ALD (Advanced Laser Development) may be used to deposit oxide films 220af and 220bf. By using ALD to deposit oxide films 220af and 220bf, films of uniform thickness can be formed even in grooves or openings with large aspect ratios. In addition, by using PEALD (Pollution-Assisted Laser Development), oxide films 220af and 220bf can be formed at lower temperatures compared to thermal ALD.

[0321] Next, it is preferable to perform a heat treatment. The heat treatment should be performed within a temperature range in which the oxide films 220af and 220bf do not undergo polycrystallization. The temperature of the heat treatment is preferably 100°C or higher, 250°C or higher, or 350°C or higher, and preferably 650°C or lower, 600°C or lower, or 550°C or lower.

[0322] The atmosphere used for the heat treatment is similar to the atmosphere that can be applied to the heat treatment performed after the deposition of the insulator 272.

[0323] Furthermore, similar to the heat treatment performed after the deposition of the insulator 272, it is preferable that the gas used in the heat treatment be highly purified. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and other substances from being incorporated into the oxide film 220af and oxide film 220bf as much as possible.

[0324] In this embodiment, the heat treatment involves a nitrogen gas to oxygen gas flow rate ratio of 4:1 and a treatment at a temperature of 400°C for 1 hour. This heat treatment containing oxygen gas can reduce impurities such as carbon, water, and hydrogen in the oxide films 220af and 220bf. By reducing impurities in the films in this way, the crystallinity of the oxide film 220bf can be improved, resulting in a denser, more compact structure. This increases the crystalline region in the oxide films 220af and 220bf, and reduces in-plane variation of the crystalline region within the oxide films 220af and 220bf. Therefore, in-plane variation in the electrical characteristics of the transistor can be reduced.

[0325] Furthermore, by performing the heat treatment, hydrogen in the insulator 266, insulating film 274f, oxide film 220af, and oxide film 220bf moves to the insulator 272 and is absorbed into the insulator 272. In other words, hydrogen in the insulator 266, insulating film 274f, oxide film 220af, and oxide film 220bf diffuses into the insulator 272. Consequently, the hydrogen concentration in the insulator 272 increases, while the hydrogen concentrations in the insulator 266, insulating film 274f, oxide film 220af, and oxide film 220bf each decrease.

[0326] In particular, the insulating film 274f (later referred to as insulator 274) functions as a gate insulator for transistors 202a and 203a, while the oxide films 220af and 220bf (later referred to as oxides 220a and 220b) function as channel formation regions for transistors 202a and 203a. Transistors 202a and 203a formed using insulating film 274f, oxide film 220af, and oxide film 220bf with reduced hydrogen concentrations are preferred because they have good reliability.

[0327] Next, the insulating film 274f, oxide film 220af, and oxide film 220bf are processed into island-like structures using lithography to form the insulator 274, oxide 220a, and oxide 220b (Figure 13B).

[0328] Here, the insulator 274, oxide 220a, and oxide 220b are formed such that at least a portion of them overlaps with the conductors 265a and 265b. In addition, the insulator 274, oxide 220a, and oxide 220b are formed so as not to overlap with the conductor 265c.

[0329] Furthermore, as shown in Figure 13B, the sides of the insulator 274, oxide 220a, and oxide 220b may be tapered. The taper angle of the sides of the insulator 274, oxide 220a, and oxide 220b may be, for example, 60° or more and less than 90°. By making the sides tapered in this way, the coverage of the insulator 276 and the like can be improved in subsequent processes, and defects such as porosity can be reduced.

[0330] However, the above is not limited to the above configuration, and the sides of the insulator 274, oxide 220a, and oxide 220b may be configured to be approximately perpendicular to the upper surface of the insulator 272. Such a configuration makes it possible to reduce the area and increase the density when providing multiple transistors.

[0331] The above processing can be performed using either a dry etching method or a wet etching method. Dry etching is suitable for microfabrication. Furthermore, the processing of the insulating film 274f, the oxide film 220af, and the oxide film 220bf may be carried out under different conditions.

[0332] In lithography, the resist is first exposed through a mask. Next, the exposed area is removed or left intact using a developer to form a resist mask. Then, by etching through the resist mask, conductors, semiconductors, or insulators can be processed into the desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. Alternatively, immersion technology may be used, where a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. In addition, an electron beam or ion beam may be used instead of the aforementioned light. When using an electron beam or ion beam, a mask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0333] Furthermore, a hard mask made of an insulator or conductor may be used beneath the resist mask. When using a hard mask, an insulating film or conductive film that serves as the hard mask material is formed on the oxide film 220bf, a resist mask is formed on top of it, and a hard mask of the desired shape can be formed by etching the hard mask material. Etching of the oxide film 220bf, etc., may be performed after removing the resist mask, or it may be performed while the resist mask remains. In the latter case, the resist mask may disappear during etching. The hard mask may also be removed by etching after etching of the oxide film 220bf, etc. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not always necessary to remove the hard mask.

[0334] Next, the insulator 272 is processed using lithography to expose the upper surface of the conductor 265c, and also the upper surface of the portion of the insulator 266 that overlaps with the conductor 209 (Figure 13C). While it is sufficient to process the insulator 272 to expose at least the upper surface of the conductor 265c, removing the portion of the insulator 272 that overlaps with the conductor 209 reduces the number of films processed in the processing step shown in Figure 17A. Furthermore, as mentioned above, the preferred materials for the insulator 272 include difficult-to-etch materials; therefore, pre-opening them broadens the range of selectable processing conditions in Figure 17A, which is preferable.

[0335] The above processing can be performed using either a dry etching method or a wet etching method. Dry etching is preferable because it is suitable for microfabrication. As the etching gas, an etching gas containing halogens can be used, specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. For example, as the etching gas, C4F6 gas, C5F6 gas, C4F8 gas, CF4 gas, SF6 gas, CHF3 gas, Cl2 gas, BCl3 gas, SiCl4 gas, or BBr3 gas can be used individually or in mixtures of two or more gases. In addition, oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas can be added to the above etching gas as appropriate. For example, when using hafnium oxide for the insulator 272, a mixed gas of C4F8, H2, and Ar can be used as the etching gas. Furthermore, the etching conditions can be appropriately set according to the object to be etched.

[0336] Furthermore, when the insulator 272 is processed, a recess may be formed in the region of the upper surface of the insulator 266 that overlaps with the conductor 209, as shown in Figure 13C.

[0337] Next, conductive films that will become conductor 252_1 are formed on the insulator 272, the conductor 265c, and the oxide 220b, and then conductive films that will become conductor 252_2 are formed on the conductive films (Figure 13D).

[0338] The conductive film that becomes conductor 252_1 and the conductive film that becomes conductor 252_2 can be deposited using, for example, sputtering, CVD, MBE, PLD, or ALD.

[0339] In this embodiment, tantalum nitride is deposited as a conductive film to become conductor 252_1 using a sputtering method, and tungsten is deposited as a conductive film to become conductor 252_2. Note that a heat treatment may be performed before depositing the conductive film to become conductor 252_1. This heat treatment may be performed under reduced pressure, and the conductive film to become conductor 252_1 may be deposited continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of oxide 220b can be removed, and the moisture and hydrogen concentrations in oxide 220a and oxide 220b can be further reduced. The heat treatment temperature is preferably 100°C to 400°C. In this embodiment, the heat treatment temperature is set to 200°C.

[0340] Next, using lithography, conductive films to become conductor 252_1 and conductive films to become conductor 252_2 are processed to form island-shaped conductors 252_1 and conductor 252_2, respectively (Figure 13D). Note that the two conductors 252_1 shown in Figure 13D may each be provided in an island shape, or they may be a single island-shaped film having an opening at a position overlapping with conductor 209. Similarly, the two conductors 252_2 shown in Figure 13D may each be provided in an island shape, or they may be a single island-shaped film having an opening at a position overlapping with conductor 209.

[0341] Here, conductors 252_1 and 252_2 are formed such that at least a portion of them overlaps with conductors 265a, 265b, and 265c. Furthermore, conductors 252_1 and 252_2 are provided in a portion of the opening in the insulator 272 and a portion of the recess in the insulator 266. In addition, by forming conductors 252_1 and 252_2, a portion of the region of the insulator 272 that overlaps with conductor 209 is exposed.

[0342] The above processing can be carried out using either a dry etching method or a wet etching method. Furthermore, the processing of the conductive film that becomes conductor 252_1 and the conductive film that becomes conductor 252_2 may be carried out under different conditions.

[0343] Next, an insulator 276 is formed by covering the insulator 274, oxide 220a, oxide 220b, conductor 252_1, and conductor 252_2, and then an insulator 290 is formed on top of the insulator 276. Subsequently, the conductor 252_1, conductor 252_2, insulator 276, and insulator 290 are processed using lithography to form openings that reach oxide 220b (Figure 14A).

[0344] In this case, it is preferable that the insulator 276 is in contact with the upper surface of the insulator 272 and the side surface of the insulator 274.

[0345] Preferably, the insulator 290 is formed by creating an insulating film that will serve as the insulator 290, and then performing a CMP treatment on the insulating film to form an insulator with a flat top surface. Alternatively, silicon nitride may be deposited on the insulator 290, for example, by sputtering, and then the silicon nitride may be subjected to a CMP treatment until it reaches the insulator 290.

[0346] The openings reaching the oxide 220b are provided in two locations: one in the region where the oxide 220b and the conductor 265a overlap, and another in the region where the oxide 220b and the conductor 265b overlap.

[0347] The insulator 276 and the insulator 290 can be deposited using, for example, sputtering, CVD, MBE, PLD, or ALD.

[0348] It is preferable to use an insulator 276 that has the function of suppressing oxygen permeation. For example, it is preferable to deposit silicon nitride as the insulator 276 using the ALD method. Alternatively, it is preferable to deposit aluminum oxide as the insulator 276 using the sputtering method, and then deposit silicon nitride on top of it using the PEALD method. By making the insulator 276 such a layered structure, it is possible to improve the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0349] In this way, oxide 220a, oxide 220b, conductor 252_1, and conductor 252_2 can be covered with an insulator 276 that has the function of suppressing the diffusion of oxygen. This makes it possible to suppress the direct diffusion of oxygen from the insulator 290, etc., to the insulator 274, oxide 220a, oxide 220b, conductor 252_1, and conductor 252_2 in a later process.

[0350] For example, it is preferable to deposit silicon oxide as the insulator 290 using a sputtering method. By depositing the insulating film that will become the insulator 290 using a sputtering method in an oxygen-containing atmosphere, an insulator 290 containing excess oxygen can be formed. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 290 can be reduced. Note that a heat treatment may be performed before the deposition of the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be deposited continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 276 can be removed, and the moisture and hydrogen concentrations in oxide 220a, oxide 220b, and the insulator 274 can be further reduced. The heat treatment conditions described above can be used for this heat treatment.

[0351] The above processing can be carried out using either a dry etching method or a wet etching method. Furthermore, the processing of the conductor 252_1, conductor 252_2, insulator 276, and insulator 290 may be carried out under different conditions.

[0352] This process divides the conductor 252_1 into island-like conductors 252a1, 252b1, and 252c1. Similarly, the conductor 252_2 is divided into island-like conductors 252a2, 252b2, and 252c2. Note that the two conductors 252a1 shown in Figure 14A may each be provided in an island-like manner, or they may be a single island-like film having an opening at a position overlapping with the conductor 209. Similarly, the two conductors 252a2 shown in Figure 14A may each be provided in an island-like manner, or they may be a single island-like film having an opening at a position overlapping with the conductor 209.

[0353] The above etching process may result in the adhesion of impurities to the sides of oxide 220a, the top and sides of oxide 220b, the sides of conductors 252a, 252b, and 252c, the sides of insulator 276, and the sides of insulator 290, or the diffusion of such impurities into these surfaces. A step to remove such impurities may be performed. In addition, the above dry etching may form damaged areas on the surface of oxide 220b. Such damaged areas may be removed. Examples of such impurities include components contained in insulator 290, insulator 276, conductors 252a, 252b, and 252c, components contained in the components of the apparatus used to form the above-mentioned openings, and components contained in the gas or liquid used for etching. Examples of such impurities include hafnium, aluminum, silicon, tantalum, fluorine, and chlorine.

[0354] In particular, impurities such as aluminum and silicon may reduce the crystallinity of oxide 220b. Therefore, it is preferable to remove impurities such as aluminum and silicon from the surface of oxide 220b and its vicinity. Furthermore, it is preferable to reduce the concentration of such impurities. For example, the concentration of aluminum atoms on the surface of oxide 220b and its vicinity is preferably 5.0 atomic% or less, more preferably 2.0 atomic% or less, more preferably 1.5 atomic% or less, even more preferably 1.0 atomic% or less, and even more preferably less than 0.3 atomic%.

[0355] Furthermore, due to impurities such as aluminum and silicon, the density of the crystal structure is reduced in regions where the crystallinity of oxide 220b is low, therefore V O A large amount of H is formed, making it easier for the transistor to become normally-on. Therefore, it is preferable that regions with low crystallinity of oxide 220b are reduced or removed.

[0356] In contrast, it is preferable that the oxide 220b has a layered CAAC structure. In particular, it is preferable that the CAAC structure extends to the lower end of the drain of the oxide 220b. Here, in the transistor, the conductor 252a, conductor 252b, or conductor 252c, and their vicinity, function as drains. That is, it is preferable that the oxide 220b near the lower end of the conductor 252a, conductor 252b, or conductor 252c has a CAAC structure. In this way, even at the drain end, which significantly affects the drain breakdown voltage, the region of low crystallinity of the oxide 220b is removed and a CAAC structure is present, which further suppresses fluctuations in the electrical characteristics of the transistor. Furthermore, the reliability of the transistor can be improved.

[0357] In order to remove impurities and other contaminants adhering to the oxide 220b surface during the etching process described above, a cleaning treatment is performed. Cleaning methods include wet cleaning using a cleaning solution (which can also be called wet etching), plasma treatment using plasma, and cleaning by heat treatment. These cleaning methods may be combined as appropriate. Note that this cleaning treatment may deepen the grooves.

[0358] Wet cleaning may be performed using aqueous solutions of one or more of ammonia water, oxalic acid, phosphoric acid, and hydrofluoric acid diluted with carbonated water or distilled water, distilled water, carbonated water, etc. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, distilled water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0359] In this specification, an aqueous solution obtained by diluting hydrofluoric acid with pure water is sometimes referred to as diluted hydrofluoric acid, and an aqueous solution obtained by diluting ammonia water with pure water is sometimes referred to as diluted ammonia water. The concentration and temperature of the aqueous solution are adjusted as appropriate depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water is preferably 0.01% to 5%, and more preferably 0.1% to 0.5%. The hydrogen fluoride concentration of the diluted hydrofluoric acid is preferably 0.01 ppm to 100 ppm, and more preferably 0.1 ppm to 10 ppm.

[0360] Furthermore, it is preferable to use a frequency of 200 kHz or higher for ultrasonic cleaning, and more preferably a frequency of 900 kHz or higher. Using these frequencies can reduce damage to oxides such as 220b.

[0361] Furthermore, the above cleaning process may be performed multiple times, and the cleaning solution may be changed each time. For example, the first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and the second cleaning process may be performed using pure water or carbonated water.

[0362] In this embodiment, the cleaning process described above involves wet cleaning using diluted ammonia water. This cleaning process removes impurities that have adhered to the surface or diffused into the interior of oxide 220a, oxide 220b, etc. Furthermore, it can improve the crystallinity of oxide 220b.

[0363] Heat treatment may be performed after etching or cleaning as described above. The temperature of the heat treatment is preferably 100°C or higher, 250°C or higher, or 350°C or higher, and preferably 650°C or lower, 600°C or lower, 550°C or lower, or 400°C or lower. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. This allows oxygen to be supplied to oxide 220a and oxide 220b, thereby reducing oxygen deficiency. Furthermore, by performing such heat treatment, the crystallinity of oxide 220b can be improved. In addition, the supplied oxygen reacts with the hydrogen remaining in oxide 220a and oxide 220b, removing the hydrogen as H2O (dehydration). As a result, the hydrogen remaining in oxide 220a and oxide 220b recombines with the oxygen deficiency and V O The formation of H can be suppressed. Furthermore, the heat treatment may be carried out under reduced pressure. Alternatively, the heat treatment may be performed in an oxygen atmosphere, followed by continuous heat treatment in a nitrogen atmosphere without exposure to the atmosphere.

[0364] When heat treatment is performed on oxide 220b while conductors 252a and 242b are in contact, the sheet resistance may decrease in the regions of oxide 220b that overlap with conductor 242a and conductor 242b, respectively. In addition, the carrier concentration may increase. Therefore, the regions of oxide 220b that overlap with conductor 242a and conductor 242b can be made to have their resistance reduced in a self-aligned manner.

[0365] Next, insulating films and conductive films are formed and processed to fill the openings, thereby providing insulators 243a, 244a, conductors 270a1, and 270a2 in positions overlapping with conductor 265a, and insulators 243b, 244b, conductors 270b1, and conductors 270b2 in positions overlapping with conductor 265b (Figure 14B).

[0366] First, insulating films that will become insulators 243a and 243b are deposited. These insulating films can be deposited using methods such as sputtering, CVD, MBE, PLD, or ALD. It is preferable to deposit these insulating films using the ALD method. Similar to the insulator 253 described above, it is preferable to form insulators 243a and 243b with thin films, and it is necessary to minimize variations in film thickness. In contrast, the ALD method is a film deposition method that alternately introduces a precursor and a reactant (e.g., an oxidizing agent), and the film thickness can be adjusted by the number of times this cycle is repeated, thus enabling precise film thickness adjustment. Furthermore, as shown in Figure 14B, insulators 243a and 243b need to be deposited with good coverage on the bottom and sides of the opening. By using the ALD method, atomic layers can be deposited one by one on the bottom and sides of the opening, so that insulators 243a and 243b can be formed with good coverage on the opening.

[0367] Furthermore, when forming insulating films that will become insulators 243a and 243b using the ALD method, ozone (O3), oxygen (O2), water (H2O), etc., can be used as oxidizing agents. By using hydrogen-free oxidizing agents such as ozone (O3) and oxygen (O2), the amount of hydrogen diffusing into oxide 220b can be reduced.

[0368] In this embodiment, hafnium oxide is deposited as an insulating film to form the insulators 243a and 243b by thermal ALD.

[0369] Next, it is preferable to perform microwave processing in an oxygen-containing atmosphere. Here, microwave processing refers to processing using a device that has a power supply that generates high-density plasma using microwaves, for example. In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0370] In microwave processing, it is preferable to use a microwave processing apparatus that has a power supply for generating a high-density plasma using microwaves. Here, the frequency of the microwave processing apparatus is preferably 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, and can be, for example, 2.45 GHz. By using a high-density plasma, high-density oxygen radicals can be generated. The power of the power supply for applying microwaves to the microwave processing apparatus is preferably 1000 W to 10000 W, and preferably 2000 W to 5000 W. The microwave processing apparatus may also have a power supply for applying RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by the high-density plasma can be efficiently guided into the oxide 220b.

[0371] Furthermore, the microwave treatment described above is preferably carried out under reduced pressure, with a pressure of 10 Pa to 1000 Pa, and more preferably 300 Pa to 700 Pa. The treatment temperature is preferably 750°C or lower, more preferably 500°C or lower, and can be, for example, around 250°C. In addition, after oxygen plasma treatment, heat treatment may be carried out continuously without exposure to the outside air. The temperature for the heat treatment is preferably, for example, 100°C to 750°C, and more preferably 300°C to 500°C.

[0372] Furthermore, for example, the above microwave treatment can be carried out using oxygen gas and argon gas. Here, the oxygen flow rate ratio (O2 / (O2+Ar)) is greater than 0% and 100% or less. Preferably, the oxygen flow rate ratio (O2 / (O2+Ar)) is greater than 0% and 50% or less. More preferably, the oxygen flow rate ratio (O2 / (O2+Ar)) is 10% or more and 40% or less. Even more preferably, the oxygen flow rate ratio (O2 / (O2+Ar)) is 10% or more and 30% or less. In this way, by performing microwave treatment in an oxygen-containing atmosphere, the carrier concentration in oxide 220b can be reduced. In addition, by preventing an excessive amount of oxygen from being introduced into the chamber during microwave treatment, it is possible to prevent an excessive reduction in the carrier concentration in oxide 220b.

[0373] By performing microwave processing in an oxygen-containing atmosphere, the oxygen gas can be plasma-generated using microwaves or high-frequency waves such as RF, and this oxygen plasma can be applied to the region between conductors 252a and 252c, and between conductors 252b and 252c, of the oxide 220b. Through the action of plasma, microwaves, etc., the V in the region can be generated. O H can be separated into an oxygen vacancy and hydrogen, and hydrogen can be removed from that region. In other words, V included in the channel formation region O H can be reduced. Therefore, oxygen deficiency in the channel formation region, and V O By reducing H, the carrier concentration can be lowered. Furthermore, by supplying oxygen radicals generated by the oxygen plasma to the oxygen vacancies formed in the channel formation region, the oxygen vacancies in the channel formation region can be further reduced, and the carrier concentration can be lowered.

[0374] The oxygen injected into the channel-forming region can take various forms, including oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (also called O radicals, which are atoms, molecules, or ions with unpaired electrons). The oxygen injected into the channel-forming region can be one or more of the above forms, with oxygen radicals being particularly preferred. Furthermore, this improves the film quality of the insulator 243, thereby improving the reliability of the transistor.

[0375] On the other hand, oxide 220b has a region that overlaps with any of the conductors 252a, 252b, or 252c. This region can function as a source region or a drain region. Here, it is preferable that the conductors 252a, 252b, and 252c function as shielding films against the effects of microwaves, high frequencies such as RF, and oxygen plasma when microwave processing is performed in an oxygen-containing atmosphere. For this reason, it is preferable that the conductors 252a, 252b, and 252c have the function of shielding electromagnetic waves between 300 MHz and 300 GHz, for example, between 2.4 GHz and 2.5 GHz.

[0376] Conductors 252a, 252b, and 252c shield against the effects of microwaves, RF or other high-frequency waves, oxygen plasma, etc., so these effects do not extend to the region of oxide 220b that overlaps with any of the conductors 252a, 252b, or 252c. As a result, microwave processing does not affect the source and drain regions. O This reduces H and prevents excessive oxygen supply, thus preventing a decrease in carrier concentration.

[0377] Furthermore, an insulator 243, which has barrier properties against oxygen, is provided in contact with the sides of the conductors 252a, 252b, and 252c. This suppresses the formation of an oxide film on the sides of the conductors 252a, 252b, and 252c due to microwave processing.

[0378] Furthermore, since the film quality of the insulator 243 can be improved, the reliability of the transistor is enhanced.

[0379] As described above, oxygen vacancies are selectively formed in the channel formation region of the oxide semiconductor, and V O By removing H, the channel formation region can be made i-type or substantially i-type. Furthermore, it is possible to suppress the supply of excess oxygen to the region that functions as the source or drain region, and maintain the conductivity (low resistance state) before microwave processing. This suppresses variations in the electrical properties of the transistor and prevents variations in the electrical properties of the transistor within the substrate surface.

[0380] In microwave processing, electromagnetic interaction between microwaves and molecules in oxide 220b can directly transfer thermal energy to the oxide 220b. This thermal energy can cause the oxide 220b to heat up. This type of heat treatment is sometimes called microwave annealing. Performing microwave processing in an oxygen-containing atmosphere can sometimes achieve effects equivalent to oxygen annealing. Furthermore, if the oxide 220b contains hydrogen, this thermal energy may be transferred to the hydrogen in the oxide 220b, causing activated hydrogen to be released from the oxide 220b.

[0381] Furthermore, microwave treatment may be performed before the deposition of the insulating films that will become insulators 243a and 243b, rather than after deposition.

[0382] Alternatively, after the deposition of the insulating films that will become insulators 243a and 243b, a heat treatment may be performed while maintaining a reduced pressure state after microwave treatment. By performing such a treatment, hydrogen can be efficiently removed from the insulating film, oxide 220b, and oxide 220a. In addition, some of the hydrogen may be gettered into the conductor 252 (conductors 252a, 252b, and 252c). Alternatively, the step of performing a heat treatment while maintaining a reduced pressure state after microwave treatment may be repeated multiple times. By repeating the heat treatment, hydrogen can be removed even more efficiently from the insulating film, oxide 220b, and oxide 220a. The heat treatment temperature is preferably 300°C to 500°C. Furthermore, the above microwave treatment, i.e., microwave annealing, may also serve as the heat treatment. If the oxide 220b, etc., is sufficiently heated by microwave annealing, the heat treatment may not be necessary.

[0383] Furthermore, by performing microwave treatment to modify the film quality of the insulating film that becomes the insulators 243a and 243b, the diffusion of hydrogen, water, impurities, etc. can be suppressed. Therefore, in subsequent processes such as deposition of a conductive film that becomes the conductor 270, or post-treatment such as heat treatment, the diffusion of hydrogen, water, impurities, etc., through the insulator 243 to the oxides 220b and 220a can be suppressed.

[0384] Next, insulating films that will become insulators 244a and 244b are deposited. These insulating films can be deposited using, for example, sputtering, CVD, MBE, PLD, or ALD. It is preferable to deposit these insulating films using the ALD method, similar to the insulating films that will become insulators 243a and 243b. By using the ALD method, insulating films that will become insulators 244a and 244b can be deposited with a thin film thickness and good coverage. In this embodiment, silicon nitride is deposited as the insulating film using the PEALD method.

[0385] Next, conductive films that will become conductors 270a1 and 270b1, and conductive films that will become conductors 270a2 and 270b2 are deposited in sequence. The conductive films that will become conductors 270a1 and 270b1, and the conductive films that will become conductors 270a2 and 270b2, can be deposited using, for example, sputtering, CVD, MBE, PLD, or ALD. In this embodiment, titanium nitride is deposited as the conductive films that will become conductors 270a1 and 270b1 using the ALD method, and tungsten is deposited as the conductive films that will become conductors 270a2 and 270b2 using the CVD method.

[0386] Next, the insulating films that will become insulators 243a and 243b, insulating films that will become insulators 244a and 244b, conductive films that will become conductors 270a1 and 270b1, and conductive films that will become conductors 270a2 and 270b2 are polished by CMP treatment until the insulator 290 is exposed. In other words, the portions of the insulating films that will become insulators 243a and 243b, insulating films that will become insulators 244a and 244b, conductive films that will become conductors 270a1 and 270b1, and conductive films that will become conductors 270a2 and 270b2 that are exposed from the openings are removed. As a result, insulators 243a, 244a, and conductor 270a (conductors 270a1 and 270a2) are formed in the opening overlapping with conductor 265a, and insulators 243b, 244b, and conductor 270b (conductors 270b1 and 270b2) are formed in the opening overlapping with conductor 265b (Figure 14B).

[0387] As a result, insulators 243a and 243b are provided in contact with the inner wall and side surface of the opening superimposed on the oxide 220b. Insulators 244a and 244b are provided along the inner wall and side surface of the opening superimposed on the oxide 220b. Conductor 270a is positioned to fill the opening via insulators 243a and 244a, and conductor 270b is positioned to fill the opening via insulators 243b and 244b. In this way, transistors 202a, 202b, 203a, and 203b are formed. As shown above, transistors 202a, 202b, 203a, and 203b can be manufactured in parallel using the same process.

[0388] Next, a heat treatment may be performed under the same conditions as the heat treatment described above. In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400°C for 1 hour. This heat treatment can reduce the moisture concentration and hydrogen concentration in the insulator 290. After the heat treatment, the insulator 262 may be formed continuously without exposure to the atmosphere.

[0389] Next, an insulator 262 is formed on insulators 243a, 243b, 244a, 244b, conductors 270a, 270b, and insulator 290 (Figure 14B). The insulator 262 can be deposited using, for example, sputtering, CVD, MBE, PLD, or ALD. It is preferable to deposit the insulator 262 using sputtering. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 262 can be reduced.

[0390] In this embodiment, aluminum oxide is deposited as the insulator 262 using a pulsed DC sputtering method with an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. The RF power applied to the substrate is 1.86 W / cm². 2 The following applies: Preferably, 0 W / cm² 2 More than 0.62W / cm 2The following applies. Note that the RF power is 0W / cm². 2 This is equivalent to not applying RF power to the substrate. The amount of oxygen injected into the layer below the insulator 282 can be controlled by the magnitude of the RF power applied to the substrate. For example, the smaller the RF power, the less oxygen is injected into the layer below the insulator 262, and the oxygen amount will be more easily saturated even if the thickness of the insulator 262 is thin. Also, the larger the RF power, the more oxygen is injected into the layer below the insulator 262. By reducing the RF power, the amount of oxygen injected into the insulator 290 can be suppressed. Alternatively, the insulator 262 may be formed as a two-layer laminated structure. In this case, for example, the lower layer of the insulator 262 may be formed by setting the RF power applied to the substrate to 0 W / cm². 2 The film is formed as follows, and the upper layer of the insulator 262 is subjected to an RF power applied to the substrate at 0.62 W / cm². 2 It is used to form a film.

[0391] Furthermore, an RF frequency of 10 MHz or higher is preferable. Typically, it is 13.56 MHz. The higher the RF frequency, the less damage can be inflicted on the substrate.

[0392] Furthermore, by using the sputtering method to deposit the insulator 262 in an oxygen-containing atmosphere, oxygen can be added to the insulator 290 during film formation. This allows the insulator 290 to contain excess oxygen. In this case, it is preferable to deposit the insulator 262 while heating the substrate.

[0393] Next, the insulator 262 is processed using lithography to expose the upper surface of the portion of the insulator 290 that overlaps with the conductor 209 (Figure 14B). By removing the portion of the insulator 262 that overlaps with the conductor 209, the number of films to be processed in the processing step shown in Figure 17A can be reduced. Furthermore, as mentioned above, the materials that are preferable to use for the insulator 262 include materials that are difficult to etch, so opening it up in advance broadens the range of choices for processing conditions in Figure 17A, which is preferable.

[0394] Dry etching or wet etching can be used to form the openings. Dry etching is preferable because it is suitable for microfabrication. As the etching gas, an etching gas containing halogens can be used, specifically an etching gas containing one or more of fluorine, chlorine, and bromine. For example, as the etching gas, C4F6 gas, C5F6 gas, C4F8 gas, CF4 gas, SF6 gas, CHF3 gas, Cl2 gas, BCl3 gas, SiCl4 gas, or BBr3 gas can be used individually or in mixtures of two or more gases. In addition, oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas can be added to the above etching gas as appropriate. For example, when aluminum oxide is used for the insulator 262, a mixed gas of CHF3 and Ar can be used as the etching gas. Furthermore, the etching conditions can be appropriately set according to the object to be etched.

[0395] Furthermore, when the insulator 262 is processed, a recess may be formed in the region of the upper surface of the insulator 290 that overlaps with the conductor 209, as shown in Figure 14B.

[0396] Next, an insulator 216 is formed on the insulator 262, and openings are formed in the insulator 216 that reach the insulator 262 and openings that reach the conductor 270b. Then, conductors 205a and 205b are formed to fill these openings (Figure 14C). Conductor 205b is physically and electrically connected to conductor 270b through the openings provided in the insulator 262.

[0397] In the insulator 262, the timing of forming the opening that reaches the conductor 270b may be before the formation of the insulator 216 or after the formation of the insulator 216.

[0398] The insulator 216 is provided to fill the openings in the insulator 262 and the recesses in the insulator 290.

[0399] For the materials and manufacturing methods of the insulator 216, refer to the materials and manufacturing methods that can be used for the insulator 266.

[0400] For materials and manufacturing methods of conductors 205a1 and 205b1, refer to materials and manufacturing methods that can be used for conductors 265a1 and 265b1.

[0401] For materials and manufacturing methods of conductors 205a2 and 205b2, refer to materials and manufacturing methods that can be used for conductors 265a2 and 265b2.

[0402] For forming the conductors 205a and 205b, it is preferable to use the dual damascene method.

[0403] As shown in Figure 5, the conductor 205b and the conductor 270b may be electrically connected using the conductor 263.

[0404] Next, as shown in Figure 15A, transistors 201a and 201b are formed. For the materials and manufacturing methods of each layer from insulator 222 to insulator 282, refer to the materials and manufacturing methods of each layer from insulator 272 to insulator 262, respectively.

[0405] Next, as shown in Figure 15B, the insulators 275, 280, and 282 are processed to form openings that reach the conductor 242b.

[0406] The width of the aperture created in this process is preferably very fine. For example, the aperture width is preferably 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more, or 5 nm or more. In order to form such a fine aperture, it is preferable to use lithography using short-wavelength light such as EUV light or an electron beam.

[0407] Since the openings created in this process have a large aspect ratio, it is preferable to process a portion of the insulator 282, a portion of the insulator 280, and a portion of the insulator 275 using anisotropic etching. In particular, processing by dry etching is preferred because it is suitable for micro-processing. Furthermore, each of these processes may be carried out under different conditions.

[0408] Next, as shown in Figure 16A, capacitive elements 101a and 101b are formed to fill the opening. Specifically, a conductor 153, an insulator 154, a conductor 160a, and a conductor 160b are formed.

[0409] First, a conductive film that will become the conductor 153 is formed so as to cover the opening and the insulator 282. Preferably, the conductive film that will become the conductor 153 is formed in contact with the side and bottom surfaces of the opening. For this reason, it is preferable to form the conductive film that will become the conductor 153 using a film formation method that has good coverage, such as the ALD method or the CVD method. For example, it is preferable to form titanium nitride or tantalum nitride using the ALD method.

[0410] Next, a conductive film that will become the conductor 153 is processed using lithography to form the conductor 153. As a result, a portion of the conductor 153 is formed inside the opening and comes into contact with a portion of the upper surface of the insulator 282.

[0411] Alternatively, the conductive film that will become the conductor 153 may be processed using the CMP method. In this case, the uppermost part of the conductor 153 can be made to have a shape that roughly coincides with the upper surface of the insulator 282.

[0412] Next, an insulating film that will become an insulator 154 is formed on the conductor 153. Preferably, the insulating film that will become an insulator 154 is formed in contact with the conductor 153 provided inside the opening. For this reason, it is preferable to form the insulating film that will become an insulator 154 using a film formation method with good coverage, such as the ALD method or the CVD method. Preferably, the insulating film that will become an insulator 154 is formed using the high-k material described above.

[0413] Next, a conductive film to become conductor 160a and a conductive film to become conductor 160b are deposited in sequence. Preferably, the conductive film to become conductor 160a is formed in contact with the insulating film to become insulator 154 provided inside the opening, and preferably, the conductive film to become conductor 160b is formed so as to fill the opening. For this reason, it is preferable to deposit the conductive film to become conductor 160a and the conductive film to become conductor 160b using a film deposition method that provides good coverage, such as the ALD method or the CVD method. For example, it is preferable to deposit titanium nitride as the conductive film to become conductor 160a using the ALD method and tungsten as the conductive film to become conductor 160b using the CVD method.

[0414] Furthermore, when a conductive film that becomes conductor 160b is deposited using the CVD method, the average surface roughness of the upper surface of the conductive film may increase. In this case, it is preferable to flatten the conductive film using the CMP method.

[0415] Next, the insulating film that will become the insulator 154, the conductive film that will become the conductor 160a, and the conductive film that will become the conductor 160b are processed using lithography to form the insulator 154, the conductor 160a, and the conductor 160b (Figure 16A). At this time, it is preferable that the insulator 154, the conductor 160a, and the conductor 160b are formed so as to cover the side edge of the conductor 153. With this configuration, the conductor 160 and the conductor 153 can be separated by the insulator 154, and a short circuit between the conductor 160 and the conductor 153 can be suppressed.

[0416] Although the above example shows the processing of an insulating film that will become the insulator 154, the present invention is not limited to this. The conductor may be processed only, and the insulating film may be left unprocessed. This reduces the processing steps for the insulator 154 and improves productivity.

[0417] As described above, multiple transistors 201, 202, 203 and capacitive elements 101 can be formed to constitute a single memory layer.

[0418] Next, the insulator 282 is processed using lithography to expose the upper surface of the portion of the insulator 280 that overlaps with the conductor 209 (Figure 16B). By removing the portion of the insulator 282 that overlaps with the conductor 209, the number of films to be processed in the processing step shown in Figure 17A can be reduced. Furthermore, as mentioned above, the materials that are preferable to use for the insulator 282 include materials that are difficult to etch, so opening it up in advance broadens the range of choices for processing conditions in Figure 17A, which is preferable.

[0419] Dry etching or wet etching can be used to form the openings. Dry etching is preferable because it is suitable for microfabrication. As the etching gas, an etching gas containing halogens can be used, specifically an etching gas containing one or more of fluorine, chlorine, and bromine. For example, as the etching gas, C4F6 gas, C5F6 gas, C4F8 gas, CF4 gas, SF6 gas, CHF3 gas, Cl2 gas, BCl3 gas, SiCl4 gas, or BBr3 gas can be used individually or in mixtures of two or more gases. In addition, oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas can be added to the above etching gas as appropriate. For example, when aluminum oxide is used for the insulator 282, a mixture of CHF3 and Ar can be used as the etching gas. Furthermore, the etching conditions can be appropriately set according to the object to be etched.

[0420] Furthermore, when the insulator 282 is processed, a recess may be formed on the upper surface of the insulator 280 in the area that overlaps with the conductor 209, as shown in Figure 16B.

[0421] Subsequently, by repeatedly fabricating the transistors 201, 202, 203 and the capacitive element 101 as described above, a multilayer memory layer can be formed (Figure 16B). For example, when fabricating a memory device having N layers (where N is an integer greater than or equal to 1), the above fabrication process (from the deposition of the insulator 266 to the formation of the capacitive element 101) is repeated N times.

[0422] After forming multiple transistors 201, 202, 203 and capacitive elements 101 that constitute the N-layer memory layer, the process proceeds to the step of providing the conductor 240.

[0423] Next, openings reaching the conductor 209 are formed in insulators 212, 214, 266, 272, 276, 290, 262, 216, 222, 275, 280, 282, and 284 (Figure 17A). It is preferable to form these openings using lithography. In this case, parts of the conductors 242a, 242b, 252a, and 252b protrude into the openings. Therefore, in the openings, the sides of the conductors 242a, 242b, 252a, and 252b are formed to protrude from at least one side of the insulator in which the openings were formed.

[0424] By pre-opening insulators made of difficult-to-etch materials such as insulators 282, 272, and 262, the processing steps shown in Figure 17A can be performed with a higher yield, thereby improving the productivity of semiconductor devices.

[0425] For example, it is preferable to first form openings in insulators 212, 214, 266, 272, 276, 290, 262, 216, 222, 275, 280, 282, and 284 by anisotropic etching. In this case, the width of the opening can be approximately the same as the width between two conductors 252a and the width between two conductors 242a, or both. It is preferable to use a dry etching method for anisotropic etching.

[0426] Next, it is preferable to widen the width of the opening by isotropic etching. In this case, by using conditions in which the conductors 252a and 242a are not etched or are difficult to etch, the width of the openings of insulators 212, 214, 266, 272, 276, 290, 262, 216, 222, 275, 280, 282, and 284 can be widened while maintaining the width between the two conductors 252a and the width between the two conductors 242a. For isotropic etching, a dry etching method or a wet etching method can be used.

[0427] It is preferable to perform anisotropic etching and isotropic etching continuously without exposure to the atmosphere by changing the conditions in the same etching apparatus. For example, when using the dry etching method for both anisotropic and isotropic etching, it is possible to switch from anisotropic etching to isotropic etching by changing one or more of the conditions such as power supply power, bias power, etching gas flow rate, etching gas type, and pressure.

[0428] Alternatively, different etching methods may be used for anisotropic etching and isotropic etching. For example, a dry etching method can be used for anisotropic etching, and a wet etching method can be used for isotropic etching.

[0429] Next, a conductive film to become conductor 240a and a conductive film to become conductor 240b are deposited in sequence. The conductive film to become conductor 240a preferably has the function of suppressing the permeation of impurities such as water and hydrogen. For example, tantalum nitride or titanium nitride can be used as the conductive film to become conductor 240a. For example, tungsten, molybdenum, or copper can be used as the conductive film to become conductor 240b. These conductive films can be deposited using, for example, sputtering, CVD, MBE, PLD, or ALD.

[0430] Next, by performing CMP treatment, a portion of the conductive film that will become conductor 240a and a portion of the conductive film that will become conductor 240b are removed, exposing the top surface of the uppermost insulator. As a result, these conductive films remain only in the openings, making it possible to form a conductor 240 (conductor 240a and conductor 240b) with a flat top surface (Figure 17B). For example, in the case of Figure 1, CMP treatment is performed until the insulator 281 is exposed. Note that this CMP treatment may remove a portion of the top surface of the insulator 281. Conductor 240 is electrically connected to conductors 209, 242a, 242b, 252a, and 252b.

[0431] Based on the above, the semiconductor device shown in Figure 1 can be fabricated.

[0432] When manufacturing a semiconductor device with the configuration shown in Figure 7, the insulator 262 is processed so that the width of the opening provided in the insulator 262 in Figure 14B is narrower than the width of the conductor 240 (see, for example, Figure 18A). Similarly, the insulator 282 is processed so that the width of the opening provided in the insulator 282 in Figure 16B is narrower than the width of the conductor 240. As a result, as shown in Figure 18B, after forming an opening that reaches the conductor 209, the ends of the insulator 262 and the ends of the insulator 282 can be made to protrude from the opening.

[0433] In this embodiment, the semiconductor device allows two transistors to be formed in an area smaller than the area of ​​two transistors combined, by having the two transistors share a metal oxide and a conductor on the metal oxide. This enables miniaturization or high integration of the semiconductor device. Furthermore, the semiconductor device of this embodiment can be used to realize a memory device with a large storage capacity and a small footprint.

[0434] Furthermore, the semiconductor device of this embodiment includes an OS transistor. Because the OS transistor has a low off-current, it is possible to realize a semiconductor device or memory device with low power consumption. Also, because the OS transistor has high frequency characteristics, it is possible to realize a semiconductor device or memory device with high operating speed. Moreover, by using an OS transistor, it is possible to realize a semiconductor device with good electrical characteristics, a semiconductor device with little variation in the electrical characteristics of the transistor, a semiconductor device with a high on-current, and a semiconductor device or memory device with high reliability.

[0435] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0436] (Embodiment 2) In this embodiment, a storage device according to one aspect of the present invention will be described with reference to Figures 19 to 24.

[0437] Figure 19A shows a schematic perspective view of a storage device according to one embodiment of the present invention. Figure 19B shows a block diagram of a storage device according to one embodiment of the present invention.

[0438] The storage device 100 shown in Figures 19A and 19B has a drive circuit layer 50 and an N-layer (N is an integer of 1 or more) storage layer 60. Each storage layer 60 has a memory cell array 15. The memory cell array 15 has a plurality of memory cells 10 (also called memory elements).

[0439] The N-layer storage layer 60 is provided on the drive circuit layer 50. By providing the N-layer storage layer 60 on the drive circuit layer 50, the occupied area of ​​the storage device 100 can be reduced. In addition, the storage capacity per unit area can be increased.

[0440] In this embodiment, the first storage layer 60 is referred to as storage layer 60_1, the second storage layer 60 as storage layer 60_2, and the third storage layer 60 as storage layer 60_3. Furthermore, the kth storage layer 60 (where k is an integer between 1 and N) is referred to as storage layer 60_k, and the Nth storage layer 60 as storage layer 60_N. In this embodiment, when describing matters relating to the entire N-layer storage 60, or when referring to matters common to each layer of the N-layer storage 60, the term "storage layer 60" may be used.

[0441] <Example of configuration of the drive circuit layer 50> The drive circuit layer 50 includes a PSW22 (power switch), a PSW23, and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.

[0442] In the storage device 100, each circuit, each signal, and each voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or other signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals, and signal RDA is an external output signal.

[0443] Signal CLK is the clock signal. Signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data, and signal RDA is the read data. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 32.

[0444] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the storage device 100. For example, the control circuit performs logical operations on signals CE, GW, and BW to determine the operating mode of the storage device 100 (e.g., write operation, read operation). Alternatively, the control circuit 32 generates control signals for the peripheral circuit 41 so that this operating mode is executed.

[0445] The voltage generation circuit 33 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 33. For example, when a high-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generation circuit 33, and the voltage generation circuit 33 generates a negative voltage.

[0446] The peripheral circuit 41 is a circuit for writing and reading data to and from the memory cell 10. The peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier circuit 46.

[0447] The row decoder 42 and column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying the row to access, and the column decoder 44 is a circuit for specifying the column to access. The row driver 43 has the function of selecting the wiring WWL (write word line) or wiring SL (read word line) specified by the row decoder 42. The column driver 45 has the function of writing data to the memory cell 10, reading data from the memory cell 10, and holding the read data. The column driver 45 has the function of selecting the wiring BL (write and read bit line) specified by the column decoder 44.

[0448] The input circuit 47 has the function of holding the signal WDA. The data held by the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is the data (Din) to be written to the memory cell 10. The data (Dout) read by the column driver 45 from the memory cell 10 is output to the output circuit 48. The output circuit 48 has the function of holding Dout. The output circuit 48 also has the function of outputting Dout to the outside of the storage device 100. The data output from the output circuit 48 is the signal RDA.

[0449] PSW22 has the function of controlling the supply of VDD to the peripheral circuit 31. PSW23 has the function of controlling the supply of VHM to the row driver 43. Here, the high power supply voltage of the memory device 100 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to raise the word line to a high level, and is higher than VDD. The on / off state of PSW22 is controlled by signal PON1, and the on / off state of PSW23 is controlled by signal PON2. In Figure 19B, the number of power supply domains to which VDD is supplied in the peripheral circuit 31 is set to 1, but it can be multiple. In this case, a power switch can be provided for each power supply domain.

[0450] <Example configuration of memory layer 60> An example configuration of an N-layer storage layer 60 will be described. Each of the N-layer storage layers 60 has a memory cell array 15. The memory cell array 15 has multiple memory cells 10. Figures 19A and 19B show an example in which the memory cell array 15 has multiple memory cells 10 arranged in an m x n matrix (where m and n are integers of 2 or more).

[0451] Note that rows and columns extend in mutually orthogonal directions. In this embodiment, the X direction is defined as "rows" and the Y direction as "columns," but the X direction may be defined as "columns" and the Y direction as "rows."

[0452] In Figure 19B, the memory cell 10 located in the 1st row and 1st column is shown as memory cell 10[1,1], and the memory cell 10 located in the mth row and nth column is shown as memory cell 10[m,n]. Furthermore, the memory cell 10 located in the ith row and jth column (where i is an integer between 1 and m, and j is an integer between 1 and n) is shown as memory cell 10[i,j].

[0453] Examples of memory cell circuit configurations are shown in Figures 20A and 20B. For an example of a cross-sectional configuration of the memory cell 10 corresponding to this circuit configuration, refer to Embodiment 1.

[0454] As described in Embodiment 1, in a semiconductor device according to one aspect of the present invention, the wiring BL[i,s] (where s is an integer between 1 and n / 2 if n is even, and an integer between 1 and (n+1) / 2 if n is odd) (conductor 240) directly contacts at least one of the top, side, and bottom surfaces of conductor 242a, which includes a region that functions as either the source or drain electrode of transistor M1 (transistor 201a), and at least one of the top, side, and bottom surfaces of conductor 252a, which includes a region that functions as either the source or drain electrode of transistor M3 (transistor 203a). As a result, there is no need to provide separate connecting electrodes, thus reducing the occupied area of ​​the memory cell array 15. Furthermore, the integration density of the memory cells 10 is improved, and the storage capacity of the storage device 100 can be increased.

[0455] The memory cell 10 has transistors M1, M2, M3, and a capacitive element C. A memory cell composed of three transistors and one capacitive element is also called a 3Tr1C type memory cell. Therefore, the memory cell 10 shown in this embodiment is a 3Tr1C type memory cell.

[0456] The memory cell 10 can be called NOSRAM (registered trademark, Nonvolatile Oxide Semiconductor Random Access Memory).

[0457] Transistor M1 corresponds to transistor 201a or transistor 201b shown in Embodiment 1. Transistor M2 corresponds to transistor 202a or transistor 202b shown in Embodiment 1. Transistor M3 corresponds to transistor 203a or transistor 203b shown in Embodiment 1. Capacitive element C corresponds to capacitive element 101a or capacitive element 101b shown in Embodiment 1. Wiring BL corresponds to conductor 240 shown in Embodiment 1.

[0458] In memory cell 10[i,j], the gate of transistor M1 is electrically connected to wiring WWL[j], and one of its source or drain is electrically connected to wiring BL[i,s]. Figure 20A shows an example configuration where a portion of wiring WWL[j] functions as the gate of transistor M1. One electrode of capacitive element C is electrically connected to wiring PL[i,s], and the other electrode is electrically connected to the other source or drain of transistor M1. Figure 20A and others show an example configuration where a portion of wiring PL[i,s] functions as one electrode of capacitive element C. Furthermore, the gate of transistor M2 is electrically connected to the other electrode of capacitive element C, and one of its source or drain is electrically connected to one of the source or drain of transistor M3, and the other source or drain is electrically connected to wiring PL[i,s]. Furthermore, the gate of transistor M3 is electrically connected to wiring SL[j], and the other source or drain is electrically connected to wiring BL[i,s].

[0459] In memory cell 10[i,j], the region where the other electrode of the capacitive element C, the other source or drain of transistor M1, and the gate of transistor M2 are electrically connected and always at the same potential is called "node ND".

[0460] In memory cell 10[i,j+1], the gate of transistor M1 is electrically connected to wiring WWL[j+1], and one of its source or drain is electrically connected to wiring BL[i,s]. Figure 20A shows an example configuration where a portion of wiring WWL[j+1] functions as the gate of transistor M1. One electrode of capacitive element C is electrically connected to wiring PL[i,s+1], and the other electrode is electrically connected to the other source or drain of transistor M1. Figure 20A and others show an example configuration where a portion of wiring PL[i,s+1] functions as one electrode of capacitive element C. Furthermore, the gate of transistor M2 is electrically connected to the other electrode of capacitive element C, and one of its source or drain is electrically connected to one of the source or drain of transistor M3, and the other source or drain is electrically connected to wiring PL[i,s+1]. Furthermore, the gate of transistor M3 is electrically connected to wiring SL[j+1], and the other end of either the source or drain is electrically connected to wiring BL[i,s].

[0461] In memory cell 10[i,j+1], the region where the other electrode of the capacitive element C, the other source or drain of transistor M1, and the gate of transistor M2 are electrically connected and always at the same potential is called node ND.

[0462] Furthermore, as shown in Figure 20A, transistors M1, M2, and M3 may each be transistors having back gates. The gate and back gate are arranged so as to sandwich the semiconductor channel formation region between them. The gate and back gate are formed of a conductor. The back gate can be made to function in the same way as the gate. Also, the threshold voltage of the transistor can be changed by changing the potential of the back gate. The potential of the back gate may be the same as the gate potential, or it may be the ground potential or any other potential.

[0463] Note that transistors M1, M2, and M3 do not necessarily have back gates. For example, as shown in Figure 20B, transistor M1 may be a transistor with a back gate, while transistors M2 and M3 may be transistors without a back gate.

[0464] Furthermore, since the gate and back gate are formed from a conductor, they also have the function of preventing electric fields generated outside the transistor from acting on the semiconductor in which the channel is formed (particularly an electrostatic shielding function against static electricity). In other words, it is possible to prevent the electrical characteristics of the transistor from fluctuating due to the influence of external electric fields such as static electricity. In addition, by providing a back gate, the change in the threshold voltage of the transistor before and after BT testing can be reduced.

[0465] For example, by using a transistor with a back gate in transistor M1, the influence of external electric fields is reduced, and the off state can be stably maintained. Therefore, the data written to node ND can be stably retained. By providing a back gate, the operation of the memory cell 10 is stabilized, and the reliability of the memory device including the memory cell 10 can be improved.

[0466] Similarly, by using a transistor with a back gate for transistor M3, the influence of the external electric field is reduced, and the off state can be maintained stably. Therefore, the leakage current between wiring BL and wiring PL is reduced, and the power consumption of the memory device including memory cell 10 can be reduced.

[0467] The semiconductor layer on which the channels of transistors M1, M2, and M3 are formed can be a single-crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor, either individually or in combination. Examples of semiconductor materials include silicon and germanium. Compound semiconductors such as silicon-germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors may also be used.

[0468] Furthermore, it is preferable that the transistors (also called "OS transistors") use an oxide semiconductor, a type of metal oxide, in the semiconductor layer where the channels of transistors M1, M2, and M3 are formed. Since oxide semiconductors have a band gap of 2 eV or more, the off-current is significantly low. Therefore, the power consumption of the memory cell 10 can be reduced. Therefore, the power consumption of the memory device 100 including the memory cell 10 can be reduced.

[0469] Furthermore, a memory cell containing an OS transistor can be called an "OS memory." Similarly, a storage device 100 containing such memory cells can also be called an "OS memory."

[0470] Furthermore, OS transistors operate stably even in high-temperature environments and exhibit minimal characteristic fluctuations. For example, the off-current hardly increases even in high-temperature environments. Specifically, the off-current hardly increases even at ambient temperatures between room temperature and 200°C. Also, the on-current does not decrease significantly even in high-temperature environments. Therefore, OS memory operates stably even in high-temperature environments, resulting in high reliability.

[0471] <Example of operation of memory cell 10> Examples of data writing and reading operations for the memory cell 10 will be described. It is preferable that transistors M1, M2, and M3 are normally-off type transistors. In the following description, it will be assumed that normally-off type n-channel transistors are used for transistors M1, M2, and M3.

[0472] Figure 21 is a timing chart illustrating an example of the operation of the memory cell 10. Figures 22A, 22B, 23A, and 23B are circuit diagrams illustrating an example of the operation of the memory cell 10.

[0473] Furthermore, in drawings and other diagrams, to indicate the potential of wiring and electrodes, the letter "H" indicating a high potential or "L" indicating a low potential may be added adjacent to the wiring and electrodes. In addition, wiring and electrodes where a potential change has occurred may have "H" or "L" enclosed in a box. Also, if a transistor is in the off state, the symbol "×" may be superimposed on the transistor.

[0474] Furthermore, when a potential H is supplied to the gate of an n-channel transistor, the transistor is assumed to be in the ON state. Conversely, when a potential L is supplied to the gate of an n-channel transistor, the transistor is assumed to be in the OFF state. Therefore, potential H is higher than potential L. Potential H may be the same potential as the high power supply potential VDD. Also, potential L is lower than potential H. Potential L may be the same potential as the ground potential GND. In this embodiment, potential L is set to be the same potential as the ground potential GND.

[0475] First, assume that during period T0, the potentials of wiring WWL, wiring BL, wiring SL, wiring PL, and node ND are all at potential L (Figure 21). Also, assume that the ground potential GND is supplied to the back gates of transistors M1, M2, and M3.

[0476] [Data writing operation] During period T1, potential H is supplied to wiring WWL and wiring BL (Figures 21 and 22A). As a result, transistor M1 turns on, and potential H is written to node ND as data indicating "1".

[0477] When the potential of node ND becomes high, transistor M2 turns on. Also, since the potential of wiring SL is low, transistor M3 is off. Keeping transistor M3 off prevents a short circuit between wiring BL and wiring PL.

[0478] [Holding operation] During period T2, a potential L is supplied to the wiring WWL. As a result, transistor M1 turns off, and node ND becomes floating. Therefore, the data (potential H) written to node ND is retained (Figures 21 and 22B).

[0479] As mentioned above, OS transistors are transistors with extremely low off-current. By using an OS transistor for transistor M1, data written to node ND can be retained for a long period of time. Therefore, it is not necessary to refresh node ND, or the frequency of node ND refresh operations can be greatly reduced, thereby reducing the power consumption of memory cell 10. Consequently, the power consumption of storage device 100 can be reduced.

[0480] Furthermore, by using OS transistors for one or both of transistors M2 and M3, the leakage current flowing between wiring BL and wiring PL during writing and holding operations can be significantly reduced.

[0481] In addition, OS transistors have a higher dielectric breakdown voltage between the source and drain compared to Si transistors. By using an OS transistor for transistor M1, a higher potential can be supplied to node ND. Therefore, the potential range that node ND can hold can be increased. By increasing the potential range that node ND can hold, it becomes easier to realize multi-level data retention or analog data retention.

[0482] [Read operation] During period T3, the wiring BL is precharged with potential H. That is, after raising the potential of wiring BL to potential H, wiring BL is put into a floating state (Figures 21 and 23A).

[0483] Next, during period T4, a potential H is supplied to wiring SL, turning on transistor M3 (Figures 21 and 23B). At this time, if the potential of node ND is potential H, transistor M2 is in the ON state, and wiring BL and wiring PL become conductive through transistors M2 and M3. When wiring BL and wiring PL become conductive, the potential of wiring BL, which is in a floating state, changes from potential H to potential L.

[0484] Furthermore, if the potential L is written to node ND as data indicating "0", transistor M2 is in the off state. Therefore, even if transistor M3 is turned on, wiring BL and wiring PL will not become conductive, and the potential of wiring BL will remain at potential H.

[0485] In this way, by detecting the change in potential of wiring BL when potential H is supplied to wiring SL, the data written to memory cell 10 can be read.

[0486] In the memory cell 10 using an OS transistor, charge is written to node ND via the OS transistor, eliminating the need for the high voltage required in conventional flash memory and enabling high-speed writing operations. Furthermore, unlike flash memory, charge injection and extraction to the floating gate or charge trapping layer are not performed, so the memory cell 10 using an OS transistor can perform virtually unlimited data writing and reading operations. Unlike flash memory, the memory cell 10 using an OS transistor does not exhibit instability due to an increase in electron trapping centers even with repeated rewriting operations. Compared to conventional flash memory, the memory cell 10 using an OS transistor exhibits less degradation and higher reliability.

[0487] Unlike magnetic memory or resistive random-access memory, the memory cell 10 using an OS transistor does not undergo structural changes at the atomic level. Therefore, the memory cell 10 using an OS transistor has superior rewrite endurance compared to magnetic memory and resistive random-access memory.

[0488] <Example configuration of sense amplifier circuit 46> Next, an example configuration of the sense amplifier circuit 46 will be described. Specifically, an example configuration of a write / read circuit that includes the sense amplifier circuit 46 and performs writing or reading of data signals will be described.

[0489] Figure 24 is a circuit diagram showing an example configuration of a circuit 600 that performs data signal writing and reading, including a sense amplifier circuit 46. The wiring BL connected to the memory cell 10 has the circuit 600 shown in Figure 24 provided in each row.

[0490] Circuit 600 includes a switching circuit 601, transistors 661 to 666, a sense amplifier circuit 46, an AND circuit 652, an analog switch 653, and an analog switch 654.

[0491] Circuit 600 operates according to signals R / W, SEN, SEP, BPR, RSEL, WSEL, GRSEL, and GWSEL.

[0492] The data DIN input to circuit 600 is transmitted to wiring BL via wiring WBL, which is electrically connected to node NS, and is written to memory cell 10. The data DOUT written to memory cell 10 is transmitted via wiring BL to wiring RBL, which is electrically connected to node NSB, and is output as data DOUT from circuit 600.

[0493] Note that data DIN and data DOUT are internal signals, corresponding to signal WDA and signal RDA, respectively.

[0494] Transistor 661 constitutes a precharge circuit. Transistor 661 precharges wiring BL and wiring RBL to the precharge potential Vpre. In this embodiment, the case where the precharge potential Vpre is the potential Vdd (high level) is described (in Figure 24, it is written as Vdd(Vpre)). Signal BPR is the precharge signal, and the conduction state of transistor 661 is controlled by signal BPR.

[0495] During read operations, the sense amplifier circuit 46 determines whether the data input to wiring RBL via wiring BL is at a high or low level. During write operations, the sense amplifier circuit 46 functions as a latch circuit that temporarily holds the data DIN input to circuit 600.

[0496] The sense amplifier circuit 46 shown in Figure 24 is a latch-type sense amplifier. The sense amplifier circuit 46 has two inverter circuits, and the input node of one inverter circuit is connected to the output node of the other inverter circuit. If the input node of one inverter circuit is node NS and the output node is node NSB, complementary data is held at node NS and node NSB.

[0497] Signal R / W is a signal for switching the conduction state between wiring BL and wiring WBL, or between wiring BL and wiring RBL. The switching circuit 601 can switch the conduction state between wiring BL and wiring WBL, or between wiring BL and wiring RBL, by controlling an analog switch with signal R / W. Signal R / W can be a signal that can be switched at the same timing as the write selection signal WSEL and the read selection signal RSEL.

[0498] The switching circuit 601 can conduct between wiring BL and wiring WBL when writing data, and conduct between wiring BL and wiring RBL when reading data. Wiring BL can be configured to serve both the function of wiring for writing data to the memory cell 10 and wiring for reading data from the memory cell 10. Therefore, the number of wires between the memory cell 10 and the circuit 600 having the sense amplifier circuit 46 can be reduced.

[0499] Signals SEN and SEP are sense amplifier enable signals for activating the sense amplifier circuit 46, and the reference potential Vref is the readout determination potential. The sense amplifier circuit 46 determines whether the potential of node NSB at the time of activation is high level or low level, based on the reference potential Vref.

[0500] The AND circuit 652 controls the conduction state between node NS and wiring WBL. Additionally, analog switch 653 controls the conduction state between node NSB and wiring RBL, and analog switch 654 controls the conduction state between node NS and the wiring supplying the reference potential Vref.

[0501] During data retrieval, wiring BL and wiring RBL are made conductive, and the potential of wiring RBL, which is the same potential as wiring BL, is transmitted to node NSB by analog switch 653. When the potential of wiring RBL falls below the reference potential Vref, the sense amplifier circuit 46 determines that wiring RBL is at a low level. Also, if the potential of wiring RBL, which is the same potential as wiring BL, does not fall below the reference potential Vref, the sense amplifier circuit 46 determines that wiring RBL is at a high level.

[0502] The signal WSEL is a write selection signal that controls the AND gate 652. The signal RSEL is a read selection signal that controls the analog switches 653 and 654.

[0503] Transistors 662 and 663 constitute the output MUX (multiplexer) circuit. The signal GRSEL is a global readout selection signal that controls the output MUX circuit. The output MUX circuit has the function of selecting the RBL wiring from which to read data.

[0504] The output MUX circuit has the function of outputting the data DOUT read from the sense amplifier circuit 46.

[0505] Transistors 664, 665, and 666 constitute the write driver circuit. The signal GWSEL is a global write selection signal that controls the write driver circuit. The write driver circuit has the function of writing data DIN to the sense amplifier circuit 46.

[0506] The write driver circuit has the function of selecting the column to write data DIN to. The write driver circuit writes data in byte units, half-word units, or whole-word units according to the signal GWSEL.

[0507] Gain cell type memory cells require at least two transistors per memory cell, making it difficult to increase the number of memory cells that can be placed per unit area. However, by using OS transistors in the transistors that make up the memory cell 10, multiple memory cell arrays 15 can be stacked. In other words, the amount of data that can be stored per unit area can be increased. Furthermore, even if the capacity for storing charge in a gain cell type memory cell is small, it can function as a memory by amplifying the stored charge with the nearest transistor. In addition, by using OS transistors, which have a very low off-current, in the transistors that make up the memory cell 10, the capacitance of the capacitive elements can be reduced. Alternatively, the gate capacitance of the transistor and / or the parasitic capacitance of the wiring can be used as the capacitive elements, and the capacitive elements can be omitted. In other words, the area of ​​the memory cell 10 can be reduced.

[0508] This embodiment can be combined with other embodiments as appropriate.

[0509] (Embodiment 3) In this embodiment, an example of a chip on which a storage device according to one aspect of the present invention is mounted will be described with reference to Figure 25.

[0510] The chip 1200 shown in Figures 25A and 25B has multiple circuits (systems) mounted on it. This technology of integrating multiple circuits (systems) onto a single chip is sometimes called a System on Chip (SoC).

[0511] As shown in Figure 25A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0512] The chip 1200 is provided with bumps (not shown) that connect to the first surface of the package substrate 1201, as shown in Figure 25B. In addition, multiple bumps 1202 are provided on the back surface of the first surface of the package substrate 1201, which connect to the motherboard 1203.

[0513] The motherboard 1203 may be equipped with storage devices such as DRAM 1221 and flash memory 1222. For example, the NOSRAM shown in the previous embodiment can be used for DRAM 1221. This makes it possible to reduce power consumption, increase speed, and increase the capacity of DRAM 1221.

[0514] The CPU 1211 preferably has multiple CPU cores. Similarly, the GPU 1212 preferably has multiple GPU cores. The CPU 1211 and GPU 1212 may each have memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and GPU 1212 may be provided on the chip 1200. The aforementioned NOSRAM can be used for this memory. The GPU 1212 is suitable for parallel computation of a large amount of data and can be used for image processing or multiply-accumulate operations. By providing the GPU 1212 with an image processing circuit or a multiply-accumulate operation circuit using OS transistors, it becomes possible to perform image processing or multiply-accumulate operations with low power consumption.

[0515] Furthermore, because the CPU 1211 and GPU 1212 are located on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, enabling high-speed data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculations have been performed by the GPU 1212.

[0516] The analog arithmetic unit 1213 includes one or both of the A / D (analog-to-digital) conversion circuit and the D / A (digital-to-analog) conversion circuit. Alternatively, the analog arithmetic unit 1213 may also be provided with the sum-of-accumulate circuit.

[0517] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222.

[0518] Interface 1215 has interface circuits for connecting to external devices such as display devices, speakers, microphones, cameras, and controllers. Controllers include mice, keyboards, and game controllers. Such interfaces can include USB (Universal Serial Bus) and HDMI (High-Definition Multimedia Interface).

[0519] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network). It may also include a circuit for network security.

[0520] The above-mentioned circuits (systems) can be formed on chip 1200 using the same manufacturing process. Therefore, even if the number of circuits required for chip 1200 increases, there is no need to increase the number of manufacturing processes, and chip 1200 can be manufactured at a low cost.

[0521] A package substrate 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided can be called a GPU module 1204.

[0522] The GPU module 1204 has a chip 1200 that uses SoC technology, which allows for a smaller size. Furthermore, its excellent image processing capabilities make it suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable game consoles. Additionally, the multiply-accumulate circuit using the GPU 1212 enables the execution of techniques such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN), allowing the chip 1200 to be used as an AI chip, or the GPU module 1204 as an AI system module.

[0523] This embodiment can be combined with other embodiments as appropriate.

[0524] (Embodiment 4) This embodiment shows an example of an electronic component incorporating a storage device according to one aspect of the present invention.

[0525] [Electronic components] Figure 26A shows a perspective view of an electronic component 700 and a substrate (mounted substrate 704) on which the electronic component 700 is mounted. The electronic component 700 shown in Figure 26A has a storage device 100, which is a storage device according to one embodiment of the present invention, within a mold 711. Some details have been omitted in Figure 26A to show the inside of the electronic component 700. The electronic component 700 has a land 712 on the outside of the mold 711. The land 712 is electrically connected to an electrode pad 713, and the electrode pad 713 is electrically connected to the storage device 100 via a wire 714. The electronic component 700 is mounted, for example, on a printed circuit board 702. Multiple such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounted substrate 704.

[0526] As shown in the above embodiment, the storage device 100 includes a drive circuit layer 50 and a storage layer 60 (including a memory cell array 15).

[0527] Figure 26B shows a perspective view of the electronic component 730. The electronic component 730 is an example of a SiP (System in package) or MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple storage devices 100 are provided on the interposer 731.

[0528] Electronic component 730 shows an example where the storage device 100 is used as high-bandwidth memory (HBM). Furthermore, the semiconductor device 735 can be an integrated circuit (semiconductor device) such as a CPU, GPU, or FPGA.

[0529] The package substrate 732 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 can be, for example, a silicon interposer or a resin interposer.

[0530] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "redistribution substrate" or "intermediate substrate". In addition, through electrodes may be provided on the interposer 731, and these through electrodes may be used to electrically connect the integrated circuits and the package substrate 732. Furthermore, in silicon interposers, TSVs (Through Silicon Vias) can also be used as through electrodes.

[0531] It is preferable to use a silicon interposer as the interposer 731. Since silicon interposers do not require active elements, they can be manufactured at a lower cost than integrated circuits. On the other hand, since the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring, which is difficult with resin interposers.

[0532] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0533] Furthermore, in SiP and MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit placed on the silicon interposer and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0534] Alternatively, a heat sink (heat dissipation plate) may be provided on top of the electronic component 730. If a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the heights of the memory device 100 and the semiconductor device 735.

[0535] To mount the electronic component 730 onto another substrate, electrodes 733 may be provided at the bottom of the package substrate 732. Figure 26B shows an example where the electrodes 733 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 733 may be formed with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0536] The electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0537] This embodiment can be combined with other embodiments as appropriate.

[0538] (Embodiment 5) This embodiment describes an application example of a storage device according to one aspect of the present invention.

[0539] A storage device according to one aspect of the present invention can be applied to the storage devices of various electronic devices (for example, information terminals, computers, smartphones, e-book readers, digital still cameras, video cameras, recording and playback devices, navigation systems, and game consoles). It can also be used in image sensors, IoT (Internet of Things), healthcare-related equipment, etc. This makes it possible to reduce the power consumption of electronic devices. Here, "computer" includes tablet computers, notebook computers, and desktop computers, as well as large computers such as server systems.

[0540] An example of an electronic device having a memory device according to one embodiment of the present invention will be described. Figures 27A to 27J and 28A to 28E illustrate how the electronic component 700 or electronic component 730 having the memory device described in the previous embodiment is included in each electronic device.

[0541] [mobile phone] The information terminal 5500 shown in Figure 27A is a type of information terminal, specifically a mobile phone (smartphone). The information terminal 5500 has a housing 5510 and a display unit 5511. For input interfaces, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 5510.

[0542] The information terminal 5500 can store temporary files generated during application execution (for example, cache when using a web browser) by applying a storage device according to one aspect of the present invention.

[0543] [Wearable devices] Figure 27B shows an information terminal 5900, which is an example of a wearable device. The information terminal 5900 includes a housing 5901, a display unit 5902, operation switches 5903 and 5904, a band 5905, and the like.

[0544] Similar to the information terminal 5500 described above, a wearable device can store temporary files generated during application execution by applying a storage device according to one aspect of the present invention.

[0545] [Information terminal] Figure 27C shows a desktop information terminal 5300. The desktop information terminal 5300 comprises a main unit 5301, a display unit 5302, and a keyboard 5303.

[0546] The desktop information terminal 5300, like the information terminal 5500 described above, can store temporary files generated during application execution by applying a storage device according to one aspect of the present invention.

[0547] Figures 27A to 27C describe smartphones, wearable devices, and desktop information terminals as electronic devices. Other information terminals include, for example, PDAs (Personal Digital Assistants), notebook computers, and workstations.

[0548] [electric appliances] Figure 27D shows an electric refrigerator-freezer 5800 as an example of an electrical appliance. The electric refrigerator-freezer 5800 has a casing 5801, a refrigerator door 5802, a freezer door 5803, etc. For example, the electric refrigerator-freezer 5800 is an electric refrigerator-freezer compatible with IoT (Internet of Things).

[0549] A storage device according to one aspect of the present invention can be applied to an electric refrigerator 5800. The electric refrigerator 5800 can send and receive information such as the food stored in the electric refrigerator 5800 and the expiration date of that food to an information terminal or the like via the internet. The electric refrigerator 5800 can store temporary files generated when transmitting such information in a storage device according to one aspect of the present invention.

[0550] Figure 27D describes electric refrigerators as electrical appliances, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cooktops, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audiovisual equipment.

[0551] [Game console] Figure 27E shows a portable game console 5200, which is an example of a game console. The portable game console 5200 has a casing 5201, a display unit 5202, buttons 5203, etc.

[0552] Figure 27F also shows a home console 7500, which is an example of a game console. The home console 7500 can be specifically described as a home console. The home console 7500 has a main unit 7520 and a controller 7522. The controller 7522 can be connected to the main unit 7520 wirelessly or wired. Although not shown in Figure 27F, the controller 7522 may also be equipped with a display unit for displaying game images, and input interfaces other than buttons, such as a touch panel, a joystick, a rotary knob, or a sliding knob. Furthermore, the shape of the controller 7522 is not limited to the shape shown in Figure 27F, and the shape of the controller 7522 may be changed in various ways depending on the genre of game. For example, in shooting games such as FPS (First Person Shooter), a controller with triggers as buttons and shaped like a gun can be used. Also, for example, in music games, a controller shaped like a musical instrument or musical equipment can be used. Furthermore, home game consoles may not use controllers, but instead be operated by the game player's gestures or voice, using one or more cameras, depth sensors, and microphones.

[0553] Furthermore, the video from the aforementioned game console can be output by display devices such as televisions, personal computer displays, game displays, or head-mounted displays.

[0554] By applying a storage device according to one aspect of the present invention to a portable game console 5200 or a home game console 7500, power consumption can be reduced. Furthermore, by reducing power consumption, heat generation from the circuit can be reduced, thereby minimizing the impact of heat on the circuit itself, peripheral circuits, and modules.

[0555] Furthermore, by applying a storage device according to one aspect of the present invention to a portable game console 5200 or a home game console 7500, it is possible to retain temporary files and the like that necessary for calculations that occur during game execution.

[0556] Figures 27E and 27F illustrate portable game consoles and home consoles as examples of game machines. Other examples of game machines include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0557] [Mobile] A storage device according to one aspect of the present invention can be applied to a mobile vehicle and the area around the driver's seat of the vehicle.

[0558] Figure 27G shows an example of a mobile vehicle, automobile 5700.

[0559] The driver's seat area of ​​the 5700 automobile is equipped with an instrument panel that provides various information by displaying the speedometer, tachometer, odometer, fuel gauge, gear status, and air conditioning settings. A storage device for displaying this information may also be provided around the driver's seat.

[0560] In particular, by displaying images from an imaging device (not shown) installed in the automobile 5700, the display device can compensate for obstructed views from pillars and other obstructions, as well as blind spots in the driver's seat, thereby enhancing safety. In other words, by displaying images from an imaging device installed on the outside of the automobile 5700, blind spots can be compensated for, and safety can be enhanced.

[0561] A storage device according to one aspect of the present invention can temporarily hold information, and therefore can be used, for example, to hold necessary temporary information in a system that performs autonomous driving, road guidance, and hazard prediction for a vehicle 5700. The display device may be configured to display temporary information such as road guidance and hazard prediction. Alternatively, it may be configured to hold video footage from a driving recorder installed in the vehicle 5700.

[0562] While the above explanation uses automobiles as an example of a moving object, the definition of a moving object is not limited to automobiles. For example, other examples of moving objects include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets).

[0563] [camera] A storage device according to one aspect of the present invention can be applied to a camera.

[0564] Figure 27H shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, an operation switch 6243, a shutter button 6244, etc., and a detachable lens 6246 is attached to the digital camera 6240. In this example, the digital camera 6240 is configured so that the lens 6246 can be removed from the housing 6241 and replaced, but the lens 6246 and housing 6241 may be integrated. The digital camera 6240 may also be configured to allow for the attachment of a strobe device, viewfinder, etc. separately.

[0565] By applying a storage device according to one aspect of the present invention to the digital camera 6240, power consumption can be reduced. Furthermore, reduced power consumption can reduce heat generation from the circuit, thereby minimizing the impact of heat on the circuit itself, peripheral circuits, and modules.

[0566] [Video camera] A storage device according to one aspect of the present invention can be applied to a video camera.

[0567] Figure 27I shows a video camera 6300, which is an example of an imaging device. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, etc. The operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by a connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0568] When recording video footage captured by the video camera 6300, encoding is required according to the data recording format. By using a storage device according to one aspect of the present invention, the video camera 6300 can retain temporary files generated during encoding.

[0569] [ICD] A memory device according to one aspect of the present invention can be applied to an implantable cardioverter-defibrillator (ICD).

[0570] Figure 27J is a schematic cross-sectional view showing an example of an ICD. The ICD unit 5400 includes at least a battery 5401, electronic components 700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0571] The ICD unit 5400 is surgically implanted in the body, and two wires are routed through the subclavian vein 5405 and superior vena cava 5406 so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0572] The ICD unit 5400 functions as a pacemaker, pacing the heart if the heart rate falls outside the specified range. If pacing does not improve the heart rate (e.g., in cases of rapid ventricular tachycardia or ventricular fibrillation), treatment with an electric shock is administered.

[0573] The ICD unit 5400 needs to constantly monitor the heart rate in order to properly perform pacing and electric shocks. Therefore, the ICD unit 5400 has a sensor for detecting the heart rate. In addition, the ICD unit 5400 can store heart rate data acquired by the sensor, the number of times pacing treatment was performed, the duration, etc., in the electronic component 700.

[0574] Furthermore, the antenna 5404 can receive power, which is then used to charge the battery 5401. The ICD unit 5400 also benefits from having multiple batteries, thus enhancing safety. Specifically, even if some of the batteries in the ICD unit 5400 fail, the remaining batteries can still function, thus acting as an auxiliary power source.

[0575] In addition to the antenna 5404 that can receive power, the system may also have an antenna that can transmit physiological signals. For example, a system may be configured to monitor cardiac activity so that physiological signals such as pulse, respiratory rate, heart rate, and body temperature can be checked on an external monitoring device.

[0576] [Extension devices for PCs] A storage device according to one aspect of the present invention can be applied to computers such as PCs (Personal Computers) and expansion devices for information terminals.

[0577] Figure 28A shows an example of such an expansion device, an external expansion device 6100 for a PC, equipped with a portable chip capable of storing information. The expansion device 6100 can store information using the chip by connecting to a PC, for example, via USB (Universal Serial Bus). Although Figure 28A illustrates a portable form of the expansion device 6100, the expansion device according to one embodiment of the present invention is not limited to this, and may be a relatively large form of expansion device equipped with, for example, a cooling fan.

[0578] The expansion device 6100 comprises a housing 6101, a cap 6102, a USB connector 6103, and a circuit board 6104. The circuit board 6104 is housed in the housing 6101. The circuit board 6104 is provided with a circuit for driving a storage device or the like according to one embodiment of the present invention. For example, electronic components 700 and a controller chip 6106 are mounted on the circuit board 6104. The USB connector 6103 functions as an interface for connecting to an external device.

[0579] [SD card] A storage device according to one aspect of the present invention can be applied to an SD card that can be attached to electronic devices such as information terminals and digital cameras.

[0580] Figure 28B is a schematic diagram of the external appearance of an SD card, and Figure 28C is a schematic diagram of the internal structure of an SD card. The SD card 5110 has a housing 5111, a connector 5112, and a circuit board 5113. The connector 5112 functions as an interface for connecting to an external device. The circuit board 5113 is housed in the housing 5111. The circuit board 5113 is provided with a storage device and a circuit for driving the storage device. For example, an electronic component 700 and a controller chip 5115 are mounted on the circuit board 5113. Note that the circuit configurations of the electronic component 700 and the controller chip 5115 are not limited to those described above, and the circuit configurations may be changed as appropriate depending on the situation. For example, the writing circuit, load driver, and read circuit provided in the electronic component may be incorporated into the controller chip 5115 instead of the electronic component 700.

[0581] By providing electronic components 700 on the back side of the circuit board 5113, the capacity of the SD card 5110 can be increased. Alternatively, a wireless chip with wireless communication capabilities may be provided on the circuit board 5113. This allows for wireless communication between an external device and the SD card 5110, enabling the reading and writing of data to and from the electronic components 700.

[0582] [SSD] One embodiment of the present invention can be applied to an SSD (Solid State Drive) that can be attached to an electronic device such as an information terminal.

[0583] Figure 28D is a schematic diagram of the external appearance of the SSD, and Figure 28E is a schematic diagram of the internal structure of the SSD. The SSD 5150 has a housing 5151, a connector 5152, and a circuit board 5153. The connector 5152 functions as an interface for connecting to external devices. The circuit board 5153 is housed in the housing 5151. The circuit board 5153 is equipped with a storage device and a circuit for driving the storage device. For example, electronic components 700, a memory chip 5155, and a controller chip 5156 are mounted on the circuit board 5153. The capacity of the SSD 5150 can be increased by also providing electronic components 700 on the back side of the circuit board 5153. Work memory is incorporated into the memory chip 5155. For example, a DRAM chip can be used for the memory chip 5155. The controller chip 5156 incorporates a processor, an ECC (Error Check and Correct) circuit, etc. The circuit configurations of the electronic component 700, the memory chip 5155, and the controller chip 5115 are not limited to those described above, and may be modified as appropriate depending on the circumstances. For example, the controller chip 5156 may also be provided with memory that functions as work memory.

[0584] [Calculator] The computer 5600 shown in Figure 29A is an example of a large-scale computer. The computer 5600 houses multiple rack-mount type computers 5620 in rack 5610.

[0585] Computer 5620 can have a configuration similar to the perspective view shown in Figure 29B. In Figure 29B, computer 5620 has a motherboard 5630, which has multiple slots 5631 and multiple connection terminals. A PC card 5621 is inserted into slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0586] The PC card 5621 shown in Figure 29C is an example of a processing board equipped with a CPU, GPU, storage device, etc. The PC card 5621 has a board 5622. The board 5622 also has connection terminals 5623, 5624, and 5625, as well as semiconductor devices 5626, 5627, 5628, and 5629. Although Figure 29C shows semiconductor devices other than semiconductor devices 5626, 5627, and 5628, you can refer to the descriptions of semiconductor devices 5626, 5627, and 5628 below for details on these semiconductor devices.

[0587] The connector 5629 has a shape that allows it to be inserted into slot 5631 of the motherboard 5630, and the connector 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of standards for the connector 5629 include PCIe.

[0588] Terminals 5623, 5624, and 5625 can serve as interfaces for, for example, power supply and signal input to the PC card 5621. They can also serve as interfaces for, for example, outputting signals calculated by the PC card 5621. Examples of standards for terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). When outputting video signals from terminals 5623, 5624, and 5625, examples of standards include HDMI (registered trademark).

[0589] The semiconductor device 5626 has terminals (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting these terminals into sockets (not shown) provided on the board 5622.

[0590] The semiconductor device 5627 has multiple terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, reflow soldering, to the wiring provided on the board 5622 using these terminals. Examples of semiconductor devices 5627 include FPGAs (Field Programmable Gate Arrays), GPUs, and CPUs. For example, an electronic component 730 can be used as the semiconductor device 5627.

[0591] The semiconductor device 5628 has multiple terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by soldering these terminals to the wiring on the board 5622, for example, using a reflow soldering method. Examples of semiconductor devices 5628 include memory devices. For example, an electronic component 700 can be used as the semiconductor device 5628.

[0592] Computer 5600 can also function as a parallel computer. By using Computer 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, artificial intelligence training and inference.

[0593] By using a memory device according to one aspect of the present invention in the various electronic devices described above, it is possible to miniaturize and reduce the power consumption of the electronic devices. Furthermore, because the memory device according to one aspect of the present invention consumes little power, it is possible to reduce heat generation from the circuit. Therefore, adverse effects on the circuit itself, peripheral circuits, and modules due to such heat generation can be reduced. In addition, by using a memory device according to one aspect of the present invention, it is possible to realize electronic devices that operate stably even in high-temperature environments. Therefore, the reliability of electronic devices can be improved.

[0594] This embodiment can be combined with other embodiments as appropriate.

[0595] (Embodiment 6) In this embodiment, a specific example of applying a semiconductor device according to one aspect of the present invention to space equipment will be explained with reference to Figure 30.

[0596] One embodiment of the present invention includes an OS transistor. The OS transistor exhibits small fluctuations in electrical properties due to radiation exposure. In other words, it has high resistance to radiation and can be suitably used in environments where radiation may be incident. For example, the OS transistor can be suitably used in outer space. Specifically, the OS transistor can be used as a transistor constituting a semiconductor device installed in a space shuttle, artificial satellite, or space probe. Examples of radiation include X-rays and neutrons. Outer space refers to, for example, an altitude of 100 km or more, but outer space as described herein may include one or more of the thermosphere, mesosphere, and stratosphere.

[0597] Figure 30 shows satellite 6800 as an example of space equipment. Satellite 6800 consists of a body 6801, solar panels 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Figure 30, planet 6804 is shown as an example in outer space.

[0598] Furthermore, outer space is an environment with radiation levels more than 100 times higher than those on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutrons, protons, heavy ions, and mesons.

[0599] When sunlight shines on the solar panel 6802, the power necessary for the satellite 6800 to operate is generated. However, if, for example, the solar panel does not receive sunlight, or if the amount of sunlight hitting the solar panel is low, the amount of power generated will decrease. Therefore, there is a possibility that the power necessary for the satellite 6800 to operate may not be generated. To operate the satellite 6800 even under conditions of low power generation, it is advisable to install a secondary battery 6805 on the satellite 6800. Note that solar panels are sometimes called solar cell modules.

[0600] Satellite 6800 can generate a signal. This signal is transmitted via antenna 6803, and can be received by, for example, a receiver on the ground or another satellite. By receiving the signal transmitted by satellite 6800, the position of the receiver that received the signal can be measured. Thus, satellite 6800 can constitute a satellite positioning system.

[0601] Furthermore, the control device 6807 has the function of controlling the artificial satellite 6800. The control device 6807 is configured using one or more selected from, for example, a CPU, a GPU, and a memory device. It is preferable to use a semiconductor device including an OS transistor, which is one embodiment of the present invention, for the control device 6807. Compared to Si transistors, OS transistors exhibit smaller fluctuations in electrical characteristics due to radiation irradiation. In other words, they are highly reliable and can be suitably used even in environments where radiation may be incident.

[0602] Furthermore, the satellite 6800 can be configured to include sensors. For example, by configuring it to include a visible light sensor, the satellite 6800 can have the function of detecting sunlight reflected off objects on the ground. Alternatively, by configuring it to include a thermal infrared sensor, the satellite 6800 can have the function of detecting thermal infrared radiation emitted from the Earth's surface. Thus, the satellite 6800 can function, for example, as an Earth observation satellite.

[0603] In this embodiment, an artificial satellite was used as an example of space equipment, but the invention is not limited to this. For example, a semiconductor device according to one aspect of the present invention can be suitably used in space equipment such as spacecraft, space capsules, and space probes.

[0604] Alternatively, for example, OS transistors can be used in semiconductor devices installed in robots used in nuclear power plants and radioactive waste treatment or disposal facilities. They are particularly suitable for use in semiconductor devices installed in remotely operated robots used for tasks such as dismantling reactor facilities, removing nuclear fuel or fuel debris, and conducting on-site surveys of spaces with high levels of radioactive material.

[0605] This embodiment can be combined with other embodiments as appropriate. [Explanation of symbols]

[0606] ADDR: signal, BL[i,s]: wiring, BL: wiring, BPR: signal, BW: signal, CE: signal, CLK: signal, DIN: data, DOUT: data, GND: ground potential, GRSEL: signal, GW: signal, GWSEL: signal, ND: node, NS: node, NSB: node, PL[i,s+1]: wiring, PL[i,s]: wiring, PL: wiring, RBL: wiring, RDA: signal, RSEL: signal, SEN: signal, SEP: signal, SL[j+1]: wiring, SL[j]: wiring, SL: wiring, Vdd: potential, VDD: high power potential, Vref: reference potential, WA KE: signal, WBL: wiring, WDA: signal, WSEL: signal, WWL[j+1]: wiring, WWL[j]: wiring, WWL: wiring, 10[1,1]: memory cell, 10[i,j+1]: memory cell, 10[i,j]: memory cell, 10[m,n]: memory cell, 10: memory cell, 11_1: first layer, 11_2: second layer, 11_n: nth layer, 15: memory cell array, 22: PSW, 23: PSW, 31: peripheral circuit, 32: control circuit, 33: voltage generation circuit, 41: peripheral circuit, 42: row decoder, 43: row driver, 44: column decoder, 45: column Driver, 46: Sense amplifier circuit, 47: Input circuit, 48: Output circuit, 50: Drive circuit layer, 60_1: Memory layer, 60_2: Memory layer, 60_3: ​​Memory layer, 60_k: Memory layer, 60_N: Memory layer, 60: Memory layer, 100: Memory device, 101a: Capacitive element, 101b: Capacitive element, 153: Conductor, 154: Insulator, 160a: Conductor, 160b: Conductor, 160: Conductor, 201a: Transistor, 201b: Transistor, 202a: Transistor, 202b: Transistor, 203a: Transistor, 203b: Transistor, 205a: Conductor, 20 5b: Conductor, 209: Conductor, 210a: Insulator, 210b: Insulator, 210: Insulator, 212: Insulator, 214: Insulator, 216: Insulator, 220a: Oxide, 220af: Oxide film, 220b: Oxide, 220bf: Oxide film, 220: Oxide, 222: Insulator, 224: Insulator, 230a: Oxide, 230b: Oxide, 230: Oxide, 231a: Conductor, 231b: Conductor, 231: Conductor, 232: Insulator, 240a: Conductor, 240b: Conductor, 240: Conductor, 242a: Conductor, 242b: Conductor, 243a: Insulator, 243b: Insulator,244a: insulator, 244b: insulator, 250: region, 252_1: conductor, 252_2: conductor, 252a: conductor, 252b: conductor, 252c: conductor, 252: conductor, 253: insulator, 254: insulator, 260a: conductor, 260b: conductor, 260: conductor, 262: insulator, 263a: conductor, 263b: conductor, 263: conductor, 264: insulator, 265a: conductor, 265b: conductor, 265c: conductor, 266: insulator, 270a: conductor, 270b: conductor, 272: insulator, 274f: insulating film, 274: insulator, 275: insulator, 276: Insulator, 280: Insulator, 281: Insulator, 282: Insulator, 283: Insulator, 284: Insulator, 285: Insulator, 290: Insulator, 300: Transistor, 311: Substrate, 313: Semiconductor area, 314a: Low resistance area, 314b: Low resistance area, 315: Insulator, 316: Conductor, 320: Insulator, 322: Insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 350: Insulator, 357: Insulator, 600: Circuit, 601: Switching circuit, 652: AND circuit, 653: Analog switch, 654: Analog switch, 661: Transistor, 662: Transistor, 663: Transistor, 664: Transistor, 665: Transistor, 666: Transistor, 700: Electronic component, 702: Printed circuit board, 704: Mounted circuit board, 711: Mold, 712: Land, 713: Electrode pad, 714: Wire, 730: Electronic component, 731: Interposer, 732: Package substrate, 733: Electrode, 735: Semiconductor device, 1200: Chip, 1201: Package substrate, 1202: Bump, 1203: Motherboard, 1204: GPU module, 1211: CPU, 1212: GPU ,1213: Analog processing unit, 1214: Memory controller, 1215: Interface, 1216: Network circuit, 1221: DRAM, 1222: Flash memory, 5110: SD card, 5111: Enclosure, 5112: Connector, 5113: Circuit board, 5115: Controller chip, 5150: SSD, 5151: Enclosure, 5152: Connector, 5153: Circuit board, 5155: Memory chip, 5156: Controller chip, 5200: Portable game console, 5201: Enclosure, 5202: Display unit, 5203: Button, 5300: Desktop information terminal,5301: Main unit, 5302: Display unit, 5303: Keyboard, 5400: ICD main unit, 5401: Battery, 5402: Wire, 5403: Wire, 5404: Antenna, 5405: Subclavian vein, 5406: Superior vena cava, 5500: Information terminal, 5510: Enclosure, 5511: Display unit, 5600: Calculator, 5610: Rack, 5620: Calculator, 5621: PC card, 5622: Board D, 5623: Connection terminal, 5624: Connection terminal, 5625: Connection terminal, 5626: Semiconductor equipment, 5627: Semiconductor equipment, 5628: Semiconductor equipment, 5629: Connection terminal, 5630: Motherboard, 5631: Slot, 5700: Automobile, 5800: Electric refrigerator / freezer, 5801: Enclosure, 5802: Door for refrigerator compartment, 5803: Door for freezer compartment, 5900: Information terminal, 5901: Enclosure, 5902: Display unit, 5903: Operation switch, 5904: Operation switch, 5905: Band, 6100: Expansion device, 6101: Housing, 6102: Cap, 6103: USB connector, 6104: Circuit board, 6106: Controller chip, 6240: Digital camera, 6241: Housing, 6242: Display unit, 6243: Operation switch, 6244: Shutter button, 6246: Lens, 630 0: Video camera, 6301: First enclosure, 6302: Second enclosure, 6303: Display unit, 6304: Operation switch, 6305: Lens, 6306: Connection unit, 6800: Artificial satellite, 6801: Aircraft body, 6802: Solar panel, 6803: Antenna, 6804: Planet, 6805: Rechargeable battery, 6807: Control unit, 7500: Home game console, 7520: Main unit, 7522: Controller,

Claims

1. It comprises a first transistor, a second transistor, a third transistor, a first insulator, a second insulator, a third insulator, and a capacitive element. The first transistor and the second transistor each share a first metal oxide on the first insulator and a first conductor on the first metal oxide, The first transistor comprises a second conductor and a fourth insulator on the first metal oxide, and a third conductor on the fourth insulator. The second transistor has a fourth conductor and a fifth insulator on the first metal oxide, and a fifth conductor on the fifth insulator. The third transistor comprises a second metal oxide, a sixth conductor, a seventh conductor, and a sixth insulator on the second metal oxide, and an eighth conductor on the sixth insulator. The capacitive element comprises a ninth conductor, a seventh insulator on the ninth conductor, and a tenth conductor on the seventh insulator. The side surface of the first insulator has a portion that is in contact with the fourth conductor, The end of the fourth conductor has a portion that is located outside the end of the first insulator. The second insulator is located on the first transistor and on the second transistor. The second conductor and the sixth conductor are electrically connected through an opening provided in the second insulator. The third insulator is located on the third transistor, The portion where the ninth conductor, the seventh insulator, and the tenth conductor overlap is located on the third insulator. A semiconductor device in which the sixth conductor and the ninth conductor are electrically connected through an opening provided in the third insulator.

2. In claim 1, A semiconductor device wherein the end of the fourth conductor has a portion located outside the end of the second insulator.

3. In claim 1, A semiconductor device wherein the end of the second insulator has a portion located outside the end of the first insulator.

4. In claim 1, A semiconductor device wherein the end of the seventh conductor has a portion located outside the end of the second insulator.

5. In claim 1, A semiconductor device wherein the end of the third insulator has a portion located outside the end of the first insulator.

6. In claim 1, The seventh insulator is a semiconductor device having one or both of zirconium oxide and aluminum oxide.

7. In claim 2 or claim 4, Having an eleventh conductor, A semiconductor device wherein the eleventh conductor has a portion that contacts a part of the upper surface of the fourth conductor, a portion that contacts a part of the side surface of the fourth conductor, a portion that contacts a part of the upper surface of the seventh conductor, and a portion that contacts a part of the side surface of the seventh conductor.

8. In claim 7, A semiconductor device wherein the eleventh conductor has a portion that contacts a part of the lower surface of the fourth conductor and a portion that contacts a part of the lower surface of the seventh conductor.

Images