DC / DC converter

Abstract

To maintain the average value of coil current constant without depending on an input-output condition.SOLUTION: A DC / DC converter includes an oscillator that generates a lamp signal and an inversion lamp signal having reverse polarity and repeating rise / drop and reset in a common period, a comparator that compares an analog signal, the lamp signal, and the inversion lamp signal, a logic operation unit that performs logic operation on the comparison result and generates a step-down control signal and a step-up control signal of a step up and down type switch output stage, a current detection unit that samples the coil current of the switch output stage and generates a current sensing signal, and a timing control unit that performs timing control so as to sample the coil current at a reset timing of the lamp signal and the inversion lamp signal. The step-down control signal and the step-up control signal turn on / off step-down and step-up output transistors and a synchronization rectifying transistor. Using the current sensing signal, output feedback control of a current mode control system is performed.SELECTED DRAWING: Figure 29

Description

Technical Field

[0001] The invention disclosed in this specification relates to a DC / DC converter.

Background Art

[0002] Conventionally, as a power supply means for various applications, a DC / DC converter (so-called switching power supply) that turns on / off an output transistor to generate a desired output voltage from an input voltage has been used.

[0003] As an example of the prior art related to the above, Patent Document 1 and Patent Document 2 can be cited.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] By the way, as an output feedback control method of a DC / DC converter, a current mode control method that detects both an output voltage and a coil current to perform output feedback control is widely known in general. However, in the conventional current mode control method (peak value detection type or bottom value detection type), the average coil current fluctuates depending on input / output conditions, so there is a risk of adversely affecting various operations of the DC / DC converter (such as overcurrent protection operation and light load detection operation).

[0006] In view of the above problems found by the inventors of the present application, the invention disclosed in this specification aims to provide a DC / DC converter that can maintain a constant average value of the coil current without depending on input / output conditions. [Means for solving the problem]

[0007] The DC / DC converter disclosed herein is configured to generate a desired output voltage from an input voltage by sampling the coil current of the switch output stage at the center timing of the on or off period of the switch output stage, and performing output feedback control in a current mode control manner using a current sense signal corresponding to the sampled value.

[0008] Furthermore, the DC / DC converter disclosed herein includes a comparator that compares an analog signal with a first ramp signal to generate a control signal for a switch output stage, a current detection unit that generates a current sense signal by sampling the coil current of the switch output stage at a timing corresponding to the timing control signal, and a timing control unit that generates the timing control signal so that the coil current is sampled at the center timing of the on or off period of the switch output stage using a second ramp signal having twice the slew rate of the first ramp signal, and generates a desired output voltage from the input voltage by performing output feedback control in a current mode control method using the current sense signal.

[0009] Furthermore, the DC / DC converter disclosed herein includes a comparator that compares a first analog signal and a ramp signal to generate a control signal for a switch output stage, a current detection unit that generates a current sense signal by sampling the coil current of the switch output stage at a timing corresponding to the timing control signal, an average value generation unit that generates a second analog signal having a simple average value of the signal value of the first analog signal and the start or end value of the ramp signal, and a timing control unit that uses the ramp signal and the second analog signal to generate the timing control signal so that the coil current is sampled at the center timing of the on or off period of the switch output stage, and is configured to generate a desired output voltage from the input voltage by performing output feedback control in a current mode control method using the current sense signal.

[0010] Furthermore, the DC / DC converter disclosed herein includes a comparator that compares a first analog signal and a first ramp signal to generate a control signal for a switch output stage, a current detection unit that generates a current sense signal by sampling the coil current of the switch output stage at a timing corresponding to the timing control signal, an average value generation unit that generates a second analog signal having a weighted average value of the signal value of the first analog signal and the start or end value of the first ramp signal, and a timing control unit that generates the timing control signal so that the coil current is sampled at the center timing of the on or off period of the switch output stage using a second ramp signal having a different slew rate than the first ramp signal and the second analog signal, and is configured to generate a desired output voltage from the input voltage by performing output feedback control in a current mode control method using the current sense signal.

[0011] Furthermore, the DC / DC converter disclosed herein includes an oscillator that generates a triangular waveform ramp signal with equal up / down slew rates, a comparator that compares an analog signal with the ramp signal to generate a control signal for a switch output stage, a current detection unit that generates a current sense signal by sampling the coil current of the switch output stage at a timing corresponding to the timing control signal, and a timing control unit that generates the timing control signal so that the coil current is sampled at the timing when the ramp signal takes a peak or bottom value. The converter is configured to generate a desired output voltage from an input voltage by performing output feedback control using a current mode control method with respect to the current sense signal.

[0012] Furthermore, the DC / DC converter disclosed herein includes an oscillator that generates sawtooth waveform ramp signals and inverting ramp signals that repeatedly rise or fall and reset with a common switching period while having opposite polarities to each other; a first comparator and a second comparator that compare an analog signal with the ramp signal and the inverting ramp signal, respectively, to generate a first comparison signal and a second comparison signal; a logic operation unit that generates a control signal for a switch output stage by performing a logic operation using the first comparison signal and the second comparison signal; a current detection unit that generates a current sense signal by sampling the coil current of the switch output stage at a timing corresponding to the timing control signal; and a timing control unit that generates the timing control signal so that the coil current is sampled at the reset timing of the ramp signal and the inverting ramp signal. The DC / DC converter is configured to generate a desired output voltage from an input voltage by performing output feedback control in a current mode control method using the current sense signal.

[0013] Furthermore, the DC / DC converter disclosed herein includes a current detection unit that generates a current sense signal by sampling the coil current of a switch output stage at a timing corresponding to a timing control signal, and a timing control unit that generates the timing control signal using a first internal signal and a second internal signal that it generates in synchronization with the on / off control of the switch output stage, so that the coil current is sampled at the center timing of the off period of the switch output stage. The converter is configured to generate a desired output voltage from an input voltage by performing output feedback control in a current mode control method using the current sense signal.

[0014] Further features, elements, steps, advantages, and characteristics of the present invention will become clearer from the detailed description of the best mode and the accompanying drawings that follow. [Effects of the Invention]

[0015] According to the invention disclosed in this specification, it is possible to provide a DC / DC converter that can maintain a constant average value of the coil current regardless of input / output conditions.

Brief Description of the Drawings

[0016] [Figure 1] Figure showing the first embodiment of the DC / DC converter [Figure 2] Figure showing the first operation example (peak value detection type) of the timing control unit [Figure 3] Figure showing the second operation example (bottom value detection type) of the timing control unit [Figure 4] Figure showing the third operation example (on-period center value detection type) of the timing control unit [Figure 5] Figure showing the fourth operation example (off-period center value detection type) of the timing control unit [Figure 6] Figure showing the second embodiment of the DC / DC converter [Figure 7] Figure showing the third embodiment of the DC / DC converter [Figure 8] Figure showing the fourth embodiment of the DC / DC converter [Figure 9] Figure showing the first operation example of the timing control unit in the fourth embodiment [Figure 10] Figure showing the second operation example of the timing control unit in the fourth embodiment [Figure 11] Figure showing the third operation example of the timing control unit in the fourth embodiment [Figure 12] Figure showing the fourth operation example of the timing control unit in the fourth embodiment [Figure 13] Figure showing the fifth operation example of the timing control unit in the fourth embodiment [Figure 14] Figure showing the fifth embodiment of the DC / DC converter [Figure 15] Figure showing the first operation example of the timing control unit in the fifth embodiment [Figure 16] Figure showing the second operation example of the timing control unit in the fifth embodiment [Figure 17]This figure shows a third example of the operation of the timing control unit in the fifth embodiment. [Figure 18] Figure showing the sixth embodiment of a DC / DC converter. [Figure 19] This figure shows an example of the oscillator configuration in the sixth embodiment. [Figure 20] This figure shows an example of oscillator oscillation operation in the sixth embodiment. [Figure 21] This figure shows a first example of the operation of the timing control unit in the sixth embodiment. [Figure 22] This figure shows a second example of the operation of the timing control unit in the sixth embodiment. [Figure 23] Figure showing the seventh embodiment of a DC / DC converter. [Figure 24] This figure shows an example of the oscillator configuration in the seventh embodiment. [Figure 25] This figure shows an example of oscillator oscillation operation in the seventh embodiment. [Figure 26] This figure shows an example of the operation of the timing control unit in the seventh embodiment. [Figure 27] Figure showing the eighth embodiment of the DC / DC converter. [Figure 28] This figure shows an example of the operation of the timing control unit in the eighth embodiment. [Figure 29] Figure showing the ninth embodiment of a DC / DC converter. [Figure 30] Timing chart showing the generation operation of the step-down drive signal. [Figure 31] Timing chart showing the generation operation of the boost drive signal. [Figure 32] This figure shows the first example of operation of the timing control unit in the ninth embodiment (during voltage reduction). [Figure 33] This figure shows a second example of the operation of the timing control unit in the ninth embodiment (during voltage boosting). [Figure 34] This figure shows an example of the oscillator configuration in the 10th embodiment. [Figure 35] This figure shows an example configuration of the timing control unit in the 10th embodiment. [Figure 36]This figure shows an example of the operation of the timing control unit in the 10th embodiment. [Modes for carrying out the invention]

[0017] <First Embodiment> Figure 1 is a circuit diagram showing a first embodiment of a DC / DC converter. The DC / DC converter 1 of this embodiment is a step-down switching power supply that generates a desired output voltage Vo from an input voltage Vi and supplies it to a load (not shown, such as a CPU [central processing unit]), and includes a switch output stage 10, a feedback voltage generation unit 20, an error amplifier 30, a phase compensation unit 40, a current detection unit 50, a differential amplifier 60, an oscillator 70, a PWM [pulse width modulation] comparator 80, a driver 90, a clamper 100, a light load detection comparator 110, and a timing control unit 120.

[0018] In addition to the circuit elements described above, the DC / DC converter 1 may also incorporate other protection circuits (such as undervoltage protection circuits, overvoltage protection circuits, and temperature protection circuits) as appropriate.

[0019] The switch output stage 10 is a step-down type that steps down the input voltage Vi to generate a desired output voltage Vo, and includes an output transistor 11 (PMOSFET [P channel type metal oxide semiconductor field effect transistor] in this figure), a synchronous rectifier transistor 12 (NMOSFET [N channel type MOSFET] in this figure), a coil 13, and a capacitor 14.

[0020] The source of the output transistor 11 is connected to the terminal to which the input voltage Vi is applied. The drain of the output transistor 11 is connected to the first terminal of the coil 13. The gate of the output transistor 11 is connected to the terminal to which the gate signal G1 is applied. The output transistor 11 is off when the gate signal G1 is high level and on when the gate signal G1 is low level.

[0021] The source of the synchronous rectifier transistor 12 is connected to the ground terminal (the terminal to which the ground voltage GND is applied). The drain of the synchronous rectifier transistor 12 is connected to the first terminal of the coil 13. The gate of the synchronous rectifier transistor 12 is connected to the terminal to which the gate signal G2 is applied. The synchronous rectifier transistor 12 turns on when the gate signal G2 is high level and turns off when the gate signal G2 is low level.

[0022] Furthermore, when a high voltage is applied to the switch output stage 10, it is preferable to use high-voltage elements such as power MOSFETs, IGBTs (insulated gate bipolar transistors), and SiC transistors as the output transistor 11 and synchronous rectifier transistor 12, respectively.

[0023] The output transistor 11 and the synchronous rectifier transistor 12 are switched on and off complementaryly in response to gate signals G1 and G2. This on / off operation generates a rectangular wave switch voltage Vsw at the first end of the coil 13, which is pulsed between the input voltage Vi and the ground voltage GND. The term "complementary" above includes not only the case where the on / off states of the output transistor 11 and the synchronous rectifier transistor 12 are completely reversed, but also the case where there is a simultaneous off period (dead time) for both transistors.

[0024] Furthermore, when integrating the components of the DC / DC converter 1 into an IC, the output transistor 11 and the synchronous rectifier transistor 12 may be built into the IC or provided externally. The output transistor 11 can also be replaced with an NMOSFET. However, in that case, it is necessary to raise the high level of the gate signal G1 above the input voltage Vi using a bootstrap circuit or the like. It is also possible to use a rectifier diode instead of the synchronous rectifier transistor 12.

[0025] The coil 13 and capacitor 14 form an LC filter that rectifies and smooths the switch voltage Vsw to generate the output voltage Vo. As mentioned earlier, the first end of the coil 13 is connected to the drains (= the application terminals of the switch voltage Vsw) of the output transistor 11 and the synchronous rectifier transistor 12, respectively. The second end of the coil 13 and the first end of the capacitor 14 are both connected to the application terminals of the output voltage Vo. The second end of the capacitor 14 is connected to the ground terminal.

[0026] The feedback voltage generation unit 20 includes resistors 21 and 22 connected in series between the application terminal and the ground terminal of the output voltage Vo, and outputs a feedback voltage FB (a divided voltage of the output voltage Vo) corresponding to the output voltage Vo from the connection node between the two resistors. If the output voltage Vo is within the input dynamic range of the error amplifier 30, the feedback voltage generation unit 20 may be omitted and the output voltage Vo may be input directly to the error amplifier 30.

[0027] The error amplifier 30 is a current-output type transconductance amplifier (a so-called gm amplifier) ​​that generates an error current signal I30 corresponding to the difference between the feedback voltage FB input to the inverting input terminal (-) and the first reference voltage REF1 (= corresponding to the target setting value of the output voltage Vo) input to the non-inverting input terminal (+). The error current signal I30 flows in the positive direction (= from the error amplifier 30 to the phase compensation unit 40) when the feedback voltage FB is lower than the first reference voltage REF1, and flows in the negative direction (= from the phase compensation unit 40 to the error amplifier 30) when the feedback voltage FB is higher than the first reference voltage REF1.

[0028] The phase compensation unit 40 includes a resistor 41 and a capacitor 42 connected in series between the output terminal and the ground terminal of the error amplifier 30, and generates an error voltage signal COMP upon receiving the error current signal I30. By appropriately setting the resistance value of resistor 41 and the capacitance value of capacitor 42, the phase of the error voltage signal COMP can be compensated to prevent oscillation of the output feedback loop.

[0029] The current detection unit 50 samples the coil current IL flowing through the coil 13 at a timing corresponding to the timing control signal ST, and generates a current sense signal ISNS according to the sampled value. The current sense signal ISNS can be, for example, a voltage signal that becomes higher as the sampled value of the coil current IL increases, and conversely, becomes lower as the sampled value of the coil current IL decreases.

[0030] The differential amplifier 60 generates a first analog signal VC1 corresponding to the difference between the error voltage signal COMP input to the non-inverting input terminal (+) and the current sense signal ISNS input to the inverting input terminal (-). The first analog signal VC1 decreases as the current sense signal ISNS is high and increases as the current sense signal ISNS is low. In other words, the first analog signal VC1 decreases as the coil current IL is large and increases as the coil current IL is small. Thus, the DC / DC converter 1 of this embodiment employs a current mode control method that detects both the output voltage Vo and the coil current IL and performs output feedback control.

[0031] The oscillator 70 generates a first ramp signal VR1, which is a ramp waveform (sawtooth waveform in this embodiment) that is pulse-driven with a predetermined switching period T (and consequently a predetermined switching frequency fsw (=1 / T)).

[0032] The PWM comparator 80 compares the first analog signal VC1 input to the non-inverting input terminal (+) with the first ramp signal VR1 input to the inverting input terminal (-) to generate the first comparison signal CMP1 (=corresponding to the control signal of the switch output stage 10). The first comparison signal CMP1 is at a high level when the first analog signal VC1 is higher than the first ramp signal VR1, and at a low level when the first analog signal VC1 is lower than the first ramp signal VR1. In other words, the on-duty cycle Don of the switch output stage 10 (=ton / T, i.e., the ratio of the on-period ton to the switching period T) becomes larger as the first analog signal VC1 is higher, and conversely, becomes smaller as the first analog signal VC1 is lower.

[0033] The driver 90 includes a NAND gate 91 and an AND gate 92, and generates gate signals G1 and G2 (corresponding to the drive signals for the switch output stage 10, respectively) in response to the first comparison signal CMP1. Specifically, the NAND gate 91 outputs a gate signal G1 which is the negative AND operation signal of the sleep control signal XSLP and the first comparison signal CMP1. The AND gate 92 outputs a gate signal G2 which is the AND operation signal of the sleep control signal XSLP and the first comparison signal CMP1 which is inverted.

[0034] Therefore, when the sleep control signal XSLP is at a high level (= the logic level at wake-up), the gate signals G1 and G2 are essentially the logic inversion signals of the first comparison signal CMP1. More specifically, when the first comparison signal CMP1 is at a high level, both gate signals G1 and G2 are at a low level, so the output transistor 11 turns on and the synchronous rectifier transistor 12 turns off. Conversely, when the first comparison signal CMP1 is at a low level, both gate signals G1 and G2 are at a high level, so the output transistor 11 turns off and the synchronous rectifier transistor 12 turns on.

[0035] On the other hand, when the sleep control signal XSLP is at a low level (= the logic level during sleep), the gate signal G1 becomes high level regardless of the first comparison signal CMP1, and the gate signal G2 becomes low level regardless of the first comparison signal CMP1. Consequently, both the output transistor 11 and the synchronous rectifier transistor 12 are turned off.

[0036] Thus, the DC / DC converter 1 of this embodiment has a function to switch to sleep mode (=output stopped state) by turning off both the output transistor 11 and the synchronous rectifier transistor 12 when the sleep control signal XSLP is at a low level.

[0037] The clamper 100 applies overcurrent protection (OCP) or reverse current protection (NCP) to the coil current IL (and consequently the load current flowing to the load) by limiting the error voltage signal COMP to below a predetermined upper limit or above a predetermined lower limit.

[0038] As mentioned earlier, in the DC / DC converter 1 of this embodiment, a current sense signal ISNS corresponding to the coil current IL is fed back to the differential amplifier 60. Therefore, when the error voltage signal COMP increases, the coil current IL increases, and when the error voltage signal COMP decreases, the coil current IL decreases. In this way, the magnitude of the coil current IL can be controlled according to the error voltage signal COMP.

[0039] Conversely, when the coil current IL increases, the on-duty cycle Don decreases, causing the output voltage Vo to decrease and the error voltage signal COMP to rise. When the coil current IL decreases, the on-duty cycle Don increases, causing the output voltage Vo to rise and the error voltage signal COMP to fall. In other words, the error voltage signal COMP can be said to contain information about the magnitude (current value) of the coil current IL. Therefore, by using clamper 100 to limit the error voltage signal COMP, it is possible to indirectly limit the coil current IL.

[0040] The light load detection comparator 110 compares the error voltage signal COMP input to the non-inverting input terminal (+) with the second reference voltage REF2 (corresponding to the light load detection threshold) input to the inverting input terminal (-) to generate a sleep control signal XSLP. The sleep control signal XSLP is at a high level (= the logic level at wake-up) when the error voltage signal COMP is higher than the second reference voltage REF2, and at a low level (= the logic level at sleep) when the error voltage signal COMP is lower than the second reference voltage REF2.

[0041] Thus, the sleep control signal XSLP goes to a low level when the coil current IL (and consequently the load current) decreases until the error voltage signal COMP falls below the second reference voltage REF2. Therefore, when the DC / DC converter 1 is under light load, the switching operation of the switch output stage 10 is stopped, which significantly improves the efficiency under light load.

[0042] The timing control unit 120 generates a timing control signal ST to determine the sampling timing of the coil current IL in the current detection unit 50. Next, an example of the operation of the timing control unit 120 (method for generating the timing control signal ST) will be described in detail.

[0043] <Timing Control Unit> Figure 2 is a waveform diagram showing a first operation example (peak value detection type) of the timing control unit 120, with the input voltage Vi, coil current IL, and timing control signal ST depicted from top to bottom. In this first operation example, the timing control signal ST is generated to sample the peak value Ip (maximum value) of the coil current IL. Therefore, the DC / DC converter 1 applies output feedback control to maintain the peak value Ip of the coil current IL at a constant level.

[0044] Figure 3 is a waveform diagram showing a second operation example (bottom value detection type) of the timing control unit 120. As with Figure 2, the input voltage Vi, coil current IL, and timing control signal ST are depicted from top to bottom. In this second operation example, the timing control signal ST is generated to sample the bottom value Ib (minimum value) of the coil current IL. Therefore, the DC / DC converter 1 applies output feedback control to maintain the bottom value Ib of the coil current IL at a constant level.

[0045] Thus, general current-mode control methods are classified into peak-value detection type (Figure 2) and bottom-value detection type (Figure 3) depending on the sampling timing of the coil current IL. However, in these control methods, for example, if the ripple component of the coil current IL changes due to fluctuations in the input voltage Vi, the average coil current Idc (corresponding to the DC component of the coil current Idc) changes when the error voltage signal COMP is kept constant. As a result, the thresholds for overcurrent protection operation and light load detection operation change depending on the input / output conditions, making application design difficult. Countermeasures are described below.

[0046] Figure 4 is a waveform diagram showing the third operation example (on-period center value detection type) of the timing control unit 120, and from top to bottom, the input voltage Vi, coil current IL, switch voltage Vsw, and timing control signal ST are depicted. In this third operation example, the timing control signal ST is generated to sample the center value Ic of the coil current IL at the center timing of the on-period ton of the switch output stage 10 (= the period when the output transistor 11 is on and the synchronous rectifier transistor 12 is off, i.e., the high-level period of the switch voltage Vsw). Therefore, the DC / DC converter 1 applies output feedback control to maintain the center value Ic of the coil current IL at a constant level.

[0047] Here, the center value Ic of the coil current IL is equal to the average coil current Idc (and consequently the load current) mentioned above. Therefore, by limiting the error voltage signal COMP to below a predetermined upper limit or above a predetermined lower limit, it becomes possible to apply overcurrent protection or reverse current protection with a constant load current, regardless of input / output conditions. Furthermore, by stopping the switching operation of the switch output stage 10 when the error voltage signal COMP falls below a predetermined threshold, it becomes possible to transition to sleep mode with a constant load current, regardless of input / output conditions.

[0048] Figure 5 is a waveform diagram showing the fourth operation example (off-period center value detection type) of the timing control unit 120. As with Figure 4, the input voltage Vi, coil current IL, switch voltage Vsw, and timing control signal ST are depicted from top to bottom. In this fourth operation example, the timing control signal ST is generated to sample the center value Ic of the coil current IL at the center timing of the off-period tooff of the switch output stage 10 (= the period when the output transistor 11 is off and the synchronous rectifier transistor 12 is on, i.e., the low-level period of the switch voltage Vsw). Therefore, as with the third operation example, the DC / DC converter 1 applies output feedback control to maintain the center value Ic of the coil current IL at a constant level.

[0049] Furthermore, if the ON period ton is short, it becomes difficult to complete the sampling of the coil current IL during that period, so it is desirable to set the sampling timing to the OFF period Toff. Conversely, if the OFF period toff is short, the sampling of the coil current IL can be performed during the ON period Ton.

[0050] <Second Embodiment> Figure 6 is a circuit diagram showing a third embodiment of the DC / DC converter. The DC / DC converter 1 of this embodiment is based on the first embodiment (Figure 1), but has an arithmetic unit 130 instead of a differential amplifier 60, and is characterized in that the current sense signal ISNS is fed back to the arithmetic unit 130 instead of the differential amplifier 60. Therefore, for components that are the same as in the first embodiment, the same reference numerals as in Figure 1 are used to omit redundant explanations, and the following will focus on the characteristic parts of the second embodiment.

[0051] The arithmetic unit 130 generates a first analog signal VC (=COMP-ISNS) by performing calculations on the error voltage signal COMP and the current sense signal ISNS (for example, subtraction by subtracting the current sense signal ISNS from the error voltage signal COMP).

[0052] Thus, when performing output feedback control using the current mode control method, the current sense signal ISNS can be subtracted from the error voltage signal COMP input to the non-inverting input terminal (+) of the PWM comparator 80.

[0053] <Third Embodiment> Figure 7 is a circuit diagram showing a third embodiment of the DC / DC converter. The DC / DC converter 1 of this embodiment is based on the second embodiment (Figure 6), but is characterized by the use of an arithmetic unit 140 instead of an arithmetic unit 130. Therefore, for components similar to those of the second embodiment, the same reference numerals as in Figure 6 are used to omit redundant explanations, and the following explanation will focus on the distinctive features of the third embodiment.

[0054] The arithmetic unit 140 generates an offset first ramp signal VR1' (=VR1+ISNS) by performing calculations on the first ramp signal VR1 and the current sense signal ISNS (for example, by adding the first ramp signal VR1 and the current sense signal ISNS).

[0055] Following the above changes, the PWM comparator 80 compares the first analog signal VC1 input to the non-inverting input terminal (+) with the offset first ramp signal VR1' input to the inverting input terminal (-) to generate the first comparison signal CMP1.

[0056] Thus, when performing output feedback control using the current mode control method, the current sense signal ISNS may be added to the first ramp signal VR1 which is input to the inverting input terminal (-) of the PWM comparator 80.

[0057] Furthermore, since various variations are possible for implementing the current mode control method, we will refrain from illustrating all of them due to space limitations. However, for example, output feedback control of the current mode control method can be performed by adding or subtracting a signal containing the error information of the output voltage from the current sense signal and inputting the result to an amplifier or comparator. Alternatively, output feedback control of the current mode control method can be performed by inputting the current sense signal or a signal obtained by applying a predetermined arithmetic operation (addition, subtraction, multiplication, or division) to it, along with a signal containing the error information of the output voltage, to an amplifier or comparator.

[0058] In the embodiments described above, the advantages of adopting a center value detection type (Figures 4 and 5) current mode control method were explained. In the following embodiments, the timing control method for correctly detecting the center value Ic of the coil current IL will be described in detail with specific examples.

[0059] <Fourth Embodiment> Figure 8 shows a fourth embodiment of the DC / DC converter. The DC / DC converter 1 of this embodiment is based on the first embodiment (Figure 1) but is characterized by generating a timing control signal ST using a first analog signal VC1 and a second ramp signal VR2. Therefore, for components similar to those of the first embodiment, the same reference numerals as in Figure 1 are used to omit redundant explanations, and the following will focus on the characteristic features of the fourth embodiment.

[0060] In the DC / DC converter 1 of this embodiment, the oscillator 70 generates a first ramp signal VR1 and supplies it to the inverting input terminal (-) of the PWM comparator 80, while simultaneously generating a second ramp signal VR2 synchronized with the first ramp signal VR1 and supplying it to the timing control unit 120. The second ramp signal VR2 is a sawtooth waveform signal with twice the slew rate of the first ramp signal VR1.

[0061] The timing control unit 120 generates a timing control signal ST using both the first analog signal VC1 and the second ramp signal VR2, so that the coil current IL is sampled at the center timing of the on period ton or the off period tooff of the switch output stage 10. The following describes in detail a specific example of the operation of the timing control unit 120.

[0062] Figure 9 is a waveform diagram showing a first operation example of the timing control unit 120 in the fourth embodiment. From top to bottom, the first analog signal VC1 (dotted line), the first ramp signal VR1 (solid line), the second ramp signal VR2 (dashed line), the coil current IL, and the timing control signal ST are depicted.

[0063] As shown in this figure, both the first lamp signal VR1 and the second lamp signal VR2 repeatedly increase and reset with a common switching period T.

[0064] When the first analog signal VC1 is higher than the first ramp signal VR1, the switch output stage 10 enters an on period ton, and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than the first ramp signal VR1, the switch output stage 10 enters an off period tooff, and the coil current IL decreases.

[0065] In other words, the higher the first analog signal VC1, the larger the on-duty cycle Don (=ton / T) of the switch output stage 10 becomes, and conversely, the lower the first analog signal VC1, the smaller the on-duty cycle Don of the switch output stage 10 becomes.

[0066] Here, the timing control unit 120 compares the first analog signal VC1 and the second ramp signal VR2 to generate a timing control signal ST. More specifically, the timing control unit 120 generates a one-shot pulse in the timing control signal ST at the timing when the second ramp signal VR2 rises and intersects with the first analog signal VC1.

[0067] As shown in this figure, the timing at which the second lamp signal VR2 and the first analog signal VC1 intersect coincides with the center timing of the ON period ton (= the timing when ton / 2 has elapsed since the coil current IL began to increase).

[0068] Therefore, the current detection unit 50 can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL during the ON period ton by sampling the coil current IL using a one-shot pulse of the timing control signal ST as a trigger.

[0069] Figure 10 is a waveform diagram showing a second operation example of the timing control unit 120 in the fourth embodiment. Similar to Figure 9, the first analog signal VC1 (dotted line), the first ramp signal VR1 (solid line), the second ramp signal VR2 (dashed line), the coil current IL, and the timing control signal ST are depicted from top to bottom.

[0070] In the second operation example shown in this figure, both the first lamp signal VR1 and the second lamp signal VR2 repeatedly rise and reset with a common switching period T. However, the relationship between the first analog signal VC1 and the on-duty cycle Don is reversed compared to the first operation example (Figure 9).

[0071] Specifically, when the first analog signal VC1 is higher than the first ramp signal VR1, the switch output stage 10 enters an off period (toff), and the coil current IL decreases. On the other hand, when the first analog signal VC1 is lower than the first ramp signal VR1, the switch output stage 10 enters an on period (ton), and the coil current IL increases.

[0072] In other words, the higher the first analog signal VC1, the smaller the on-duty cycle Don (=ton / T) of the switch output stage 10 becomes, and conversely, the lower the first analog signal VC1, the larger the on-duty cycle Don of the switch output stage 10 becomes.

[0073] To achieve this operation, for example, the input polarity of the error amplifier 30 and the input polarity of the PWM comparator 80 can be inverted from those shown in Figure 8.

[0074] Here, the timing control unit 120 compares the first analog signal VC1 and the second ramp signal VR2 to generate a timing control signal ST, just as in the first operation example (Figure 9). More specifically, the timing control unit 120 generates a one-shot pulse for the timing control signal ST at the timing when the second ramp signal VR2 rises and intersects with the first analog signal VC1.

[0075] As shown in this figure, the timing at which the second ramp signal VR2 and the first analog signal VC1 intersect coincides with the center timing of the off period toff (= the timing when toff / 2 has elapsed since the coil current IL began to decrease).

[0076] Therefore, the current detection unit 50 can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL during the off period tooff by sampling the coil current IL using a one-shot pulse of the timing control signal ST as a trigger.

[0077] Figure 11 is a waveform diagram showing a third operation example of the timing control unit 120 in the fourth embodiment. Similar to Figures 9 and 10, the first analog signal VC1 (dotted line), the first ramp signal VR1 (solid line), the second ramp signal VR2 (dashed line), the coil current IL, and the timing control signal ST are depicted from top to bottom.

[0078] In the third operating example shown in this figure, the polarity of the first lamp signal VR1 and the second lamp signal VR2 is reversed compared to the first operating example (Figure 9). That is, both the first lamp signal VR1 and the second lamp signal VR2 repeatedly decrease and reset with a common switching period T.

[0079] When the first analog signal VC1 is higher than the first ramp signal VR1, the switch output stage 10 enters an on period ton, and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than the first ramp signal VR1, the switch output stage 10 enters an off period tooff, and the coil current IL decreases.

[0080] In other words, the higher the first analog signal VC1, the larger the on-duty cycle Don (=ton / T) of the switch output stage 10. Conversely, the lower the first analog signal VC1, the smaller the on-duty cycle Don of the switch output stage 10. This is the same as in the first operation example (Figure 9) mentioned earlier.

[0081] Here, the timing control unit 120 compares the first analog signal VC1 and the second ramp signal VR2 to generate a timing control signal ST, just as in the first operation example (Figure 9). More specifically, the timing control unit 120 generates a one-shot pulse for the timing control signal ST at the timing when the second ramp signal VR2 decreases and intersects with the first analog signal VC1.

[0082] As shown in this figure, the timing at which the second ramp signal VR2 and the first analog signal VC1 intersect coincides with the center timing of the off period toff (= the timing when toff / 2 has elapsed since the coil current IL began to decrease).

[0083] Therefore, the current detection unit 50 can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL during the off period tooff by sampling the coil current IL using a one-shot pulse of the timing control signal ST as a trigger.

[0084] Thus, in the third operation example shown in this figure, unlike the second operation example (Figure 10), it is possible to sample the center value Ic of the coil current IL during the off period tooff while maintaining the relationship between the first analog signal VC1 and the on-duty cycle Don as before.

[0085] Figure 12 is a waveform diagram showing a fourth example of the operation of the timing control unit 120 in the fourth embodiment. Similar to Figures 9 to 11, the first analog signal VC1 (dotted line), the first ramp signal VR1 (solid line), the second ramp signal VR2 (dashed line), the coil current IL, and the timing control signal ST are depicted from top to bottom.

[0086] In the fourth operation example shown in this figure, just like in the first operation example (Figure 9), both the first lamp signal VR1 and the second lamp signal VR2 repeatedly rise and reset with a common switching period T. However, the second lamp signal VR2 starts rising with a delay of 1 / 2 of the switching period T from the point when the first lamp signal VR1 starts rising.

[0087] When the first analog signal VC1 is higher than the first ramp signal VR1, the switch output stage 10 enters an on period ton, and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than the first ramp signal VR1, the switch output stage 10 enters an off period tooff, and the coil current IL decreases.

[0088] In other words, the higher the first analog signal VC1, the larger the on-duty cycle Don (=ton / T) of the switch output stage 10. Conversely, the lower the first analog signal VC1, the smaller the on-duty cycle Don of the switch output stage 10. This is the same as in the first operation example (Figure 9) mentioned earlier.

[0089] Here, the timing control unit 120 compares the first analog signal VC1 and the second ramp signal VR2 to generate a timing control signal ST, just as in the first operation example (Figure 9). More specifically, the timing control unit 120 generates a one-shot pulse for the timing control signal ST at the timing when the second ramp signal VR2 rises and intersects with the first analog signal VC1.

[0090] As shown in this figure, the timing at which the second ramp signal VR2 and the first analog signal VC1 intersect coincides with the center timing of the off period toff (= the timing when toff / 2 has elapsed since the coil current IL began to decrease).

[0091] Therefore, the current detection unit 50 can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL during the off period tooff by sampling the coil current IL using a one-shot pulse of the timing control signal ST as a trigger.

[0092] Thus, in the fourth operation example shown in this figure, unlike the third operation example (Figure 11), it is possible to sample the center value Ic of the coil current IL during the off period tooff while maintaining the relationship between the first analog signal VC1 and the on-duty cycle Don as before, without reversing the polarity of the first lamp signal VR1 and the second lamp signal VR2.

[0093] Figure 13 is a waveform diagram showing a fifth operation example of the timing control unit 120 in the fourth embodiment. From top to bottom, it depicts the first analog signal VC1 (dotted line), the equivalent analog signal VC1' (double-dotted line), the first ramp signal VR1 (solid line), the second ramp signal VR2 (dashed line), the coil current IL, and the timing control signal ST.

[0094] The fifth operation example in this figure is basically the same as the first operation example (Figure 9). However, the timing control unit 120 differs in that it generates the timing control signal ST by comparing an equivalent analog signal VC1', which has equivalent information to the first analog signal VC1, with the second ramp signal VR2 instead of the first analog signal VC1.

[0095] In a configuration where the first analog signal VC1 is compared with multiple ramp signals (=first ramp signal VR1 and second ramp signal VR2), the risk of the first analog signal VC1 fluctuating due to noise (=risk of unstable PWM control) is higher compared to a configuration where the first analog signal VC1 is compared with a single ramp signal (=first ramp signal VR1 only).

[0096] Therefore, in order to improve the stability of PWM control, it is desirable to compare the second ramp signal VR2 with an equivalent analog signal VC1' that has the same information as the first analog signal VC1, rather than comparing the first analog signal VC1 itself with the second ramp signal VR2.

[0097] As for generating the equivalent analog signal VC1', a simple method is to simply buffer the first analog signal VC1.

[0098] Another approach is to calculate the theoretical value of the first analog signal VC1 (=α × (Vo / Vi) × T, where α is the slew rate of the first ramp signal VR1) from the actual value of the input voltage Vi and the target value of the output voltage Vo, and then generate an equivalent analog signal VC1' with that value.

[0099] In the latter method, as shown in this figure, if the first analog signal VC1 fluctuates transiently, it becomes impossible to correctly sample the center value Ic of the coil current IL. However, the shift in sampling timing is only temporary and does not cause any particular problems with overcurrent protection or light load detection.

[0100] In the fifth operation example shown in this figure, an example based on the first operation example (Figure 9) is given. However, it is also possible to perform a comparison process between the equivalent analog signal VC1' and the second ramp signal VR2 in the second to fourth operation examples (Figures 10 to 12).

[0101] <Fifth Embodiment> Figure 14 shows a fifth embodiment of the DC / DC converter. The DC / DC converter 1 of this embodiment is based on the first embodiment (Figure 1) but is characterized by generating a timing control signal ST using a first ramp signal VR1 and a second analog signal VC2. Therefore, for components similar to those of the first embodiment, the same reference numerals as in Figure 1 are used to omit redundant explanations, and the following will focus on the characteristic features of the fifth embodiment.

[0102] The DC / DC converter 1 of this embodiment has an average value generation unit 150 as a means for generating a second analog signal VC2. The average value generation unit 150 generates a second analog signal VC2 which has a simple average value of the signal value of the first analog signal VC1 and the start value or end value of the first ramp signal VR1.

[0103] The timing control unit 120 generates a timing control signal ST using both the first ramp signal VR1 and the second analog signal VC2, so that the coil current IL is sampled at the center timing of the on period ton or the off period tooff of the switch output stage 10. The following describes in detail a specific example of the operation of the timing control unit 120.

[0104] Figure 15 is a waveform diagram showing a first operation example of the timing control unit 120 in the fifth embodiment, and from top to bottom, it depicts the first analog signal VC1 (dotted line), the second analog signal VC2 (double dotted line), the first ramp signal VR1 (solid line), the coil current IL, and the timing control signal ST.

[0105] As shown in this figure, the first ramp signal VR1 is a sawtooth waveform signal that repeatedly rises and resets with a predetermined switching period T.

[0106] When the first analog signal VC1 is higher than the first ramp signal VR1, the switch output stage 10 enters an on period ton, and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than the first ramp signal VR1, the switch output stage 10 enters an off period tooff, and the coil current IL decreases.

[0107] In other words, the higher the first analog signal VC1, the larger the on-duty cycle Don (=ton / T) of the switch output stage 10 becomes, and conversely, the lower the first analog signal VC1, the smaller the on-duty cycle Don of the switch output stage 10 becomes.

[0108] Here, the average value generation unit 150 generates a second analog signal VC2 (=(VC1+VR1L) / 2) which has a simple average value of the signal value of the first analog signal VC1 and the starting value of the first ramp signal VR1 (=the bottom value VR1L of the first ramp signal VR1 in this figure).

[0109] Furthermore, the timing control unit 120 compares the first ramp signal VR1 and the second analog signal VC2 to generate a timing control signal ST. More specifically, the timing control unit 120 generates a one-shot pulse in the timing control signal ST at the timing when the first ramp signal VR1 rises and intersects with the second analog signal VC2.

[0110] As shown in this figure, the timing at which the first ramp signal VR1 and the second analog signal VC2 intersect coincides with the center timing of the ON period ton (= the timing when ton / 2 has elapsed since the coil current IL began to increase).

[0111] Therefore, the current detection unit 50 can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL during the ON period ton by sampling the coil current IL using a one-shot pulse of the timing control signal ST as a trigger.

[0112] In the previous fourth embodiment (Figures 8 to 13), it was necessary to generate a second lamp signal VR2 with twice the slew rate to track the first lamp signal VR1, whose voltage value fluctuates rapidly. However, in this embodiment, the second lamp signal VR2 is not required. Therefore, if generating the second lamp signal VR2 is difficult, it is desirable to adopt this embodiment.

[0113] Figure 16 is a waveform diagram showing a second operation example of the timing control unit 120 in the fifth embodiment. Similar to Figure 15, the first analog signal VC1 (dotted line), the second analog signal VC2 (double-dotted line), the first ramp signal VR1 (solid line), the coil current IL, and the timing control signal ST are depicted from top to bottom.

[0114] The second example of operation in this figure is basically the same as the first example of operation (Figure 15) shown earlier, but the difference is that the average value generation unit 150 generates a second analog signal VC2 (= (VC1 + VR1H) / 2) which has a simple average value of the signal value of the first analog signal VC1 and the endpoint value of the first ramp signal VR1 (= the peak value of the first ramp signal VR1, VR1H, in this figure).

[0115] In this case, the timing at which the first ramp signal VR1 and the second analog signal VC2 intersect coincides with the center timing of the off period toff (= the timing when toff / 2 has elapsed since the coil current IL began to decrease).

[0116] Therefore, the current detection unit 50 can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL during the off period tooff by sampling the coil current IL using a one-shot pulse of the timing control signal ST as a trigger.

[0117] Figure 17 is a waveform diagram showing a third operation example of the timing control unit 120 in the fifth embodiment, and from top to bottom, it depicts the first analog signal VC1 (dotted line), the second analog signal VC2 (double dotted line), the first ramp signal VR1 (solid line), the second ramp signal VR2 (dashed line), the coil current IL, and the timing control signal ST.

[0118] The operation example shown in this figure is basically the same as the first operation example (Figure 15) mentioned earlier, but the difference is that the average value generation unit 150 generates a second analog signal VC2 which has a weighted average value of the signal value of the first analog signal VC1 and the start value or end value of the first ramp signal VR1.

[0119] Furthermore, in accordance with the above changes, the timing control unit 120 generates a timing control signal ST using a second ramp signal VR2 having a different slew rate than the first ramp signal VR1 and a second analog signal VC2, so that the coil current IL is sampled at the center timing of the on period ton or off period toff of the switch output stage 10. Note that, unlike the previous fourth embodiment (Figures 8 to 13), the second ramp signal VR2 does not necessarily have twice the slew rate of the first ramp signal VR1.

[0120] For example, as shown in this diagram, the second analog signal VC2 has a weighted average value (=mVC1+nVR1L) of the signal value (weight m) of the first analog signal VC1 and the bottom value VR1L (weight n) of the first ramp signal VR1. Also, the second ramp signal VR2 has a slew rate 2m / (m+n) times that of the first ramp signal VR1.

[0121] With this configuration, the timing at which the second ramp signal VR2 and the second analog signal VC2 intersect coincides with the center timing of the ON period ton (= the timing when ton / 2 has elapsed since the coil current IL began to increase).

[0122] Therefore, the current detection unit 50 can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL during the ON period ton by sampling the coil current IL using a one-shot pulse of the timing control signal ST as a trigger.

[0123] <Sixth Embodiment> Figure 18 shows a sixth embodiment of the DC / DC converter. The DC / DC converter 1 of this embodiment is based on the first embodiment (Figure 1), but is characterized in that it uses a triangular waveform third ramp signal VR3 instead of a sawtooth waveform first ramp signal VR1 for PWM control, and detects the timing when the third ramp signal VR3 takes a peak value VR3H or a bottom value VR3L (= peak timing or bottom timing) to generate a timing control signal ST.Therefore, for components that are the same as in the first embodiment, the same reference numerals as in Figure 1 are used to omit redundant explanations, and the following will focus on the characteristic parts of the sixth embodiment.

[0124] In the DC / DC converter 1 of this embodiment, the oscillator 70 generates a third ramp signal VR3, which is a triangular waveform with equal up / down slew rates, and supplies it to the inverting input terminal (-) of the PWM comparator 80. The oscillator 70 also generates a first clock signal CLK1, whose logic level switches at the peak and bottom timings of the third ramp signal VR3, and supplies it to the timing control unit 120.

[0125] Figure 19 is a circuit diagram showing one example configuration of the oscillator 70 in the sixth embodiment. The oscillator 70 in this example configuration includes current sources 71a and 71b, switches 72a and 72b, a capacitor 73a, a comparator 74a, resistors 75a, 75b and 75c, and a selector 76.

[0126] The first terminal of the current source 71a is connected to the application terminal of the power supply voltage VDD. The second terminal of the current source 71a is connected to the first terminal of the switch 72a. The second terminal of the switch 72a, the first terminal of the switch 72b, the first terminal of the capacitor 73a, and the non-inverting input terminal (+) of the comparator 74a are all connected to the output terminal of the third ramp signal VR3. The second terminal of the switch 72b is connected to the first terminal of the current source 71b. The second terminal of the current source 71b and the second terminal of the capacitor 73a are connected to the ground terminal.

[0127] Resistors 75a, 75b, and 75c are connected in series between the application terminal and the ground terminal of the reference voltage VREF in the order shown in the diagram. The connection node between resistor 75a and resistor 75b is connected to the first input terminal of selector 76 as the output terminal of the first voltage divider (corresponding to the peak value VR3H of the third ramp signal VR3). The connection node between resistor 75b and resistor 75c is connected to the second input terminal of selector 76 as the output terminal of the second voltage divider (corresponding to the bottom value VR3L of the third ramp signal VR3), which is lower than the first voltage divider. The output terminal of selector 76 is connected to the inverting input terminal (-) of comparator 74 as the output terminal of the threshold voltage VTH. The control terminals of switches 72a and 72b, and selector 76, are all connected to the output terminal of comparator 74a (= output terminal of the first clock signal CLK1).

[0128] In the oscillator 70 having the above configuration, the current source 71a generates a predetermined charging current I71a, and the current source 71b generates a discharge current I71b that is equal to the charging current I71a.

[0129] Furthermore, switches 72a and 72b are turned on / off in response to the first clock signal CLK1 to switch between charging capacitor 73a with charging current I71a and discharging capacitor 73a with discharge current I71b.

[0130] Specifically, when the first clock signal CLK1 is at a low level, switch 72a turns on and switch 72b turns off, causing capacitor 73a to be charged by the charging current I71a. Consequently, the third ramp signal VR3 rises monotonically at a predetermined upward slew rate (see time t1~t2 in Figure 20).

[0131] On the other hand, when the first clock signal CLK1 is at a high level, switch 72a turns off and switch 72b turns on, causing capacitor 73a to discharge with discharge current I71b. Consequently, the third ramp signal VR3 decreases monotonically with a down slew rate equal to the up slew rate (with the opposite polarity) (see time t2~t3 in Figure 20).

[0132] Comparator 74a generates the first clock signal CLK1 by comparing the third ramp signal VR3 with the threshold voltage VTH (= peak value VR3H or bottom value VR3L). Selector 76 selects the peak value VR3H as the threshold voltage VTH when the first clock signal CLK1 is at a low level (see times t1~t2 in Figure 20), and conversely, selects the bottom value VR3L as the threshold voltage VTH when the first clock signal CLK1 is at a high level (see times t2~t3 in Figure 20).

[0133] Therefore, when the first clock signal CLK1 is at a low level, the first clock signal CLK1 is maintained at a low level until the third ramp signal VR3 exceeds its peak value VR3H. When the third ramp signal VR3 exceeds its peak value VR3H, the first clock signal CLK1 is raised from a low level to a high level (see times t1 to t2 in Figure 20).

[0134] On the other hand, when the first clock signal CLK1 is at a high level, the first clock signal CLK1 is maintained at a high level until the third ramp signal VR3 falls below the bottom value VR3L. When the third ramp signal VR3 falls below the bottom value VR3L, the first clock signal CLK1 is lowered from a high level to a low level (see time t2~t3 in Figure 20).

[0135] Thus, the comparator 74a, resistors 75a to 75c, and selector 76 function as a clock signal generation unit that generates the first clock signal CLK1 by comparing the third ramp signal VR3 with the peak value VR3H and the bottom value VR3L.

[0136] The timing control unit 120 receives the input of the first clock signal CLK1 described above and generates a timing control signal ST so that the coil current IL is sampled at the timing when its logic level switches (= the peak timing or bottom timing of the third ramp signal VR3). The following describes in detail a specific example of the operation of the timing control unit 120.

[0137] Figure 21 is a waveform diagram showing a first operation example of the timing control unit 120 in the sixth embodiment, and from top to bottom, the first analog signal VC1 (dotted line), the third ramp signal VR3 (solid line), the coil current IL, and the timing control signal ST are depicted.

[0138] As shown in this figure, the third ramp signal VR3 has a predetermined switching period T, and it rises to a peak value VR3H, then starts to decrease, and then starts to rise again when it reaches a bottom value VR3L, repeating the cycle of rising and falling between the peak value VR3H and the bottom value VR3L.

[0139] When the first analog signal VC1 is higher than the third ramp signal VR3, the switch output stage 10 enters an ON period (ton), and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than the third ramp signal VR3, the switch output stage 10 enters an OFF period (toff), and the coil current IL decreases.

[0140] In other words, the higher the first analog signal VC1, the larger the on-duty cycle Don (=ton / T) of the switch output stage 10 becomes, and conversely, the lower the first analog signal VC1, the smaller the on-duty cycle Don of the switch output stage 10 becomes.

[0141] Here, the timing control unit 120 generates a one-shot pulse for the timing control signal ST at the bottom timing when the third ramp signal VR3 takes its bottom value VR3L (corresponding to the timing when the first clock signal CLK1 falls from a high level to a low level).

[0142] As shown in this figure, the bottom timing of the third ramp signal VR3 coincides with the center timing of the on period ton (= the timing when ton / 2 has elapsed since the coil current IL began to increase).

[0143] Therefore, the current detection unit 50 can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL during the ON period ton by sampling the coil current IL using a one-shot pulse of the timing control signal ST as a trigger.

[0144] Thus, if PWM control is performed using a triangular waveform third ramp signal VR3 instead of a sawtooth waveform first ramp signal VR1, it becomes possible to easily sample the center value Ic of the coil current IL simply by detecting the peak timing or bottom timing of the third ramp signal VR3.

[0145] Figure 22 is a waveform diagram showing a second example of the operation of the timing control unit 120 in the sixth embodiment. Similar to Figure 21, the first analog signal VC1 (dotted line), the third ramp signal VR3 (solid line), the coil current IL, and the timing control signal ST are depicted from top to bottom.

[0146] The second example of operation in this figure is basically the same as the first example of operation (Figure 21). However, the timing control unit 120 differs in that it generates a one-shot pulse for the timing control signal ST at the peak timing when the third ramp signal VR3 takes its peak value VR3H (corresponding to the timing when the first clock signal CLK1 rises from a low level to a high level).

[0147] As shown in this figure, the peak timing of the third ramp signal VR3 coincides with the center timing of the off period toff (= the timing when toff / 2 has elapsed since the coil current IL began to decrease).

[0148] Therefore, the current detection unit 50 can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL during the off period tooff by sampling the coil current IL using a one-shot pulse of the timing control signal ST as a trigger.

[0149] <Seventh Embodiment> Figure 23 shows a seventh embodiment of the DC / DC converter. The DC / DC converter 1 of this embodiment is based on the first embodiment (Figure 1), but has a newly added PWM comparator 160 and OR gate 170. It is characterized by performing PWM control using a first ramp signal VR1 and an inverted first ramp signal VR1B obtained by inverting its polarity, and by detecting the reset timing of each to generate a timing control signal ST. Therefore, for components similar to those of the first embodiment, the same reference numerals as in Figure 1 are used to omit redundant explanations, and the following will focus on the characteristic features of the seventh embodiment.

[0150] In the DC / DC converter 1 of this embodiment, the oscillator 70 generates a sawtooth waveform first ramp signal VR1 and an inverted first ramp signal VR1B, which have opposite polarities to each other but repeatedly rise or fall and reset with a common switching period T, and supplies them to the inverted input terminals (-) of the PWM comparators 80 and 160, respectively. The oscillator 70 also generates a second clock signal CLK2, which generates a one-shot pulse at the reset timing of the first ramp signal VR1 and the inverted first ramp signal VR1B, and supplies it to the timing control unit 120.

[0151] As mentioned earlier, the PWM comparator 80 generates a first comparison signal CMP1 by comparing the first analog signal VC1 input to the non-inverting input terminal (+) with the first ramp signal VR1 input to the inverting input terminal (-). The first comparison signal CMP1 is at a high level when the first analog signal VC1 is higher than the first ramp signal VR1, and at a low level when the first analog signal VC1 is lower than the first ramp signal VR1.

[0152] Meanwhile, the PWM comparator 160 compares the first analog signal VC1 input to the non-inverting input terminal (+) with the inverting first ramp signal VR1B input to the inverting input terminal (-) to generate a second comparison signal CMP2. The second comparison signal CMP2 is high level when the first analog signal VC1 is higher than the inverting first ramp signal VR1B, and low level when the first analog signal VC1 is lower than the inverting first ramp signal VR1B.

[0153] The OR gate 170 generates a logical OR signal SX (corresponding to the control signal of the switch output stage 10) of the first comparison signal CMP1 and the second comparison signal CMP2, and outputs it to the driver 90. The logical OR signal SX is high level when at least one of the first comparison signal CMP1 and the second comparison signal CMP2 is high level, and low level when both the first comparison signal CMP1 and the second comparison signal CMP2 are low level.

[0154] Figure 24 is a circuit diagram showing one example configuration of the oscillator 70 in the seventh embodiment. The oscillator 70 in this example configuration includes a current source 71c, switches 72c and 72d, capacitors 73b and 73c, a comparator 74b, and a delay unit 77.

[0155] The first terminal of the current source 71c is connected to the application terminal of the power supply voltage VDD. The second terminal of the current source 71c, the first terminal of the switch 73b, the first terminal of the capacitor 73b, and the non-inverting input terminal (+) of the comparator 74b are all connected to the output terminal of the first ramp signal VR1. The second terminal of the switch 72c and the second terminal of the capacitor 73b are connected to the application terminal (e.g., the ground terminal) of the first voltage VR1L (=corresponding to the bottom value VR1L of the first ramp signal VR1 and the inverted first ramp signal VR1B, respectively). The inverting input terminal (-) of the comparator 74b is connected to the application terminal of the second voltage VR1H (=corresponding to the peak value VR1H of the first ramp signal VR1 and the inverted first ramp signal VR1B). The output terminal of the comparator 74b is connected to the input terminal of the delay unit 77.

[0156] The first terminal of switch 72d and the first terminal of capacitor 73c are both connected to the application terminal of the second voltage VR1H. The second terminal of switch 72d, the second terminal of capacitor 73c, and the first terminal of current source 71d are all connected to the output terminal of the inverting first ramp signal VR1B. The second terminal of current source 71d is connected to the application terminal of the first voltage VR1L. The control terminals of switches 72c and 72d are both connected to the output terminal of the delay unit 77 (= the output terminal of the second clock signal CLK2).

[0157] In the oscillator 70 configured as described above, the current source 71c generates a charging current I71c for charging the capacitor 73b, and the current source 71d generates a charging current I71d for charging the capacitor 73c. ​​The charging currents I71c and I71d are set to equal values.

[0158] Furthermore, switches 72c and 72d are both switched on / off in accordance with the second clock signal CLK2 to discharge capacitors 73b and 73c. ​​More specifically, when the second clock signal CLK2 is at a low level, both switches 72c and 72d are turned off, so that capacitors 73b and 73c are charged by charging currents I71c and I71d, respectively. Consequently, the first ramp signal VR1 rises monotonically from the bottom value VR1L to the peak value VR1H at a predetermined upward slew rate, and the inverted first ramp signal VR1B rises monotonically from the peak value VR1H to the bottom value VR1L at a downward slew rate equal to the upward slew rate (with the opposite polarity) (see time t11~t12 in Figure 25).

[0159] On the other hand, when the second clock signal CLK2 is at a high level, both switches 72c and 72d turn on, causing capacitors 73b and 73c to discharge without delay (i.e., short-circuiting their respective ends). As a result, the first ramp signal VR1 is reset to its bottom value VR1L, and the inverted first ramp signal VR1B is reset to its peak value VR1H (see time t12~t13 in Figure 25).

[0160] Comparator 74b generates a comparison signal S74b by comparing the first ramp signal VR1 with the second voltage VR1H (corresponding to the peak value VR1H). The comparison signal S74b is low level when the first ramp signal VR1 is lower than the peak value VR1H, and high level when the first ramp signal VR1 is higher than the peak value VR1H.

[0161] The delay unit 77 performs a delay process on the comparison signal S74b to generate the second clock signal CLK2. More specifically, when the comparison signal S74b rises to the high level, the delay unit 77 immediately raises the second clock signal CLK2 to the high level (refer to time t12 in FIG. 25). On the other hand, when the comparison signal S74b falls to the low level, the delay unit 77 waits for a predetermined delay time to pass before lowering the second clock signal CLK2 to the low level (refer to times t12 to t13 in FIG. 25). With such a configuration, it becomes possible to reliably discharge the capacitors 73b and 73c.

[0162] In this way, the comparator 74b and the delay unit 77 function as a clock signal generation unit that compares the first lamp signal VR1 with the second voltage VR3H (corresponding to the peak value VR1H) to generate the second clock signal CLK2.

[0163] The timing control unit 120 receives the input of the second clock signal CLK2 described above, and generates a timing control signal ST so that the sampling of the coil current IL is performed at the timing when the logic level of the second clock signal CLK2 switches (= the reset timing of the first lamp signal VR1 and the inverted first lamp signal VR1B). Hereinafter, a specific operation example of the timing control unit 120 will be described in detail.

[0164] FIG. 26 is a waveform diagram showing an operation example of the timing control unit 120 in the seventh embodiment. From top to bottom, the first analog signal VC1 (dashed line), the first lamp signal VR1 (solid line), and the inverted first lamp signal VR1B (dotted line), the coil current IL, and the timing control signal ST are depicted.

[0165] As also shown in the previous FIG. 25, the first lamp signal VR1 and the inverted first lamp signal VR1B have opposite polarities to each other and repeat rising, falling, and resetting at a common switching period T between the peak value VR1H and the bottom value VR1L. On the other hand, the first analog signal VC1 varies within a voltage range of VR1L < VC1 < (VR1H + VR1L) / 2.

[0166] When the first analog signal VC1 is higher than at least one of the first ramp signal VR1 and the inverted first ramp signal VR1B, the switch output stage 10 enters an ON period ton, and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than both the first ramp signal VR1 and the inverted first ramp signal VR1B, the switch output stage 10 enters an OFF period tooff, and the coil current IL decreases.

[0167] In other words, the higher the first analog signal VC1, the larger the on-duty cycle Don (=ton / T) of the switch output stage 10 becomes, and conversely, the lower the first analog signal VC1, the smaller the on-duty cycle Don of the switch output stage 10 becomes.

[0168] Here, the timing control unit 120 generates a one-shot pulse for the timing control signal ST at the reset timing of the first ramp signal VR1 and the inverted first ramp signal VR1B (which corresponds to the timing when the second clock signal CLK2 rises to a high level).

[0169] As shown in this figure, the reset timing of the first ramp signal VR1 and the inverted first ramp signal VR1B coincides with the center timing of the ON period ton (= the timing when ton / 2 has elapsed since the coil current IL began to increase).

[0170] Therefore, the current detection unit 50 can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL during the ON period ton by sampling the coil current IL using a one-shot pulse of the timing control signal ST as a trigger.

[0171] <Eighth Embodiment> FIG. 27 is a diagram showing an eighth embodiment of the DC / DC converter. The DC / DC converter 1 of the present embodiment is characterized in that an AND gate 180 is used instead of the OR gate 170 while based on the seventh embodiment (FIG. 23). Therefore, for the components similar to those in the seventh embodiment, the same reference numerals as in FIG. 23 are assigned, and redundant explanations are omitted. Hereinafter, the characteristic parts of the eighth embodiment will be mainly described.

[0172] In the DC / DC converter 1 of the present embodiment, the AND gate 180 generates a logical product signal SY (corresponding to the control signal of the switch output stage 10) of the first comparison signal CMP1 and the second comparison signal CMP2 and outputs it to the driver 90. The logical product signal SY becomes high level when both the first comparison signal CMP1 and the second comparison signal CMP2 are high level, and becomes low level when at least one of the first comparison signal CMP1 and the second comparison signal CMP2 is low level.

[0173] FIG. 28 is a waveform diagram showing an operation example of the timing control unit 120 in the eighth embodiment. Similar to FIG. 26 above, in order from the top, the first analog signal VC1 (dashed line), the first lamp signal VR1 (solid line), and the inverted first lamp signal VR1B (dotted line), the coil current IL, and the timing control signal ST are depicted.

[0174] Also in the operation example of this figure, the first lamp signal VR1 and the inverted first lamp signal VR1B repeat rising, falling, and resetting at a common switching period T while having opposite polarities to each other between the peak value VR1H and the bottom value VR1L. On the other hand, the first analog signal VC1 varies within a voltage range of (VR1H + VR1L) / 2 < VC1 < VR1H.

[0175] When the first analog signal VC1 is higher than both the first ramp signal VR1 and the inverted first ramp signal VR1B, the switch output stage 10 enters an ON period ton, and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than at least one of the first ramp signal VR1 and the inverted first ramp signal VR1B, the switch output stage 10 enters an OFF period tooff, and the coil current IL decreases.

[0176] In other words, the higher the first analog signal VC1, the larger the on-duty cycle Don (=ton / T) of the switch output stage 10 becomes, and conversely, the lower the first analog signal VC1, the smaller the on-duty cycle Don of the switch output stage 10 becomes.

[0177] Here, the timing control unit 120 generates a one-shot pulse for the timing control signal ST at the reset timing of the first ramp signal VR1 and the inverted first ramp signal VR1B (which corresponds to the timing when the second clock signal CLK2 rises to a high level).

[0178] As shown in this figure, the reset timing of the first ramp signal VR1 and the inverted first ramp signal VR1B coincides with the center timing of the off period toff (= the timing when toff / 2 has elapsed since the coil current IL began to decrease).

[0179] Therefore, the current detection unit 50 can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL during the off period tooff by sampling the coil current IL using a one-shot pulse of the timing control signal ST as a trigger.

[0180] <Ninth Embodiment> Figure 29 shows the ninth embodiment of the DC / DC converter. The DC / DC converter 1 of this embodiment is based on the seventh embodiment (Figure 23) and the eighth embodiment (Figure 27), but is characterized by changing the switch output stage 10 to a step-up / step-down type, reversing the input polarities of the PWM comparators 80 and 160 respectively, and using a logic unit 190 instead of the OR gate 170 and AND gate 180. Therefore, for components that are the same as those in the seventh and eighth embodiments, the same reference numerals as in Figures 23 and 27 are used to omit redundant explanations, and the following will focus on the characteristic parts of the ninth embodiment.

[0181] In the DC / DC converter 1 of this embodiment, the switch output stage 10 includes a step-down output transistor 11 and a synchronous rectifier transistor 12, as well as a step-up output transistor 15 (NMOSFET in this figure) and a synchronous rectifier transistor 16 (PMOSFET in this figure), which step down or step up the input voltage Vin to generate a desired output voltage Vout.

[0182] The source of output transistor 11 is connected to the input voltage Vi application terminal. The drain of output transistor 11 and the drain of synchronous rectifier transistor 12 are connected to the first terminal of coil 13. The source of synchronous rectifier transistor 12 is connected to ground. The drain of output transistor 15 and the drain of synchronous rectifier transistor 16 are connected to the second terminal of coil 13. The source of output transistor 15 is connected to ground. The source of synchronous rectifier transistor 16 is connected to the output terminal of output voltage Vo and the first terminal of capacitor 14. The second terminal of capacitor 14 is connected to ground.

[0183] Output transistor 11 turns on when the buck drive signal D1 is low level and turns off when the buck drive signal D1 is high level. Synchronous rectifier transistor 12 turns on when the buck drive signal D2 is high level and turns off when the buck drive signal D2 is low level. Output transistor 15 turns on when the boost drive signal U1 is high level and turns off when the boost drive signal U1 is low level. Synchronous rectifier transistor 16 turns on when the boost drive signal U2 is low level and turns off when the boost drive signal U2 is high level.

[0184] Furthermore, in the DC / DC converter 1 of this embodiment, the logic unit 190 includes a NAND gate 191 and an OR gate 192, and receives inputs of a first comparison signal CMP1 and a second comparison signal CMP2 to generate a step-down control signal D0 and a step-up control signal U0.

[0185] The NAND gate 191 generates a buck control signal D0 by performing a negative logical AND operation on the first comparison signal CMP1 and the second comparison signal CMP2. Therefore, the buck control signal D0 is low when both the first comparison signal CMP1 and the second comparison signal CMP2 are high, and high when at least one of the first comparison signal CMP1 and the second comparison signal CMP2 is low.

[0186] The OR gate 192 generates a boost control signal U0 by performing a logical OR operation on the first comparison signal CMP1 and the second comparison signal CMP2. Therefore, the boost control signal U0 is low when both the first comparison signal CMP1 and the second comparison signal CMP2 are low, and high when at least one of the first comparison signal CMP1 and the second comparison signal CMP2 is high.

[0187] In other words, the logic unit 190 receives the inputs of the first comparison signal CMP1 and the second comparison signal CMP2, and extracts two states: one in which the first analog signal VC1 is lower than either the first ramp signal VR1 or the inverted first ramp signal VR1B (CMP1=CMP2=H), and the other in which the first analog signal VC1 is higher than either the first ramp signal VR1 or the inverted first ramp signal VR1B (CMP1=CMP2=L). Based on one of these extraction results, it generates a step-down control signal D0, and based on the other extraction result, it generates a step-up control signal U0.

[0188] Furthermore, in the DC / DC converter 1 of this embodiment, the driver 90 receives inputs of a step-down control signal D0 and a step-up control signal U0, generates step-down drive signals D1 and D2, and step-up drive signals U1 and U2, and uses these to drive the switch output stage 10.

[0189] Figure 30 is a timing chart showing the generation operation of the buck drive signals D1 and D2, illustrating the buck control signal D0 and the buck drive signals D1 and D2.

[0190] The buck drive signal D1 becomes low level with a delay time d from the rising edge of the buck control signal D0, and becomes high level simultaneously with the falling edge of the buck control signal D0. In contrast, the buck drive signal D2 becomes low level simultaneously with the rising edge of the buck control signal D0, and becomes high level with a delay time d from the falling edge of the buck control signal D0.

[0191] Thus, the buck drive signals D1 and D2 are essentially the logic inversion signals of the buck control signal D0. Therefore, the output transistor 11 and the synchronous rectifier transistor 12 are switched on / off complementaryly. However, the buck drive signals D1 and D2 have a period (so-called dead time) during which both the output transistor 11 and the synchronous rectifier transistor 12 are switched off for a delay time d. Therefore, it is possible to prevent the generation of shoot-through current caused by the simultaneous on-up of the output transistor element 11 and the synchronous rectifier transistor 12.

[0192] Figure 31 is a timing chart showing the generation operation of boost drive signals U1 and U2, illustrating the boost control signal U0 and the boost drive signals U1 and U2.

[0193] The boost drive signal U1 goes low simultaneously with the rising edge of the boost control signal U0, and becomes high after a delay of time d from the falling edge of the boost control signal U0. In contrast, the boost drive signal U2 goes low after a delay of time d from the rising edge of the boost control signal U0, and becomes high simultaneously with the falling edge of the boost control signal U0.

[0194] Thus, the boost drive signals U1 and U2 are essentially the logic inversion signals of the boost control signal U0. Therefore, the output transistor 15 and the synchronous rectifier transistor 16 are switched on / off complementaryly. However, the boost drive signals U1 and U2 have a period (so-called dead time) during which both the output transistor 15 and the synchronous rectifier transistor 16 are switched off over a delay time d. Therefore, it is possible to prevent the generation of shoot-through current caused by the simultaneous on-up of the output transistor 15 and the synchronous rectifier transistor 16.

[0195] Figure 32 is a waveform diagram showing a first operation example (down-down) of the timing control unit 120 in the ninth embodiment. From top to bottom, it shows the first analog signal VC1 (dotted line), the first ramp signal VR1 (solid line), the inverted first ramp signal VR1B (dashed line), the first comparison signal CMP1 and the second comparison signal CMP2, the down-down control signal D0 and the boost control signal U0, the coil current IL, and the timing control signal ST.

[0196] As shown in Figure 25 above, the first ramp signal VR1 and the inverted first ramp signal VR1B repeatedly rise or fall and reset with a common switching period T, while having opposite polarities to each other between the peak value VR1H and the bottom value VR1L.

[0197] Here, when VR1L < VC1 < (VR1H + VR1L) / 2, the boost control signal U0 is always at a high level, so the output transistor 15 is always off and the synchronous rectifier transistor 16 is always on. On the other hand, the buck control signal D0 is in a state of being pulse-driven with an on-duty ratio Don (= the ratio of the on-period ton to the switching period T) corresponding to the first analog signal VC1, so the output transistor 11 and the synchronous rectifier transistor 12 are complementarily turned on / off.

[0198] When the output transistor 11 is on and the synchronous rectifier transistor 12 is off, energy is stored in the coil 13. On the other hand, when the output transistor 11 is off and the synchronous rectifier transistor 12 is on, the energy stored in the coil 13 is released. By repeating such energy storage and release, an output voltage Vo obtained by stepping down the input voltage Vi is generated.

[0199] When the first analog signal VC1 is higher than at least one of the first ramp signal VR1 and the inverted first ramp signal VR1B, the switch output stage 10 is in the on-period ton and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than both the first ramp signal VR1 and the inverted first ramp signal VR1B, the switch output stage 10 is in the off-period toff and the coil current IL decreases.

[0200] That is, during the buck operation of this figure, the higher the first analog signal VC1, the larger the on-duty ratio Don (= ton / T) of the switch output stage 10, and conversely, the lower the first analog signal VC1, the smaller the on-duty ratio Don of the switch output stage 10.

[0201] Here, the timing control unit 120 generates a one-shot pulse in the timing control signal ST at the reset timing of the first ramp signal VR1 and the inverted first ramp signal VR1B (corresponding to the timing when the second clock signal CLK2 rises to a high level).

[0202] Note that, as shown in this figure, the reset timing of the first lamp signal VR1 and the inverted first lamp signal VR1B coincides with the center timing of the on period ton (= the timing when ton / 2 has elapsed since the coil current IL started to increase).

[0203] Therefore, the current detection unit 50 can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL in the on period ton by sampling the coil current IL triggered by the one-shot pulse of the timing control signal ST. Thus, the sampling timing during the step-down operation is the same as that in FIG. 26 described above.

[0204] FIG. 33 is a waveform diagram showing a second operation example (during boost) of the timing control unit 120 in the ninth embodiment, and in order from the top, the first analog signal VC1 (dashed-dotted line), the first lamp signal VR1 (solid line), and the inverted first lamp signal VR1B (dashed line), the first comparison signal CMP1 and the second comparison signal CMP2, the step-down control signal D0 and the boost control signal U0, the coil current IL, and the timing control signal ST are depicted.

[0205] Also in the operation example of this figure, the first lamp signal VR1 and the inverted first lamp signal VR1B repeat rising, falling, and resetting at a common switching period T while having opposite polarities to each other between the peak value VR1H and the bottom value VR1L.

[0206] Here, when (VR1H + VR1L) / 2 < VC1 < VR1H, the step-down control signal D0 is always at a high level, so the output transistor 11 is always on and the synchronous rectifier transistor 12 is always off. On the other hand, the boost control signal U0 is in a state of being pulse-driven with an on duty ratio Don (= the ratio of the on period ton in the switching period T) corresponding to the first analog signal VC1, so the output transistor 15 and the synchronous rectifier transistor 16 are complementarily turned on / off.

[0207] When the output transistor 15 is on and the synchronous rectifier transistor 16 is off, energy is stored in the coil 13. On the other hand, when the output transistor 15 is off and the synchronous rectifier transistor 16 is on, the energy stored in the coil 13 is released. By repeatedly storing and releasing energy in this way, an output voltage Vo is generated by boosting the input voltage Vi.

[0208] When the first analog signal VC1 is higher than both the first ramp signal VR1 and the inverted first ramp signal VR1B, the switch output stage 10 enters an ON period ton, and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than at least one of the first ramp signal VR1 and the inverted first ramp signal VR1B, the switch output stage 10 enters an OFF period tooff, and the coil current IL decreases.

[0209] In other words, during the boost operation shown in this diagram, the higher the first analog signal VC1, the larger the on-duty cycle Don (=ton / T) of the switch output stage 10 becomes, and conversely, the lower the first analog signal VC1, the smaller the on-duty cycle Don of the switch output stage 10 becomes.

[0210] Here, the timing control unit 120 generates a one-shot pulse for the timing control signal ST at the reset timing of the first ramp signal VR1 and the inverted first ramp signal VR1B (which corresponds to the timing when the second clock signal CLK2 rises to a high level).

[0211] As shown in this figure, the reset timing of the first ramp signal VR1 and the inverted first ramp signal VR1B coincides with the center timing of the off period toff (= the timing when toff / 2 has elapsed since the coil current IL began to decrease).

[0212] Therefore, the current detection unit 50 can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL during the off period tooff by sampling the coil current IL using a one-shot pulse of the timing control signal ST as a trigger. Thus, the sampling timing during the boost operation is the same as in Figure 28 above.

[0213] <Tenth Embodiment> The DC / DC converter 1 of this embodiment has basically the same configuration as the first embodiment (Figure 1), and is characterized by the circuit configuration of the timing control unit 120. Therefore, the overall configuration of the DC / DC converter 1 will not be explained, and the following will focus on the characteristic parts of the tenth embodiment.

[0214] First, before explaining the configuration and operation of the timing control unit 120, we will provide a supplementary explanation of the configuration and operation of the oscillator 70 with reference to Figure 34.

[0215] Figure 34 is a circuit diagram showing one example configuration of the oscillator 70 in the tenth embodiment. In this example configuration of the oscillator 70, the components related to the generation of the inverted first ramp signal VR1B (current source 71d, switch 72d, and capacitor 73c) are omitted, while the seventh embodiment (Figure 24) is based on the oscillator 70.

[0216] Furthermore, in this example configuration, for the sake of easier understanding, it is assumed that oscillator 70 generates a first ramp signal VR1 with a reference voltage Vref as its peak value and a ground voltage GND as its bottom value. More specifically, the reference voltage Vref is input to the inverting input terminal (-) of comparator 74b, and the ground voltage GND is applied to the second terminal of capacitor 73b.

[0217] Furthermore, in this example of a configuration, the oscillator 70 specifically describes the circuit elements forming the current source 71c as P-channel MOS field-effect transistors P1 and P2, N-channel MOS field-effect transistor N1, operational amplifier AMP1, and resistor R1.

[0218] The sources of transistors P1 and P2 are both connected to the terminal to which the power supply voltage VDD is applied. The gates of transistors P1 and P2 are both connected to the drain of transistor P1. The drain of transistor P1 is connected to the drain of transistor N1. The drain of transistor P2 is connected to the first terminal of capacitor 73b as the output terminal of the charging current I71c.

[0219] The non-inverting input terminal (+) of op-amp AMP1 is connected to the application terminal of constant voltage V1. The inverting input terminal (-) of op-amp AMP1 is connected to the source of transistor N1 and the first terminal of resistor R1. The output terminal of op-amp AMP1 is connected to the gate of transistor N1. The second terminal of resistor R1 is connected to ground.

[0220] In the current source 71c configured as described above, the operational amplifier AMP1 controls the gate of transistor N1 so that the non-inverting input terminal (+) and the inverting input terminal (-) are imaginarily short-circuited. Consequently, a constant voltage V1 is applied to the first terminal of resistor R1, and a predetermined drain current (V1 / R1) flows through transistor N1.

[0221] Transistors P1 and P2 form a Karen mirror, and by mirroring the drain current (V1 / R1) with a mirror ratio α, they generate the charging current I71c (=α × (V1 / R1)) of capacitor 73b.

[0222] Furthermore, when the charging current I71c is defined as I0 and the capacitance of capacitor 73b as C0, in order to generate the first ramp signal VR1 and the second clock signal CLK2 at the desired switching period T, the Miller ratio α, the voltage value of the constant voltage V1, and the resistance value of the resistor R1 should be appropriately set so that I0 = Vref × C0 × (1 / T).

[0223] Figure 35 is a circuit diagram showing one example configuration of the timing control unit 120 in the tenth embodiment. The timing control unit 120 in this example configuration includes a first internal signal generation unit 121, a second internal signal generation unit 122, and a comparator 123.

[0224] The first internal signal generation unit 121 is a circuit unit that generates a first internal signal V11 by charging and discharging a capacitor C1 in synchronization with an ON signal ON, and includes a capacitor C1, current sources CS1 to CS3, switches SW1 and SW2, a pnp type bipolar transistor Qp, an npn type bipolar transistor Qn, and resistors R11 and R12.

[0225] The first terminals of current sources CS1 to CS3 are all connected to the power supply terminal. The second terminal of current source CS1 is connected to the base of transistor Qp and the first terminal of switch SW1. The second terminal of switch SW1 is connected to the first terminal of capacitor C1 and the first terminal of switch SW2. The second terminal of current source CS2 is connected to the base of transistor Qn and the emitter of transistor Qp. The second terminal of current source CS3 is connected to the non-inverting input terminal (+) of comparator 123, the collector of transistor Qn, and the first terminal of resistor R12. The emitter of transistor Qn is connected to the first terminal of resistor R11. The second terminals of capacitor C1, the second terminal of switch SW2, the collector of transistor Qp, and the second terminals of resistors R11 and R12 are all connected to ground. The control terminal of switch SW1 is connected to the application terminal of the ON signal. The control terminal of switch SW2 is connected to the application terminal of the reset signal RST.

[0226] Switch SW1 turns on when the switch output stage 10 is in the ON period ton (e.g., ON=H) and turns off when the switch output stage 10 is in the OFF period tooff (e.g., ON=L). The ON signal ON is a logic signal synchronized with the ON / OFF control of the switch output stage 10, and for example, the first comparison signal CMP1 can be used.

[0227] Switch SW2 turns on, for example, when the reset signal RST is high, and turns off when the reset signal RST is low. The reset signal RST is a signal to discharge capacitor C1 prior to the ON period ton, and for example, the aforementioned second clock signal CLK2 (see Figure 34) can be reused.

[0228] The second internal signal generation unit 122 is a circuit unit that generates a second internal signal V12 by charging and discharging a capacitor C2 in synchronization with the OFF signal, and includes a capacitor C2, a current source CS4, and a switch SW3.

[0229] The first terminal of the current source CS4 is connected to the power supply terminal. The second terminal of the current source CS4 is connected to the inverting input terminal (-) of the comparator 123, the first terminal of the capacitor C2, and the first terminal of the switch SW3. The second terminal of the capacitor C2 and the second terminal of the switch SW3 are connected to the ground terminal. The control terminal of the switch SW3 is connected to the terminal to which the OFF signal is applied.

[0230] Switch SW3 turns on when the switch output stage 10 is in the ON period ton (e.g., OFF=H) and turns off when the switch output stage 10 is in the OFF period toff (e.g., OFF=L). The OFF signal OFF is a logic signal synchronized with the ON / OFF control of the switch output stage 10, and for example, the first comparison signal CMP1 can be used.

[0231] Comparator 123 generates a timing control signal ST by comparing a first internal signal V11 input to the non-inverting input terminal (+) with a second internal signal V12 input to the inverting input terminal (-). The timing control signal ST becomes high level when the first internal signal V11 is higher than the second internal signal V12, and conversely, becomes low level when the first internal signal V11 is lower than the second internal signal V12.

[0232] Thus, unlike the previous fourth to ninth embodiments (Figures 8 to 33), the timing control unit 120 in this embodiment generates a timing control signal ST using a first internal signal V11 and a second internal signal V12 that it generates itself in synchronization with the on / off control of the switch output stage 10, so that the coil current IL is sampled at the center timing of the off period toff of the switch output stage 10. Below, a specific example of the operation of the timing control unit 120 will be described in detail with reference to this figure and Figure 36.

[0233] Figure 36 is a waveform diagram showing an example of operation of the timing control unit 120 in the 10th embodiment. From top to bottom, the first ramp signal VR1 (solid line) and the first analog signal VC1 (dotted line) are shown, the first comparison signal CMP1 (= ON signal and OFF signal) is shown, the coil current IL is shown, the reset signal RST is shown, the charging voltage V10 of the capacitor C1 is shown, the first internal signal V11 (solid line) and the second internal signal V12 (dashed line) are shown, and the timing control signal ST is shown.

[0234] First, let's review the overall operation of DC / DC converter 1 by referring to the top three sections of this diagram (VR1 / VC1, CMP1, and IL).

[0235] When the first analog signal VC1 is higher than the first ramp signal VR1, the switch output stage 10 enters an on period ton (=time t21~t22), and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than the first ramp signal VR1, the switch output stage 10 enters an off period tooff (=time t22~t24), and the coil current IL decreases. In other words, the higher the first analog signal VC1, the larger the on duty cycle Don (=ton / T) of the switch output stage 10, and conversely, the lower the first analog signal VC1, the smaller the on duty cycle Don of the switch output stage 10.

[0236] Thus, the overall operation of the DC / DC converter 1 is no different from that of the first embodiment (Figure 1).

[0237] Next, the operation of the timing control unit 120 will be described in detail, referring to the lower four rows of this figure (RST, V10, V11 / V12, and ST).

[0238] First, focusing on the first internal signal generation unit 121, at time t21, a one-shot pulse is generated for the reset signal RST prior to the ON period ton of the switch output stage 10. As a result, the switch SW2 turns on and the capacitor C1 is discharged, so the charging voltage V10 is reset to zero (=GND).

[0239] Subsequently, during the ON period ton (=time t21~t22) of the switch output stage 10, switch SW1 is turned ON, and conduction occurs between the current source CS1 and capacitor C1. As a result, capacitor C1 is charged using the charging current I1 supplied from the current source CS1, and the charging voltage V10 rises with a predetermined slope (=I1 / C1) as time t progresses. Therefore, if I1 = Vref × C1 × (1 / T) is set, the charging voltage V10[t] after time t has elapsed from time t21 can be expressed as V10[t] = Vref × (t / T). That is, at time t21 (t=0), V10 = GND, and at time t22 (t=ton), V10 = Vref × (ton / T).

[0240] The charging voltage V10 is applied to the first terminal of resistor R11 via transistors Qp and Qn, which receive the drive current I2 from the current source CS2. Therefore, a lower current I11 (=V10 / R11) corresponding to the charging voltage V10 flows through resistor R11. In this way, the current source CS2, transistors Qp and Qn, and resistor R11 function as a voltage / current conversion unit that converts the charging voltage V10 of capacitor C1 into a lower current I11.

[0241] Furthermore, the difference current I12 (=I3-I11), which is obtained by subtracting the aforementioned lower current I11 from the upper current I3 generated by the current source CS3, flows through resistor R12. Therefore, the first internal signal V11 drawn from the first end of resistor R12 can be expressed as V11 = I12 × R12. In this way, resistor R12 functions as a current / voltage converter that converts the difference current I12 between the upper current I3 and the lower current I11 into the first internal signal V11.

[0242] Here, if we set I3 = Vref / R11 and R11 = 2 × R12, then the first internal signal V11[t] after time t has elapsed from time t21 can be expressed as V11[t] = (1 / 2) × Vref × {1 - (t / T)}. In other words, at time t21 (t=0), V11 = (1 / 2) × Vref, and at time t22 (t=ton), V11 = (1 / 2) × Vref × (toff / T).

[0243] On the other hand, during the off period toff (=time t22~t24) of the switch output stage 10, switch SW1 is turned off. Consequently, the rise in the charging voltage V10 stops, and the first internal signal V11 is maintained at the voltage value just before turning off (=(1 / 2)×Vref×(toff / T)).

[0244] Thus, during the ON period ton of the switch output stage 10, the first internal signal V11 changes from half of the reference voltage Vref (= (1 / 2) × Vref) to a value obtained by multiplying this by the off-duty cycle of the switch output stage 10 (= tooff / T, i.e., the ratio of the off-period tooff to the switching period T) (= (1 / 2) × Vref × (toff / T)), and then is held at that value during the OFF period tooff of the switch output stage 10.

[0245] Next, focusing on the second internal signal generation unit 122, during the ON period ton (=time t21~t22) of the switch output stage 10, the switch SW3 is turned on and the terminals of the capacitor C2 are shorted, so the second internal signal V12 is maintained at zero value (=GND). Therefore, during the ON period ton of the switch output stage 10, the first internal signal V11 is always higher than the second internal signal V12, so the timing control signal ST is maintained at a low level.

[0246] On the other hand, during the off period toff (=time t22~t24) of the switch output stage 10, switch SW3 is turned off. As a result, capacitor C2 is charged using the charging current I4 supplied from the current source CS4, so the second internal signal V12 rises with a predetermined slope (=I4 / C2) as time t progresses. Therefore, if I4 = Vref × C2 × (1 / T) is set, the second internal signal V12[t] after time t has elapsed from time t22 can be expressed as V12[t] = Vref × (t / T). That is, at time t22 (t=0), V12 = GND, and at time t24 (t=toff), V12 = Vref × (toff / T).

[0247] Thus, the second internal signal V12 is held at zero value (=GND) during the ON period ton of the switch output stage 10, and then changes from that zero value to a value obtained by multiplying the reference voltage Vref by the off duty cycle (=toff / T) (=Vref × (toff / T)) during the OFF period toff of the switch output stage 10.

[0248] Here, the timing at which the first internal signal V11 and the second internal signal V12 intersect (=time t23) coincides with the center timing of the off period toff (=the timing when toff / 2 has elapsed since the coil current IL began to decrease). In other words, the timing control signal ST rises from a low level to a high level at time t23.

[0249] Therefore, the current detection unit 50 can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL during the off period tooff by sampling the coil current IL using the rising edge of the timing control signal ST as a trigger.

[0250] <Summary> The following section provides a summary of the various embodiments described so far.

[0251] The DC / DC converter disclosed herein includes a current detection unit that generates a current sense signal by sampling the coil current of a switch output stage at a timing corresponding to a timing control signal, and a timing control unit that generates the timing control signal using a first internal signal and a second internal signal generated by itself in synchronization with the on / off control of the switch output stage, so that the coil current is sampled at the center timing of the off period of the switch output stage, and a desired output voltage is generated from the input voltage by performing output feedback control in a current mode control method using the current sense signal (first configuration).

[0252] Furthermore, in the DC / DC converter having the first configuration described above, the timing control unit may be configured to include a first internal signal generation unit that generates the first internal signal in synchronization with the ON period, a second internal signal generation unit that generates the second internal signal in synchronization with the OFF period, and a comparator that generates the timing control signal by comparing the first internal signal and the second internal signal (second configuration).

[0253] Furthermore, in a DC / DC converter consisting of the second configuration described above, the first internal signal may change during the ON period from half the reference voltage to a value obtained by multiplying this by the off-duty cycle of the switch output stage, and then be held at that value during the OFF period, while the second internal signal may be held at zero during the ON period, and then change during the OFF period from zero to a value obtained by multiplying the reference voltage by the off-duty cycle (third configuration).

[0254] Furthermore, in a DC / DC converter having the third configuration described above, the first internal signal generation unit may be configured to include a first capacitor, a first current source for generating a charging current for the first capacitor, a first switch for charging the first capacitor during the ON period, a second switch for discharging the first capacitor prior to the ON period, a second current source for generating a predetermined upper current, a voltage / current conversion unit for converting the charging voltage of the first capacitor into a lower current, and a current / voltage conversion unit for converting the difference current between the upper current and the lower current into the first internal signal (fourth configuration).

[0255] Furthermore, in a DC / DC converter comprising the third or fourth configuration described above, the second internal signal generation unit may be configured to include a second capacitor, a current source that generates a charging current for the second capacitor, and a switch that charges the second capacitor during the off period (fifth configuration).

[0256] Furthermore, a DC / DC converter consisting of any of the first to fifth configurations described above may have a configuration (sixth configuration) comprising: an error amplifier that generates an error signal corresponding to the difference between the output voltage or a corresponding feedback voltage and a predetermined reference voltage; an oscillator that generates a ramp signal at a predetermined switching period; a differential amplifier that generates an analog signal corresponding to the difference between the error signal and the current sense signal; a comparator that compares the analog signal and the ramp signal to generate a comparison signal; and a driver that generates a drive signal for the switch output stage according to the comparison signal.

[0257] Furthermore, the DC / DC converter consisting of the sixth configuration described above may be configured to further include a clamper that limits the error signal to a predetermined upper limit or a predetermined lower limit (seventh configuration).

[0258] Furthermore, the DC / DC converter consisting of the sixth or seventh configuration described above may be configured to further include a light load detection comparator that compares the error signal with a predetermined threshold to control whether or not the switch output stage can operate (eighth configuration).

[0259] Furthermore, the DC / DC converter disclosed herein includes a comparator that compares a first analog signal and a ramp signal to generate a control signal for a switch output stage, a current detection unit that generates a current sense signal by sampling the coil current of the switch output stage at a timing corresponding to the timing control signal, an average value generation unit that generates a second analog signal having a simple average value of the signal value of the first analog signal and the start or end value of the ramp signal, and a timing control unit that uses the ramp signal and the second analog signal to generate the timing control signal so that the coil current is sampled at the center timing of the on or off period of the switch output stage, and is configured to generate a desired output voltage from the input voltage by performing output feedback control in a current mode control method using the current sense signal (9th configuration).

[0260] Furthermore, the DC / DC converter disclosed herein includes a comparator that compares a first analog signal and a first ramp signal to generate a control signal for a switch output stage, a current detection unit that generates a current sense signal by sampling the coil current of the switch output stage at a timing corresponding to the timing control signal, an average value generation unit that generates a second analog signal having a weighted average value of the signal value of the first analog signal and the start or end value of the first ramp signal, and a timing control unit that generates the timing control signal so that the coil current is sampled at the center timing of the on or off period of the switch output stage using a second ramp signal having a different slew rate than the first ramp signal and the second analog signal, and is configured to generate a desired output voltage from the input voltage by performing output feedback control in a current mode control method using the current sense signal.

[0261] Also, in the DC / DC converter having the tenth configuration described above, the second analog signal has a weighted average value of the signal value (weight m) of the first analog signal and the starting point value (weight n) of the first ramp signal (where m + n = 1, 0 < m < 1, 0 < n < 1, m ≠ n), and the second ramp signal may have a slew rate that is 2m / (m + n) times that of the first ramp signal (eleventh configuration).

[0262] Also, in the DC / DC converter having any of the ninth to eleventh configurations described above, both the first ramp signal and the second ramp signal may have a sawtooth waveform that repeats rising or falling and resetting in a common switching period (twelfth configuration).

[0263] Also, the DC / DC converter having any of the ninth to twelfth configurations described above may further have an error amplifier that generates an error signal according to the difference between the output voltage or a feedback voltage corresponding thereto and a predetermined reference voltage, and a differential amplifier that generates the first analog signal according to the difference between the error signal and the current sense signal (thirteenth configuration).

[0264] Also, the DC / DC converter having the thirteenth configuration described above may further have a clamper that limits the error signal to be below a predetermined upper limit value or above a predetermined lower limit value (fourteenth configuration).

[0265] Also, the DC / DC converter having the thirteenth or fourteenth configuration described above may further have a light load detection comparator that compares the error signal with a predetermined threshold value to control the operability of the switch output stage (fifteenth configuration).

[0266] Also, the DC / DC converter disclosed in this specification includes an oscillator that generates a triangular-wave lamp signal with equal up / down slew rates, a comparator that compares an analog signal with the lamp signal to generate a control signal for a switch output stage, a current detection unit that generates a current sense signal by sampling the coil current of the switch output stage at a timing corresponding to a timing control signal, and a timing control unit that generates the timing control signal so that the sampling of the coil current is performed at a timing when the lamp signal reaches a peak value or a bottom value. By performing output feedback control in a current mode control method using the current sense signal, a configuration (16th configuration) is adopted to generate a desired output voltage from an input voltage.

[0267] In the DC / DC converter having the above 16th configuration, it is preferable that the oscillator includes a capacitor connected between an output terminal and a constant potential terminal of the lamp signal, a first current source that generates a predetermined charging current, a second current source that generates a discharge current equal to the charging current, a switch that switches whether to charge the capacitor with the charging current or discharge the capacitor with the discharge current according to a clock signal, and a clock signal generation unit that compares the lamp signal with the peak value and the bottom value to generate the clock signal, forming a configuration (17th configuration).

[0268] Also, in the DC / DC converter having the above 17th configuration, it is preferable that the timing control unit generates the timing control signal using the clock signal, forming a configuration (18th configuration).

[0269] Furthermore, the DC / DC converter disclosed herein includes an oscillator that generates sawtooth waveform ramp signals and inverting ramp signals that rise or fall and reset repeatedly with a common switching period while having opposite polarities to each other; a first comparator and a second comparator that compare an analog signal with the ramp signal and the inverting ramp signal, respectively, to generate a first comparison signal and a second comparison signal; a logic operation unit that generates a control signal for a switch output stage by performing a logic operation using the first comparison signal and the second comparison signal; a current detection unit that generates a current sense signal by sampling the coil current of the switch output stage at a timing corresponding to the timing control signal; and a timing control unit that generates the timing control signal so that the coil current is sampled at the reset timing of the ramp signal and the inverting ramp signal. The DC / DC converter is configured to generate a desired output voltage from an input voltage by performing output feedback control in a current mode control method using the current sense signal (configuration 19).

[0270] In the DC / DC converter comprising the configuration of the 19th configuration described above, the oscillator may be configured to include a first capacitor connected between the output terminal of the ramp signal and the application terminal of the first voltage, a second capacitor connected between the application terminal of a second voltage different from the first voltage and the output terminal of the inverting ramp signal, a first current source and a second current source that generate charging currents for the first capacitor and the second capacitor respectively, a first switch and a second switch that discharge the first capacitor and the second capacitor respectively according to a clock signal, and a clock signal generation unit that generates the clock signal by comparing the ramp signal and the second voltage (configuration of the 20th configuration).

[0271] Furthermore, in the DC / DC converter consisting of the 20 configuration described above, the timing control unit may be configured to generate the timing control signal using the clock signal (21st configuration).

[0272] Furthermore, in a DC / DC converter consisting of any of the above configurations 19 to 21, the switch output stage is configured such that it is ON when the analog signal is higher than at least one of the ramp signal and the inverting ramp signal, and OFF when the analog signal is lower than both the ramp signal and the inverting ramp signal (configuration 22).

[0273] Furthermore, in a DC / DC converter consisting of any of the above configurations 19 to 21, the switch output stage may be configured such that it is ON when the analog signal is higher than both the ramp signal and the inverting ramp signal, and OFF when the analog signal is lower than at least one of the ramp signal and the inverting ramp signal (configuration 23).

[0274] Furthermore, a DC / DC converter consisting of any of the above configurations 16 to 23 may further include an error amplifier that generates an error signal corresponding to the difference between the output voltage or a corresponding feedback voltage and a predetermined reference voltage, and a differential amplifier that generates the analog signal according to the difference between the error signal and the current sense signal (configuration 24).

[0275] Furthermore, the DC / DC converter consisting of the 24th configuration described above may be configured to further include a clamper that limits the error signal to a predetermined upper limit or a predetermined lower limit (25th configuration).

[0276] Furthermore, the DC / DC converter consisting of the 24th or 25th configuration described above may further include a light load detection comparator that controls whether or not the switch output stage can operate by comparing the error signal with a predetermined threshold (the 26th configuration).

[0277] Furthermore, the DC / DC converter disclosed herein is configured to generate a desired output voltage from an input voltage (configuration 27) by sampling the coil current of the switch output stage at the center timing of the on or off period of the switch output stage, and performing output feedback control in a current mode control method using a current sense signal corresponding to the sampled value.

[0278] Furthermore, the DC / DC converter consisting of the configuration of the 27th shown above may be configured to perform output feedback control using a current mode control method (configuration of the 28th shown) by inputting the current sense signal or a signal obtained by applying predetermined calculations thereto and a signal containing the error information of the output voltage to an amplifier or comparator.

[0279] Furthermore, the DC / DC converter consisting of the 27th configuration described above may also be configured to perform output feedback control using a current mode control method (29th configuration) by adding or subtracting a signal containing error information between the current sense signal and the output voltage and inputting the result to an amplifier or comparator.

[0280] Furthermore, the DC / DC converter consisting of the 27th configuration described above may also be configured to monitor the current sense signal and control whether or not the switch output stage operates according to the result of comparing it with a predetermined threshold (30th configuration).

[0281] Furthermore, the DC / DC converter consisting of the 28th or 29th configuration described above may be configured to perform overcurrent protection or reverse current protection of the coil current by clamping a signal that is added to or subtracted from the current sense signal, or a signal that is differentiated or compared with the current sense signal by the amplifier or the comparator (the 31st configuration).

[0282] Furthermore, the DC / DC converter consisting of the configuration of the 28th or 29th described above may be configured to monitor a signal that is added to or subtracted from the current sense signal, or a signal that is differentiated from or compared with the current sense signal by the amplifier or the comparator, and to control whether or not the switch output stage operates according to the result of comparing this signal with a predetermined threshold (configuration 32).

[0283] Furthermore, a DC / DC converter consisting of any of the above configurations 27 to 32 may have a configuration (configuration 33) that includes a current detection unit that generates the current sense signal by sampling the coil current at a timing corresponding to a timing control signal, and a timing control unit that generates the timing control signal so that the coil current is sampled at the center timing of the on or off period of the switch output stage.

[0284] Furthermore, the DC / DC converter comprising the 33 configuration described above may have a configuration (34 configuration) comprising: an error amplifier that generates an error signal corresponding to the difference between the output voltage or a corresponding feedback voltage and a predetermined reference voltage; an oscillator that generates a ramp signal at a predetermined switching period; a differential amplifier that generates an analog signal corresponding to the difference between the error signal and the current sense signal; a comparator that compares the analog signal and the ramp signal to generate a comparison signal; and a driver that generates a drive signal for the switch output stage according to the comparison signal.

[0285] Furthermore, the DC / DC converter consisting of the 34th configuration described above may be configured to further include a clamper that limits the error signal to a predetermined upper limit or a predetermined lower limit (35th configuration).

[0286] Furthermore, the DC / DC converter consisting of the 34th or 35th configuration described above may further include a light load detection comparator that compares the error signal with a predetermined threshold to control whether or not the switch output stage can operate (the 36th configuration).

[0287] In addition, the DC / DC converter disclosed in this specification includes a comparator that compares an analog signal with a first ramp signal to generate a control signal for a switch output stage, a current detection unit that generates a current sense signal by sampling the coil current of the switch output stage at a timing according to a timing control signal, and a timing control unit that generates the timing control signal so that the coil current is sampled at the center timing of the on-period or off-period of the switch output stage using a second ramp signal having a slew rate twice that of the first ramp signal. By performing output feedback control in a current mode control method using the current sense signal, a configuration (the 37th configuration) is adopted to generate a desired output voltage from an input voltage.

[0288] In the DC / DC converter having the 37th configuration, it is preferable that the timing control unit has a configuration (the 38th configuration) that compares the analog signal with the second ramp signal to generate the timing control signal.

[0289] In addition, in the DC / DC converter having the 38th configuration, both the first ramp signal and the second ramp signal repeat rising and resetting in a common switching period, and the switch output stage has a configuration (the 39th configuration) in which it enters an on-period when the analog signal is higher than the first ramp signal and enters an off-period when the analog signal is lower than the first ramp signal.

[0290] In addition, in the DC / DC converter having the 38th configuration, both the first ramp signal and the second ramp signal repeat rising and resetting in a common switching period, and the switch output stage may have a configuration (the 40th configuration) in which it enters an off-period when the analog signal is higher than the first ramp signal and enters an on-period when the analog signal is lower than the first ramp signal.

[0291] Furthermore, in the DC / DC converter comprising the 38th configuration described above, the first ramp signal and the second ramp signal may both repeatedly decrease and reset with a common switching period, and the switch output stage may be configured such that it is ON when the analog signal is higher than the first ramp signal and OFF when the analog signal is lower than the first ramp signal (the 41st configuration).

[0292] Furthermore, in the DC / DC converter comprising the configuration of the 38th described above, the second ramp signal may be configured to begin changing with a delay of 1 / 2 of the switching period from the time the first ramp signal starts to change (configuration of the 42nd).

[0293] Furthermore, in a DC / DC converter consisting of any of the above configurations 38 to 42, the timing control unit may be configured to compare the second ramp signal with an equivalent analog signal having equivalent information to the analog signal (configuration 43).

[0294] Furthermore, a DC / DC converter consisting of any of the above configurations 37 to 43 may further include an error amplifier that generates an error signal corresponding to the difference between the output voltage or a corresponding feedback voltage and a predetermined reference voltage, and a differential amplifier that generates the analog signal according to the difference between the error signal and the current sense signal (configuration 44).

[0295] Furthermore, the DC / DC converter consisting of the 44th configuration described above may be configured to further include a clamper that limits the error signal to a predetermined upper limit or a predetermined lower limit (45th configuration).

[0296] Furthermore, the DC / DC converter consisting of the 44th or 45th configuration may be configured to further include a light load detection comparator that controls whether the switch output stage can operate by comparing the error signal with a predetermined threshold (46th configuration).

[0297] <Other variations> In the above embodiments, step-down or step-up / step-down DC / DC converters were used as examples for explanation. However, the configuration of the present invention is not limited to these, and can also be applied to DC / DC converters employing other output types (boost type, inverting type).

[0298] Furthermore, various technical features disclosed herein can be modified in various ways, in addition to the embodiments described above, without departing from the spirit of the technical creation. For example, mutual substitution between bipolar transistors and MOS field-effect transistors, and logic level inversion of various signals are optional. In other words, the embodiments described above should be considered illustrative and not restrictive in all respects, and the technical scope of the present invention should be understood to include all modifications that fall within the meaning and scope equivalent to the claims, rather than being limited to the embodiments described above. [Industrial applicability]

[0299] The DC / DC converters disclosed herein can be used as power sources for a variety of applications. [Explanation of symbols]

[0300] 1 DC / DC converter 10 Switch output stage 11. Output transistor (for step-down conversion) 12 Synchronous rectifier transistor (for step-down conversion) 13 coils 14 Capacitors 15 Output transistor (for boosting voltage) 16 Synchronous rectifier transistor (for boosting voltage) 20 Feedback voltage generation unit 21, 22 resistors 30 Error Amplifier 40 Phase Compensation Section 41 Resistors 42 Capacitors 50 Current detection unit 60 Differential Amplifiers 70 Oscillators 71a, 71b, 71c current source 72a, 72b, 72c, 72d switches 73a, 73b, 73c Capacitors 74a, 74b Comparators 75a, 75b, 75c resistor 76 Selector 77 Delay section 80 PWM Comparator 90 Drivers 91 NAND gate 92 AND gate 100 Crampas 110 Light load detection comparator 120 Timing Control Unit 121 1st internal signal generation section 122 Second internal signal generation section 123 Comparator 130, 140 arithmetic unit 150 Average Value Generation Unit 160 PWM comparator 170 OR Gate 180 AND Gate 190 Logical Operation Unit 191 NAND gate 192 OR Gate P1, P2 P-channel MOS field-effect transistors N1 N-channel MOS field-effect transistor AMP1 operational amplifier R1, R11, R12 Resistors Capacitors C0, C1, and C2 CS1, CS2, CS3, CS4 current sources SW1, SW2, SW3 switches Qp PNP type bipolar transistor Qn npn type bipolar transistor

Claims

1. An oscillator that generates sawtooth waveform ramp signals and inverted ramp signals that have opposite polarities to each other but repeatedly rise or fall and reset with a common switching period, and generates a clock signal at the reset timing of the ramp signals and the inverted ramp signals, A first comparator and a second comparator that compare an analog signal with the ramp signal and the inverted ramp signal, respectively, to generate a first comparison signal and a second comparison signal, A logic unit that generates a step-down control signal and a step-up control signal for a step-up type switch output stage by performing logic operations using the first comparison signal and the second comparison signal, A timing control unit receives the clock signal and generates a timing control signal such that sampling of the coil current of the switch output stage is performed at the timing when the logic level of the clock signal switches. A current detection unit generates a current sense signal corresponding to the center value of the coil current by sampling the coil current at a timing corresponding to the timing control signal, It has, The step-down control signal is used to control the on / off state of the first step-down output transistor and the first synchronous rectifier transistor included in the switch output stage. The aforementioned boost control signal is used to control the on / off state of the second boost output transistor and the second synchronous rectifier transistor included in the switch output stage. A DC / DC converter that generates a desired output voltage from an input voltage by performing output feedback control using a current mode control method with the aforementioned current sense signal.

2. The aforementioned switch output stage is During step-down operation, the second output transistor is always off, the second synchronous rectifier transistor is always on, and the first output transistor and the first synchronous rectifier transistor are switched on / off complementaryly. During boost operation, the first output transistor is always on, the first synchronous rectifier transistor is always off, and the second output transistor and the second synchronous rectifier transistor are switched on / off complementaryly. The DC / DC converter according to claim 1.

3. The DC / DC converter according to claim 1 or 2, wherein the logic unit extracts a state in which the analog signal is lower than either the ramp signal or the inverting ramp signal, and a state in which the analog signal is higher than either the ramp signal or the inverting ramp signal, generates a step-down control signal based on one of the extraction results, and generates a step-up control signal based on the other extraction result.

4. The aforementioned switch output stage is During step-down operation, the ON period occurs when the analog signal is higher than at least one of the ramp signal and the inverting ramp signal, and the OFF period occurs when the analog signal is lower than both the ramp signal and the inverting ramp signal. During boost operation, the ON period occurs when the analog signal is higher than both the ramp signal and the inverting ramp signal, and the OFF period occurs when the analog signal is lower than at least one of the ramp signal and the inverting ramp signal. A DC / DC converter according to any one of claims 1 to 3.

5. The reset timing for the lamp signal and the inverting lamp signal is: During the step-down operation, the timing coincides with the center timing of the ON period. During the boost operation, the timing coincides with the center timing of the off period. The DC / DC converter according to claim 4.

6. A DC / DC converter according to any one of claims 1 to 5, further comprising: an error amplifier that generates an error signal corresponding to the difference between the output voltage or a corresponding feedback voltage and a predetermined reference voltage; and a differential amplifier that generates the analog signal according to the difference between the error signal and the current sense signal.

7. The DC / DC converter according to claim 6, further comprising a clamper for limiting the error signal to a predetermined upper limit or a predetermined lower limit.

8. The DC / DC converter according to claim 6 or 7, further comprising a light load detection comparator that controls whether the switch output stage can operate by comparing the error signal with a predetermined threshold.

9. The DC / DC converter according to claim 1, wherein the oscillator includes a third comparator that compares the ramp signal and the inverted ramp signal to generate a third comparison signal, and generates the clock signal corresponding to the third comparison signal.

10. The DC / DC converter according to claim 9, wherein the oscillator includes a delay unit that applies a delay process to the third comparison signal to generate the clock signal.

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