Semiconductor device and power conversion device using the same

Abstract

To provide a semiconductor device which has the low conduction loss and switching loss, can improve a turn-off cutoff resistance amount and has the high reliability.SOLUTION: A semiconductor device having a switching gate and a carrier control gate to be driven independently of each other, includes a central region cell, an outer peripheral region cell surrounding the whole periphery of the central region cell and a termination region surrounding the whole periphery of the outer peripheral region cell when the semiconductor device is viewed from above. The central region cell includes a switching element having the switching gate and the carrier control gate. The outer peripheral region cell is arranged between the central region cell and the termination region. A gate of the switching element of the outer peripheral region cell is constituted by only the carrier control gate.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to the structure of a semiconductor device, and more particularly to a technology that is effective when applied to a power semiconductor device for power control. [Background technology]

[0002] Global warming has become a critical and urgent issue shared by the entire world, and expectations are rising for the contribution of power electronics technology as one of the countermeasures. In particular, in order to improve the efficiency of inverters, which are responsible for power conversion, there is a need to reduce the power consumption of power semiconductor devices, mainly IGBTs (Insulated Gate Bipolar Transistors) that perform the power switching function and diodes that perform the rectification function.

[0003] Figure 25 shows a partial circuit diagram of a typical inverter. A diode 99 is connected in antiparallel to an IGBT 97 which has an insulated gate terminal 98. The inverter is powered by a DC power supply 96, and a voltage is applied to the insulated gate terminal 98 of the IGBT 97, causing it to rapidly turn on and off to control the power supplied to the connected inductive load 95. The inductive load 95 is, for example, a motor.

[0004] Since the IGBT97 and diode99 generate conduction losses when conducting and switching losses when switching, it is necessary to reduce the conduction losses and switching losses of the IGBT97 and diode99 in order to miniaturize and improve the efficiency of the inverter. Here, the switching loss consists of the turn-on loss and turn-off loss generated from the IGBT97, and the recovery loss generated from the diode99 when it is turned on.

[0005] As a technique for reducing the conduction loss and turn-off loss of IGBTs, for example, the technique relating to a double-gate type (also called a dual-gate type) IGBT structure having two independently controllable gates, as described in Patent Document 1, is known.

[0006] Figure 26 is a cross-sectional view of an IGBT described in Patent Document 1. Both gate Gs and gate Gc have a trench shape. When a high voltage is applied to the insulating gate electrode 91 of gate Gs and the insulating gate electrode 92 of gate Gc with respect to the emitter electrode 7, an electron layer, which is an inversion layer, is generated at the gate electrode interface of the p-type well layer 2. As a result, when a forward voltage is applied between the collector electrode 8 and the emitter electrode 7, electron carriers are injected from the emitter electrode 7 into the n-type drift layer 1 via the electron layer formed on the surfaces of the insulating gate electrode (Gs) 91 and the insulating gate electrode (Gc) 92, drawing out hole carriers from the p-type collector layer 4. Conductivity modulation occurs inside the n-type drift layer 1, and the IGBT becomes conductive.

[0007] Next, during turn-off, by applying a voltage to the gate below the threshold voltage that does not form an inversion layer at the gate electrode interface of the p-type well layer 2, the carriers that contributed to conductivity modulation are discharged to the emitter electrode 7 and collector electrode 8, transitioning to a non-conductive state. At this time, a power loss called turn-off loss occurs due to the current generated and the reverse voltage applied to the emitter electrode 7 and collector electrode 8.

[0008] In this structure, which has two independently controllable gates, it is possible to apply a voltage below the threshold voltage to one of the insulated gate electrodes (Gc) 92 prior to the insulated gate electrode (Gs) 91 immediately before turn-off, thereby suppressing conductivity modulation and temporarily forming a drift region with reduced carrier concentration. This reduces the current caused by carriers discharged during turn-off, and also reduces turn-off losses by rapidly applying a reverse voltage between the collector electrode 8 and the emitter electrode 7.

[0009] In other words, by changing the gate bias applied to the insulated gate electrode (Gs) 91 and the insulated gate electrode (Gc) 92 just before the conduction state and just before the non-conduction state, it is possible to dynamically control the carrier concentration accumulated in the n-type drift layer 1, and this control makes it possible to reduce the losses that occur during turn-off.

[0010] Furthermore, as another form of the double-gate type, a technique is known that temporarily reduces the accumulated carrier concentration near the collector region and reduces the current during turn-off. For example, a technique relating to a structure in which two IGBTs with different collector injection efficiencies are connected in parallel is described in Patent Document 2.

[0011] Figure 27 is a circuit diagram of an IGBT described in Patent Document 2. The IGBT consists of two IGBTs 33 and 34 with different structures, connected in parallel to perform the IGBT switching function. The two IGBTs 33 and 34 have different structures: IGBT 33 has high carrier injection efficiency and low on-voltage, while IGBT 34 has low injection efficiency and high on-voltage, and their respective gates 35 and 36 are controlled independently.

[0012] Here, the carrier injection efficiency is adjusted by the impurity concentration in the collector region of IGBTs 33 and 34, and the carrier lifetime control amount in the drift region. In the conduction state, by applying a voltage above the threshold voltage to the gates 35 and 36 of both IGBTs 33 and 34, both IGBTs 33 and 34 conduct, and a low on-voltage is obtained.

[0013] Next, during turn-off, a voltage below the threshold voltage is applied first to the gate 35 of the low-on-voltage IGBT 33, causing only the high-on-voltage IGBT 34 to conduct. By applying this control, a state of temporarily low carrier concentration can be created, and the current associated with carrier discharge when transitioning to a non-conductive state by applying a voltage below the threshold voltage to the high-on-voltage IGBT 34 can be reduced.

[0014] The advantage of this configuration and control system is that it allows control of the carrier concentration near the collector region in the drift region, specifically the average carrier concentration between parallel elements. By temporarily lowering the average carrier concentration by allowing only the high-on-voltage IGBT34 to conduct, the current during turn-off can be reduced.

[0015] These double-gate IGBTs offer low-loss performance, which suppresses heat generation due to power loss and thus reduces the rise in the maximum junction temperature during device operation. In other words, it is possible to increase the current that can flow through the device relative to the maximum junction temperature that can be tolerated by the device's junction life, etc., enabling higher power capacity in the same volume of inverters. On the other hand, since the current density of the device can be increased, the number of parallel connections can be reduced, leading to the value of miniaturization of power conversion devices.

[0016] Thus, reducing the losses of IGBTs is an important factor that leads to increased capacity and miniaturization of power conversion devices. For example, a power conversion device using a double-gate IGBT is known, such as the one described in Patent Document 3. [Prior art documents] [Patent Documents]

[0017] [Patent Document 1] International Publication No. 2014 / 038064 [Patent Document 2] Japanese Patent Publication No. 2012-238715 [Overview of the Initiative] [Problems that the invention aims to solve]

[0018] To increase the capacity and miniaturize power conversion devices, it is necessary to improve the turn-off interruption withstand capability of IGBTs, along with reducing their losses. Turn-off interruption withstand capability is the maximum current that can be safely interrupted without damage during turn-off switching. For example, to achieve 1.3 times the rated current with low-loss IGBTs, the turn-off interruption withstand capability must also increase by 1.3 times. Here, turn-off interruption withstand capability is also called RBSOA (Reverse Blocking Safe Operating Area).

[0019] In the double-gate IGBT structure described in Patent Documents 1 and 2, while it is described that low-loss performance can be derived by controlling accumulated carriers with two gates, the turn-off blocking tolerance is not described.

[0020] Generally, a semiconductor chip on which an IGBT is formed (hereinafter simply referred to as a "chip") is composed of an active region and a termination region arranged on the outer periphery thereof for the purpose of electric field relaxation. The accumulated carriers of the IGBT are mainly accumulated in the active region where the gate is arranged, while diffusion occurs in the lateral direction and they are also accumulated in the termination region. The carriers accumulated in this termination region concentrate on the peripheral portion of the active region during turn-off, resulting in current concentration and a risk of local power increase and breakdown. This tendency is particularly显著 confirmed in chips using thick wafers and high-voltage IGBTs that require a wide termination region.

[0021] In the double-gate IGBTs described in Patent Documents 1 and 2, while the control of carriers in the active region is described, the boundary with the termination region and the like are not described, and it is difficult to improve the current concentration from the termination region. Therefore, the turn-off blocking tolerance cannot be improved.

[0022] As described above, in the structures of Patent Document 1 and Patent Document 2, in the active region of the IGBT, by controlling the carrier concentration during conduction and switching, the accumulated carrier concentration can be optimized, and both the conduction loss and the turn-off loss can be reduced. However, carrier control is difficult in the termination region and its boundary, it is difficult to improve the turn-off blocking tolerance, and it is difficult to increase the allowable current capacity and current density.

[0023] Therefore, an object of the present invention is to provide a highly reliable semiconductor device having low conduction loss and switching loss and capable of improving the turn-off blocking tolerance, and a power conversion device using the same.

Means for Solving the Problems

[0024] "> To solve the above problems, the present invention provides a semiconductor device having a switching gate and a carrier control gate that are driven independently of each other, wherein when the semiconductor device is viewed from above, it comprises a central region cell, an outer region cell surrounding the entire circumference of the central region cell, and an end region surrounding the entire circumference of the outer region cell, the central region cell has a switching element having the switching gate and the carrier control gate, the outer region cell is arranged between the central region cell and the end region, and the gate of the switching element of the outer region cell is composed only of the carrier control gate. Furthermore, the switching element of the central region cell has an emitter layer and a well layer disposed between the switching gate and the carrier control gate, and the switching element of the outer region cell has the carrier control gate, an emitter layer and a well layer, and the spacing between the well layers in the outer region cell is narrower than the spacing between the well layers in the central region cell. It is characterized by the following: [Effects of the Invention]

[0025] According to the present invention, it is possible to realize a highly reliable semiconductor device that has both low conduction loss and switching loss, and can improve turn-off interruption withstand capability, as well as a power conversion device using the same.

[0026] This enables increased capacity and improved reliability of semiconductor devices and power conversion devices using them.

[0027] Other issues, configurations, and effects not mentioned above will be clarified by the following description of the embodiments. [Brief explanation of the drawing]

[0028] [Figure 1] This is a cross-sectional view of a semiconductor device according to Embodiment 1 of the present invention. [Figure 2] This figure shows the drive circuit diagram and drive signals using the semiconductor device shown in Figure 1. [Figure 3] This figure conceptually shows the carrier distribution during the high-conductivity period of the semiconductor device shown in Figure 1. [Figure 4] This figure conceptually shows the carrier distribution during the low conductivity period of the semiconductor device shown in Figure 1. [Figure 5] Figure 1 conceptually shows the carrier distribution during turn-off switching of the semiconductor device. [Figure 6]This diagram conceptually shows the carrier distribution during turn-off switching of a conventional semiconductor device. [Figure 7] This figure shows the turn-off switching waveform and power loss. [Figure 8] This figure shows the correlation between the maximum rated voltage (MRV) and the turn-off interruption capacity (STD). [Figure 9] This figure shows the correlation between switching loss (SL) and turn-off interruption capacity (STD). [Figure 10] This is a plan layout diagram of a semiconductor device according to Embodiment 2 of the present invention. [Figure 11] This is a top view of a semiconductor chip according to Embodiment 2 of the present invention. [Figure 12] This is a plan view of the longitudinal end of the gate in a semiconductor device according to Embodiment 2 of the present invention. [Figure 13] This is a cross-sectional view taken along line B-B' in Figure 12. [Figure 14] This figure shows a modified version of Figure 12. (Modified Version 1) [Figure 15] This figure shows a modified version of Figure 12. (Modified Version 2) [Figure 16] This is a plan layout diagram of a semiconductor device according to Embodiment 3 of the present invention. [Figure 17] This is a cross-sectional view taken along line C-C' in Figure 16. [Figure 18] This figure shows the profile distribution of the accumulated carrier concentration in the semiconductor device shown in Figure 16. [Figure 19] This is a cross-sectional view of a semiconductor device according to Embodiment 4 of the present invention. [Figure 20] This figure shows a modified version of Figure 19. (Modified Version 3) [Figure 21] Figures 19 and 20 show the profile distribution of the accumulated carrier concentration in the semiconductor device. [Figure 22] This is a plan layout diagram of a semiconductor device according to Embodiment 5 of the present invention. [Figure 23] This is a plan layout diagram of a semiconductor device according to Embodiment 6 of the present invention. [Figure 24]This is a cross-sectional view of a semiconductor device according to Embodiment 7 of the present invention. [Figure 25] This diagram shows the circuit configuration of a typical power conversion device. [Figure 26] This is a cross-sectional view of a semiconductor device to which the prior art described in Patent Document 1 is applied. [Figure 27] This is a circuit diagram of a semiconductor device to which the prior art described in Patent Document 2 is applied. [Modes for carrying out the invention]

[0029] Embodiments of the present invention will be described below with reference to the drawings. In each drawing, identical components are denoted by the same reference numerals, and detailed descriptions of overlapping parts are omitted.

[0030] Furthermore, the notations n- and n in the figure indicate that the semiconductor layer is n-type, and that the impurity concentration of n is relatively higher than that of n-. Similarly, the notations p- and p indicate that the semiconductor layer is p-type, and that the impurity concentration of p is relatively higher than that of p-.

[0031] Furthermore, in the following, IGBTs with two gates will be referred to as double-gate IGBTs, but they are also called dual-gate IGBTs, and the two terms are synonymous. [Examples]

[0032] Referring to Figures 1 to 9, an insulated gate type (gate-controlled type) semiconductor device according to Embodiment 1 of the present invention will be described. Figure 1 is a cross-sectional view of the semiconductor device 100 of this embodiment.

[0033] The semiconductor device 100 in this embodiment is a double-gate IGBT having multiple trench gate shapes, and a common n-type drift layer 20 is provided with a central region 17, an outer peripheral region 18, and a terminal region 19. The central region 17 and the outer peripheral region 18 are regions where carriers are injected into the n-type drift layer 20 by gate bias when the IGBT is conducting, while the terminal region 19 is a region for mitigating the electric field in response to a high voltage applied when the IGBT is not conducting.

[0034] A switching element having a trench-shaped switching gate (Gs) 11 and a carrier control gate (Gc) 10 as gates is arranged in the upper part of the central region 17. On the other hand, a switching element consisting only of a carrier control gate (Gc) 10, without a switching gate (Gs) 11, is arranged in the upper part of the outer peripheral region 18.

[0035] Furthermore, the semiconductor device 100 includes a p-type well layer 25 adjacent to the n-type drift layer 20 in the vertical direction, and a p-type collector layer 26 adjacent to the n-type drift layer 20 in the vertical direction on the opposite side of the p-type well layer 25.

[0036] Furthermore, a p-type power supply layer 27 and an n-type emitter layer 28 are located adjacent to each other above the p-type well layer 25. These p-type well layer 25 and n-type emitter layer 28 are in contact with the switching gate (Gs) electrode 24, which is the first gate electrode in a trench gate shape, and the carrier control gate (Gc) electrode 23, which is the second gate electrode in a trench gate shape, via a gate insulating film (gate oxide film) 29.

[0037] Here, the switching gate (Gs) 11 consists of a gate insulating film 29 in contact with the n-type emitter layer 28 and the p-type well layer 25, and a switching gate (Gs) electrode 24 provided opposite and in contact with it. The carrier control gate (Gc) 10 also consists of a gate insulating film 29 in contact with the n-type emitter layer 28 and the p-type well layer 25, and a carrier control gate (Gc) electrode 23 provided opposite and in contact with it. These switching gates (Gs) 11 and carrier control gates (Gc) 10 are collectively referred to as the "trench gate" below.

[0038] The emitter electrode 40 has a downwardly convex trench shape and is in contact with the p-type power supply layer 27 and the n-type emitter layer 28. Each trench gate is insulated from each other via a gate insulating film 29. The n-type drift layer 20 is adjacent to the p-type collector layer 26 on the surface opposite to the p-type well layer 25. The device also includes a collector electrode 41 in contact with the p-type collector layer 26.

[0039] The termination region 19 comprises a p-type high-concentration layer 6 and a floating electrode 9 intermittently provided above the n-type drift layer 20. This structure allows equipotential lines to be placed at regular intervals when a high voltage is applied between the collector electrode 41 and the emitter electrode 40, thereby preventing avalanche breakdown due to electric field concentration.

[0040] The termination region 19 is also commonly referred to as a guard ring or termination. Furthermore, the p-type high-concentration layer 6 may be arranged continuously with a concentration gradient, rather than being intermittently. Moreover, the structure may not include the floating electrode 9, and the present invention is not limited to a specific termination region structure.

[0041] In the semiconductor device 100, the n-type drift layer 20, emitter electrode 40, and collector electrode 41 of the central region 17, the outer peripheral region 18, and the terminal region 19 are common, and are configured inside a single-chip semiconductor device, as will be described later using Figure 11.

[0042] Here, the outer region 18 is arranged to surround the entire circumference of the central region 17, and furthermore, the terminal region 19 is arranged to surround the entire circumference of the outer region 18. In other words, the outer region 18 is the region sandwiched between the central region 17 and the terminal region 19 (see Figure 11). As described above, both the switching gate (Gs) 11 and the carrier control gate (Gc) 10 are arranged in the central region 17, and only the carrier control gate (Gc) 10 is arranged in the outer region 18. This configuration is designed to achieve the carrier concentration reduction effect during the carrier extraction period shown below.

[0043] In this embodiment, the semiconductor substrate is formed from, for example, silicon (Si) or silicon carbide (SiC), and the gate insulating film 29 is formed from, for example, silicon dioxide (SiO2).

[0044] Next, the operation of the semiconductor device 100 of this embodiment will be explained using Figures 2 to 6. Figure 2 shows the drive circuit diagram and drive signals using the semiconductor device 100 of this embodiment.

[0045] The semiconductor device 100 in this embodiment exhibits highly reliable operation with low loss and high turn-off breakout withstand capability, driven by drive signals from gate drivers 44 and 45 that drive the carrier control gate (Gc) 10 and the switching gate (Gs) 11, respectively.

[0046] In the right-hand diagram of Figure 2, reference numeral 48 indicates the conduction period of the IGBT, and reference numeral 49 indicates the non-conduction period. First, during the IGBT conduction period, a high-conductivity period 46 is set in which a voltage equal to or greater than the threshold voltage (Vth) that forms an inversion layer in the p-type well layer 25 of the IGBT is applied to the carrier control gate (Gc) 10 and the switching gate (Gs) 11, and a low-conductivity period 47 is set in which a voltage below the threshold is applied to the carrier control gate (Gc) 10, and a voltage equal to or greater than the threshold voltage is applied to the switching gate (Gs) 11.

[0047] During the high-conductivity period 46, the concentration of stored carriers inside the IGBT increases, resulting in low on-voltage performance. During the low-conductivity period 47, the concentration of stored carriers inside the IGBT decreases, and then during the non-conductivity period 49, when a voltage below the threshold voltage is applied to the switching gate (Gs) 11 and the IGBT is turned off, a reverse blocking voltage is rapidly applied to the IGBT, and the current is rapidly reduced, enabling turn-off switching 50 that ensures low loss and high turn-off interruption withstand capability.

[0048] In other words, by driving the IGBT structure of this embodiment shown in the left diagram of Figure 2 with a drive signal as shown in the right diagram of Figure 2, IGBT performance that ensures low loss and high turn-off interruption capability can be derived.

[0049] Figure 3 shows the carrier distribution of the semiconductor device 100 of this embodiment during the high conduction period 46. It shows the carrier distribution of electrons 51 and holes 52 when a positive voltage above the threshold voltage that generates an electron layer, which is an inversion layer, is applied to the carrier control gate (Gc) 10 and the switching gate (Gs) 11, and a forward voltage that causes the IGBT to conduct between the collector electrode 41 and the emitter electrode 40 is also applied.

[0050] Electrons 51 are injected from the n-type emitter layer 28 into the n-type drift layer 20 via the electron layer generated in the p-type well layer 25 from the emitter electrode 40. Then, in the n-type drift layer 20, holes 52 are injected from the p-type collector layer 26, triggered by the injected electrons 51, causing conductivity modulation 53 to occur inside the n-type drift layer 20.

[0051] In this embodiment, the semiconductor device 100 has a central region 17 and an outer peripheral region 18. Electrons 51 are injected from the carrier control gate (Gc) 10 and switching gate (Gs) 11 provided in the central region 17, and from the n-type emitter layer 28 adjacent to the carrier control gate (Gc) 10 provided in the outer peripheral region 18, thereby increasing the carrier concentration accumulated by conductivity modulation 53.

[0052] Furthermore, the electrons 51 injected into the outer region 18 also diffuse to the terminal region 19, inducing the injection of holes 52 from the p-type collector layer 26 beneath the terminal region 19. As a result, the carrier concentration accumulated in the terminal region 19 by the modulation of the electric field 53 also increases.

[0053] As a result, the semiconductor device 100 of this embodiment can carry a predetermined current with a low voltage drop, i.e., a low on-voltage, and thus achieves low loss performance during conduction.

[0054] Figure 4 shows the carrier distribution of the semiconductor device 100 of this embodiment during the low-conductivity period 47, after the high-conductivity period 46, when a negative voltage below the threshold voltage is applied to the carrier control gate (Gc) 10.

[0055] When a forward voltage is applied between the collector electrode 41 and the emitter electrode 40, causing the IGBT to conduct, a storage layer is formed in the p-type well layer 25 in contact with the carrier control gate (Gc) 10, and holes 52 that contributed to conductivity modulation inside the n-type drift layer 20 are discharged to the emitter electrode 40 via the storage layer.

[0056] In this embodiment, the semiconductor device 100 has holes 52 in the central region 17 and the outer peripheral region 18 discharged by the carrier control gate (Gc) 10, and holes 52 that have accumulated in the terminal region 19 are also discharged to the emitter electrode 40 via the accumulation layer formed in the p-type well layer 25 of the outer peripheral region 18 by the positive bias of the carrier control gate (Gc) 10 of the outer peripheral region 18.

[0057] Furthermore, in this embodiment, the semiconductor device 100 does not have a switching gate (Gs) 11 as a gate in the outer peripheral region 18, and the gate is composed only of a carrier control gate (Gc) 10. Therefore, unlike the central region 17, electrons 51 are not injected in the outer peripheral region 18.

[0058] This allows for the temporary formation of a low-concentration storage carrier profile 54 within the n-type drift layer 20 in the central region 17, while also allowing for the formation of an extremely low-concentration storage carrier profile 55 within the n-type drift layer 20 in the outer region 18 and the terminal region 19. In other words, when the IGBT conducts, a state can be created in which current flows only through the central region 17.

[0059] Figure 5 shows the carrier distribution of the semiconductor device 100 of this embodiment during turn-off switching 50, when a negative voltage below the threshold voltage is applied to the switching gate (Gs) 11 after a low-conductivity period 47.

[0060] After a low-conductivity period 47, when an off-bias is applied to the switched gate (Gs) 11 and the semiconductor device 100 transitions from a conductive state to a non-conductive state in a turn-off switching operation, the accumulated carrier concentration inside the n-type drift layer 20 is low. As a result, holes 52 are rapidly discharged to the emitter electrode 40 and electrons 51 are rapidly discharged to the collector electrode 41. This allows a reverse blocking voltage to be rapidly applied to the IGBT, and the current to be rapidly reduced, resulting in low-loss turn-off switching.

[0061] In this embodiment, the semiconductor device 100 was able to form a state (profile 55) in which the carrier concentration in the outer peripheral region 18 and the terminal region 19 was accumulated at an extremely low concentration during the preceding low-conductivity period 47. As a result, the current during turn-off switching hardly flows into the region of profile 55, and the current is limited to the central region 17. That is, the current due to the holes 52 flowing to the emitter electrode 40 does not concentrate in the outer peripheral region 18, thereby suppressing power generation due to localized current concentration and the resulting temperature rise, and increasing the turn-off interruption withstand capability, which is defined as the current value at which the device can be interrupted without damage after the current has passed.

[0062] Figure 6 shows the carrier distribution during turn-off switching of a conventional semiconductor device (IGBT) 1000, which is shown as a comparative example to make the present invention easier to understand. When conduction occurs, a high concentration of holes 52 accumulated is discharged to the emitter electrode 40, resulting in a slow current reduction and large turn-off switching losses. Furthermore, when conduction occurs, the holes 52 accumulated in the termination region 19 are concentrated and discharged to the emitter electrode 40 of the cell 32 located at the boundary with the termination region 19, increasing the current density of the cell 32. This leads to power generation due to localized current concentration and subsequent temperature rise, causing destruction. In other words, the turn-off interruption withstand capability is limited by the destruction resistance of the cell 32.

[0063] Therefore, with the semiconductor device 100 of this embodiment, the accumulated carrier concentration inside the IGBT can be controlled by the gate bias of the carrier control gate (Gc) 10, and in particular the controllability of the accumulated carrier concentration in the outer peripheral region 18 and the termination region 19 can be improved, achieving both low on-voltage performance during conduction and low turn-off loss performance, and further ensuring a high turn-off interruption withstand capability, thereby realizing a highly reliable IGBT.

[0064] Next, the effects of the present invention regarding turn-off interruption withstand capability will be explained using Figures 7 to 9. Figure 7 shows a comparison of the turn-off switching waveform 58 of the double-gate IGBT of the present invention and the turn-off switching waveform 57 of a conventional double-gate IGBT based on Patent Document 1. Here, the waveforms are compared under conditions where a large current exceeding the rated current, which is the operating condition of the power converter, is flowing.

[0065] By applying an off-bias to the switching gate (Gs) 11, the IGBT transitions from a conductive state to a non-conductive state, and Figure 7 shows the collector current I at that time. C and collector-emitter voltage V CE Changes, and I C and V CE This shows the power GP generated by the product of the two factors.

[0066] When an off bias is applied to the switching gate (Gs) 11, carriers inside the IGBT are discharged, and first V CE rises. Here, in the double - gate IGBT 58 of the present invention, due to the low carrier concentration in the outer peripheral region 18 and the termination region 19 during the immediately preceding low - conduction period 47, V CE rises to the power supply voltage at a higher speed compared to the conventional double - gate IGBT 57. This phenomenon is mainly due to the effect that the carrier concentration near the emitter region of the drift region, that is, near the surface, is reduced in the present invention.

[0067] Next, when V CE reaches the power supply voltage, the reduction of I C starts. In the double - gate IGBT 58 of the present invention, due to the low carrier concentration in the outer peripheral region 18 and the termination region 19 during the low - conduction period 47, especially the low carrier concentration near the collector region of the drift region, that is, near the back surface, the collector current I C decreases at a high speed, and the tail period is also small and reaches 0 A, transitioning to the non - conduction state. That is, according to the double - gate IGBT 58 of the present invention, both the collector - emitter voltage V CE and the collector current I C can be changed at a higher speed compared to the conventional double - gate IGBT 57.

[0068] By integrating the generated power GP due to these changes in V CE and I C , the power loss during turn - off switching is calculated. As shown in FIG. 7, according to the double - gate IGBT 58 of the present invention, it can be seen that the generated power loss 30 is smaller than the conventional power loss 31 because the change periods of V CE and I C are short.

[0069] The difference between the present invention and conventional double-gate IGBTs is that, while conventional IGBTs use a switching element having both a switching gate (Gs) 11 and a carrier control gate (Gc) 10 as gates in the outer peripheral region 18, the present invention uses a switching element in which the switching gate (Gs) 11 does not exist as a gate in the outer peripheral region 18, and the gate is composed only of a carrier control gate (Gc) 10. In other words, the present invention suppresses local current concentration in the outer peripheral region 18, reduces local power loss, and suppresses temperature rise. This makes it possible to increase the turn-off interruption withstand capability.

[0070] Figure 8 shows the correlation between the turn-off interruption withstand voltage (STD) and voltage V in the present invention and conventional double-gate IGBTs. MRV represents the maximum rated voltage, reference numeral 59 represents the turn-off interruption withstand voltage of a conventional double-gate IGBT, and reference numeral 60 represents the turn-off interruption withstand voltage of the double-gate IGBT of the present invention.

[0071] Here, the area inside the correlation line indicates the safe operating range (operating range RU) in which the power converter can be permitted to operate without damage during turn-off switching. The present invention expands the operating range RU, improves the breakdown withstand capability under high-voltage, high-current switching conditions, and provides design permission conditions for power converters that can handle higher power.

[0072] Figure 9 shows the correlation between the switching loss SL and turn-off interruption withstand capability STD for the present invention, the conventional double-gate type IGBTs 63 and 62, and the conventional single-gate type IGBT 61.

[0073] Here, the switching loss SL represents the performance at the rated voltage used in the normal operation of the power converter, while the turn-off interruption withstand capability STD represents the performance at the maximum rated voltage that must be guaranteed instantaneously. The relationship between the rated voltage and the maximum rated voltage is rated voltage < maximum rated voltage. Compared to the conventional IGBT61, which consists of one type of gate, the conventional double-gate IGBT62 can reduce the switching loss SL by dynamically controlling the carrier, but it was difficult to increase the turn-off interruption withstand capability STD due to the breakdown withstand capability of the outer peripheral region 18.

[0074] By applying the double-gate type IGBT63 of the present invention, it is possible to achieve both a switching loss SL equivalent to or lower than that of the conventional double-gate type IGBT62 and a higher turn-off interruption withstand capability STD. In other words, a double-gate type IGBT that achieves both low loss and high output can be provided.

[0075] As described above, the semiconductor device 100 (double-gate IGBT) of this embodiment has a switching gate (Gs) electrode 24 and a carrier control gate (Gc) electrode 23 that are driven independently of each other. When the semiconductor device 100 is viewed from above, it comprises a central region (cell) 17, an outer peripheral region (cell) 18 that surrounds the entire circumference of the central region (cell) 17, and a terminal region 19 that surrounds the entire circumference of the outer peripheral region (cell) 18. The central region (cell) 17 has a switching element having a switching gate (Gs) and a carrier control gate (Gc), and the outer peripheral region (cell) 18 is located between the central region (cell) 17 and the terminal region 19. The gate of the switching element in the outer peripheral region (cell) 18 is composed only of a carrier control gate (Gc) electrode 23.

[0076] The semiconductor device 100 (double-gate IGBT) of this embodiment achieves low-loss performance by combining low conduction loss and low turn-off loss, and has high turn-off interruption withstand capability, making it possible to realize a highly reliable IGBT that can handle high power. [Examples]

[0077] Referring to Figures 10 to 15, an insulated gate type (gate-controlled type) semiconductor device according to Embodiment 2 of the present invention will be described. Figure 10 is a plan view of the semiconductor device 200 of this embodiment, showing the longitudinal direction of the gate. Figure 11 is a top view of the chip on which the semiconductor device 200 of Figure 10 is mounted. Note that the chip shown in Figure 11 has a common configuration in all embodiments from Embodiment 1 onwards.

[0078] As shown in Figures 10 and 11, the semiconductor device 200 of this embodiment has a terminal region 19 located on the outer periphery of the chip, an outer peripheral region 18 located inside the terminal region 19, and a central region 17 located further inside the terminal region 18. The gate electrode of the trench gate of the IGBT located in the central region 17 is composed of a switching gate (Gs) electrode 24 and a carrier control gate (Gc) electrode 23. The gate electrode of the trench gate of the IGBT located in the outer peripheral region 18 is composed of only a carrier control gate (Gc) electrode 23.

[0079] The central region 17 and the outer region 18 are formed, for example, by differentiating them using a mask through a common manufacturing process.

[0080] Here, multiple switching gate (Gs) electrodes 24 and carrier control gate (Gc) electrodes 23 are connected and bundled to switching gate (Gs) wiring 14 and carrier control gate (Gc) wiring 13, respectively, by a contact layer 39, and the IGBT of this embodiment operates with two gate signals.

[0081] Here, the carrier control gate (Gc) electrodes 23 in the outer peripheral region 18 are shown as four, but the number is not limited to this. The higher the voltage resistance of the element, the larger the area of ​​the termination region 19 for electric field relaxation and the thicker the drift layer, which promotes conductivity modulation in the termination region 19 during the high-conductivity period 46. Therefore, since the effects of the present invention are achieved by sufficiently extracting the carriers during the low-conductivity period 47, it is effective to widen the outer peripheral region 18 and increase the number of carrier control gate (Gc) electrodes 23.

[0082] Furthermore, although Figure 10 shows the switching gate (Gs) wiring 14 and carrier control gate (Gc) wiring 13 traversing only the outer region 18 and the central region 17, they may also be wired on the termination region 19 for the purpose of reducing wiring resistance or facilitating power supply.

[0083] Figure 12 shows a plan view of the longitudinal end of the gate in the semiconductor device 200 of the present invention. At the longitudinal end of the gate, a termination region 19 is provided for electric field relaxation in order to increase the voltage withstand capability. Since carriers accumulate in this termination region 19 as well, in this embodiment, an outer peripheral region 18 is provided between it and the central region 17.

[0084] Here, in the outer peripheral region 18 in the longitudinal direction of the gate, the switching gate (Gs) electrode 24 extends from the central region 17, while a dummy gate region 42 (a dummy region that does not function as a switching gate (Gs)) is placed that is not adjacent to the n-type emitter layer 28. This is a region where the n-type emitter layer 28, which is positioned opposite the switching gate (Gs) electrode 24 via a gate insulating film, is not formed, meaning that electrons 51 are not injected during the low-conductivity period 47. In other words, even in the outer peripheral region 18 at the longitudinal end of the gate, only the carrier-controlled gate (Gc) electrode 23 is arranged as the gate electrode of a trench gate having an n-type emitter layer 28.

[0085] During the low-conductivity period 47, holes 52 are discharged by the carrier-controlled gate (Gc) electrode 23 in the outer peripheral region 18 at the longitudinal end of the gate. Therefore, current concentration in the outer peripheral region 18 is suppressed even in the longitudinal direction of the gate during turn-off switching, and a high turn-off interruption withstand capability can be obtained.

[0086] In Figure 12, the switching gate (Gs) wiring 14 and carrier control gate (Gc) wiring 13 are shown to traverse only the outer region 18 and the central region 17. However, they may also be wired on the termination region 19 for the purpose of reducing wiring resistance or facilitating power supply.

[0087] Figure 13 shows the B-B' cross-section of Figure 12. The termination region 19 is located outside the outer peripheral region 18. In the outer peripheral region 18 of this cross-section, the switching gate (Gs) electrode 24 does not have an opposing n-type emitter layer 28, and a dummy gate region 42 is located there.

[0088] In other words, when the semiconductor device 200 is viewed from above, the gate electrode of the switching gate (Gs) electrode 24 extends into the outer peripheral region 18, but the gate electrode in the outer peripheral region 18 is a dummy gate in which an n-type emitter layer 28 is not placed via the gate insulating film 29.

[0089] The carrier control gate (Gc) electrode 23 positioned in the outer peripheral region 18 allows for the extraction of carriers accumulated in the n-type drift layer 20 by conductivity modulation during the high-conductivity period 46 during the low-conductivity period 47. This improves the breakdown withstand capability due to current concentration in the outer peripheral region 18 during turn-off switching, thereby achieving high turn-off interruption withstand capability.

[0090] ≪Extreme Variation 1≫ Figure 14 shows a modified version of Figure 12.

[0091] In the modified example shown in Figure 14, the gate is divided into a central region 17 and an outer peripheral region 18 along its longitudinal direction by carrier control gate (Gc) wiring 13, switching gate (Gs) wiring 14, and a contact layer 39. In the outer peripheral region 18 at the longitudinal end of the gate, the gate electrode consists only of a carrier control gate (Gc) electrode 23.

[0092] <<Variation 2>> Figure 15 shows another modified example of Figure 12.

[0093] In the modified example shown in Figure 15, the layout is such that there is no switching gate (Gs) electrode 24 in the outer peripheral region 18 in the longitudinal direction of the gate, so that the gate electrode of the trench gate in the outer peripheral region 18 consists only of the carrier control gate (Gc) electrode 23.

[0094]

[0094]

[0095] In FIGS. 14 and 15, the switching gate (Gs) wiring 14 and the carrier control gate (Gc) wiring 13 are shown as only passing through the outer peripheral region 18 and the central region 17. However, for the purpose of reducing the wiring resistance and facilitating the power supply, they may be wired on the terminal region 19.

Example

[0096] Referring to FIGS. 16 to 18, an insulated gate type (gate control type) semiconductor device according to Embodiment 3 of the present invention will be described. FIG. 16 is a plan layout view of the semiconductor device 300 of this embodiment, showing the longitudinal direction of the gate.

[0097] As shown in FIG. 16, in the semiconductor device 300 of this embodiment, when the center-to-center distance between adjacent emitter regions in the central region 17 is a and the center-to-center distance between adjacent emitter regions in the outer peripheral region 18 is b, the layout is such that the relationship b ≤ a, preferably b < a holds.

[0098]

[0099] Note that the carrier control gate (Gc) electrodes 23 in the outer peripheral region 18 are shown as six, but the number is not limited to this. The higher the breakdown voltage of the device, the larger the area of the termination region 19 for field relaxation, the thicker the drift layer, and the more the conductivity modulation of the termination region 19 during the high-conductivity period 46 is promoted. Therefore, since the effect of the present invention is exerted by sufficiently extracting the carriers during the low-conductivity period 47, it is effective to widen the outer peripheral region 18 and increase the number of carrier control gate (Gc) electrodes 23.

[0100] Also in FIG. 16, the switching gate (Gs) wiring 14 and the carrier control gate (Gc) wiring 13 are shown as only passing through the outer peripheral region 18 and the central region 17, but for the purpose of reducing the wiring resistance or facilitating power supply, they may be wired on the termination region 19.

[0101] FIG. 17 shows the C-C' cross section of FIG. 16. The outer peripheral region 18 is disposed outside the central region 17, and the termination region 19 is further disposed outside thereof. And by establishing the relationship of b≤a, preferably b<a described above, the density of the carrier control gate (Gc) electrodes 23 in the outer peripheral region 18 becomes higher than that in the central region 17.

[0102] The carrier control gate (Gc) electrodes 23 disposed at a high density in the outer peripheral region 18 can efficiently extract the carriers accumulated by conductivity modulation in the n-type drift layers 20 of the outer peripheral region 18 and the termination region 19 during the high-conductivity period 46 during the low-conductivity period 47. As a result, in turn-off switching, the breakdown withstand due to current concentration in the outer peripheral region 18 can be further improved, and a higher turn-off blocking withstand can be obtained.

[0103] FIG. 18 shows the profile distribution of the accumulated carrier concentration ACC of the semiconductor device 300 during the high-conduction period 46. By adopting a configuration of b < a in which the carrier control gate (Gc) electrodes 23 are arranged at a higher density with respect to the central region 17 and in the outer peripheral region 18, the hole carriers 52 injected from the p-type collector layer 26 are easily discharged from the p-type well layer 25 to the emitter electrode 40 in the outer peripheral region 18, and the conductivity modulation in the outer peripheral region 18 is suppressed. Therefore, the accumulated carrier concentration profile becomes lower toward the terminal region 19 than in the case of the b = a arrangement.

[0104] As described above, in the semiconductor device 300 of the present embodiment, the interval between the p-type well layers 25 in the outer peripheral region 18 is narrower than the interval between the p-type well layers 25 in the central region 17.

[0105] As a result, the carrier concentrations in the outer peripheral region 18 and the terminal region 19 during the low-conduction period 47 become lower, and in subsequent turn-off switching, an effect of further improving the breakdown tolerance due to current concentration in the outer peripheral region 18 can be derived.

Embodiment

[0106] Referring to FIGS. 19 to 21, an insulated-gate type (gate control type) semiconductor device 400 according to Embodiment 4 of the present invention will be described. FIG. 19 is a cross-sectional view of the semiconductor device 400 of the present embodiment.

[0107] [[ID=…]]

[0108] ​In this embodiment, since the carrier lifetime reduction layer 64 is not present in the central region 17, the impact on conduction loss during the high conduction period is limited, and the impact on the low conduction loss performance of the double-gate IGBT of the present invention is small. On the other hand, by introducing the carrier lifetime reduction layer 64 in the outer region 18 and the terminal region 19, conductivity modulation in the outer region 18 and the terminal region 19 can be suppressed.

[0109] This reduces the accumulated carrier concentration during the high-conductivity period 46, and in the low-conductivity period 47, the effect of hole 52 discharge from the carrier-controlled gate (Gc) electrode 23 further reduces the carrier concentration in the outer peripheral region 18 compared to the configurations of Examples 1 to 3. Therefore, in turn-off switching, the breakdown withstand capability due to current concentration in the outer peripheral region 18 can be further improved, and a higher turn-off interruption withstand capability can be obtained.

[0110] <<Variation 3>> Figure 20 shows a modified version of Figure 19.

[0111] In the modified example shown in Figure 20, the impurity concentration of the p-type collector layer in contact with the n-type drift layer 20 is reduced in the outer region 18 and the terminal region 19 compared to the central region 17. The p-type collector layer is the layer into which holes 52 are injected when the IGBT is conductive, and reducing its concentration reduces the injection efficiency.

[0112] In Figure 20, by increasing the density of the p-type collector layer 26 in the central region 17 and decreasing the density of the p-type collector layer 69 in the outer region 18 and the terminal region 19, the conduction loss during the high conduction period 46 is not affected, and the low conduction loss performance of the double-gate IGBT of the present invention can be maintained. On the other hand, by reducing the density of the p-type collector layer 69 in the outer region 18 and the terminal region 19, conductivity modulation in the outer region 18 and the terminal region 19 can be suppressed.

[0113] Figure 21 shows the profile distribution of the accumulated carrier concentration ACC during the high-conductivity period 46 with the configurations of Figures 19 and 20. By reducing the carrier lifetime in the outer peripheral region 18 and the terminal region 19, or by reducing the concentration of the p-type collector layer, or by applying both, the conductivity modulation in the outer peripheral region 18 and the terminal region 19 is suppressed, resulting in lower concentrations compared to the structures shown in Examples 1 to 3. Therefore, the carrier concentrations in the outer peripheral region 18 and the terminal region 19 during the low-conductivity period 47 become even lower, and the effect of further improving the breakdown withstand capability due to current concentration in the outer peripheral region 18 during subsequent turn-off switching can be derived.

[0114] Furthermore, the configurations shown in Figures 19 and 20 can be applied to the planar layouts shown in Examples 1 to 3. [Examples]

[0115] Referring to Figure 22, an insulated gate type (gate-controlled type) semiconductor device 500 according to Embodiment 5 of the present invention will be described. Figure 22 is a plan view of the semiconductor device 500 of this embodiment, showing the longitudinal direction of the gate.

[0116] Figure 22 shows the arrangement of the p-type power supply layer 27 and the n-type emitter layer 28 connected to the emitter electrode 40. The n-type emitter layer 28 is the region that injects electrons 51 into the n-type drift layer 20 when the IGBT is conducting. In this embodiment, the density per unit area of ​​the n-type emitter layer 28 in contact with the carrier control gate (Gc) electrode 23 is reduced compared to the density per unit area of ​​the n-type emitter layer 28 in contact with the switching gate (Gs) electrode 24.

[0117] In other words, the area density of the n-type emitter layer 28 in the outer peripheral region 18 is reduced compared to the area density of the n-type emitter layer 28 in the central region 17.

[0118] As described above, in the semiconductor device 500 of this embodiment, when viewed from above, the proportion of the outer peripheral region 18 in which the n-type emitter layer 28 is arranged via the gate insulating film 29 to the carrier control gate (Gc) electrode 23 is smaller than the proportion of the central region 17 in which the n-type emitter layer 28 is arranged via the gate insulating film 29 to the switching gate (Gs) electrode 24.

[0119] According to this embodiment, the electron injection efficiency from the outer region 18 during the low-conductivity period 47 can be reduced, thereby suppressing conductivity modulation between the outer region 18 and the terminal region 19 in the n-type drift layer 20, and further reducing the accumulated carrier concentration compared to the configurations of Examples 1 to 4. As a result, the breakdown withstand capability due to current concentration in the outer region 18 during turn-off switching can be further improved, and a higher turn-off interruption withstand capability can be obtained.

[0120] In Figure 22, the switching gate (Gs) wiring 14 and carrier control gate (Gc) wiring 13 are shown to traverse only the outer region 18 and the central region 17. However, they may also be wired on the termination region 19 for the purpose of reducing wiring resistance or facilitating power supply.

[0121] Furthermore, the configuration shown in Figure 22 can be applied to the planar layouts shown in Examples 1 to 3. [Examples]

[0122] Referring to Figure 23, an insulated gate type (gate-controlled type) semiconductor device 600 according to Embodiment 6 of the present invention will be described. Figure 23 is a planar layout diagram of the semiconductor device 600 of this embodiment, showing the area around the gate pad region.

[0123] As shown in Figure 23, in the semiconductor device 600 of this embodiment, a gate pad region 65 is located in a part of the inside of a termination region 19 located on the outer periphery of the chip, an outer peripheral region 18 is located adjacent to the inside of the termination region 19 and the gate pad region 65, and a central region 17 is located further inside that.

[0124] As shown in Figure 23, in the semiconductor device 600 of this embodiment, the gate pad region 65 is configured to be adjacent to the terminal region 19 and the outer peripheral region 18.

[0125] In the gate pad region 65, a common n-type drift layer 20 and p-type collector layer 26 are arranged below it, along with the outer peripheral region 18, the central region 17, and the terminal region 19. Therefore, during the high-conductivity period 46, conductivity modulation occurs in the n-type drift layer 20 of the gate pad region 65, and the carrier concentration increases.

[0126] During the low conductivity period 47, the holes 52 are extracted by the carrier-controlled gate (Gc) electrodes 23 of the outer peripheral region 18 located around the gate pad region 65. This suppresses conductivity modulation in the gate pad region 65, and in subsequent turn-off switching, current concentration in the outer peripheral region 18 is suppressed, thereby improving the breakdown withstand capability of the semiconductor device 600.

[0127] This further improves the breakdown withstand capability due to current concentration in the outer peripheral region 18 during turn-off switching, thereby achieving a higher turn-off interruption withstand capability.

[0128] Although Figure 23 shows a single gate pad region 65, in reality there are two gate pad regions 65, one for the switching gate (Gs) wiring 14 and one for the carrier control gate (Gc) wiring 13, and this configuration is applied to both of these gate pad regions 65.

[0129] Furthermore, although the switching gate (Gs) wiring 14 and carrier control gate (Gc) wiring 13 are shown to traverse only the outer region 18 and the central region 17, they may also be wired on the termination region 19 for the purpose of reducing wiring resistance or facilitating power supply.

[0130] Furthermore, although the gate pad region 65 is located adjacent to the terminal region 19, the outer peripheral region 18 may be located between the terminal region 19 and the gate pad region 65.

[0131] Furthermore, this embodiment can be applied to the planar layouts shown in Examples 1 to 3. In addition, by applying the carrier lifetime reduction layer 64 and the low-concentration p-type collector layer 69 shown in Example 4 to the gate pad region 65, an improvement in turn-off blocking tolerance can be obtained. [Examples]

[0132] Referring to Figure 24, an insulated gate type (gate-controlled type) semiconductor device 700 according to Embodiment 7 of the present invention will be described. Figure 24 is a cross-sectional view of the semiconductor device 700 of this embodiment.

[0133] As shown in Figure 24, in the semiconductor device 700 of this embodiment, the gate electrode has a side gate shape characterized in that one side is in contact with a p-type well layer (emitter well layer) 25 via a gate insulating film 29, and the other side is in contact with an insulating film (thick oxide film 16) without the presence of a p-type well layer (emitter well layer) 25 or an n-drift layer 20.

[0134] In the trench gate shapes described in Examples 1 to 6, in addition to the MOS capacitance formed by the gate electrode, gate insulating film 29, and n-type drift layer 20 at the bottom of the trench gate, a MOS capacitance formed by the p-type floating layer (or n-type drift layer) 15, gate insulating film 29, and gate electrode, which is located on the side opposite to the side facing the p-type well layer 25, is arranged in parallel.

[0135] As a result, in trench gate type IGBTs, the MOS capacitance acts as a feedback capacitance, and its value is large. When the IGBT turns off or turns on, a Miller period occurs in which this capacitance is charged, hindering rapid current and voltage changes and increasing losses.

[0136] On the other hand, in the side gate shape of this embodiment, a thick insulating film 16 is placed on the side opposite to the side facing the p-type well layer 25 (i.e., the other side), and there is no capacitive component. Therefore, the feedback capacitance is formed only by the MOS capacitance formed by the gate electrode, gate insulating film 29 and n-type drift layer 20 at the bottom of the side gate, and its capacitance value is smaller than that of the trench gate type.

[0137] Therefore, compared to trench gate type IGBTs, the current and voltage change faster during switching, resulting in lower switching losses. Consequently, even when the present invention is applied to a side-gate IGBT, similar to Example 1, it becomes possible to achieve both the low-loss performance that is an effect of the present invention and a higher turn-off interruption withstand capability by suppressing power generation during switching in the outer peripheral region 18. In other words, a double-gate type IGBT that achieves both low loss and high output can be realized.

[0138] Furthermore, the p-type layer 70 located at the boundary between the outer peripheral region 18 and the terminal region 19, as shown in Figure 24, acts as a resistor to the hole carriers 52 during turn-off switching, and is provided as a region to reduce the current concentrated in the outer peripheral region 18.

[0139] According to this embodiment, the hole concentration in the outer peripheral region 18 and the terminal region 19 can be reduced during the low conductivity period 47, thereby reducing the current in the outer peripheral region 18 and the terminal region 19, and shortening the length 71 of the p-type layer 70. In other words, by applying the present invention, the overall area of ​​the semiconductor device consisting of the central region 17, the outer peripheral region 18, and the terminal region 19 can be reduced, resulting in miniaturization.

[0140] Furthermore, the present invention can be applied to semiconductor devices, semiconductor circuit drive devices, and power conversion devices that are suitable for a wide range of applications, from low-power devices such as air conditioners and microwave ovens to high-power devices such as inverters in automobiles, railways, and steel mills.

[0141] Furthermore, the present invention is not limited to the embodiments described above, and various modifications are included. For example, the embodiments described above are described in detail to make the present invention easier to understand, and are not necessarily limited to those having all the configurations described. Also, it is possible to replace parts of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add configurations from other embodiments to the configuration of one embodiment. In addition, it is possible to add, delete, or replace parts of the configuration of each embodiment with other configurations. [Explanation of symbols]

[0142] 1…n-type drift layer 2…p-type well layer 3…n-type emitter layer 4…p-type collector layer 5…Gate insulating film (oxide film) 6...p-type high concentration layer 7…Emitter electrode 8...Collector electrode 9…Floating electrode 10…Carrier control gate (Gc) 11…Switching gate (Gs) 12...p-type feed layer 13…Carrier control gate (Gc) wiring 14…Switching gate (Gs) wiring 15...p-type floating layer or n-type drift layer 16…Thick insulating film 17…Central region (cell) 18…Outer region (cell) 19…Terminal area 20...n-type drift layer 23…Carrier-controlled gate (Gc) electrode 24…Switching gate (Gs) electrode 25... p-type well layer 26...p-type collector layer 27...p-type feed layer 28...n-type emitter layer 29…Gate insulating film (gate oxide film) 30...Power loss of the double-gate IGBT of the present invention 31…Power loss of conventional double-gate IGBTs 32...Cells located at the boundary with terminal region 19 33... Low ON-voltage IGBTs 34… High ON-voltage IGBTs 35...Gate of IGBT33 with low on-voltage 36…Gate of high ON-voltage IGBT34 38...Gate control circuit 39… Contact layer 40…Emitter electrode 41...Collector electrode 42...Dummy gate area 44... Gate Driver 45... Gate Driver 46…High conductivity period 47…Low conductivity period 48…Continuity period 49… Non-conductive period 50... Turn-off switching 51…Electron carriers 52… The career of a positive hole 53... Conductivity Modulation 54…Temporarily low concentration of accumulated carrier profile 55…Temporarily low concentration of accumulated carrier profile 56…High concentration of accumulated carriers 57... Turn-off switching waveform of a conventional double-gate IGBT 58...Turn-off switching waveform of the double-gate IGBT of the present invention 59…Turn-off interruption capacity of conventional double-gate IGBTs 60...Turn-off interruption tolerance of the double-gate type IGBT of the present invention 61…Performance of conventional IGBTs consisting of one type of gate 62…Performance of conventional double-gate IGBTs 63…Performance of the double-gate type IGBT of the present invention 64…Career Lifetime Reduction Group 65... Gate pad area 69... Low-concentration p-type collector layer 70... p-type layer at the boundary between the outer and terminal regions 71... Length of the p-type layer at the boundary between the outer region and the terminal region 91...Insulated gate electrode (Gs) 92...Insulating gate electrode (Gc) 93...Control circuit 94…Drive circuit 95...Inductive load 96…DC power supply 97…IGBT 98...Insulated gate terminal 99... Diode 100... Semiconductor equipment (double-gate IGBT) 200... Semiconductor equipment (double-gate IGBT) 300... Semiconductor equipment (double-gate IGBT) 400... Semiconductor equipment (double-gate IGBT) 401... Semiconductor equipment (double-gate IGBT) 500... Semiconductor equipment (double-gate IGBT) 600... Semiconductor equipment (double-gate IGBT) 700... Semiconductor equipment (double-gate IGBT) 1000... Conventional semiconductor equipment (IGBT) I / V…Current / Voltage I C ...Collector current V CE ...collector-emitter voltage GP…Generated power STD…Turn-off interruption capacity V...Voltage MRV…Maximum Rated Voltage RU… Usage range SL…Switching Loss ACC...Accumulated carrier concentration during high conductivity period

Claims

1. In a semiconductor device having a switching gate and a carrier control gate that are driven independently of each other, When the semiconductor device is viewed in plan view, it comprises a central region cell, an outer region cell surrounding the entire circumference of the central region cell, and an end region surrounding the entire circumference of the outer region cell. The central region cell has a switching element having the switching gate and the carrier control gate, The outer peripheral region cell is positioned between the central region cell and the terminal region. The gate of the switching element in the outer peripheral region cell consists only of the carrier control gate. The switching element of the central region cell has an emitter layer and a well layer disposed between the switching gate and the carrier control gate. The switching element of the outer peripheral region cell comprises the carrier control gate, an emitter layer, and a well layer. A semiconductor device characterized in that the spacing between the well layers in the outer peripheral region cell is narrower than the spacing between the well layers in the central region cell.

2. In the semiconductor device described in claim 1, A first state in which a voltage is applied to the switching gate and the carrier control gate such that an inversion layer is formed on the switching elements, A second state in which a voltage is applied to the switching gate such that an inversion layer is formed on the switching element, and a voltage is applied to the carrier control gate such that an accumulation layer is formed on the switching element, The switching gate and the carrier control gate are in a third state in which a voltage is applied such that a storage layer is formed on the switching element. A semiconductor device characterized in that, when the semiconductor device transitions from a conductive state to a non-conductive state, it transitions in the order of the first state, the second state, and the third state.

3. In the semiconductor device described in claim 1, A semiconductor device characterized in that, when viewed in plan view, the proportion of the area in the outer peripheral region cell where the emitter layer is located via a gate insulating film relative to the carrier control gate is smaller than the proportion of the area in the central region cell where the emitter layer is located via a gate insulating film relative to the switching gate.

4. In the semiconductor device described in claim 1, The central region cell, the outer region cell, and the terminal region have a common drift layer. A semiconductor device characterized by having a carrier lifetime killer layer in the outer peripheral region cell and the drift layer in the terminal region.

5. In the semiconductor device described in claim 1, The central region cell, the outer region cell, and the terminal region have a common drift layer. The central region cell has a first carrier injection layer for injecting carriers into the drift layer, The cell comprises the outer peripheral region and a second carrier injection layer for injecting carriers into the drift layer of the terminal region. A semiconductor device characterized in that the impurity concentration of the second carrier injection layer is lower than the impurity concentration of the first carrier injection layer.

6. In the semiconductor device described in claim 1, A semiconductor device characterized by comprising the outer peripheral region cell and the gate pad region adjacent to the terminal region.

7. In the semiconductor device described in claim 1, A semiconductor device characterized in that the switching gate and the carrier control gate are trench gate shape or side gate shape.

8. In the semiconductor device described in claim 1, When the semiconductor device is viewed in plan view, the switching gate extends to the outer peripheral region cell as well. A semiconductor device characterized in that the switching gate in the outer peripheral region cell is a dummy gate in which an emitter layer is not provided via a gate insulating film.

9. A power conversion device using a semiconductor device according to any one of claims 1 to 8.

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