Semiconductor device and method for manufacturing a semiconductor device

Abstract

To provide a semiconductor device capable of improving an adhesion between a Ni plating film and a passivation layer, and provide a manufacturing method of the semiconductor device.SOLUTION: A semiconductor device includes: a substrate having a first main surface; a first metal layer provided above the first main surface; a passivation layer covering the first metal layer; and a second metal layer. The passivation layer is provided with an opening where a part of the first metal layer is exposed, and the second metal layer includes: an Al or an Al alloy film covering an inner wall surface of the opening; and a Ni plating film that is in contact with the Al or the Al alloy film, and is provided above the first metal layer in an inner side of the opening.SELECTED DRAWING: Figure 1

Description

Technical Field

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[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background Art

[0002] A semiconductor device is known in which an opening is formed in an aluminum film, a passivation layer is formed, and a Ni plating film is formed on the aluminum film inside the opening.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Improvement in adhesion between the Ni plating film and the passivation layer is desired.

[0005] An object of the present disclosure is to provide a semiconductor device and a method for manufacturing the semiconductor device capable of improving the adhesion between the Ni plating film and the passivation layer.

Means for Solving the Problems

[0006] The semiconductor device of the present disclosure includes a substrate having a first main surface, a first metal layer provided above the first main surface, a passivation layer covering the first metal layer, and a second metal layer. An opening through which a part of the first metal layer is exposed is provided in the passivation layer. The second metal layer includes an Al or Al alloy film covering an inner wall surface of the opening, and a Ni plating film that is in contact with the Al or Al alloy film and is provided above the first metal layer inside the opening.

Effects of the Invention

[0007] According to this disclosure, the adhesion between the Ni plating film and the passivation layer can be improved. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a cross-sectional view showing the configuration of a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a cross-sectional view (part 1) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 3] Figure 3 is a cross-sectional view (part 2) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 4] Figure 4 is a cross-sectional view (part 3) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] Figure 5 is a cross-sectional view (part 4) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] Figure 6 is a cross-sectional view (part 5) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 7] Figure 7 is a cross-sectional view (part 6) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] Figure 8 is a cross-sectional view (part 7) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] Figure 9 is a cross-sectional view (part 8) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 10] Figure 10 is a cross-sectional view (part 9) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 11] Figure 11 is a cross-sectional view (part 10) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 12] Figure 12 is a cross-sectional view (part 11) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 13] Figure 13 is a cross-sectional view (part 12) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 14] Figure 14 is a cross-sectional view showing the configuration of a semiconductor device according to the second embodiment. [Modes for carrying out the invention]

[0009] The implementation methods are described below.

[0010] [Description of Embodiments in this Disclosure] The embodiments of this disclosure are listed and described below. In the following description, the same or corresponding elements are denoted by the same reference numeral, and the same description is not repeated. In the crystallographic descriptions in this specification, individual orientations are indicated by [], collective orientations by <>, individual planes by () and collective planes by {}. Also, while negative crystallographic exponents are usually indicated by placing a "-" (bar) above the number, in this disclosure a negative sign is placed before the number. Also, the following description uses the XYZ Cartesian coordinate system, but this coordinate system is defined for illustrative purposes and is not limited to the orientation of the semiconductor device. Also, the XY plane view is called a plan view, and from any point, the +Z direction may be called up, upper side, or up, and the -Z direction may be called down, lower side, or down.

[0011] [1] A semiconductor device according to one aspect of the present disclosure includes a substrate having a first main surface, a first metal layer provided above the first main surface, a passivation layer covering the first metal layer, and a second metal layer, wherein the passivation layer is provided with an opening through which a part of the first metal layer is exposed, and the second metal layer includes an Al or Al alloy film covering the inner wall surface of the opening and a Ni plating film in contact with the Al or Al alloy film and provided above the first metal layer on the inside of the opening.

[0012] An Al or Al alloy film covers the inner wall surface of the opening, and the Ni plating film contacts the Al or Al alloy film and is provided above the first metal layer inside the opening. The adhesion between the Ni plating film and the Al or Al alloy film and the adhesion between the Al or Al alloy film and the passivation layer are higher than the adhesion between the Ni plating film and the passivation layer when the Ni plating film and the passivation layer are in direct contact. Therefore, excellent adhesion can be obtained between the Ni plating film and the passivation layer through the Al or Al alloy film.

[0013] 〔2〕 In 〔1〕, the thickness of the Al or Al alloy film may be 10 nm or more. In this case, it is easy to obtain excellent adhesion between the Ni plating film and the passivation layer through the Al or Al alloy film.

[0014] 〔3〕 In 〔1〕 or 〔2〕, the angle formed by the inner wall surface and the first main surface may be 15° or more and 90° or less. In this case, it is easy to form an Al or Al alloy film so as to cover the inner wall surface of the opening.

[0015] 〔4〕 In 〔1〕~〔3〕, it may have a Au plating film or an Ag plating film provided above the Ni plating film. In this case, it is easy to obtain excellent corrosion resistance for the second metal layer. [[ID=I4]]

[0016] 〔5〕 In 〔4〕, it may have a Pd plating film provided between the Ni plating film and the Au plating film or the Ag plating film. In this case, it is easy to obtain excellent adhesion between the Ni plating film and the Au plating film or the Ag plating film.

[0017] 〔6〕 In 〔1〕~〔5〕, the passivation layer may include at least one selected from the group consisting of a polyimide layer, a silicon nitride layer, and a silicon oxide layer. In this case, it is easy to obtain excellent insulation.

[0018] 〔7〕 In 〔1〕~〔6〕, the substrate may be a silicon carbide substrate. In this case, it is easy to obtain excellent pressure resistance.

[0019] [8] A method for manufacturing a semiconductor device according to one aspect of the present disclosure includes: a substrate having a first main surface; a step of forming a first metal layer on the first main surface; a step of forming a passivation layer covering the first metal layer; a step of forming an opening in the passivation layer in which a part of the first metal layer is exposed; a step of forming an Al or Al alloy film covering the inner wall surface of the opening; and a step of forming a Ni plating film in contact with the Al or Al alloy film on the inside of the opening and on the first metal layer.

[0020] An Al or Al alloy film is formed covering the inner wall surface of the opening, and a Ni plating film is formed on the inside of the opening above the first metal layer, in contact with the Al or Al alloy film. Therefore, excellent adhesion can be obtained between the Ni plating film and the passivation layer via the Al or Al alloy film.

[0021] [9] In [8], the Al or Al alloy film may be formed by sputtering. In this case, particularly excellent adhesion between the Al or Al alloy film and the passivation layer can be easily obtained.

[0022] (First Embodiment) A first embodiment will now be described. The first embodiment relates to a so-called vertical MOS-type field-effect transistor (FET) using silicon carbide, and this MOS-type FET is an example of a semiconductor device. Figure 1 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment.

[0023] As shown in Figure 1, the semiconductor device 100 according to the first embodiment mainly comprises a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, a drain electrode 70, a passivation layer 20, an aluminum (Al) film 31, and a plating film 35.

[0024] The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The first main surface 1 and the second main surface 2 are parallel to the XY plane, and the first main surface 1 is in the +Z direction when viewed from the second main surface 2. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are made of, for example, polytype 4H hexagonal silicon carbide. The silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen (N) and has an n-type conductivity type (first conductivity type).

[0025] The first main surface 1 is the {0001} surface or a surface inclined by an off-angle of 8° or less in the off-direction. Preferably, the first main surface 1 is the (000-1) surface or a surface inclined by an off-angle of 8° or less in the off-direction. The off-direction may be, for example, the <11-20> direction or the <1-100> direction. The off-angle may be, for example, 1° or more or 2° or more. The off-angle may be 6° or less or 4° or less.

[0026] The silicon carbide epitaxial layer 40 mainly comprises a drift region 11, a body region 12, a source region 13, and a contact region 18.

[0027] The drift region 11 contains n-type impurities such as nitrogen or phosphorus (P), and has an n-type conductivity.

[0028] The body region 12 contains p-type impurities such as aluminum and has a p-type conductivity. The body region 12 is located on top of the drift region 11.

[0029] The source region 13 contains n-type impurities such as nitrogen or phosphorus and has an n-type conductivity. The source region 13 is located on top of the body region 12. The source region 13 is separated from the drift region 11 by the body region 12. The source region 13 constitutes the first main surface 1.

[0030] The contact region 18 contains p-type impurities such as aluminum and has a p-type conductivity. The contact region 18 penetrates the source region 13 and contacts the body region 12. The contact region 18 constitutes the first main surface 1.

[0031] A gate trench 5 is provided on the first principal surface 1, defined by a side surface 3 and a bottom surface 4. The gate trench 5 extends, for example, along the Y-axis. Multiple gate trenches 5 are aligned along the X-axis. Side surface 3 penetrates the source region 13, the body region 12, and a portion of the drift region 11, reaching the drift region 11. The bottom surface 4 is continuous with side surface 3. The bottom surface 4 is located in the drift region 11. For example, the bottom surface 4 is parallel to the first principal surface 1 and the second principal surface 2. The angle θ1 of side surface 3 with respect to the plane containing the bottom surface 4 is, for example, 45° or more and 65° or less. The angle θ1 may be, for example, 50° or more. The angle θ1 may be, for example, 60° or less. Side surface 3 preferably has a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent mobility.

[0032] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is composed of a material containing, for example, silicon dioxide. The gate insulating film 81 is in contact with the side surface 3 and the bottom surface 4. The gate insulating film 81 is in contact with the drift region 11 at the bottom surface 4. The gate insulating film 81 is in contact with the source region 13, the body region 12 and the drift region 11 at the side surface 3. The gate insulating film 81 may also be in contact with the source region 13 at the first main surface 1.

[0033] The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is made of, for example, polysilicon (polySi) containing conductive impurities. The gate electrode 82 is located inside the gate trench 5. A portion of the gate electrode 82 may be located on the first main surface 1.

[0034] The interlayer insulating film 83 covers the gate electrode 82. The interlayer insulating film 83 is in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is, for example, an oxide film. The interlayer insulating film 83 is composed of a material containing, for example, silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 and the source electrode 60 from each other. A portion of the interlayer insulating film 83 may be provided inside the gate trench 5.

[0035] A barrier metal film 84 is provided to cover the upper and side surfaces of the interlayer insulating film 83 and the side surfaces of the gate insulating film 81. The barrier metal film 84 is in contact with the interlayer insulating film 83 and the gate insulating film 81. The barrier metal film 84 is made of a material containing, for example, titanium nitride (TiN).

[0036] Contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81. The source region 13 is exposed from the interlayer insulating film 83 and the gate insulating film 81 through the contact holes 90.

[0037] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 has a contact electrode 61 provided in the contact hole 90 and a source wiring 62. The contact electrode 61 is in contact with the source region 13 and the contact region 18 on the first main surface 1. The contact electrode 61 is made of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be made of a material containing titanium (Ti), aluminum, and silicon. The contact electrode 61 is ohmic bonded to the source region 13 and the contact region 18. The source wiring 62 covers the upper and side surfaces of the interlayer insulating film 83 and the upper surface of the contact electrode 61. The source wiring 62 is in contact with the barrier metal film 84 and the contact electrode 61. The source wiring 62 is made of a material containing, for example, aluminum or copper. The source wiring 62 may be made of a material containing aluminum and copper. For example, the source wiring 62 is an aluminum film or an aluminum alloy film. The source wiring 62 is an example of the first metal layer.

[0038] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 on the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is made of a material containing, for example, nickel silicide. The drain electrode 70 may be made of a material containing titanium, aluminum, and silicon. The drain electrode 70 is ohmic bonded to the silicon carbide single crystal substrate 50.

[0039] A passivation layer 20 is formed on the source wiring 62. The passivation layer 20 covers the source wiring 62. The passivation layer 20 is provided with an opening 21 through which a portion of the source wiring 62 is exposed. The passivation layer 20 is, for example, a polyimide layer.

[0040] The semiconductor device 100 has a second metal layer 30. The second metal layer 30 has an Al film 31 and a plating film 35.

[0041] The Al film 31 is provided on the inner wall surface 22 of the opening 21 and on the upper surface of the source wiring 62 exposed from the opening 21. The Al film 31 includes a portion that covers the inner wall surface 22 of the opening 21 and a portion that covers the upper surface of the source wiring 62 exposed from the opening 21. The thickness of the Al film 31 is, for example, 10 nm or more. The thickness of the Al film 31 is the thickness in the direction perpendicular to the inner wall surface 22 of the opening 21 in the portion that covers the inner wall surface 22 of the opening 21, and the thickness in the direction perpendicular to the upper surface of the source wiring 62 in the portion that covers the upper surface of the source wiring 62 exposed from the opening 21. The angle θ2 between the inner wall surface 22 and the first main surface 1 is 90°. The inner wall surface 22 does not have to be a plane. If the inner wall surface 22 is not a plane, the angle θ2 between the inner wall surface 22 and the first main surface 1 is the angle between the first main surface 1 and a plane that is in contact with the inner wall surface 22 at a position within the inner wall surface 22, at a distance of half the average thickness of the passivation layer 20 above the upper surface of the source wiring 62.

[0042] The plating film 35 comprises a nickel (Ni) plating film 32, a palladium (Pd) plating film 33, and a gold (Au) plating film 34. The Ni plating film 32 is in contact with the Al film 31 and is provided above the source wiring 62. Most of the Ni plating film 32 is inside the opening 21. The Ni plating film 32 is provided inside the opening 21 and above the source wiring 62. A portion of the Ni plating film 32 may be in contact with the Al film 31 and a portion of the upper surface of the passivation layer 20. The Ni plating film 32 may contain phosphorus. The Pd plating film 33 is provided on top of the Ni plating film 32. The Au plating film 34 is provided on top of the Pd plating film 33.

[0043] Next, a method for manufacturing the semiconductor device 100 according to the first embodiment will be described. Figures 2 to 13 are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment.

[0044] First, a silicon carbide single crystal substrate 50 is prepared as shown in Figure 3. Next, a silicon carbide epitaxial layer 40 is formed on the silicon carbide single crystal substrate 50. For example, the silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen and has an n-type conductivity. For example, the silicon carbide epitaxial layer 40 can be formed by epitaxial growth with the addition of n-type impurities such as nitrogen. In this way, a silicon carbide substrate 10 having a first main surface 1 and a second main surface 2 is obtained.

[0045] Next, as shown in Figure 3, ion implantation is performed into the silicon carbide epitaxial layer 40 to form a body region 12, a source region 13, and a contact region 18. The remaining portion of the silicon carbide epitaxial layer 40 becomes the drift region 11. In the ion implantation to form the body region 12 or the contact region 18, p-type impurities such as aluminum are implanted. In the ion implantation to form the source region 13, n-type impurities such as phosphorus are implanted.

[0046] Next, as shown in Figure 4, multiple gate trenches 5 are formed in the source region 13, the body region 12, and the drift region 11. The gate trenches 5 can be formed as follows.

[0047] First, a mask (not shown) having an opening is formed over the region where the gate trench 5 is to be formed. Next, using the mask, a portion of the source region 13, a portion of the body region 12, and a portion of the drift region 11 are removed by etching. The etching is, for example, reactive ion etching (RIE). By etching, a recess is formed in the region where the gate trench 5 is to be formed, having a side portion that is substantially perpendicular to the first main surface 1, and a bottom portion that is continuously provided with the side portion and substantially parallel to the first main surface 1.

[0048] Next, thermal etching is performed in the recesses. Thermal etching can be performed by heating in an atmosphere containing a reactive gas having at least one type of halogen atom, with a mask formed on the first main surface 1. The at least one type of halogen atom includes at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere may include, for example, chlorine (Cl2), boron trichloride (BCl3), sulfur hexafluoride (SF6), or carbon tetrafluoride (CF4). For example, a mixed gas of chlorine gas and oxygen (O2) gas is used as the reaction gas, and thermal etching is performed at a heat treatment temperature of 800°C to 900°C. In addition to the chlorine gas and oxygen gas mentioned above, the reaction gas may also contain a carrier gas. Examples of carrier gases include nitrogen (N2), argon (Ar), or helium (He).

[0049] The above thermal etching process forms a gate trench 5 on the first main surface 1. The gate trench 5 has a bottom surface 4 consisting of a drift region 11 and a side surface 3 that penetrates the source region 13 and the body region 12 and connects to the bottom surface 4. After thermal etching, the mask is removed from the first main surface 1.

[0050] Next, as shown in Figure 5, a gate insulating film 81 is formed. For example, by thermal oxidation of the silicon carbide substrate 10, a gate insulating film 81 is formed that is in contact with the source region 13, the body region 12, the drift region 11, and the contact region 18. Specifically, the silicon carbide substrate 10 is heated in an oxygen-containing atmosphere at a temperature of, for example, 1300°C to 1400°C. This forms a gate insulating film 81 that is in contact with the first main surface 1, the side surface 3, and the bottom surface 4. When the gate insulating film 81 is formed by thermal oxidation, strictly speaking, a part of the silicon carbide substrate 10 is incorporated into the gate insulating film 81. Therefore, in the subsequent processing, it is assumed that the first main surface 1, the side surface 3, and the bottom surface 4 have moved slightly to the interface between the thermally oxidized gate insulating film 81 and the silicon carbide substrate 10.

[0051] Next, the silicon carbide substrate 10 may be subjected to heat treatment (NO annealing) in a nitric oxide (NO) gas atmosphere. In NO annealing, the silicon carbide substrate 10 is held for about 1 hour under conditions of, for example, 1100°C to 1400°C. This introduces nitrogen atoms into the interface region between the gate insulating film 81 and the body region 12. As a result, the formation of interface states in the interface region is suppressed, thereby improving channel mobility.

[0052] Next, as shown in Figure 6, the gate electrode 82 is formed. The gate electrode 82 is formed on the gate insulating film 81. The gate electrode 82 is formed, for example, by a low-pressure chemical vapor deposition (LP-CVD) method. The gate electrode 82 is formed to face the source region 13, the body region 12, and the drift region 11, respectively.

[0053] Next, an interlayer insulating film 83 is formed. Specifically, the interlayer insulating film 83 is formed to cover the gate electrode 82 and to be in contact with the gate insulating film 81. The interlayer insulating film 83 is formed, for example, by a CVD method. The interlayer insulating film 83 is composed of a material containing, for example, silicon dioxide. A portion of the interlayer insulating film 83 may be formed inside the gate trench 5.

[0054] Next, as shown in Figure 7, the interlayer insulating film 83 and the gate insulating film 81 are etched to form contact holes 90 in the interlayer insulating film 83 and the gate insulating film 81. As a result, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81. Next, a metal film (not shown) for the contact electrode 61, which is in contact with the source region 13 and the contact region 18, is formed on the first main surface 1. The metal film for the contact electrode 61 is formed, for example, by sputtering. The metal film for the contact electrode 61 is made of a material containing nickel, for example. Next, alloying annealing is performed. The metal film for the contact electrode 61 is held at a temperature of, for example, 900°C to 1100°C for about 5 minutes. As a result, at least a portion of the metal film for the contact electrode 61 reacts with the silicon contained in the silicon carbide substrate 10 and silicides. This forms a contact electrode 61 that ohmic-bonds with the source region 13 and the contact region 18. The contact electrode 61 may be made of a material containing titanium, aluminum, and silicon.

[0055] Next, as shown in Figure 8, the source wiring 62 is formed. Specifically, the source wiring 62 is formed to cover the contact electrode 61 and the interlayer insulating film 83. The source wiring 62 is formed, for example, by sputtering. The source wiring 62 is made of a material containing, for example, aluminum or copper. The source wiring 62 may be made of a material containing aluminum and copper. For example, the source wiring 62 is an aluminum film or an aluminum alloy film. In this way, a source electrode 60 having the contact electrode 61 and the source wiring 62 is formed.

[0056] Next, a passivation layer 20 is formed to cover the source wiring 62, as shown in Figure 9. The passivation layer includes, for example, at least one selected from the group consisting of a polyimide layer, a silicon nitride layer, and a silicon oxide layer. Next, an opening 21 is formed in the passivation layer 20, in which a portion of the source wiring 62 is exposed. For example, if the polyimide layer is photosensitive, the opening can be formed by exposure and development. For example, the opening may be formed in the polyimide layer, silicon nitride layer, or silicon oxide layer by etching.

[0057] Next, as shown in Figure 10, an Al film 38 is formed on the upper surface of the passivation layer 20, on the inner wall surface 22 of the opening 21, and on the upper surface of the source wiring 62 exposed from the opening 21. The thickness of the Al film 38 is, for example, 10 nm or more. The Al film 38 is formed, for example, by sputtering.

[0058] Next, as shown in Figure 11, a mask 39 is formed that covers the upper portion of the Al film 38 that is exposed on the upper surface of the source wiring 62 through the opening 21.

[0059] Next, as shown in Figure 12, the Al film 38 is etched using the mask 39. The etching is, for example, driver etching or wet etching. As a result, the portion of the Al film 38 above the top surface of the passivation layer 20 is removed. Next, the mask 39 is removed. In this way, an Al film 31 is obtained from the Al film 38. The thickness of the Al film 31 is, for example, 10 nm or more.

[0060] Next, as shown in Figure 13, a plating film 35 is formed on the Al film 31. In forming the plating film 35, a phosphorus-containing Ni plating film 32 is formed on the Al film 31, a Pd plating film 33 is formed on the Ni plating film 32, and an Au plating film 34 is formed on the Pd plating film 33. The Ni plating film 32, Pd plating film 33, and Au plating film 34 can be formed, for example, by electroless plating. In addition, a drain electrode 70 that is in contact with the silicon carbide single crystal substrate 50 is formed on the second main surface 2.

[0061] In this way, a semiconductor device 100 including a field-effect transistor can be manufactured.

[0062] In the semiconductor device 100 according to the first embodiment, the Al film 31 covers the inner wall surface 22 of the opening 21, and the Ni plating film 32 is in contact with the Al film 31 and is provided inside the opening 21 above the source wiring 62. The Al film 31 is located between the Ni plating film 32 and the passivation layer 20. The adhesion between the Ni plating film 32 and the Al film 31 and the adhesion between the Al film 31 and the passivation layer 20 is higher than the adhesion between the Ni plating film 32 and the passivation layer 20 when the Ni plating film 32 and the passivation layer 20 are in direct contact. Therefore, according to the first embodiment, excellent adhesion can be obtained between the Ni plating film 32 and the passivation layer 20 via the Al film 31. When the Al film 31 is formed by sputtering, particularly excellent adhesion can be obtained between the Al film 31 and the passivation layer 20. An Al alloy film may be used instead of the Al film 31. An Al alloy film is, for example, an Al-Cu alloy film.

[0063] Having an Al film thickness of 10 nm or more makes it easier to obtain excellent adhesion between the Ni plating film 32 and the passivation layer 20 via the Al film 31. The thickness of the Al film 31 is preferably 15 nm or more, and more preferably 20 nm or more. The thickness of the Al film 31 may be 30 nm or less.

[0064] The presence of the Au plating film 34 in the plating film 35 provides excellent corrosion resistance and superior long-term reliability. Furthermore, the presence of the Pd plating film 33 between the Ni plating film 32 and the Au plating film 34 in the plating film 35 provides excellent adhesion between the Ni plating film 32 and the Au plating film 34. An Ag plating film may be used instead of the Au plating film 34.

[0065] The passivation layer 20 may be a silicon nitride layer or a silicon oxide layer. Excellent insulation properties can be obtained if the passivation layer 20 includes at least one selected from the group consisting of a polyimide layer, a silicon nitride layer, and a silicon oxide layer.

[0066] Excellent voltage resistance can be obtained by using the silicon carbide substrate 10.

[0067] (Second Embodiment) A second embodiment will now be described. The second embodiment differs from the first embodiment mainly in the shape of the opening 21 of the passivation layer 20. Figure 14 is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment.

[0068] As shown in Figure 14, in the semiconductor device 200 according to the second embodiment, the angle θ2 between the inner wall surface 22 and the first main surface 1 is less than 90°. The angle θ2 is, for example, 15° or more and less than 90°. As in the first embodiment, the inner wall surface 22 does not have to be a plane. If the inner wall surface 22 is not a plane, the angle θ2 between the inner wall surface 22 and the first main surface 1 is the angle between the first main surface 1 and a plane that is in contact with the inner wall surface 22 at a position within the inner wall surface 22, at a distance of 1 / 2 the average thickness of the passivation layer 20 above the upper surface of the source wiring 62.

[0069] The other components are the same as those of the first embodiment.

[0070] The same effects as the first embodiment can be obtained with the second embodiment. Furthermore, with the second embodiment, it is easier to form the Al film 31 so as to cover the inner wall surface 22 of the opening 21.

[0071] In this disclosure, the angle θ2 is, for example, 15° to 90°, preferably 20° to 90°, more preferably 30° to 90°, and even more preferably 45° to 90°. Even if the angle θ2 is 90°, the Al film 31 is easily formed to cover the inner wall surface 22 of the opening 21.

[0072] Although embodiments have been described in detail above, the invention is not limited to any particular embodiment, and various modifications and changes are possible within the scope described in the claims. [Explanation of symbols]

[0073] 1. First main surface 2. Second main surface 3 Sides 4. Bottom 5 Gate Trench 10 Silicon carbide substrate 11. Drift Region 12 Body Region 13 Source Area 18 Contact Area 20 Passivation Layer 21 Opening 22 Interior wall surface 30 Second metal layer 31, 38 Al film 32 Ni plating film 33 Pd plated film 34 Au plating film 35 Plating film 39 masks 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 source electrodes 61 Contact electrodes 62 Source Wiring 70 Drain electrode 81 Gate Insulator 82 Grid gate 83 Interlayer insulating film 84 Barrier metal film 90 Contact Holes 100, 200 semiconductor equipment θ1, θ2 angle

Claims

1. A substrate having a first main surface, A first metal layer provided above the first main surface, A passivation layer covering the first metal layer, The second metal layer, It has, The first metal layer is a source wiring containing aluminum, The passivation layer is provided with an opening through which a portion of the first metal layer is exposed. The aforementioned second metal layer is An Al or Al alloy film covering the inner wall surface of the opening, A Ni plating film is provided in contact with the Al or Al alloy film and on the inside of the opening above the first metal layer, It has, A semiconductor device having a thickness of 10 nm or more (excluding 2 μm or more) of the Al or Al alloy film.

2. The semiconductor device according to claim 1, wherein the thickness of the Al or Al alloy film is 10 nm or more and 30 nm or less.

3. The substrate has a second main surface opposite to the first main surface, The second main surface has a third metal layer, The semiconductor device according to claim 1 or claim 2, wherein an electric current flows between the second metal layer and the third metal layer through the substrate.

4. The semiconductor device according to claim 1 or claim 2, wherein the upper surface of the passivation layer is not covered with the Al or Al alloy film.

5. The semiconductor device according to claim 1 or claim 2, wherein the angle between the inner wall surface and the first main surface is 15° or more and 90° or less.

6. The semiconductor device according to claim 1 or claim 2, having an Au plating film or an Ag plating film provided above the Ni plating film.

7. The semiconductor device according to claim 6, further comprising a Pd plating film provided between the Ni plating film and the Au plating film or Ag plating film.

8. The semiconductor device according to claim 1 or claim 2, wherein the passivation layer comprises at least one selected from the group consisting of a polyimide layer, a silicon nitride layer, and a silicon oxide layer.

9. The semiconductor device according to claim 1 or claim 2, wherein the substrate is a silicon carbide substrate.

10. A step of forming a source wiring containing aluminum as a first metal layer above the first main surface of a substrate having a first main surface, A step of forming a passivation layer covering the first metal layer, The steps include forming an opening in the passivation layer in which a portion of the first metal layer is exposed, A step of forming an Al or Al alloy film that covers the inner wall surface of the opening, A step of forming a Ni plating film in contact with the Al or Al alloy film on the inside of the opening and above the first metal layer, It has, A method for manufacturing a semiconductor device, wherein the thickness of the Al or Al alloy film is 10 nm or more (excluding 2 μm or more).

11. The method for manufacturing a semiconductor device according to claim 10, wherein the Al or Al alloy film is formed by sputtering.

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