Semiconductor device and power conversion device using the same
The semiconductor device controls avalanche occurrence and suppresses carrier flow using a second body layer with an electric field concentration layer and floating layer, addressing latch-up issues and maintaining RBSOA in semiconductor devices.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- MINEBEA POWER SEMICON DEVICE INC
- Filing Date
- 2022-05-23
- Publication Date
- 2026-07-23
AI Technical Summary
Existing semiconductor devices fail to completely prevent latch-up of parasitic thyristors or npn parasitic transistors due to avalanche current flow into the region where the switching element body is located, leading to reduced RBSOA (Reverse Bias Safe Operating Area) tolerance.
The semiconductor device incorporates a second body layer with an electric field concentration layer and a floating layer or wide trench with a field plate, separating the first and second body layers to control avalanche occurrence and suppress carrier flow into the switching element body, thereby preventing latch-up and maintaining RBSOA.
The solution effectively prevents latch-up and maintains RBSOA by directing avalanches to a separate region, ensuring stable operation and preventing increased ON voltage.
Smart Images
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Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor device and a power conversion device using the same.
Background Art
[0002] With the increasing power density of power modules, switching elements such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are required to operate at higher current densities than before and have a wide RBSOA (Reverse Bias Safe Operating Area) tolerance.
[0003] For example, in FIG. 1 and paragraph 0029 of Patent Document 1, it is described that "by forming an n electric field concentration layer 115 having a higher carrier concentration than the n barrier layer 114 in the second region, current concentration occurs in the second region where the parasitic thyristor does not exist, and the current flowing through the first region where the parasitic thyristor exists decreases", and in paragraph 0024 of Patent Document 1, it is described that "by dispersing the current at turn-off, heat generation due to latch-up can be reduced, and an IGBT having a wide RBSOA can be provided".
Prior Art Documents
Patent Documents
[0004]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0005] However, in Patent Document 1, although the first and second regions are separated by a trench, they are adjacent to each other. Therefore, some of the avalanche current generated in the n-field concentration layer 115 flows into the first region (the region where the switching element body is located) where the parasitic thyristor exists, potentially causing the parasitic thyristor to latch up, resulting in the problem that latch-up prevention is not complete.
[0006] Furthermore, in the case of MOSFETs instead of IGBTs, the p-collector layer on the back becomes an n+ layer, so there are no pnpn parasitic thyristors in the region where the switching element itself is located. However, there are npn parasitic transistors in the region where the switching element itself is located, which leads to the problem that the npn parasitic transistors turn on when an avalanche current is generated.
[0007] The problem that the present invention aims to solve is to provide a semiconductor device and a power conversion device using the same that can control the location where an avalanche occurs by forming an electric field concentration layer, while suppressing the flow of carriers due to the avalanche into the region where the switching element body is located. [Means for solving the problem]
[0008] To solve the above-mentioned problems, the first semiconductor device of the present invention comprises, for example, a drift layer of a first conductivity type, a first body layer of a second conductivity type formed on the surface of the drift layer, a surface electrode layer of a first conductivity type formed on the surface of the first body layer, a surface main electrode connected to the first body layer and the surface electrode layer, a first trench formed in contact with the first body layer and the surface electrode layer, a gate electrode formed inside the first trench, and a gate insulating film formed inside the first trench between the first body layer and the gate electrode, and between the surface electrode layer and the gate electrode, wherein the drift The invention is characterized by comprising: a second body layer of a second conductivity type formed on the surface of the drift layer, without the surface electrode layer formed thereon, and connected to the surface main electrode; a second trench formed in contact with the second body layer; a dummy electrode formed inside the second trench and at the same potential as the surface main electrode; an insulating film formed inside the second trench between the second body layer and the dummy electrode; a first conductivity type field concentration layer formed at the bottom of the second body layer and having a higher impurity concentration than the drift layer; and a second conductivity type floating layer formed between the first trench and the second trench and electrically floating.
[0009] Furthermore, in order to solve the above-mentioned problems, the second semiconductor device of the present invention is, for example, a semiconductor device having a drift layer of a first conductivity type, a first body layer of a second conductivity type formed on the surface of the drift layer, a surface-side electrode layer of a first conductivity type formed on the surface of the first body layer, a surface-side main electrode connected to the first body layer and the surface-side electrode layer, a trench formed in contact with the first body layer and the surface-side electrode layer, a gate electrode formed on the side wall of the trench on the side of the first body layer, and a gate insulating film formed inside the trench between the first body layer and the gate electrode, and between the surface-side electrode layer and the gate electrode, wherein a surface-side electrode layer is formed on the surface of the drift layer in contact with the trench and on the side opposite to the first body layer, and the surface-side electrode layer is not formed. The present invention is characterized by comprising: a second body layer of a second conductivity type connected to the surface-side main electrode; a dummy electrode formed on the side wall of the second body layer inside the trench and at the same potential as the surface-side main electrode; a first insulating film formed inside the trench between the second body layer and the dummy electrode; a first conductivity type field concentration layer formed at the bottom of the second body layer and having a higher impurity concentration than the drift layer; a field plate formed inside the trench and at the same potential as the surface-side main electrode; a second insulating film formed inside the trench between the field plate and the drift layer; and a third insulating film formed inside the trench between the field plate and the gate electrode, and between the field plate and the dummy electrode.
[0010] Furthermore, the power conversion device of the present invention is characterized in that, for example, the first semiconductor device or the second semiconductor device of the present invention is used as a switching element. [Effects of the Invention]
[0011] According to the present invention, an avalanche is generated in a region of the second body layer by an electric field concentration layer, and a floating layer or a wide trench with a field plate formed inside is provided between the first body layer where the switching element body is located and the second body layer where the avalanche is generated. This separates the first body layer and the second body layer from each other, thereby suppressing the flow of carriers due to the avalanche into the first body layer where the switching element body is located. [Brief explanation of the drawing]
[0012] [Figure 1] A cross-sectional view illustrating the semiconductor device of Example 1. [Figure 2] A cross-sectional view illustrating the semiconductor device of Example 2. [Figure 3] A cross-sectional view illustrating the semiconductor device of Example 3. [Figure 4] A cross-sectional view illustrating the semiconductor device of Example 4. [Figure 5] A cross-sectional view illustrating the semiconductor device of Example 5. [Figure 6] A cross-sectional view illustrating the semiconductor device of Example 6. [Modes for carrying out the invention]
[0013] The embodiments of the present invention will be described below with reference to the drawings. In each figure and each embodiment, the same or similar components are denoted by the same reference numerals, and redundant explanations are omitted. [Examples]
[0014] Figure 1 is a cross-sectional view illustrating the semiconductor device of Example 1.
[0015] Figure 1 shows an example of application to a trench IGBT. However, it is not limited to IGBTs; it may also be applied to MOSFETs, as will be discussed later.
[0016] The semiconductor device of Example 1 includes, within the unit cell 9, for example, a drift layer 10 of the first conductivity type (n-type in FIG. 1), a first body layer 5a of the second conductivity type (p-type in FIG. 1) formed on the surface of the drift layer 10, an emitter layer 6 (surface-side electrode layer) of the first conductivity type formed on the surface of the first body layer 5a, an emitter electrode 2 (surface-side main electrode) connected to the first body layer 5a and the emitter layer 6, a first trench 20a formed in contact with the first body layer 5a and the emitter layer 6, a gate electrode 3 formed inside the first trench 20a, and a gate insulating film 21a formed inside the first trench 20a between the first body layer 5a and the gate electrode 3 and between the emitter layer 6 and the gate electrode 3.
[0017] Further, the semiconductor device of Example 1 includes, for example, a buffer layer 11 of the first conductivity type formed on the back surface of the drift layer 10 (opposite side to the first body layer 5a), a collector layer 12 (back-surface-side electrode layer) of the second conductivity type formed on the back surface of the buffer layer 11, and a collector electrode 1 (back-surface-side main electrode) formed on the back surface of the collector layer 12.
[0018] And these constitute the switching element main body.
[0019] Here, the impurity concentration of the drift layer 10 is low concentration (n-), and the impurity concentration of the emitter layer 6 is high concentration (n+). Regarding the conductivity type, in FIG. 1, the case where the first conductivity type is n-type and the second conductivity type is p-type is taken as an example for explanation, but the first conductivity type may be p-type and the second conductivity type may be n-type. In that case, the carriers are electrons instead of holes.
[0020] In FIG. 1, an IGBT is taken as an example for explanation. In the case of a MOSFET, the emitter layer 6 which is the surface-side electrode layer may be read as the source layer, the emitter electrode 2 which is the surface-side main electrode may be read as the source electrode, and the collector electrode 1 which is the back-surface-side main electrode may be read as the drain electrode, respectively. Also, in the case of a MOSFET, the second-conductivity-type collector layer 12 which is the back-surface-side electrode layer is replaced by a first-conductivity-type drain layer. The impurity concentration of the drain layer is high concentration (n+).
[0021] In addition, the semiconductor device of Example 1 has, within the unit cell 9, for example, a second body layer 5b of the second conductivity type formed on the surface of the drift layer 10, where the emitter layer 6 is not formed and which is connected to the emitter electrode 2; a second trench 20b formed in contact with the second body layer 5b; a dummy electrode 4 formed inside the second trench 20b and having the same potential as the emitter electrode 2; an insulating film 21b formed inside the second trench 20b between the second body layer 5b and the dummy electrode 4; and an electric field concentration layer 7 of the first conductivity type formed at the bottom of the second body layer 5b and having a higher impurity concentration than the drift layer 10.
[0022] Since the electric field concentration layer 7 is formed at the bottom of the second body layer 5b, the avalanche voltage at this location is lower than others. When the IGBT is off and avalanche occurs, it occurs at this location. The holes, which are a large number of carriers generated by avalanche, flow through the second body layer 5b and escape to the emitter electrode 2. Since the emitter layer 6 of the first conductivity type is not formed in the second body layer 5b, there is no pnpn parasitic thyristor in the second body layer 5b, and latch-up of the parasitic thyristor does not occur.
[0023] Here, if the first body layer 5a of the switching element body having the emitter layer 6 of the first conductivity type is close, carriers due to avalanche also flow through the first body layer 5a, and latch-up of the parasitic thyristor may occur.
[0024] Therefore, the semiconductor device of Example 1 is configured to have, within the unit cell 9, for example, a floating layer 8 of the second conductivity type formed between the first trench 20a and the second trench 20b and electrically floated. Note that the floating layer 8 is insulated from the emitter electrode 2 by the insulating film 22 in order to be electrically floated.
[0025] This floating layer 8 separates the first body layer 5a and the second body layer 5b from each other, suppressing the flow of avalanche carriers into the first body layer 5a where the switching element body is located. This also suppresses the latch-up of the parasitic thyristor. Furthermore, it prevents a decrease in RBSOA withstand capability caused by the latch-up of the parasitic thyristor. In the case of a MOSFET, since an npn parasitic transistor exists instead of a parasitic thyristor, it is possible to suppress the turning on of the parasitic transistor.
[0026] Furthermore, since the floating layer 8 is electrically floating and not connected to the emitter electrode 2, when the IGBT is ON, holes cannot escape to the emitter electrode 2 through the floating layer 8. If holes were to escape to the emitter electrode 2 from a certain region of the floating layer 8 when the IGBT is ON, the hole density would decrease, the IE (Injection Enhancement) effect would weaken, and conductivity modulation would become insufficient, leading to a problem where the ON voltage would increase. However, since the floating layer 8 is electrically floating and not connected to the emitter electrode 2, this problem does not occur.
[0027] As described above, according to Embodiment 1, the electric field concentration layer 7 generates an avalanche in a certain region of the second body layer 5b, and by having a floating layer 8 between the first body layer 5a where the switching element body is located and the second body layer 5b where the avalanche is generated, the first body layer 5a and the second body layer 5b are separated from each other, and the flow of carriers due to the avalanche into the first body layer 5a where the switching element body is located can be suppressed. [Examples]
[0028] Example 2 is a modified version of Example 1. The explanation will focus on the differences from Example 1, omitting redundant explanations.
[0029] Figure 2 is a cross-sectional view illustrating the semiconductor device of Example 2.
[0030] Figure 2 shows an example of application to a so-called side-gate structure IGBT. Note that, as with Example 1, it is not limited to IGBTs and may also be applied to MOSFETs. Furthermore, the conductivity type may be reversed.
[0031] The semiconductor device of Example 2 has, for example, a drift layer 10 of a first conductivity type, a first body layer 5a of a second conductivity type formed on the surface of the drift layer 10, an emitter layer 6 (surface-side electrode layer) of a first conductivity type formed on the surface of the first body layer 5a, an emitter electrode 2 (surface-side main electrode) connected to the first body layer 5a and the emitter layer 6, a trench 20c formed in contact with the first body layer 5a and the emitter layer 6, a gate electrode 13 formed on the side wall of the trench 20c on the side of the first body layer 5a, and a gate insulating film 23a formed inside the trench 20c between the first body layer 5a and the gate electrode 13, and between the emitter layer 6 and the gate electrode 13. The structure of the back side is the same as in Example 1, so its description is omitted. These constitute the main body of a switching element with a so-called side-gate structure.
[0032] Furthermore, the semiconductor device of Example 2 has, within the unit cell 9, for example, a second body layer 5b of a second conductivity type formed on the surface of the drift layer 10, in contact with the trench 20c and on the opposite side from the first body layer 5a, without an emitter layer 6, and connected to the emitter electrode 2; a dummy electrode 14 formed on the side wall of the second body layer 5b inside the trench 20c and at the same potential as the emitter electrode 2; a first insulating film 23b formed inside the trench 20c between the second body layer 5b and the dummy electrode 14; and a first conductivity type field concentration layer 7 formed at the bottom of the second body layer 5b and having a higher impurity concentration than the drift layer 10. The effect of the field concentration layer 7 is the same as in Example 1, so its explanation is omitted.
[0033] Furthermore, the semiconductor device of Example 2 has, within a unit cell 9, a field plate 15 formed, for example, inside a trench 20c and at the same potential as the emitter electrode 2, a second insulating film 23c formed inside the trench 20c between the field plate 15 and the drift layer 10, and a third insulating film 24a formed inside the trench 20c between the field plate 15 and the gate electrode 13, and between the field plate 15 and the dummy electrode 14. The third insulating film 24a refers to the portion of the insulating film 24 formed inside the trench 20c.
[0034] In Example 2, instead of the floating layer 8 of Example 1, the configuration has a wide trench 20c in which a field plate 15 is formed inside. As a result, similar to Example 1, the first body layer 5a and the second body layer 5b are separated from each other, and the flow of carriers due to avalanche into the first body layer 5a where the switching element body is located can be suppressed.
[0035] The reason the field plate 15 is at the same potential as the emitter electrode 2 is that if this were not done, the electric field would concentrate beneath the dummy electrode 14, causing carriers to flow through the first insulating film 23b and into the dummy electrode 14.
[0036] Furthermore, since the field plate 15 is surrounded by the second insulating film 23c and the third insulating film 24a, when the IGBT is ON, holes do not pass through the field plate 15 to the emitter electrode 2. Therefore, the problem of high ON voltage is avoided, as in Example 1.
[0037] Other effects are the same as in Example 1, or the same as the effects of the side gate structure, so their explanation will be omitted. [Examples]
[0038] Example 3 is a modified version of Example 1. The explanation will focus on the differences from Example 1, omitting redundant explanations. Note that Example 3 may also be applied to Example 2.
[0039] Figure 3 is a cross-sectional view illustrating the semiconductor device of Example 3.
[0040] In Example 3, the difference from Example 1 is that the width Wb of the second body layer 5b is greater than the width Wa of the first body layer 5a. Otherwise, it is the same as Example 1.
[0041] By increasing the width Wb, the area of the pn junction between the second body layer 5b and the drift layer 10, or between the second body layer 5b and the electric field concentration layer 7, can be increased. This allows for a lower avalanche voltage compared to the case with width Wa, and ensures that an avalanche is reliably generated at the location of the second body layer 5b. However, if the width Wb is made too wide, the avalanche voltage will drop too low, resulting in a lower overall breakdown voltage. Therefore, it is desirable to set the width Wb while considering the balance with the overall breakdown voltage.
[0042] Other effects are the same as in Example 1, so their explanation will be omitted. [Examples]
[0043] Example 4 is a modified version of Example 1. The explanation will focus on the differences from Example 1, omitting redundant explanations. Note that Example 4 may also be applied to Example 2 or Example 3.
[0044] Figure 4 is a cross-sectional view illustrating the semiconductor device of Example 4.
[0045] In Example 4, the difference from Example 1 is that the first body layer 5a also has an electric field concentration layer 7 at its bottom, and the avalanche voltage in the second body layer 5b is smaller than the avalanche voltage in the first body layer 5a. Otherwise, it is the same as Example 1.
[0046] According to Example 4, during RBSOA operation when the IGBT is off, a negative voltage is applied between the gate and the emitter, so the electric field is distributed between the pn junction composed of the first body layer 5a and the electric field concentration layer 7 and the bottom of the first trench 20a. As a result, the avalanche voltage of the first body layer 5a increases. Therefore, the avalanche voltage in the second body layer 5b becomes smaller than the avalanche voltage in the first body layer 5a, and an avalanche can be generated on the side where the second body layer 5b is located. Similarly, when applied to Example 2, the electric field is distributed between the pn junction composed of the first body layer 5a and the electric field concentration layer 7 and the bottom of the trench 20c, and the avalanche voltage of the first body layer 5a increases, so an avalanche can be generated on the side where the second body layer 5b is located.
[0047] Furthermore, in Example 4, the electric field concentration layer 7 formed at the bottom of the first body layer 5a can block the escape routes of holes in the first body layer 5a, thereby preventing the IE (Injection Enhancement) effect from weakening when the IGBT is ON, and preventing the ON voltage from becoming high.
[0048] Other effects are the same as in Example 1, so their explanation will be omitted. [Examples]
[0049] Example 5 is a modified version of Example 4. The explanation will focus on the differences from Example 4, omitting redundant explanations. Note that Example 5 may also be applied to any of Examples 1 through 3.
[0050] Figure 5 is a cross-sectional view illustrating the semiconductor device of Example 5.
[0051] In Example 5, the difference from Example 4 is that the impurity concentration (n+) of the electric field concentration layer 7 formed at the bottom of the second body layer 5b is higher than the impurity concentration (n) of the electric field concentration layer 7 formed at the bottom of the first body layer 5a. Otherwise, it is the same as Example 4.
[0052] According to Example 5, the avalanche voltage of the pn junction composed of the second body layer 5b and the high-density electric field concentration layer 7 is lower than that of the pn junction composed of the first body layer 5a and the electric field concentration layer 7, so that an avalanche can be reliably generated in the second body layer 5b.
[0053] Other effects are the same as in Example 4, so their explanation will be omitted. [Examples]
[0054] Example 6 is a modified version of Example 4. The explanation will focus on the differences from Example 4, omitting redundant explanations. Note that Example 6 may also be applied to any of Examples 1 through 3 or Example 5.
[0055] Figure 6 is a cross-sectional view illustrating the semiconductor device of Example 6.
[0056] In Example 6, the difference from Example 4 is that the bottom (depth Db) of the electric field concentration layer 7 formed at the bottom of the second body layer 5b is deeper than the bottom (depth Da) of the electric field concentration layer 7 formed at the bottom of the first body layer 5a. Otherwise, it is the same as Example 4.
[0057] According to Example 6, by increasing the depth Db of the electric field concentration layer 7 in the second body layer 5b, the avalanche voltage is reduced, making it possible to reliably generate an avalanche in the second body layer 5b.
[0058] Other effects are the same as in Example 4, so their explanation will be omitted. [Examples]
[0059] Example 7 is an example of a power conversion device.
[0060] A power converter can be constructed using any of the semiconductor devices from Examples 1 to 6 as switching elements. Since the configuration of the power converter is general, a detailed explanation will be omitted.
[0061] Although embodiments of the present invention have been described above, the present invention is not limited to the configurations described in the embodiments, and various modifications are possible within the scope of the technical idea of the present invention. Furthermore, some or all of the configurations described in each embodiment may be combined and applied. [Explanation of symbols]
[0062] 1. Collector electrode (main electrode on the back side) 2. Emitter electrode (main electrode on the surface side) 3. Foodstuffs 4 Dummy electrodes 5a First body layer 5b Second body layer 6. Emitter layer (surface electrode layer) 7. Electric field concentration layer 8. Floating layer 9 unit cells 10 Drift Layers 11 Buffer Layer 12. Collector layer (backside electrode layer) 13 gates 14 Dummy electrodes 15 Field Plate 20a Trench 1 20b Second Trench 20cm Trench 21a Gate insulating film 21b Insulating film 22 Insulating film 23a Gate insulating film 23b First insulating film 23c Second insulating film 24 Insulating film 24a Third insulating film
Claims
1. A first conductive drift layer, A second conductive first body layer formed on the surface of the drift layer, A first conductivity type surface electrode layer formed on the surface of the first body layer, A surface-side main electrode connected to the first body layer and the surface-side electrode layer, A first trench formed in contact with the first body layer and the surface electrode layer, A gate electrode formed inside the first trench, A gate insulating film formed inside the first trench between the first body layer and the gate electrode, and between the surface electrode layer and the gate electrode, In a semiconductor device having, A second body layer of a second conductivity type is formed on the surface of the drift layer, the surface-side electrode layer is not formed thereon, and it is connected to the surface-side main electrode, A second trench formed in contact with the second body layer, A dummy electrode formed inside the second trench and at the same potential as the surface-side main electrode, Inside the second trench, an insulating film formed between the second body layer and the dummy electrode, A first conductivity type electric field concentration layer is formed at the bottom of the second body layer and has a higher impurity concentration than the drift layer, A second conductive floating layer is formed between the first trench and the second trench and is electrically floating, A semiconductor device characterized by having the following features.
2. A first conductive drift layer, A second conductive first body layer formed on the surface of the drift layer, A first conductivity type surface electrode layer formed on the surface of the first body layer, A surface-side main electrode connected to the first body layer and the surface-side electrode layer, A trench formed in contact with the first body layer and the surface electrode layer, A gate electrode formed on the side wall of the first body layer inside the trench, A gate insulating film formed inside the trench between the first body layer and the gate electrode, and between the surface electrode layer and the gate electrode, In a semiconductor device having, In contact with the trench, on the side opposite to the first body layer, a second body layer of second conductivity type is formed on the surface of the drift layer, the surface side electrode layer is not formed, and it is connected to the surface side main electrode, A dummy electrode is formed on the side wall of the second body layer inside the trench and is at the same potential as the surface-side main electrode, Inside the trench, a first insulating film is formed between the second body layer and the dummy electrode, A first conductivity type electric field concentration layer is formed at the bottom of the second body layer and has a higher impurity concentration than the drift layer, A field plate formed inside the trench and at the same potential as the surface-side main electrode, Inside the trench, a second insulating film formed between the field plate and the drift layer, A third insulating film is formed inside the trench between the field plate and the gate electrode, and between the field plate and the dummy electrode, A semiconductor device characterized by having the following features.
3. In claim 1 or 2, A semiconductor device characterized in that the width of the second body layer is greater than the width of the first body layer.
4. In claim 1 or 2, The bottom of the first body layer also has the electric field concentration layer, A semiconductor device characterized in that the avalanche voltage in the second body layer is smaller than the avalanche voltage in the first body layer.
5. In claim 4, A semiconductor device characterized in that the impurity concentration of the electric field concentration layer formed at the bottom of the second body layer is higher than the impurity concentration of the electric field concentration layer formed at the bottom of the first body layer.
6. In claim 4, A semiconductor device characterized in that the bottom of the electric field concentration layer formed at the bottom of the second body layer is formed to be deeper than the bottom of the electric field concentration layer formed at the bottom of the first body layer.
7. In claim 1 or 2, A semiconductor device characterized in that the surface electrode layer is an emitter layer and the surface main electrode is an emitter electrode.
8. In claim 1 or 2, A semiconductor device characterized in that the surface-side electrode layer is a source layer and the surface-side main electrode is a source electrode.
9. A power conversion device characterized by using the semiconductor device described in claim 1 or 2 as a switching element.