Output circuit

Abstract

A semiconductor integrated circuit device, wherein an output circuit is provided with a transistor (N1) connected between a VSS and an output terminal (OUT). A power supply wiring (11) for supplying the VSS is formed on an embedded wiring layer. A power supply wiring (41) for supplying the VSS is formed on an M1 wiring layer above the embedded wiring layer. A power supply wiring (7) connected to the power supply wiring (41) is formed on an M2 wiring layer. An output wiring (42) is formed on the M1 wiring layer. An output wiring (51) connected to the output wiring (42) is formed on the M2 wiring layer.

Description

Technical Field

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[0001] The present disclosure relates to a semiconductor integrated circuit device including a buried power rail (BPR), and particularly to the layout structure of an output circuit.

Background Art

[0002] A semiconductor integrated circuit device includes an input / output circuit that performs input / output of signals with the outside through input / output pads. Regarding the output circuit in the input / output circuit, sufficient attention must be paid to its layout structure in order to allow a large current to flow.

[0003] For high integration of semiconductor integrated circuit devices, instead of a power supply wiring provided in a metal wiring layer formed on top of a transistor as in the prior art, it has been proposed to use a buried power rail (BPR) formed by a metal wiring provided in a buried interconnect layer buried in a substrate.

[0004] In Patent Documents 1 and 2, techniques using BPR in the diode portion of an input / output circuit in a semiconductor integrated circuit device are disclosed.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, Patent Documents 1 and 2 do not disclose a specific layout structure for a circuit that allows a large current to flow, such as an output circuit in an input / output circuit. [[ID=​This disclosure aims to realize an output circuit capable of supplying a large current to the output terminal in a semiconductor integrated circuit device equipped with a BPR. [Means for solving the problem]

[0008] In a first aspect of this disclosure, an output circuit for outputting a signal from a semiconductor integrated circuit comprises a first power supply that supplies a first power supply voltage, a first transistor of a first conductivity type connected between the first power supply and an output terminal, a first power supply wiring formed in an embedded wiring layer and extending in a first direction and supplying the first power supply voltage, a second power supply wiring formed in a first wiring layer above the embedded wiring layer and extending in the first direction and supplying the first power supply voltage, a third power supply wiring formed in a second wiring layer above the first wiring layer and extending in a second direction perpendicular to the first direction and connected to the second power supply wiring, a first output wiring formed in the first wiring layer and extending in the first direction and connected to the output terminal, and a second output wiring formed in the second wiring layer and extending in the second direction and connected to the first output wiring.

[0009] In this embodiment, the output circuit includes a first transistor of a first conductivity type connected between a first power supply that supplies a first power supply voltage and the output terminal. The power supply wiring that supplies the first power supply voltage is formed in the embedded wiring layer and the first and second wiring layers above it. As a result, the resistance value of the power supply path of the first power supply is reduced, so that the output wiring of the first and second wiring layers can be made thicker while suppressing an increase in the area of ​​the output circuit. Consequently, a large current can be passed through the output terminal.

[0010] In a second aspect of the present disclosure, an output circuit for outputting a signal from a semiconductor integrated circuit comprises a first power supply that supplies a first power supply voltage, a first transistor of a first conductivity type connected between the first power supply and an output terminal, a first power supply wiring formed in an embedded wiring layer and extending in a first direction and supplying the first power supply voltage, a second power supply wiring formed in a first wiring layer above the embedded wiring layer and extending in a second direction perpendicular to the first direction and supplying the first power supply voltage, a third power supply wiring formed in a second wiring layer above the first wiring layer and extending in the first direction and connected to the second power supply wiring, a first output wiring formed in the first wiring layer and extending in the second direction and connected to the output terminal, and a second output wiring formed in the second wiring layer and extending in the first direction and connected to the first output wiring.

[0011] In this embodiment, the output circuit includes a first transistor of a first conductivity type connected between a first power supply that supplies a first power supply voltage and the output terminal. The power supply wiring that supplies the first power supply voltage is formed in the embedded wiring layer and the first and second wiring layers above it. As a result, the resistance value of the power supply path of the first power supply is reduced, so that the output wiring of the second wiring layer can be made thicker while suppressing an increase in the area of ​​the output circuit. Consequently, a large current can be passed through the output terminal.

[0012] In a third aspect of this disclosure, an output circuit is configured in a semiconductor integrated circuit device comprising a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip, wherein the back surface of the first semiconductor chip and the main surface of the second semiconductor chip face each other. The output circuit in the first semiconductor chip comprises a first power supply that supplies a first power supply voltage, a first transistor of a first conductivity type connected between the first semiconductor chip and an output terminal, a first power supply wiring formed in an embedded wiring layer and extending in a first direction and supplying the first power supply voltage, a first output wiring formed in a first wiring layer above the embedded wiring layer and extending in the first direction and connected to the output terminal, and a second output wiring formed in a second wiring layer above the first wiring layer and extending in a second direction perpendicular to the first direction and connected to the first output wiring. The second semiconductor chip comprises a second power supply wiring extending in the second direction and overlapping with the second output wiring in a plan view, the second power supply wiring being connected to the first power supply wiring via a via formed on the back surface of the first semiconductor chip.

[0013] In this embodiment, the output circuit includes a first transistor of a first conductivity type connected to the output terminal of the first semiconductor chip, which supplies a first power supply voltage. Power supply wiring for supplying the first power supply voltage is formed in the embedded wiring layer of the first semiconductor chip and in the second semiconductor chip. This makes it possible to reduce the resistance of the power supply path of the first power supply without providing power supply wiring in the first and second wiring layers of the first semiconductor chip. Therefore, the output wiring of the first and second wiring layers of the first semiconductor chip can be made thicker, allowing a large current to flow through the output terminal. Furthermore, the power supply wiring formed on the second semiconductor chip can also be made thicker because it overlaps with the output wiring in a plan view.

[0014] In a fourth aspect of this disclosure, an output circuit is configured in a semiconductor integrated circuit device comprising a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip, wherein the back surface of the first semiconductor chip and the main surface of the second semiconductor chip face each other. The output circuit in the first semiconductor chip comprises a first power supply that supplies a first power supply voltage, a first transistor of a first conductivity type connected between the first semiconductor chip and an output terminal, a first power supply wiring formed in an embedded wiring layer and extending in a first direction and supplying the first power supply voltage, a first output wiring formed in a first wiring layer above the embedded wiring layer and extending in a second direction perpendicular to the first direction and connected to the output terminal, and a second output wiring formed in a second wiring layer above the first wiring layer and extending in the first direction and connected to the first output wiring. The second semiconductor chip comprises a second power supply wiring extending in the first direction and overlapping with the second output wiring in a plan view, the second power supply wiring being connected to the first power supply wiring via vias formed on the back surface of the first semiconductor chip.

[0015] In this embodiment, the output circuit includes a first transistor of a first conductivity type connected between a first power supply that supplies a first power supply voltage to the first semiconductor chip and the output terminal. Power supply wiring that supplies the first power supply voltage is formed in the embedded wiring layer of the first semiconductor chip and in the second semiconductor chip. This makes it possible to reduce the resistance of the power supply path of the first power supply without providing power supply wiring in the second wiring layer of the first semiconductor chip. Therefore, the output wiring of the second wiring layer in the first semiconductor chip can be made thicker, allowing a large current to flow through the output terminal. Furthermore, the power supply wiring formed on the second semiconductor chip can also be made thicker because it overlaps with the output wiring in a plan view. [Effects of the Invention]

[0016] According to this disclosure, in a semiconductor integrated circuit device equipped with a BPR, an output circuit capable of supplying a large current to the output terminal can be realized. [Brief explanation of the drawing]

[0017] [Figure 1] Overall configuration of the semiconductor integrated circuit device according to the embodiment [Figure 2] (a) and (b) are simplified configuration diagrams of the IO cell [Figure 3] Circuit diagram of the output circuit in the embodiment [Figure 4] Planar view showing the layout of the IO cell in the first embodiment [Figure 5] Planar view showing a part of the layers in FIG. 4 [Figure 6] Planar view showing a part of the layers in FIG. 4 [Figure 7] (a) to (c) are cross-sectional structures of the layout in FIG. 4 [Figure 8] Planar view showing the layout of the IO cell in the first embodiment [Figure 9] Circuit diagram of the output circuit in the modification [Figure 10] Planar view showing the layout of the IO cell in the modification [Figure 11] Planar view showing the layout of the IO cell in the modification [Figure 12] Overall configuration of the semiconductor integrated circuit device according to the second embodiment [Figure 13] Planar view showing the layout of the IO cell in the second embodiment [Figure 14] Planar view showing a part of the layers in FIG. 13 [Figure 15] Planar view showing a part of the layers in FIG. 13 [Figure 16] Planar view showing a part of the layers in FIG. 13 [Figure 17] (a) to (c) are cross-sectional structures of the layout in FIG. 13 [Figure 18] Planar view showing the layout of the IO cell in the second embodiment [Figure 19] Planar view showing the layout of the IO cell in Configuration Example 1 of the third embodiment [Figure 20] Planar view showing a part of the layers in FIG. 19 [Figure 21] Planar view showing a part of the layers in FIG. 19 [Figure 22]Plan view showing the layout of the IO cell in Configuration Example 1 of the third embodiment. [Figure 23] Plan view showing the layout of the IO cell in Configuration Example 2 of the third embodiment. [Figure 24] Plan view showing some of the layers in Figure 23 [Figure 25] Plan view showing some of the layers in Figure 23 [Figure 26] Modified configuration of Figure 23 [Figure 27] Plan view showing the layout of the IO cell in Configuration Example 2 of the third embodiment. [Figure 28] Modified configuration of Figure 27 [Figure 29] Plan view showing the layout of the IO cell in Configuration Example 3 of the third embodiment. [Figure 30] Plan view showing some of the layers in Figure 29 [Figure 31] Plan view showing some of the layers in Figure 29 [Figure 32] Plan view showing some of the layers in Figure 29 [Figure 33] Plan view showing the layout of the IO cell in Configuration Example 3 of the third embodiment. [Modes for carrying out the invention]

[0018] The embodiments will be described below with reference to the drawings. In the following description, "VSS" and "VDDIO" refer to either the power supply itself or both the power supply voltage.

[0019] (First Embodiment) Figure 1 is a schematic plan view showing the overall configuration of a semiconductor integrated circuit device (semiconductor chip) according to an embodiment. In Figure 1, the horizontal direction of the drawing is the X direction, and the vertical direction of the drawing is the Y direction (the same applies to subsequent figures). The semiconductor integrated circuit device 1 shown in Figure 1 comprises a core region 2 in which an internal core circuit is formed, and an IO region 3 provided around the core region 2, in which an interface circuit (IO circuit) is formed. In the IO region 3, an IO cell row 5 is provided so as to surround the core region 2 in the peripheral part of the semiconductor integrated circuit device 1. Although the illustration is simplified in Figure 1, the IO cell row 5 has multiple IO cells 10 that constitute the interface circuit arranged in a row.

[0020] Here, IO cell 10 includes a signal IO cell for inputting, outputting, or inputting / outputting signals, a power IO cell for supplying ground potential (power supply voltage VSS), and a power IO cell mainly for supplying power (power supply voltage VDDIO) to IO area 3. For example, VDDIO is 1.8V. In Figure 1, IO cell 10A for signal input / output is located on the upper side of the core area 2, and IO cell 10B for signal input / output is located on the left side of the core area 2.

[0021] The IO area 3 is provided with power supply wiring 6 and 7 that extend in the direction in which the IO cells 10 are aligned. Power supply wiring 6 and 7 are formed in a ring shape around the periphery of the semiconductor integrated circuit device 1 (also called ring power supply wiring). Power supply wiring 6 supplies VDDIO, and power supply wiring 7 supplies VSS. Although not shown in Figure 1, the semiconductor integrated circuit device 1 has multiple external connection pads.

[0022] Figure 2 shows a simplified configuration diagram of IO cells 10A and 10B. As shown in Figure 2(a), IO cell 10A has power supply wiring 6 and 7 extending in the X direction. In IO cell 10A, an N-conductivity output transistor section 101 is provided below power supply wiring 7, and a P-conductivity output transistor section 102 is provided below power supply wiring 6. The N-conductivity output transistor section 101 and the P-conductivity output transistor section 102 are located closer to the outside of the chip in IO cell 10A. Also, as shown in Figure 2(b), IO cell 10B has power supply wiring 6 and 7 extending in the Y direction. In IO cell 10B, an N-conductivity output transistor section 103 is provided below power supply wiring 7, and a P-conductivity output transistor section 104 is provided below power supply wiring 6. The N-conductivity output transistor section 103 and the P-conductivity output transistor section 104 are located closer to the outside of the chip in IO cell 10B.

[0023] Figure 3 is a circuit diagram of the output circuit in this embodiment. In the output circuit of Figure 3, a P-conductivity transistor P1 (hereinafter referred to as P-type as appropriate) is provided between the power supply VDDIO and the output terminal (which outputs the output signal OUT), and an N-conductivity transistor N1 (hereinafter referred to as N-type as appropriate) is provided between the power supply VSS and the output signal line. The output control circuit 20 outputs output control signals INP and INN. Transistor P1 receives the output control signal INP at its gate, and transistor N1 receives the output control signal INN at its gate. The output signal OUT is supplied to an external connection pad. When the output control signals INP and INN are low level, the output signal OUT is high level (VDDIO), and when the output control signals INP and INN are high level, the output signal OUT is low level (VSS).

[0024] Figure 4 is a plan view showing the layout of the output transistor section in the IO cell 10B shown in Figure 2(b) in this embodiment. Figures 5 and 6 are plan views showing Figure 4 divided into layers; Figure 5 shows the local wiring and the configuration of the lower layer, and Figure 6 shows the local wiring and the configuration of the upper layer. Figure 7 is a cross-sectional view showing the cross-sectional structure of the layout in Figure 4; (a) shows the cross-sectional structure of line Y1-Y1', (b) shows the cross-sectional structure of line Y2-Y2', and (c) shows the cross-sectional structure of line Y3-Y3'.

[0025] In Figures 4 to 6, the left side of the diagram corresponds to the N-conductivity output transistor section 103 that constitutes transistor N1, and the right side of the diagram corresponds to the P-conductivity output transistor section 104 that constitutes transistor P1. FinFETs (Field Effect Transistors) are formed in the N-conductivity output transistor section 103 and the P-conductivity output transistor section 104. In addition, power supply wiring 6 and 7 shown in Figure 2(b) are formed in the M2 wiring layer. Power supply wiring 7 that supplies VSS is provided on the N-conductivity output transistor section 103, and power supply wiring 6 that supplies VDDIO is provided on the P-conductivity output transistor section 104.

[0026] The N-conducting output transistor section 103 has three sections 103a, 103b, and 103c, each with five fins 21 extending in parallel in the X direction. Embedded power supply wiring 11 extending in the X direction is positioned above and below sections 103a, 103b, and 103c in the diagram. The embedded power supply wiring 11 supplies VSS. Gate wiring 22 extending in the Y direction is positioned across sections 103a, 103b, and 103c. The fins 21 and gate wiring 22 form a fin FET.

[0027] A local wiring 31 extending in the Y direction is commonly connected to the terminals of the fin 21 that serves as the source of the finFET. The local wiring 31 is connected to the embedded power wiring 11 via vias and supplies VSS to the source of the finFET. A local wiring 32 extending in the Y direction is commonly connected to the terminals of the fin 21 that serves as the drain of the finFET.

[0028] Local wiring 31 is connected via via to M1 wiring 41, which extends in the X direction. Here, M1 wiring 41 is positioned to overlap with the embedded power wiring 11 in a plan view. M1 wiring 41 is connected via via to power wiring 7 formed in the M2 wiring layer.

[0029] Local wiring 32 is connected via via to wiring M1 42, which extends in the X direction. Wiring M1 42 is connected via via to wiring M2 51. Wiring M1 42 and M2 51 correspond to output wiring. Wiring M2 51 is connected to an upper layer pad electrode (not shown).

[0030] The configuration of the P-conductivity output transistor section 104 is almost the same as that of the N-conductivity output transistor section 103. The P-conductivity output transistor section 104 has three sections 104a, 104b, and 104c, each with five fins 23 extending in parallel in the Y direction. Embedded power supply wiring 12 extending in the X direction is arranged above and below the diagram of sections 104a, 104b, and 104c. The embedded power supply wiring 12 supplies VDDIO. Gate wiring 24 extending in the Y direction is arranged across sections 104a, 104b, and 104c. The fins 23 and gate wiring 24 form a fin FET.

[0031] A local wiring 33 extending in the Y direction is commonly connected to the terminals of fin 23, which serves as the source of the finFET. The local wiring 33 is connected to the embedded power wiring 12 via vias, supplying VDDIO to the source of the finFET. A local wiring 34 extending in the Y direction is commonly connected to the terminals of fin 23, which serves as the drain of the finFET.

[0032] Local wiring 33 is connected via via to M1 wiring 43, which extends in the X direction. Here, M1 wiring 43 is positioned to overlap with the embedded power wiring 12 in a plan view. M1 wiring 43 is connected via via to power wiring 6 formed in the M2 wiring layer.

[0033] Local wiring 34, like local wiring 32, is connected via vias to M1 wiring 42, which extends in the X direction.

[0034] With the above configuration, power supply wiring for VSS is formed in the embedded wiring layer as power supply wiring 11, in the M1 wiring layer as power supply wiring 41, and in the M2 wiring layer as power supply wiring 7. As a result, the resistance value of the VSS supply path is reduced, so power supply wirings 7 and 41 can be made thinner. Also, power supply wiring for VDDIO is formed in the embedded wiring layer as power supply wiring 12, in the M1 wiring layer as power supply wiring 43, and in the M2 wiring layer as power supply wiring 6. As a result, the resistance value of the VDDIO supply path is reduced, so power supply wirings 6 and 43 can be made thinner. This makes it possible to make the output wiring 42 in the M1 wiring layer and the output wiring 51 in the M2 wiring layer thicker while suppressing an increase in the area of ​​the output circuit. Consequently, a large current can be passed through the output terminals.

[0035] Figure 8 is a plan view showing the layout of the output transistor section in IO cell 10A shown in Figure 2(a). The cross-sectional structure can be easily inferred from Figure 7 and is therefore omitted from this diagram.

[0036] In Figure 8, the upper part of the drawing corresponds to the N-conducting output transistor section 101 that constitutes transistor N1, and the lower part of the drawing corresponds to the P-conducting output transistor section 102 that constitutes transistor P1. FinFETs are formed in the N-conducting output transistor section 101 and the P-conducting output transistor section 102. In addition, power supply wiring 6 and 7 shown in Figure 2(a) are formed in the M1 wiring layer. Power supply wiring 7 that supplies VSS is provided on the N-conducting output transistor section 101, and power supply wiring 6 that supplies VDDIO is provided on the P-conducting output transistor section 102.

[0037] The N-conductivity output transistor section 101 has three sections 101a, 101b, and 101c, each with five fins 21 extending in parallel in the X direction. Embedded power supply wiring 13 extending in the X direction is positioned above and below sections 101a, 101b, and 101c in the diagram. The embedded power supply wiring 13 supplies VSS. Gate wiring 22 extending in the Y direction is positioned across sections 101a, 101b, and 101c. The fins 21 and gate wiring 22 form a fin FET.

[0038] A local wiring 35 extending in the Y direction is commonly connected to the terminals of the fin 21, which serves as the source for the finFET. The local wiring 35 is connected via vias to the embedded power wiring 13 and supplies VSS to the source of the finFET. The local wiring 35 corresponds to the power wiring. The local wiring 35 is connected via vias to the power wiring 7 formed in the M1 wiring layer.

[0039] The P-conductivity output transistor section 102 has three sections 102a, 102b, and 102c, each with five fins 23 extending in parallel in the X direction. Embedded power supply wiring 14 extending in the X direction is positioned above and below sections 102a, 102b, and 102c in the diagram. The embedded power supply wiring 14 supplies VDDIO. Gate wiring 24 extending in the Y direction is positioned across sections 102a, 102b, and 102c. The fins 23 and gate wiring 24 form a fin FET.

[0040] A local wiring 37 extending in the Y direction is commonly connected to the terminals of the fin 23, which serves as the source for the finFET. The local wiring 37 is connected via vias to the embedded power wiring 14 and supplies VDDIO to the source of the finFET. The local wiring 37 corresponds to the power wiring. The local wiring 37 is connected via vias to the power wiring 6 formed in the M1 wiring layer.

[0041] A local wiring 36 extending in the Y direction is commonly connected to the terminals of the fin 21, which serves as the drain of the finFET in the N-conductivity output transistor section 101, and to the terminals of the fin 23, which serves as the drain of the finFET in the P-conductivity output transistor section 102. The local wiring 36 is connected to the M1 wiring 45 via a via. The local wiring 36 and the M1 wiring 45 correspond to the output wiring. The M1 wiring 45 is connected to an upper layer pad electrode (not shown).

[0042] With the above configuration, power supply wiring for VSS is provided by power supply wiring 13 in the embedded wiring layer, local wiring 35 in the embedded wiring layer, and power supply wiring 7 in the M1 wiring layer. As a result, the resistance value of the VSS supply path is reduced, allowing power supply wiring 7 to be made thinner. Similarly, power supply wiring for VDDIO is provided by power supply wiring 14 in the embedded wiring layer, local wiring 37 in the embedded wiring layer, and power supply wiring 6 in the M1 wiring layer. As a result, the resistance value of the VDDIO supply path is reduced, allowing power supply wiring 6 to be made thinner. This allows for thicker output wiring 45 in the M1 wiring layer while suppressing an increase in the area of ​​the output circuit. Consequently, a large current can be passed through the output terminals.

[0043] In addition, in a plan view, embedded power supply wiring 13 for supplying VSS and embedded power supply wiring 14 for supplying VDDIO are formed between transistor N1 and transistor P1. Since the embedded power supply wiring is formed by embedding metal wiring in grooves provided in the substrate, wells within the substrate, STI, etc., it has the effect of reducing noise propagation through the substrate, etc. Therefore, by providing embedded power supply wiring between transistors N1 and P1, latch-up immunity can be improved.

[0044] <Variation> Figure 9 is a circuit diagram of the output circuit in a modified example. In the output circuit of Figure 9, P-type transistors P21 and P22 are connected in series between the power supply VDDIO and the output signal line, and N-type transistors N21 and N22 are connected in series between the power supply VSS and the output signal line. The output control circuit 21 outputs output control signals INP1, INP2, INN1, and INN2. Transistor P21 receives the output control signal INP1 at its gate, and transistor P22 receives the output control signal INP2 at its gate. Transistor N21 receives the output control signal INN1 at its gate, and transistor N22 receives the output control signal INN2 at its gate. The output signal OUT is supplied to the external connection pad. When the output control signals INP1, INP2, INN1, and INN2 are low levels, the output signal OUT is high level (VDDIO), and when the output control signals INP1, INP2, INN1, and INN2 are high levels, the output signal OUT is low level (VSS). Furthermore, one of the output control signals INP1 or INP2 may be at a fixed potential (VSS), and one of the output control signals INN1 or INN2 may be at a fixed potential (VDDIO).

[0045] Figure 10 is a plan view showing the layout of the output transistor section in the IO cell 10B shown in Figure 2(b), relating to this modified example. In Figure 10, the left side of the drawing corresponds to the N-conductivity output transistor section 103 that constitutes transistors N21 and N22, and the right side of the drawing corresponds to the P-conductivity output transistor section 104 that constitutes transistors P21 and P22. FinFETs are formed in the N-conductivity output transistor section 103 and the P-conductivity output transistor section 104. In addition, power supply wiring 6 and 7 shown in Figure 2(b) are formed in the M2 wiring layer. Power supply wiring 7 that supplies VSS is provided on the N-conductivity output transistor section 103, and power supply wiring 6 that supplies VDDIO is provided on the P-conductivity output transistor section 104.

[0046] Compared to the layout in Figure 4, the layout in Figure 10 has two transistors in series, resulting in longer fins and two gate wires positioned between the local wires. However, the basic configuration is the same as in the embodiment described above, so a detailed explanation is omitted. Wire M1 44 is connected to wire M2 52, and wire M2 52 is connected to the upper layer pad electrode (not shown).

[0047] Figure 11 is a plan view showing the layout of the output transistor section in the IO cell 10A shown in Figure 2(a) in this modified example. In Figure 11, the upper part of the drawing corresponds to the N-conductivity output transistor section 101 that constitutes transistors N21 and N22, and the lower part of the drawing corresponds to the P-conductivity output transistor section 102 that constitutes transistors P21 and P22. FinFETs are formed in the N-conductivity output transistor section 101 and the P-conductivity output transistor section 102. In addition, power supply wiring 6 and 7 shown in Figure 2(b) are formed in the M1 wiring layer. Power supply wiring 7 that supplies VSS is provided on the N-conductivity output transistor section 101, and power supply wiring 6 that supplies VDDIO is provided on the P-conductivity output transistor section 102.

[0048] Compared to the layout in Figure 8, the layout in Figure 11 has two transistors in series, resulting in longer fins and two gate wires positioned between the local wires. However, the basic configuration is the same as in the embodiment described above, so a detailed explanation is omitted. Wiring M1 46 is connected to the upper layer pad electrode, which is not shown.

[0049] In this modified example, the same effects and advantages as in the above-described embodiment can be obtained. Specifically, in the layout of Figure 10, the output wiring 44 of the M1 wiring layer and the output wiring 52 of the M2 wiring layer can be made thicker while suppressing an increase in the area of ​​the output circuit. Therefore, a large current can be passed through the output terminal. In the layout of Figure 11, the output wiring 46 of the M1 wiring layer can be made thicker while suppressing an increase in the area of ​​the output circuit. Therefore, a large current can be passed through the output terminal.

[0050] In addition, in a plan view, embedded power supply wiring for VSS and embedded power supply wiring for VDDIO are formed between transistor N1 and transistor P1. Since the embedded power supply wiring is formed by embedding metal wiring in grooves provided in the substrate, wells within the substrate, STI, etc., it has the effect of reducing noise propagation through the substrate, etc. Therefore, by providing embedded power supply wiring between transistors N1 and P1, latch-up immunity can be improved.

[0051] (Second Embodiment) Figure 12 shows the overall configuration of a semiconductor integrated circuit device according to the second embodiment. As shown in Figure 12, the semiconductor integrated circuit device 200 is composed of a first semiconductor chip 201 (chip A) and a second semiconductor chip 202 (chip B) stacked on top of each other. In the stacked portion, the back surface of the first semiconductor chip 201 and the main surface of the second semiconductor chip 202 face each other. The first semiconductor chip 201 has a circuit formed thereon, including transistors that constitute an output buffer, and also has embedded power supply wiring. The second semiconductor chip 202 has power supply wiring that is connected to the embedded power supply wiring formed on the first semiconductor chip 201. The embedded power supply wiring formed on the first semiconductor chip 201 and the power supply wiring formed on the second semiconductor chip 202 are connected via a through silicon via (TSV).

[0052] The plan view of the semiconductor integrated circuit device 200 shown in Figure 12 is the same as that in Figure 1. That is, the first semiconductor chip 201 comprises a core region 2 on which an internal core circuit is formed, and an IO region 3 provided around the core region 2 on which an interface circuit (IO circuit) is formed. In the IO region 3, an IO cell row 5 is provided so as to surround the core region 2 in the peripheral part of the semiconductor integrated circuit device 200. Multiple IO cells 10 constituting the interface circuit are arranged in the IO cell row 5.

[0053] In this embodiment, the power supply wiring 6 and 7 extending in the direction in which the IO cells 10 are aligned are formed on the second semiconductor chip 202.

[0054] In this embodiment, the simplified configuration of IO cells 10A and 10B is the same as in Figure 2, and the circuit diagram of the output circuit is the same as in Figure 3.

[0055] Figure 13 is a plan view showing the layout of the output transistor section in the IO cell 10B shown in Figure 2(b) in this embodiment. The layout in Figure 13 corresponds to the circuit diagram in Figure 3. Figures 14 to 16 are plan views showing Figure 13 divided into layers. Figure 14 shows the power supply wiring of the second semiconductor chip 202 and the embedded power supply wiring and fin configuration of the first semiconductor chip 201. Figure 15 shows the M1 wiring of the first semiconductor chip 201 and the configuration of the lower layer. Figure 16 shows the local wiring of the first semiconductor chip 201 and the configuration of the upper layer. Figure 17 is a cross-sectional view showing the cross-sectional structure of the layout in Figure 13, where (a) shows the cross-sectional structure of line Y1-Y1', (b) shows the cross-sectional structure of line Y2-Y2', and (c) shows the cross-sectional structure of line Y3-Y3'.

[0056] In Figures 13 to 16, the left side of the diagram corresponds to the N-conductivity output transistor section 103 that constitutes transistor N1, and the right side of the diagram corresponds to the P-conductivity output transistor section 104 that constitutes transistor P1. FinFETs (Field Effect Transistors) are formed on the N-conductivity output transistor section 103 and the P-conductivity output transistor section 104. In addition, power supply wiring 6 and 7 shown in Figure 2(b) are formed on the second semiconductor chip 202. Power supply wiring 7 that supplies VSS is provided in a position that overlaps with the N-conductivity output transistor section 103 in a plan view, and power supply wiring 6 that supplies VDDIO is provided in a position that overlaps with the P-conductivity output transistor section 104 in a plan view.

[0057] The N-conductive output transistor section 103 has three sections 103a, 103b, and 103c, each with five fins 21 extending in parallel in the X direction. Embedded power supply wiring 11 extending in the X direction is positioned above and below sections 103a, 103b, and 103c in the diagram. The embedded power supply wiring 11 supplies VSS. The embedded power supply wiring 11 is connected to the power supply wiring 7 of the second semiconductor chip 202 via TSV.

[0058] A gate wiring 22 extending in the Y direction is arranged across sections 103a, 103b, and 103c. The fin 21 and the gate wiring 22 form a finFET. Local wiring 31 extending in the Y direction is commonly connected to the terminals of the fin 21 that serve as the source of the finFET. Local wiring 31 is connected to the embedded power wiring 11 via vias and supplies VSS to the source of the finFET. Local wiring 32 extending in the Y direction is commonly connected to the terminals of the fin 21 that serve as the drain of the finFET.

[0059] Local wiring 32 is connected via via to wiring M1 242, which extends in the X direction. Wiring M1 242 is connected via via 261 to wiring M2 251. Wiring M1 242 and M2 251 correspond to output wiring. Wiring M2 251 is connected to an upper layer pad electrode (not shown).

[0060] The P-conductivity output transistor section 104 has three sections 104a, 104b, and 104c, each with five fins 23 extending in parallel in the X direction. Embedded power supply wiring 12 extending in the X direction is positioned above and below sections 104a, 104b, and 104c in the diagram. The embedded power supply wiring 12 supplies VDDIO. The embedded power supply wiring 12 is connected to the power supply wiring 6 of the second semiconductor chip 202 via a TSV.

[0061] A gate wiring 24 extending in the Y direction is arranged across sections 104a, 104b, and 104c. The fin 23 and the gate wiring 24 form a finFET. Local wiring 33 extending in the Y direction is commonly connected to the terminals of the fin 23 that serve as the source of the finFET. Local wiring 33 is connected to the embedded power wiring 12 via vias and supplies VDDIO to the source of the finFET. Local wiring 34 extending in the Y direction is commonly connected to the terminals of the fin 23 that serve as the drain of the finFET.

[0062] Local wiring 34 is connected via via to M1 wiring 242, which extends in the X direction.

[0063] The power supply lines 6 and 7 of the second semiconductor chip 202 overlap with the M2 line 251 of the first semiconductor chip 201 in a plan view. Furthermore, the placement of the via 261 connecting the M1 line 242 and the M2 line 251 also overlaps with the power supply lines 6 and 7 of the second semiconductor chip 202 in a plan view.

[0064] With the above configuration, the power supply wiring for VSS is provided by power supply wiring 11 formed on the embedded wiring layer of the first semiconductor chip 201 and power supply wiring 7 formed on the second semiconductor chip 202. This makes it possible to reduce the resistance of the VSS supply path without providing power supply wiring on the M1 wiring layer of the first semiconductor chip 201. Furthermore, the power supply wiring for VDDIO is provided by power supply wiring 12 formed on the embedded wiring layer of the first semiconductor chip 201 and power supply wiring 6 formed on the second semiconductor chip 202. This makes it possible to reduce the resistance of the VDDIO supply path without providing power supply wiring on the M1 wiring layer of the first semiconductor chip 201. Therefore, in the first semiconductor chip 201, the output wiring 242 of the M1 wiring layer and the output wiring 251 of the M2 wiring layer can be made thicker, and the number of vias 261 connecting them can be increased, so that a large current can flow through the output terminals. Furthermore, the power supply wiring 6 and 7 formed on the second semiconductor chip 202 also overlap with the output wiring 251 in a plan view, allowing them to be made thicker.

[0065] Figure 18 is a plan view showing the layout of the output transistor section in the IO cell 10A shown in Figure 2(a) in this embodiment. The cross-sectional structure can be easily inferred from Figure 17 and is therefore omitted from the illustration here.

[0066] In Figure 18, the upper part of the drawing corresponds to the N-conductivity output transistor section 101 that constitutes transistor N1, and the lower part of the drawing corresponds to the P-conductivity output transistor section 102 that constitutes transistor P1. FinFETs are formed on the N-conductivity output transistor section 101 and the P-conductivity output transistor section 102. In addition, power supply wiring 6 and 7 shown in Figure 2(a) are formed on the second semiconductor chip 202. Power supply wiring 7 that supplies VSS is provided in a position that overlaps with the N-conductivity output transistor section 101 in a plan view, and power supply wiring 6 that supplies VDDIO is provided in a position that overlaps with the P-conductivity output transistor section 102 in a plan view.

[0067] The N-conductive output transistor section 101 has three sections 101a, 101b, and 101c, each with five fins 21 extending in parallel in the X direction. Embedded power supply wiring 13 extending in the X direction is positioned above and below sections 101a, 101b, and 101c in the diagram. The embedded power supply wiring 13 supplies VSS. The embedded power supply wiring 13 is connected to the power supply wiring 7 of the second semiconductor chip 202 via TSV.

[0068] A gate wiring 22 extending in the Y direction is arranged across sections 101a, 101b, and 101c. The fin 21 and the gate wiring 22 form a finFET. A local wiring 35 extending in the Y direction is commonly connected to the terminals of the fin 21, which serve as the source of the finFET. The local wiring 35 is connected via vias to the embedded power wiring 13, which supplies VSS to the source of the finFET.

[0069] The P-conductivity output transistor section 102 has three sections 102a, 102b, and 102c, each with five fins 23 extending in parallel in the X direction. Embedded power supply wiring 14 extending in the X direction is positioned above and below sections 102a, 102b, and 102c in the diagram. The embedded power supply wiring 14 supplies VDDIO. The embedded power supply wiring 14 is connected to the power supply wiring 6 of the second semiconductor chip 202 via a TSV.

[0070] A gate wiring 24 extending in the Y direction is arranged across sections 102a, 102b, and 102c. The fin 23 and the gate wiring 24 form a finFET. A local wiring 37 extending in the Y direction is commonly connected to the terminals of the fin 23, which serve as the source of the finFET. The local wiring 37 is connected via vias to the embedded power wiring 14, which supplies VDDIO to the source of the finFET.

[0071] A local wiring 36 extending in the Y direction is commonly connected to the terminals of the fin 21, which serves as the drain of the finFET in the N-conductivity output transistor section 101, and to the terminals of the fin 23, which serves as the drain of the finFET in the P-conductivity output transistor section 102. The local wiring 36 is connected to the M1 wiring 245 via a via 262. The local wiring 36 and the M1 wiring 245 correspond to the output wiring. The M1 wiring 245 is connected to an upper layer pad electrode (not shown).

[0072] The power supply lines 6 and 7 of the second semiconductor chip 202 overlap with the M1 line 245 of the first semiconductor chip 201 in a plan view. Furthermore, the placement of via 262 connecting local line 36 and M1 line 245 also overlaps with the power supply lines 6 and 7 of the second semiconductor chip 202 in a plan view.

[0073] With the above configuration, the power supply wiring for VSS is provided by a power supply wiring 13 formed on the embedded wiring layer of the first semiconductor chip 201 and a power supply wiring 7 formed on the second semiconductor chip 202. This makes it possible to reduce the resistance of the VSS supply path without providing power supply wiring on the M1 wiring layer of the first semiconductor chip 201. Furthermore, the power supply wiring for VDDIO is provided by a power supply wiring 14 formed on the embedded wiring layer of the first semiconductor chip 201 and a power supply wiring 6 formed on the second semiconductor chip 202. This makes it possible to reduce the resistance of the VDDIO supply path without providing power supply wiring on the M1 wiring layer of the first semiconductor chip 201. Therefore, in the first semiconductor chip 201, the output wiring 245 of the M1 wiring layer can be made thicker, and the number of vias 262 for connecting to the local wiring 36 can be increased, so that a large current can flow through the output terminal. In addition, the power supply wirings 6 and 7 formed on the second semiconductor chip 202 also overlap with the output wiring 245 in a plan view and can be made thicker.

[0074] In this embodiment, the power supply wiring 6 and 7 formed on the second semiconductor chip 202 may be a single layer or multiple layers. Furthermore, the wiring direction is not limited to those shown herein. For example, the wiring may be extended in mutually orthogonal directions for each layer to form a mesh-like power supply wiring. This can further enhance the power supply.

[0075] Furthermore, in this embodiment, both the VSS power supply wiring and the VDDIO power supply wiring are formed on the second semiconductor chip 202, but it is also possible to form only one of the power supply wirings on the second semiconductor chip 202.

[0076] Furthermore, similar to the modification of the first embodiment, the configuration can be the same even if the output transistor has a two-stage configuration.

[0077] (Third embodiment) In the above-described embodiment, the BPR, i.e., the power wiring formed in the embedded wiring layer, extended in the X direction. In this third embodiment, as a configuration corresponding to the above-described embodiment, a configuration in which the BPR extends in the Y direction is shown.

[0078] (Configuration Example 1) Configuration Example 1 corresponds to the first embodiment. The circuit configuration of the output circuit is as shown in the circuit diagram in Figure 3.

[0079] Figure 19 is a plan view showing the layout of the output transistor section in the IO cell 10B shown in Figure 2(b) in this configuration example. Figures 20 and 21 are plan views of Figure 19 divided into layers; Figure 20 shows the configuration of the local wiring and the lower layers, and Figure 21 shows the configuration of the local wiring and the upper layers. Figures 19 to 21 correspond to Figures 4 to 6 shown in the first embodiment, and explanations of configurations that can be easily inferred from the description of the first embodiment may be omitted.

[0080] In Figures 19 to 21, the left side of the diagram corresponds to the N-conducting output transistor section 103 that constitutes transistor N1, and the right side of the diagram corresponds to the P-conducting output transistor section 104 that constitutes transistor P1. FinFETs (Field Effect Transistors) are formed in the N-conducting output transistor section 103 and the P-conducting output transistor section 104. Power supply wirings 6 and 7, shown in Figure 2(b), are formed on the M2 wiring layer. Power supply wiring 7, which supplies VSS, is provided on the N-conducting output transistor section 103, and power supply wiring 6, which supplies VDDIO, is provided on the P-conducting output transistor section 104. Output wiring 51 is also formed on the M2 wiring layer. M2 wiring 51 is connected to the pad electrodes of the upper layer (not shown).

[0081] The N-conducting output transistor section 103 has 10 fins 21 extending in parallel in the X direction. Embedded power supply wiring 311 extending in the Y direction is arranged on the left and right sides of the fins 21. The embedded power supply wiring 311 supplies VSS. Gate wiring 22 is arranged across the 10 fins 21 in the Y direction. The fins 21 and gate wiring 22 form a fin FET.

[0082] A local wiring 330 is formed above the embedded power wiring 311, extending in the Y direction so as to overlap with the embedded power wiring 311 in a plan view. The local wiring 330 is connected to the embedded power wiring 311 below it via vias.

[0083] A local wiring 331 extending in the Y direction is commonly connected to the terminals of the fin 21, which serves as the source for the finFET. The local wiring 331 is connected to local wiring 330 via five M1 wirings 341 extending in parallel in the X direction, supplying VSS to the source of the finFET. The M1 wirings 341 are connected via vias to power supply wirings 7 formed in the M2 wiring layer.

[0084] A local wiring 332 extending in the Y direction is commonly connected to the terminal of fin 21, which serves as the drain of the finFET. Local wiring 332 is connected via via to M1 wiring 342, which extends in parallel in the X direction. M1 wiring 342 is connected via via to M2 wiring 51.

[0085] The configuration of the P-conductivity output transistor section 104 is almost the same as that of the N-conductivity output transistor section 103. The P-conductivity output transistor section 104 has 10 fins 23 extending in parallel in the X direction. Embedded power supply wiring 312 extending in the Y direction is arranged on the left and right sides of the fins 23. The embedded power supply wiring 312 supplies VDDIO. Gate wiring 24 is arranged across the 10 fins 23 in the Y direction. The fins 23 and gate wiring 24 form a finFET.

[0086] Above the embedded power wiring 312, a local wiring 335 is formed that extends in the Y direction, overlapping with the embedded power wiring 312 in a plan view. The local wiring 335 is connected to the embedded power wiring 312 below it via vias.

[0087] A local wiring 333 extending in the Y direction is commonly connected to the terminals of the fin 23, which serves as the source for the finFET. The local wiring 333 is connected to local wiring 335 via five M1 wirings 343 extending in parallel in the X direction, supplying VDDIO to the source of the finFET. The M1 wirings 343 are connected via vias to power supply wiring 6 formed in the M2 wiring layer.

[0088] A local wiring 334 extending in the Y direction is commonly connected to the terminal of fin 23, which serves as the drain of the finFET. Local wiring 334, like local wiring 332, is connected via vias to five M1 wirings 342 that extend in parallel in the X direction.

[0089] With the above configuration, the power supply wiring for VSS is configured as follows: power supply wiring 311 is formed in the embedded wiring layer, local wiring 330 is formed, power supply wiring 341 is formed in the M1 wiring layer, and power supply wiring 7 is formed in the M2 wiring layer. As a result, the resistance value of the VSS supply path is reduced, allowing power supply wiring 7 to be made thinner. In addition, the power supply wiring for VDDIO is configured as follows: power supply wiring 312 is formed in the embedded wiring layer, local wiring 335 is formed, power supply wiring 343 is formed in the M1 wiring layer, and power supply wiring 6 is formed in the M2 wiring layer. As a result, the resistance value of the VDDIO supply path is reduced, allowing power supply wiring 6 to be made thinner. This allows the output wiring 51 in the M2 wiring layer to be made thicker while suppressing an increase in the area of ​​the output circuit. Consequently, a large current can be passed through the output terminal.

[0090] In addition, in a plan view, embedded power wiring 311 for supplying VSS and embedded power wiring 312 for supplying VDDIO are formed between transistor N1 and transistor P1. Since the embedded power wiring is formed by embedding metal wiring in grooves provided in the substrate, wells within the substrate, STI, etc., it has the effect of reducing noise propagation through the substrate, etc. Therefore, by providing embedded power wiring 311 and 312 between transistors N1 and P1, latch-up immunity can be improved.

[0091] Figure 22 is a plan view showing the layout of the output transistor section in the IO cell 10A shown in Figure 2(a) in this configuration example. Figure 22 corresponds to Figure 8 shown in the first embodiment, and explanations of configurations that can be easily inferred from the description of the first embodiment may be omitted.

[0092] In Figure 22, the upper part of the drawing corresponds to the N-conducting type output transistor section 101 that constitutes transistor N1, and the lower part of the drawing corresponds to the P-conducting type output transistor section 102 that constitutes transistor P1. FinFETs are formed in the N-conducting type output transistor section 101 and the P-conducting type output transistor section 102. In addition, power supply wiring 6 and 7 shown in Figure 2(a) are formed in the M1 wiring layer. Power supply wiring 7 that supplies VSS is provided on the N-conducting type output transistor section 101, and power supply wiring 6 that supplies VDDIO is provided on the P-conducting type output transistor section 102.

[0093] The N-conducting output transistor section 101 has 10 fins 21 extending in parallel in the X direction. Embedded power supply wiring 313 extending in the Y direction is arranged on the left and right sides of the fins 21. The embedded power supply wiring 313 supplies VSS. Gate wiring 22 is arranged across the 10 fins 21 in the Y direction. The fins 21 and gate wiring 22 form a fin FET.

[0094] A local wiring 336 is formed above the embedded power wiring 313, extending in the Y direction so as to overlap with the embedded power wiring 313 in a plan view. The local wiring 336 is connected to the embedded power wiring 313 below it via vias. The local wiring 336 is also connected to the power wiring 7 formed in the M1 wiring layer above it via vias.

[0095] A local wiring 337 extending in the Y direction is commonly connected to the terminals of the fin 21, which serves as the source for the finFET. The local wiring 337 is connected via vias to the power supply wiring 7 formed in the M1 wiring layer and supplies VSS to the source of the finFET.

[0096] The P-conductivity output transistor section 102 has 10 fins 23 extending in parallel in the X direction. Embedded power supply wiring 314 extending in the Y direction is arranged on the left and right sides of the fins 23. The embedded power supply wiring 314 supplies VDDIO. Gate wiring 24 is arranged across the 10 fins 23 in the Y direction. The fins 23 and gate wiring 24 form a finFET.

[0097] A local wiring 340 is formed above the embedded power wiring 314, extending in the Y direction so as to overlap with the embedded power wiring 314 in a plan view. The local wiring 340 is connected to the embedded power wiring 314 below it via vias. The local wiring 340 is also connected to the power wiring 6 formed in the M1 wiring layer above it via vias.

[0098] A local wiring 338 extending in the Y direction is commonly connected to the terminals of the fin 23, which serves as the source for the finFET. The local wiring 338 is connected via vias to the power supply wiring 6 formed in the M1 wiring layer and supplies VDDIO to the source of the finFET.

[0099] A local wiring 339 extending in the Y direction is commonly connected to the terminals of the fin 21, which serves as the drain of the finFET in the N-conductivity output transistor section 101, and to the terminals of the fin 23, which serves as the drain of the finFET in the P-conductivity output transistor section 102. The local wiring 339 is connected via vias to the output wiring 45 formed in the M1 wiring layer. The M1 wiring 45 is connected to the pad electrodes of the upper layer (not shown).

[0100] With the above configuration, power wiring 313 is formed in the embedded wiring layer, local wirings 336 and 337 are formed, and power wiring 7 is formed in the M1 wiring layer as the power wiring for supplying VSS. As a result, the resistance value of the VSS supply path is reduced, allowing power wiring 7 to be made thinner. Also, power wiring 314 is formed in the embedded wiring layer, local wirings 338 and 340 are formed, and power wiring 6 is formed in the M1 wiring layer as the power wiring for supplying VDDIO. As a result, the resistance value of the VDDIO supply path is reduced, allowing power wiring 6 to be made thinner. This makes it possible to make the output wiring 45 in the M1 wiring layer thicker while suppressing an increase in the area of ​​the output circuit. Consequently, a large current can be passed through the output terminal.

[0101] (Configuration Example 2: Corresponds to the circuit diagram in Figure 9 relating to a modified example of the first embodiment) Configuration Example 2 corresponds to a modified version of the first embodiment. The circuit configuration of the output circuit is as shown in the circuit diagram of Figure 9.

[0102] Figure 23 is a plan view showing the layout of the output transistor section in the IO cell 10B shown in Figure 2(b) in this configuration example. Figures 24 and 25 are plan views showing Figure 23 divided into layers; Figure 24 shows the local wiring and the configuration of the lower layers, and Figure 25 shows the local wiring and the configuration of the upper layers. Figures 23 to 25 correspond to Figure 10 shown in the modified example of the first embodiment, and explanations of configurations that can be easily inferred from the description of the modified example of the first embodiment may be omitted.

[0103] In Figures 23 to 25, the left side of the diagram corresponds to the N-conductivity output transistor section 103 that constitutes transistors N21 and N22, and the right side of the diagram corresponds to the P-conductivity output transistor section 104 that constitutes transistors P21 and P22. FinFETs are formed in the N-conductivity output transistor section 103 and the P-conductivity output transistor section 104. Power supply wiring 6 and 7, as shown in Figure 2(b), are formed on the M2 wiring layer. Power supply wiring 7, which supplies VSS, is provided on the N-conductivity output transistor section 103, and power supply wiring 6, which supplies VDDIO, is provided on the P-conductivity output transistor section 104. Output wiring 52 is also formed on the M2 wiring layer. M2 wiring 52 is connected to the pad electrodes of the upper layer (not shown).

[0104] Compared to the layouts in Figures 19 to 21, the layouts in Figures 23 to 25 have two transistors in series, resulting in longer fins and two gate wires placed between the local wires. However, the basic configuration is the same as in Configuration Example 1 described above, so a detailed explanation is omitted.

[0105] In the layouts shown in Figures 23 to 25, the output wiring 52 of the M2 wiring layer can be made thicker while suppressing an increase in the area of ​​the output circuit. Therefore, a large current can be passed through the output terminals.

[0106] Figure 26 shows a modified version of the configuration in Figure 23. In the configuration of Figure 23, transistors N21 and N22 connected in series are formed by a single continuous fin, and transistors P21 and P22 connected in series are formed by a single continuous fin. In contrast, in the configuration of Figure 26, the fins constituting transistor N21 and transistor N22 are separated, and the fins constituting transistor P21 and transistor P22 are separated. That is, transistors N21 and N22 are constructed independently of each other, and the structures constituting the channel, gate, source, and drain are separated from each other. Similarly, transistors P21 and P22 are constructed independently of each other, and the structures constituting the channel, gate, source, and drain are separated from each other.

[0107] In the configuration shown in Figure 26, the embedded power supply wiring 311 is formed between transistors N21 and N22. Local wiring 431, connected to the drain terminal of the fin constituting transistor N21, and local wiring 432, connected to the source terminal of the fin constituting transistor N22, are connected via M1 wiring 441 extending in the X direction.

[0108] Furthermore, an embedded power supply wiring 312 is formed between transistors P21 and P22. Local wiring 433, which is connected to the drain terminal of the fin constituting transistor P21, and local wiring 434, which is connected to the source terminal of the fin constituting transistor P22, are connected via M1 wiring 442 that extends in the X direction.

[0109] In this modified example, transistors N21 and N22 are formed by fins that are separated from each other, and transistors P21 and P22 are formed by fins that are separated from each other. This improves the ESD resistance of the semiconductor integrated circuit device.

[0110] Figure 27 is a plan view showing the layout of the output transistor section in the IO cell 10A shown in Figure 2(a) in this configuration example. Figure 27 corresponds to Figure 11, which is shown as a modified example of the first embodiment, and explanations of configurations that can be easily inferred from the description of the first embodiment may be omitted.

[0111] In Figure 27, the upper part of the drawing corresponds to the N-conducting type output transistor section 101 that constitutes transistors N21 and N22, and the lower part of the drawing corresponds to the P-conducting type output transistor section 102 that constitutes transistors P21 and P22. FinFETs are formed in the N-conducting type output transistor section 101 and the P-conducting type output transistor section 102. In addition, power supply wiring 6 and 7 shown in Figure 2(b) are formed on the M1 wiring layer. Power supply wiring 7 that supplies VSS is provided on the N-conducting type output transistor section 101, and power supply wiring 6 that supplies VDDIO is provided on the P-conducting type output transistor section 102. Output wiring 45 is also formed on the M1 wiring layer.

[0112] Compared to the layout in Figure 22, the layout in Figure 27 has two transistors in series, resulting in longer fins and two gate wires positioned between the local wires. However, the basic configuration is the same as in the embodiment described above, so a detailed explanation is omitted.

[0113] In the layout shown in Figure 27, the output wiring 45 of the M1 wiring layer can be made thicker while suppressing an increase in the area of ​​the output circuit. Therefore, a large current can be passed through the output terminals.

[0114] Figure 28 shows a modified version of the configuration in Figure 27. In the configuration of Figure 27, transistors N21 and N22 connected in series are formed by a single continuous fin, and transistors P21 and P22 connected in series are formed by a single continuous fin. In contrast, in the configuration of Figure 28, the fins constituting transistor N21 and transistor N22 are separated, and the fins constituting transistor P21 and transistor P22 are separated. That is, transistors N21 and N22 are constructed independently of each other, and the structures constituting the channel, gate, source, and drain are separated from each other. Similarly, transistors P21 and P22 are constructed independently of each other, and the structures constituting the channel, gate, source, and drain are separated from each other.

[0115] In the configuration shown in Figure 28, the embedded power supply wiring 313 is formed between transistors N21 and N22. Local wiring 435, connected to the drain terminal of the fin constituting transistor N21, and local wiring 436, connected to the source terminal of the fin constituting transistor N22, are connected via M1 wiring 443 extending in the X direction.

[0116] Furthermore, an embedded power supply wiring 314 is formed between transistor P21 and transistor P22. Local wiring 437 connected to the drain terminal of the fin constituting transistor P21 and local wiring 438 connected to the source terminal of the fin constituting transistor P22 are connected via M1 wiring 444 extending in the X direction.

[0117] In this modified example, transistors N21 and N22 are formed by fins that are separated from each other, and transistors P21 and P22 are formed by fins that are separated from each other. This improves the ESD resistance of the semiconductor integrated circuit device.

[0118] (Configuration Example 3) Configuration Example 3 corresponds to the second embodiment described above. The overall configuration of the semiconductor integrated circuit device is as shown in Figure 12, and the circuit configuration of the output circuit is as shown in the circuit diagram in Figure 3.

[0119] Figure 29 is a plan view showing the layout of the output transistor section in the IO cell 10B shown in Figure 2(b) in this configuration example 3. The layout in Figure 29 corresponds to the circuit diagram in Figure 3. Figures 30 to 32 are plan views showing Figure 29 divided into layers. Figure 30 shows the power supply wiring of the second semiconductor chip 202 and the embedded power supply wiring and fin configuration of the first semiconductor chip 201, Figure 31 shows the M1 wiring of the first semiconductor chip 201 and the configuration of the lower layer, and Figure 32 shows the local wiring of the first semiconductor chip 201 and the configuration of the upper layer. Figures 29 to 32 are diagrams corresponding to Figures 13 to 16 shown in the second embodiment, and explanations of configurations that can be easily inferred from the description of the second embodiment may be omitted.

[0120] In Figures 29 to 32, the left side of the diagram corresponds to the N-conductivity output transistor section 103 that constitutes transistor N1, and the right side of the diagram corresponds to the P-conductivity output transistor section 104 that constitutes transistor P1. FinFETs (Field Effect Transistors) are formed on the N-conductivity output transistor section 103 and the P-conductivity output transistor section 104. In addition, power supply wiring 6 and 7 shown in Figure 2(b) are formed on the second semiconductor chip 202. Power supply wiring 7 that supplies VSS is provided in a position that overlaps with the N-conductivity output transistor section 103 in a plan view, and power supply wiring 6 that supplies VDDIO is provided in a position that overlaps with the P-conductivity output transistor section 104 in a plan view.

[0121] The N-conductivity output transistor section 103 has 10 fins 21 extending in parallel in the X direction. Embedded power supply wiring 511 extending in the Y direction is arranged on the left and right sides of the fins 21. The embedded power supply wiring 511 supplies VSS. The embedded power supply wiring 511 is connected to the power supply wiring 7 of the second semiconductor chip 202 via TSV. Gate wiring 22 is arranged across the 10 fins 21 in the Y direction. The fins 21 and gate wiring 22 form a finFET.

[0122] A local wiring 530 is formed above the embedded power wiring 511, extending in the Y direction so as to overlap with the embedded power wiring 511 in a plan view. The local wiring 530 is connected to the embedded power wiring 511 below it via vias.

[0123] A local wiring 531 extending in the Y direction is commonly connected to the terminals of the fin 21, which serves as the source for the finFET. Local wiring 531 is connected to local wiring 530 via M1 wiring 541 extending in the X direction, and supplies VSS to the source of the finFET.

[0124] A local wiring 532 extending in the Y direction is commonly connected to the terminal of the fin 21, which serves as the drain of the finFET. Local wiring 532 is connected via a via to M1 wiring 542, which extends in the X direction. M1 wiring 542 is connected via a via 561 to M2 wiring 551. M1 wiring 542 and M2 wiring 551 correspond to output wiring. M2 wiring 551 is connected to an upper layer pad electrode (not shown).

[0125] The P-conductivity output transistor section 104 has 10 fins 23 extending in parallel in the X direction. Embedded power supply wiring 512 extending in the Y direction is arranged on the left and right sides of the fins 23. The embedded power supply wiring 512 supplies VDDIO. The embedded power supply wiring 512 is connected to the power supply wiring 6 of the second semiconductor chip 202 via a TSV. Gate wiring 24 is arranged across the 10 fins 23 in the Y direction. The fins 23 and gate wiring 24 form a finFET.

[0126] A local wiring 535 is formed above the embedded power wiring 512, extending in the Y direction so as to overlap with the embedded power wiring 512 in a plan view. The local wiring 535 is connected to the embedded power wiring 512 below it via vias.

[0127] A local wiring 533 extending in the Y direction is commonly connected to the terminals of fin 23, which serves as the source for the finFET. Local wiring 533 is connected to local wiring 535 via M1 wiring 543 extending in the X direction, supplying VDDIO to the source of the finFET.

[0128] A local wiring 534 extending in the Y direction is commonly connected to the terminal of fin 23, which serves as the drain of the finFET. Local wiring 534 is connected via a via to M1 wiring 542, which extends in the X direction.

[0129] The power supply lines 6 and 7 of the second semiconductor chip 202 overlap with the M2 line 551 of the first semiconductor chip 201 in a plan view. Furthermore, the position of the via 561 connecting the M1 line 542 and the M2 line 551 also overlaps with the power supply lines 6 and 7 of the second semiconductor chip 202 in a plan view.

[0130] With the above configuration, the power supply wiring for VSS is provided by power supply wiring 511 formed on the embedded wiring layer of the first semiconductor chip 201 and power supply wiring 7 formed on the second semiconductor chip 202. This allows the resistance value of the VSS supply path to be reduced even if the power supply wiring of the M1 wiring layer of the first semiconductor chip 201 is reduced. In addition, the power supply wiring for VDDIO is provided by power supply wiring 512 formed on the embedded wiring layer of the first semiconductor chip 201 and power supply wiring 6 formed on the second semiconductor chip 202. This allows the resistance value of the VDDIO supply path to be reduced even if the power supply wiring of the M1 wiring layer of the first semiconductor chip 201 is reduced. Therefore, in the first semiconductor chip 201, the output wiring 542 of the M1 wiring layer and the output wiring 551 of the M2 wiring layer can be made thicker, and the number of vias 561 connecting them can be increased, so that a large current can be passed through the output terminals. Furthermore, the power supply wiring 6 and 7 formed on the second semiconductor chip 202 also overlap with the output wiring 551 in a plan view, allowing them to be made thicker.

[0131] In addition, in a plan view, embedded power wiring 511 for supplying VSS and embedded power wiring 512 for supplying VDDIO are formed between transistor N1 and transistor P1. Since the embedded power wiring is formed by embedding metal wiring in grooves provided in the substrate, wells within the substrate, STI, etc., it has the effect of reducing noise propagation through the substrate, etc. Therefore, by providing embedded power wiring between transistors N1 and P1, latch-up immunity can be improved.

[0132] Figure 33 is a plan view showing the layout of the output transistor section in the IO cell 10A shown in Figure 2(a) in this configuration example 3. Figure 33 corresponds to Figure 18 shown in the second embodiment, and explanations of configurations that can be easily inferred from the description of the second embodiment may be omitted.

[0133] In Figure 33, the upper part of the drawing corresponds to the N-conductivity output transistor section 101 that constitutes transistor N1, and the lower part of the drawing corresponds to the P-conductivity output transistor section 102 that constitutes transistor P1. FinFETs are formed on the N-conductivity output transistor section 101 and the P-conductivity output transistor section 102. In addition, power supply wiring 6 and 7 shown in Figure 2(a) are formed on the second semiconductor chip 202. Power supply wiring 7 that supplies VSS is provided in a position that overlaps with the N-conductivity output transistor section 101 in a plan view, and power supply wiring 6 that supplies VDDIO is provided in a position that overlaps with the P-conductivity output transistor section 102 in a plan view.

[0134] The N-conductivity output transistor section 101 has 10 fins 21 extending in parallel in the X direction. Embedded power supply wiring 513 extending in the Y direction is arranged on the left and right sides of the fins 21. The embedded power supply wiring 513 supplies VSS. The embedded power supply wiring 513 is connected to the power supply wiring 7 of the second semiconductor chip 202 via TSV. Gate wiring 22 is arranged across the 10 fins 21 in the Y direction. The fins 21 and gate wiring 22 form a finFET.

[0135] A local wiring 536 is formed above the embedded power wiring 513, extending in the Y direction so as to overlap with the embedded power wiring 513 in a plan view. The local wiring 536 is connected to the embedded power wiring 513 below it via vias.

[0136] A local wiring 537 extending in the Y direction is commonly connected to the terminals of the fin 21, which serves as the source for the finFET. Local wiring 537 is connected to local wiring 536 via M1 wiring 545 extending in the X direction, supplying VSS to the source of the finFET.

[0137] The P-conductivity output transistor section 102 has 10 fins 23 extending in parallel in the X direction. Embedded power supply wiring 514 extending in the Y direction is arranged on the left and right sides of the fins 23. The embedded power supply wiring 514 supplies VDDIO. The embedded power supply wiring 514 is connected to the power supply wiring 6 of the second semiconductor chip 202 via a TSV. Gate wiring 24 is arranged across the 10 fins 23 in the Y direction. The fins 23 and gate wiring 24 form a finFET.

[0138] Above the embedded power wiring 514, a local wiring 540 is formed that extends in the Y direction, overlapping with the embedded power wiring 514 in a plan view. The local wiring 540 is connected to the embedded power wiring 514 below it via vias.

[0139] A local wire 538 extending in the Y direction is commonly connected to the terminals of fin 23, which serves as the source for the finFET. Local wire 538 is connected to local wire 540 via M1 wire 546 extending in the X direction, supplying VDDIO to the source of the finFET.

[0140] A local wiring 539 extending in the Y direction is commonly connected to the terminals of the fin 21, which serves as the drain of the finFET in the N-conductivity output transistor section 101, and to the terminals of the fin 23, which serves as the drain of the finFET in the P-conductivity output transistor section 102. The local wiring 539 is connected to the M1 wiring 547 via a via 562. The local wiring 539 and the M1 wiring 547 correspond to the output wiring. The M1 wiring 547 is connected to an upper layer pad electrode (not shown).

[0141] The power supply lines 6 and 7 of the second semiconductor chip 202 overlap with the M1 line 547 of the first semiconductor chip 201 in a plan view. Furthermore, the placement of the via 562 connecting the local line 539 and the M1 line 547 also overlaps with the power supply lines 6 and 7 of the second semiconductor chip 202 in a plan view.

[0142] With the above configuration, the power supply wiring for VSS is provided by a power supply wiring 513 formed on the embedded wiring layer of the first semiconductor chip 201 and a power supply wiring 7 formed on the second semiconductor chip 202. This makes it possible to reduce the resistance of the VSS supply path without providing power supply wiring on the M1 wiring layer of the first semiconductor chip 201. Furthermore, the power supply wiring for VDDIO is provided by a power supply wiring 514 formed on the embedded wiring layer of the first semiconductor chip 201 and a power supply wiring 6 formed on the second semiconductor chip 202. This makes it possible to reduce the resistance of the VDDIO supply path without providing power supply wiring on the M1 wiring layer of the first semiconductor chip 201. Therefore, in the first semiconductor chip 201, the output wiring 547 of the M1 wiring layer can be made thicker, and the number of vias 562 for connecting to the local wiring 539 can be increased, so that a large current can flow through the output terminal. In addition, the power supply wirings 6 and 7 formed on the second semiconductor chip 202 also overlap with the output wiring 547 in a plan view and can be made thicker.

[0143] In the above-described embodiments, it is assumed that a finFET is formed in the transistor section. However, the transistor formed in the transistor section is not limited to a finFET; for example, a nanosheet FET may also be used. [Industrial applicability]

[0144] This disclosure allows for the configuration of an output circuit that carries a large current through an output pad, which is useful, for example, for improving the performance of a semiconductor chip. [Explanation of symbols]

[0145] 1. Semiconductor integrated circuit device 6,7 Power wiring 11, 12, 13, 14 Embedded power wiring 31, 33, 35, 37 Local wiring 36,38 Local wiring 41,43 Power wiring 42, 45, 46 Output wiring 51, 52 Output wiring 200 Semiconductor integrated circuit equipment 201,202 semiconductor chips 242,245 Output wiring 251 Output Wiring 261,262 beers

Claims

1. An output circuit for outputting a signal from a semiconductor integrated circuit, A first power supply that supplies a first power supply voltage, and a first transistor of a first conductivity type connected between them to the output terminal, It is formed in the embedded wiring layer, extends in a first direction, and has a first power supply wiring that supplies the first power supply voltage, A second power supply wiring is formed in the first wiring layer above the aforementioned embedded wiring layer, extends in the first direction, and supplies the first power supply voltage. A third power supply wiring is formed in a second wiring layer above the first wiring layer, extends in a second direction perpendicular to the first direction, and is connected to the second power supply wiring. A first output wiring is formed in the first wiring layer, extends in the first direction, and is connected to the output terminal, It comprises a second output wiring formed in the second wiring layer, extending in the second direction, and connected to the first output wiring. Output circuit.

2. In the output circuit according to claim 1, The second power supply wiring overlaps with the first power supply wiring in a plan view and is connected to the first power supply wiring via vias. Output circuit.

3. In the output circuit according to claim 1, The first transistor comprises a plurality of FETs arranged in the second direction, A local wiring layer is formed, extends in the second direction, and includes a first local wiring that commonly connects the sources of the plurality of FETs, The first local wiring is connected to the first power wiring and the second power wiring. Output circuit.

4. In the output circuit according to claim 1, The first transistor comprises a plurality of FETs arranged in the first direction, A local wiring layer is formed, extends in the second direction, and includes a first local wiring that commonly connects the sources of the plurality of FETs, The first local wiring is connected to the first power wiring and the second power wiring. Output circuit.

5. In the output circuit according to claim 1, Between the first power supply and the output terminal, a second transistor of the first conductivity type is provided, connected in series with the first transistor. The first transistor and the second transistor have structures that constitute the channel, gate, source, and drain that are separated from each other. Output circuit.

6. An output circuit for outputting a signal from a semiconductor integrated circuit, A first power supply that supplies a first power supply voltage, and a first transistor of a first conductivity type connected between them to the output terminal, It is formed in the embedded wiring layer, extends in a first direction, and has a first power supply wiring that supplies the first power supply voltage, A second power supply wiring is formed in a first wiring layer above the aforementioned embedded wiring layer, extends in a second direction perpendicular to the first direction, and supplies the first power supply voltage. A third power supply wiring is formed in the second wiring layer above the first wiring layer, extends in the first direction, and is connected to the second power supply wiring, A first output wiring is formed in the first wiring layer, extends in the second direction, and is connected to the output terminal, It comprises a second output wiring formed in the second wiring layer, extending in the first direction, and connected to the first output wiring. Output circuit.

7. In the output circuit according to claim 6, The first transistor comprises a plurality of FETs arranged in the second direction, The second power supply wiring is connected in common to the sources of the multiple FETs. Output circuit.

8. In the output circuit according to claim 6, The system comprises a second power supply that supplies a second power supply voltage and a second transistor of a second conductivity type connected between the output terminal, The first power supply wiring is positioned between the first transistor and the second transistor in a plan view. Output circuit.

9. In the output circuit according to claim 6, The first transistor comprises a plurality of FETs arranged in the first direction, The second power supply wiring is connected in common to the sources of the multiple FETs. Output circuit.

10. In the output circuit according to claim 6, Between the first power supply and the output terminal, a second transistor of the first conductivity type is provided, connected in series with the first transistor. The first transistor and the second transistor have structures that constitute the channel, gate, source, and drain that are separated from each other. Output circuit.

11. An output circuit is configured in a semiconductor integrated circuit device comprising a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip, wherein the back surface of the first semiconductor chip and the main surface of the second semiconductor chip face each other, In the first semiconductor chip, A first power supply that supplies a first power supply voltage, and a first transistor of a first conductivity type connected between them to the output terminal, It is formed in the embedded wiring layer, extends in a first direction, and has a first power supply wiring that supplies the first power supply voltage, A first output wiring is formed in the first wiring layer above the aforementioned embedded wiring layer, extends in the first direction, and is connected to the output terminal, It comprises a second output wiring formed in a second wiring layer above the first wiring layer, extending in a second direction perpendicular to the first direction, and connected to the first output wiring, In the second semiconductor chip, It comprises a second power supply wiring that extends in the second direction and overlaps with the second output wiring in a plan view, The second power supply wiring is connected to the first power supply wiring via vias formed on the back side of the first semiconductor chip. Output circuit.

12. In the output circuit according to claim 11, The second output wiring overlaps with the first output wiring in a plan view and is connected to the first output wiring via a first via. The position of the first via overlaps with the second power supply wiring in a plan view. Output circuit.

13. An output circuit is configured in a semiconductor integrated circuit device comprising a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip, wherein the back surface of the first semiconductor chip and the main surface of the second semiconductor chip face each other, In the first semiconductor chip, A first power supply that supplies a first power supply voltage, and a first transistor of a first conductivity type connected between them to the output terminal, It is formed in the embedded wiring layer, extends in a first direction, and has a first power supply wiring that supplies the first power supply voltage, It is formed in the first wiring layer above the aforementioned embedded wiring layer, extends in a second direction perpendicular to the first direction, and is connected to the output terminal as a first output wiring, It comprises a second output wiring formed in a second wiring layer above the first wiring layer, extending in the first direction, and connected to the first output wiring, In the second semiconductor chip, It comprises a second power supply wiring that extends in the first direction and overlaps with the second output wiring in a plan view, The second power supply wiring is connected to the first power supply wiring via vias formed on the back side of the first semiconductor chip. Output circuit.

14. In the output circuit according to claim 13, The second output wiring overlaps with the first output wiring in a plan view and is connected to the first output wiring via a first via. The position of the first via overlaps with the second power supply wiring in a plan view. Output circuit.

15. In the output circuit according to claim 13, The system comprises a second power supply that supplies a second power supply voltage and a second transistor of a second conductivity type connected between the output terminal, The first power supply wiring is positioned between the first transistor and the second transistor in a plan view. Output circuit.

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