Silicon carbide semiconductor equipment
The silicon carbide semiconductor device addresses source pad migration by using a passivation film structure with insulating separation portions and plating films to manage heat and moisture, ensuring reliable conductivity and heat dissipation.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- MITSUMI ELECTRIC CO LTD
- Filing Date
- 2022-06-23
- Publication Date
- 2026-07-23
AI Technical Summary
Conventional silicon carbide semiconductor devices experience migration of the source pad due to heat generation, particularly during short circuits, which can lead to conductivity issues and reliability concerns.
The silicon carbide semiconductor device incorporates a specific passivation film structure with insulating separation portions and plating films that prevent solder from bridging the source and gate pads, allowing heat to be dissipated effectively through the plating films, while maintaining moisture resistance and flexibility.
This design suppresses source pad migration, enhances heat dissipation, and improves moisture resistance, resulting in improved reliability and conductivity.
Smart Images
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Abstract
Description
Technical Field
[0001] The present disclosure relates to a silicon carbide semiconductor device.
[0002] This application claims priority based on Japanese Application No. 2021-168094 filed on October 13, 2021, and incorporates all the descriptions described in the above Japanese application.
Background Art
[0003] As a silicon carbide semiconductor device used in a power module, a silicon carbide semiconductor device in which a metal plate is connected to a source pad of a semiconductor chip using solder has been proposed. When a gate pad is provided near the source pad, a passivation film is provided so that the solder provided on the source pad does not reach the gate pad when the solder melts.
Prior Art Documents
Non-Patent Documents
[0004]
Non-Patent Document 1
Summary of the Invention
[0005] The silicon carbide semiconductor device of the present disclosure comprises a silicon carbide substrate having a first main surface, a gate pad and a source pad formed on the first main surface, a first passivation film formed on the gate pad and the source pad, and a second passivation film formed on the first passivation film, wherein the first passivation film has a first insulating separation portion between the gate pad and the source pad, a first opening that exposes the gate pad and has a first edge, and a second opening that exposes the source pad and has a second edge, and further, inside the first opening The second passivation film has a first plating film formed on the gate pad and a second plating film formed on the source pad inside the second opening, and the second passivation film is also formed on the first and second plating films, and the second passivation film has a second insulating separation portion that covers the first insulating separation portion, a third opening that exposes the first plating film and has a third edge, and a fourth opening that exposes the second plating film and has a fourth edge, and when viewed from a plane in a direction perpendicular to the first main surface, the first edge is outside the third edge and the second edge is outside the fourth edge Furthermore, when viewed from a plane perpendicular to the first main surface, the first distance between the first end of the source pad closest to the gate pad and the second edge is 80% or less of the second distance between the first end and the fourth edge. ru. [Brief explanation of the drawing]
[0006] [Figure 1] Figure 1 is a top view showing a silicon carbide semiconductor device according to an embodiment. [Figure 2] Figure 2 is a cross-sectional view (part 1) showing a silicon carbide semiconductor device according to an embodiment. [Figure 3] Figure 3 is a cross-sectional view (part 2) showing a silicon carbide semiconductor device according to the embodiment. [Figure 4] Figure 4 is a cross-sectional view showing the structure of a unit cell. [Figure 5] Figure 5 is a top view showing a silicon carbide semiconductor device according to a modified embodiment. [Figure 6] Figure 6 is a cross-sectional view showing a silicon carbide semiconductor device according to a modified embodiment. [Modes for carrying out the invention]
[0007] [Issues this disclosure aims to address] In conventional silicon carbide semiconductor devices, migration may occur in the source pad when a large current flows and generates a large amount of heat, such as during a short circuit.
[0008] This disclosure aims to provide a silicon carbide semiconductor device that can suppress source pad migration due to heat generation.
[0009] [Effects of this disclosure] According to this disclosure, migration of the source pad due to heat generation can be suppressed.
[0010] The implementation methods are described below.
[0011] [Description of Embodiments in this Disclosure] First, embodiments of this disclosure will be listed and described. In the following description, the same or corresponding elements will be denoted by the same reference numeral, and the same description will not be repeated. In the crystallographic descriptions in this specification, individual orientations are indicated by [], collective orientations by <>, individual planes by () and collective planes by {}. Also, while negative crystallographic exponents are usually indicated by placing a "-" (bar) above the number, in this specification a negative sign is placed before the number. In this specification and drawings, the X1-X2 direction, the Y1-Y2 direction and the Z1-Z2 direction are mutually orthogonal directions. A plane containing the X1-X2 direction and the Y1-Y2 direction is described as an XY plane, a plane containing the Y1-Y2 direction and the Z1-Z2 direction is described as a YZ plane, and a plane containing the Z1-Z2 direction and the X1-X2 direction is described as a ZX plane. For convenience, the Z1-Z2 direction is considered the up and down direction, with the Z1 side being the upper side and the Z2 side being the lower side. Furthermore, a planar view refers to viewing an object from the Z1 side, and a planar shape refers to the shape of the object as viewed from the Z1 side.
[0012] [1] A silicon carbide semiconductor device according to one aspect of the present disclosure includes a silicon carbide substrate having a first main surface, a gate pad and a source pad formed on the first main surface, a first passivation film formed on the gate pad and the source pad, and a second passivation film formed on the first passivation film, wherein the first passivation film has a first insulating separation portion between the gate pad and the source pad, a first opening that exposes the gate pad and has a first edge, and a second opening that exposes the source pad and has a second edge, and further inside the first opening The second passivation film comprises a first plating film formed on the gate pad and a second plating film formed on the source pad inside the second opening, the second passivation film also formed on the first and second plating films, the second passivation film having a second insulating separation portion covering the first insulating separation portion, a third opening that exposes the first plating film and has a third edge, and a fourth opening that exposes the second plating film and has a fourth edge, the first edge being outside the third edge and the second edge being outside the fourth edge when viewed from a direction perpendicular to the first main surface.
[0013] When viewed from a plane perpendicular to the first main surface, the first edge is outside the third edge, and the second edge is outside the fourth edge. Therefore, even if the first and second plating films are widely formed in a plane parallel to the first main surface, when the metal plate is connected to the source pad using solder, the molten solder will hit the gate pad. Do It is difficult to reach. Therefore, conductivity between the source pad and gate pad via solder can be suppressed. As a result, heat can be easily released from the silicon carbide substrate in the direction in which the first main surface is located through the first and second plating films, and migration of the source pad due to heat generation can be suppressed.
[0014] [2] In [1], when viewed from a plane perpendicular to the first main surface, the first distance between the first end of the source pad closest to the gate pad and the second edge may be 80% or less of the second distance between the first end and the fourth edge. In this case, it is easier to form a wider second plating film and to suppress migration of the source pad due to heat generation.
[0015] [3] In [2], the first distance may be 60% or less of the second distance. In this case, migration of the source pad due to heat generation is more easily suppressed.
[0016] [4] In [3], the first distance may be 40% or less of the second distance. In this case, migration of the source pad due to heat generation is further suppressed.
[0017] [5] In any of [1] to [4], the first distance between the first end of the source pad closest to the gate pad and the second edge when viewed in plan from a direction perpendicular to the first main surface may be 30 μm or less. In this case, it is easier to form a wide second plating film and to suppress migration of the source pad due to heat generation.
[0018] [6] In any of [1] to [5], the silicon carbide substrate has an active region containing a plurality of unit cells and a terminal region provided around the active region, and when viewed in plan from a direction perpendicular to the first main surface, the second edge may be separated from the plurality of unit cells. In this case, heat generated in each unit cell is easily transferred to the source pad, heat is less likely to accumulate inside the silicon carbide semiconductor device, and migration of the source pad due to heat generation is easily suppressed.
[0019] 〔7〕 In any one of 〔1〕 to 〔6〕, the silicon carbide substrate has an active region including a plurality of unit cells and a termination region provided around the active region, and the termination region may be covered by both the first passivation film and the second passivation film. In this case, excellent moisture resistance can be obtained in the termination region, and good reliability can be obtained.
[0020] 〔8〕 In any one of 〔1〕 to 〔7〕, the first passivation film may be an inorganic film, and the second passivation film may be an organic film. In this case, good moisture resistance by the first passivation film and good flexibility by the second passivation film can be obtained.
[0021] [Details of Embodiments of the Present Disclosure] Embodiments of the present disclosure relate to a so-called vertical MOSFET (silicon carbide semiconductor device). FIG. 1 is a top view showing a silicon carbide semiconductor device according to an embodiment. FIGS. 2 and 3 are cross-sectional views showing the silicon carbide semiconductor device according to the embodiment. FIG. 2 corresponds to a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 corresponds to a cross-sectional view taken along line III-III in FIG. 1. FIG. 4 is a cross-sectional view showing the configuration of a unit cell.
[0022] As shown in FIGS. 1 to 4, the silicon carbide semiconductor device 100 according to the present embodiment mainly includes a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, a source electrode 60, a drain electrode 70, an interlayer insulating film 20, a first passivation film 210, a second passivation film 220, a gate pad 110, a first plating film 112, a source pad 120, and a second plating film 122.
[0023] The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 located on the silicon carbide single crystal substrate 50. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are made of, for example, polytype 4H hexagonal silicon carbide. The silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen (N) and has an n-type conductivity type (first conductivity type). A semiconductor element is formed on the silicon carbide substrate 10.
[0024] The first main surface 1 is the {0001} surface or a surface inclined by an off-angle of 8° or less in the off-direction. Preferably, the first main surface 1 is the (000-1) surface or a surface inclined by an off-angle of 8° or less in the off-direction. The off-direction may be, for example, the <11-20> direction or the <1-100> direction. The off-angle may be, for example, 1° or more or 2° or more. The off-angle may be 6° or less or 4° or less.
[0025] The silicon carbide semiconductor device 100, when viewed from above from a direction perpendicular to the first main surface 1, has an active region 6 and a termination region 7 provided around the active region 6. The active region 6 is a region in which a plurality of unit cells 8 are arranged. The unit cells 8 have their longitudinal direction in the X1-X2 direction and are arranged in the Y1-Y2 direction. The dimensions in the Y1-Y2 direction of each unit cell 8 are common. Each unit cell 8 has one set of gate trenches 5 and gate electrodes 82. The unit cells 8 are arranged at a constant pitch in the Y1-Y2 direction.
[0026] In this embodiment, a field-effect transistor is formed on the silicon carbide substrate 10 as an example of a semiconductor element. The silicon carbide epitaxial layer 40 mainly comprises a drift region 11, a body region 12, a source region 13, a first embedded region 15A, a second embedded region 15B, a first contact region 16A, a second contact region 16B, an embedded junction termination extension (JTE) region 17, and a surface JTE region 18. The body region 12, the source region 13, the first embedded region 15A, and the first contact region 16A are located within the active region 6. The embedded JTE region 17 and the surface JTE region 18 are located within the termination region 7. The drift region 11 extends across the entire active region 6 and the termination region 7. The second embedded region 15B and the second contact region 16B extend across a portion of the active region 6 and a portion of the termination region 7.
[0027] The drift region 11 contains n-type impurities such as nitrogen or phosphorus (P), and has an n-type conductivity. Preferably, the addition of n-type impurities to the drift region 11 is carried out by impurity addition during the epitaxial growth of the drift region 11, rather than by ion implantation.
[0028] The body region 12 is located on the drift region 11. The body region 12 contains p-type impurities such as aluminum (Al) and has a p-type conductivity (second conductivity).
[0029] The source region 13 is provided on the body region 12 so as to be separated from the drift region 11 by the body region 12. The source region 13 contains n-type impurities such as nitrogen or phosphorus and has an n-type conductivity. The source region 13 constitutes the first main surface 1.
[0030] The first contact region 16A contains p-type impurities such as aluminum and has a p-type conductivity. The first contact region 16A constitutes the first main surface 1. The first contact region 16A penetrates the source region 13 and contacts the body region 12.
[0031] Multiple gate trenches 5 are provided on the first main surface 1. The gate trenches 5 extend in the X1-X2 direction, and multiple gate trenches 5 are arranged in the Y1-Y2 direction. The gate trenches 5 have a bottom surface 4 consisting of a drift region 11. The gate trenches 5 have side surfaces 3 that penetrate the source region 13 and the body region 12 and connect to the bottom surface 4. The bottom surface 4 is, for example, a plane parallel to the second main surface 2. The angle of the side surface 3 with respect to the plane containing the bottom surface 4 is, for example, 50° or more and 65° or less. This angle may be, for example, 55° or more. This angle may be, for example, 60° or less. The side surface 3 preferably has a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent mobility. The angle of the side surface 3 with respect to the plane containing the bottom surface 4 may be 90°.
[0032] The first embedded region 15A contains p-type impurities such as aluminum and has a p-type conductivity. The first embedded region 15A is located closer to the second main surface 2 (on the Z2 side) than the first contact region 16A. The first contact region 16A is located closer to the first main surface 1 (on the Z1 side) than the first embedded region 15A. The first embedded region 15A is in contact with the first contact region 16A. The first embedded region 15A is formed at a deeper position than the gate trench 5. The upper end surface of the first embedded region 15A is located closer to the second main surface 2 (on the Z2 side) than the bottom surface 4 of the gate trench 5.
[0033] The second contact region 16B contains p-type impurities, such as aluminum, and has a p-type structure. The second contact region 16B constitutes the first main surface 1. The second contact region 16B is formed in an annular shape in plan view. The second contact region 16B is formed from the edge of the active region 6 to the terminal region 7. The depth of the second contact region 16B may be equal to the depth of the first contact region 16A.
[0034] The second embedded region 15B contains p-type impurities such as aluminum and has a p-type conductivity. The second embedded region 15B is formed in an annular shape in plan view. The second embedded region 15B is located closer to the second main surface 2 (on the Z2 side) than the second contact region 16B. The second contact region 16B is located closer to the first main surface 1 (on the Z1 side) than the second embedded region 15B. The second embedded region 15B is in contact with the second contact region 16B. The second embedded region 15B is formed at a depth greater than the gate trench 5. The upper end surface of the second embedded region 15B is located closer to the second main surface 2 (on the Z2 side) than the bottom surface 4 of the gate trench 5. The depth of the second embedded region 15B may be equal to the depth of the first embedded region 15A.
[0035] The embedded JTE region 17 is in contact with the second embedded region 15B in a direction parallel to the first main surface 1. The embedded JTE region 17 is formed in an annular shape in plan view. The embedded JTE region 17 contains p-type impurities such as aluminum and has a p-type conductivity. The embedded JTE region 17 is separated from the first main surface 1 and the second main surface 2. A portion of the upper end surface of the embedded JTE region 17 is in contact with the lower end surface of the second contact region 16B.
[0036] The surface JTE region 18 is in contact with the second contact region 16B in a direction parallel to the first main surface 1. The surface JTE region 18 is formed in an annular shape in plan view. The surface JTE region 18 contains p-type impurities such as aluminum and has a p-type conductivity. The surface JTE region 18 is located above the embedded JTE region 17. The surface JTE region 18 is separated from the embedded JTE region 17. The surface JTE region 18 is located closer to the first main surface 1 (on the Z1 side) than the embedded JTE region 17. The embedded JTE region 17 is located closer to the second main surface 2 (on the Z2 side) than the surface JTE region 18. The surface JTE region 18 constitutes the first main surface 1. A part of the drift region 11 is located between the surface JTE region 18 and the embedded JTE region 17. For example, the concentration of p-type impurities in the surface JTE region 18 is lower than the concentration of p-type impurities in the second contact region 16B.
[0037] A gate insulating film 81 is provided that is in contact with the side surface 3 and the bottom surface 4. The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is made of a material containing, for example, silicon dioxide. The gate insulating film 81 is in contact with the drift region 11 at the bottom surface 4. The gate insulating film 81 is in contact with the source region 13, the body region 12, and the drift region 11, respectively, at the side surface 3. The gate insulating film 81 may also be in contact with the source region 13 at the first main surface 1.
[0038] A gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is made of, for example, polysilicon (polySi) containing conductive impurities. The gate electrode 82 is located inside the gate trench 5.
[0039] In the region within the active region 6, outside the region where multiple unit cells 8 are provided, a gate insulating film 81 is also provided on the second contact region 16B. In this region, a gate contact portion 113 is provided on the gate insulating film 81. The gate contact portion 113 is a part of the gate electrode 82.
[0040] An interlayer insulating film 20 is provided in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 20 is made of a material containing, for example, silicon dioxide. A first contact hole 21 for the gate is formed in the interlayer insulating film 20. The gate contact portion 113 is exposed from the interlayer insulating film 20 through the first contact hole 21. Second contact holes 22 for the source are formed in the interlayer insulating film 20 and the gate insulating film 81 at regular intervals in the Y1-Y2 direction. The second contact holes 22 are formed within a region where a plurality of unit cells 8 are provided. The second contact holes 22 are arranged such that the gate trench 5 is located between adjacent second contact holes 22 in the Y1-Y2 direction. The second contact holes 22 extend in the X1-X2 direction. The source region 13 and the first contact region 16A are exposed from the interlayer insulating film 20 and the gate insulating film 81 through the second contact holes 22.
[0041] The source electrode 60 is located within the second contact hole 22 and is in contact with the first main surface 1. On the first main surface 1, the source electrode 60 is in contact with the source region 13 and the first contact region 16A. The source electrode 60 is made of a material containing, for example, nickel silicide (NiSi). The source electrode 60 may also be made of a material containing titanium (Ti), aluminum, and silicon. The source electrode 60 is ohmic-bonded to the source region 13 and the first contact region 16A. In other words, the source electrode 60 is connected to the silicon carbide substrate 10 through the second contact hole 22.
[0042] The gate pad 110 is provided on the interlayer insulating film 20 and is in contact with the gate contact portion 113 through the first contact hole 21. The gate pad 110 is made of a material including, for example, aluminum, aluminum alloy, copper (Cu), or copper alloy. The gate pad 110 may also be made of a material including aluminum and copper. A barrier metal film, such as a titanium nitride (TiN) film, may be provided between the gate pad 110 and the interlayer insulating film 20. The gate pad 110 is electrically connected to all gate electrodes 82 via the gate contact portion 113.
[0043] The source pad 120 is provided on the interlayer insulating film 20 and contacts the source region 13 and the first contact region 16A on the first main surface 1 through the second contact hole 22. The source electrode 60 is in contact with The source pad 120 is made of a material including, for example, aluminum, an aluminum alloy, copper, or a copper alloy. The source pad 120 is electrically insulated from the gate electrode 82 by an interlayer insulating film 20. The source pad 120 may be made of a material including aluminum and copper. A barrier metal film, such as a titanium nitride (TiN) film, may be provided between the source pad 120 and the interlayer insulating film 20. The surface of the source pad 120 may have irregularities that reflect the second contact hole 22.
[0044] The first passivation film 210 is formed on the gate pad 110 and the source pad 120. The first passivation film 210 is an inorganic film, such as a silicon nitride film. The first passivation film 210 has a first insulating separation portion 211 between the gate pad 110 and the source pad 120. The first passivation film 210 has a first opening 212 that exposes the gate pad 110 and a second opening 213 that exposes the source pad 120. The first opening 212 has a first edge 214, and the second opening 213 has a second edge 215. When viewed from above from a direction perpendicular to the first main surface 1, the shapes of the first opening 212 and the second opening 213 are rectangular.
[0045] The first plating film 112 is formed on the gate pad 110 inside the first opening 212. The first plating film 112 may include, for example, a nickel (Ni) plating film, a palladium (Pd) plating film, and a gold (Au) plating film. The Ni plating film is formed on the gate pad 110 and contains phosphorus (P). The Pd plating film is formed on the Ni plating film. The Au plating film is formed on the Pd plating film.
[0046] The second plating film 122 is formed on the source pad 120 inside the second opening 213. The second plating film 122 may include, for example, a nickel plating film, a palladium plating film, and a gold plating film. The Ni plating film is formed on the source pad 120 and contains phosphorus. The Pd plating film is formed on the Ni plating film. The Au plating film is formed on the Pd plating film.
[0047] The second passivation film 220 is formed on the first passivation film 210, the first plating film 112, and the second plating film 122. The second passivation film 220 is an organic film, such as a polyimide film. The second passivation film 220 has a second insulating separation portion 221 that covers the first insulating separation portion 211. The second passivation film 220 has a third opening 222 that exposes the first plating film 112 and a fourth opening 223 that exposes the second plating film 122. The third opening 222 has a third edge 224, and the fourth opening 223 has a fourth edge 225. When viewed from above from a direction perpendicular to the first main surface 1, the shapes of the third opening 222 and the fourth opening 223 are rectangular. When viewed from a plane perpendicular to the first main surface 1, the first edge 214 is outside the third edge 224, and the second edge 215 is outside the fourth edge 225.
[0048] The terminal region 7 is covered by both the first passivation film 210 and the second passivation film 220. The first passivation film 210 is formed to expose the peripheral edge of the first main surface 1. The second passivation film 220 covers the first passivation film 210 from above and the sides and is in contact with the first main surface 1 outside of the first passivation film 210.
[0049] Next, the effects and advantages of the silicon carbide semiconductor device 100 according to this embodiment will be described.
[0050] In the silicon carbide semiconductor device 100 according to this embodiment, when viewed from a plane perpendicular to the first main surface 1, the first edge 214 of the first opening 212 is outside the third edge 224 of the third opening 222, and the second edge 215 of the second opening 213 is outside the fourth edge 225 of the fourth opening 223. Therefore, even if the first plating film 112 and the second plating film 122 are widely formed in a plane parallel to the first main surface 1 (XY plane), when a metal plate is connected to the source pad 120 using solder, the molten solder has difficulty reaching the gate pad 110. Consequently, conductivity between the source pad 120 and the gate pad 110 via solder can be suppressed. Therefore, heat can be easily released from the silicon carbide substrate 10 in the direction in which the first main surface 1 is located through the first plating film 112 and the second plating film 122, and migration of the source pad 120 due to heat generation can be suppressed. A bonding wire may also be connected to the source pad 120.
[0051] Furthermore, since the terminal region 7 is covered by both the first passivation film 210 and the second passivation film 220, excellent moisture resistance is obtained in the terminal region 7, resulting in good reliability. In particular, since the second passivation film 220 covers the first passivation film 210 from above and the side, and is in contact with the first main surface 1 on the outside of the first passivation film 210, good resistance to moisture intrusion from the side is also obtained.
[0052] Furthermore, if the first passivation film 210 is an inorganic film and the second passivation film 220 is an organic film, then good moisture resistance from the first passivation film 210 and good flexibility from the second passivation film 220 can be obtained.
[0053] Furthermore, when viewed from a plane perpendicular to the first main surface 1, the first distance L1 between the first end 121 closest to the gate pad 110 of the source pad 120 and the second edge 215 is preferably 80% or less of the second distance L2 between the first end 121 and the fourth edge 225. This is because it facilitates the formation of a wide second plating film 122 and makes it easier to suppress migration of the source pad 120 due to heat generation. The first distance L1 is more preferably 60% or less of the second distance L2, and even more preferably 40% or less of the second distance L2.
[0054] The side surface of the source pad 120 closest to the gate pad 110, the inner wall surface of the second opening 213, and the inner wall surface of the fourth opening 223 may or may not be perpendicular to the first main surface 1. If the side surface of the source pad 120 closest to the gate pad 110 is not perpendicular to the first main surface 1, the first end 121 in the plan view refers to the part of the side surface of the source pad 120 closest to the gate pad 110 that is furthest from the gate pad 110. If the inner wall surface of the second opening 213 is not perpendicular to the first main surface 1, the second edge 215 in the plan view refers to the part of the inner wall surface of the second opening 213 that is furthest from the gate pad 110. If the inner wall surface of the fourth opening 223 is not perpendicular to the first main surface 1, the fourth edge 225 in the plan view refers to the part of the inner wall surface of the fourth opening 223 that is furthest from the gate pad 110.
[0055] Furthermore, the first distance L1 is preferably 30 μm or less. This is because it facilitates the formation of a wide second plating film 122 and makes it easier to suppress migration of the source pad 120 due to heat generation. The first distance L1 is more preferably 25 μm or less, and even more preferably 20 μm or less.
[0056] When viewed from above in a direction perpendicular to the first main surface 1, it is preferable that the second edge 215 is separated from all the unit cells 8. In other words, when viewed from above in a direction perpendicular to the first main surface 1, it is preferable that the first passivation film 210 does not overlap with the unit cells 8. This is because the heat generated in each unit cell 8 is easily transferred to the source pad 120, making it less likely for heat to accumulate inside the silicon carbide semiconductor device 100, and thus making it easier to suppress migration of the source pad 120 due to heat generation.
[0057] A gate runner may be connected to the gate pad 110, and a plating film may also be formed on the gate runner. Figure 5 is a top view showing a modified silicon carbide semiconductor device according to the embodiment. Figure 6 is a cross-sectional view showing a modified silicon carbide semiconductor device according to the embodiment. Figure 6 corresponds to a cross-sectional view along the line VI-VI in Figure 5.
[0058] As shown in Figure 5, the silicon carbide semiconductor device 100A according to a modified embodiment has three gate runners 110A connected to a gate pad 110. Each gate runner 110A has a portion extending in the Y1-Y2 direction. The source pad 120 is provided between two adjacent gate runners 110A in the X1-X2 direction.
[0059] As shown in Figure 6, in addition to the first contact hole 21, a third contact hole 21A for the gate runner 110A is formed in the interlayer insulating film 20. The gate contact portion 113 is exposed from the interlayer insulating film 20 through the third contact hole 21A.
[0060] The first passivation film 210 has a first insulating isolation portion 211, as well as a third insulating isolation portion 211A between the gate runner 110A and the source pad 120. The first passivation film 210 has a first opening 212 and a second opening 213, as well as a fifth opening 212A that exposes the gate runner 110A. The silicon carbide semiconductor device 100A has a third plating film 112A formed on the gate runner 110A inside the fifth opening 212A. The third plating film 112A may be, for example, a nickel plating film, a palladium plating film, or a gold plating film. The Ni plating film is formed on the gate runner 110A and contains phosphorus. The Pd plating film is formed on the Ni plating film. The Au plating film is formed on the Pd plating film. The third plating film 112A is covered by a second passivation film 220.
[0061] The other components are the same as in the embodiment.
[0062] The silicon carbide semiconductor device 100A according to the modified example also provides the same effects as the first embodiment. Furthermore, since heat is transferred through the third plating film 112A, the uniformity of the internal temperature of the silicon carbide semiconductor device 100A can be improved.
[0063] Although embodiments have been described in detail above, the present invention is not limited to any particular embodiment, and various modifications and changes are possible within the scope described in the claims. [Explanation of Symbols]
[0064] 1. First main surface 2. Second main surface 3 Sides 4. Bottom 5 Gate Trench 6 Active area 7 Termination area 8 unit cells 10 Silicon carbide substrate 11. Drift Region 12 Body Region 13 Source Area 15A First implantation area 15B Second implantation area 16A First Contact Area 16B Second Contact Area 17 Embedded JTE area 18 Surface JTE area 20 Interlayer insulating film 21. First Contact Hole 21A Third Contact Hole 22 Second Contact Hole 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 source electrodes 70 Drain electrode 81 Gate Insulator 82 Grid gate 100, 100A Silicon Carbide Semiconductor Device 110 Gate Pad 110A Gate Runner 112 First Plating Film 112A Third plating film 113 Gate Contact Section 120 Sourcepad 121 First end 122 Second plating film 210 First Passivation Membrane 211 First Insulation Separation Section 211A Third Insulation Separation Section 212 First opening 212A 5th opening 213 Second opening 214 First Edge 215 Second Edge 220 Second Passivation Membrane 221 Second Insulation Separation Section 222 Third opening 223 Fourth opening 224 Third Edge 225 The 4th Edge
Claims
1. A silicon carbide substrate having a first main surface, A gate pad and a source pad formed on the first main surface, A first passivation film formed on the gate pad and the source pad, A second passivation film formed on the first passivation film, It has, The first passivation membrane is The first insulating separation portion between the gate pad and the source pad, The gate pad is exposed, and a first opening having a first edge is provided, The source pad is exposed, and a second opening having a second edge is provided, It has, Furthermore, A first plating film formed on the gate pad inside the first opening, The second plating film formed on the source pad inside the second opening, It has, The second passivation film is also formed on the first plating film and the second plating film. The aforementioned second passivation membrane is A second insulating separation portion covers the first insulating separation portion, The first plating film is exposed, and a third opening having a third edge is provided, The second plating film is exposed, and a fourth opening having a fourth edge is provided, It has, When viewed from a plane perpendicular to the first principal surface, The first edge is outside the third edge, The second edge is outside the fourth edge, A silicon carbide semiconductor device, wherein, when viewed from a plane perpendicular to the first main surface, the first distance between the first end of the source pad closest to the gate pad and the second edge is 80% or less of the second distance between the first end and the fourth edge.
2. The silicon carbide semiconductor device according to claim 1, wherein the first distance is 60% or less of the second distance.
3. The silicon carbide semiconductor device according to claim 2, wherein the first distance is 40% or less of the second distance.
4. The silicon carbide semiconductor device according to any one of claims 1 to 3, wherein, when viewed from a plane perpendicular to the first main surface, the first distance between the first end of the source pad closest to the gate pad and the second edge is 30 μm or less.
5. A silicon carbide substrate having a first main surface, A gate pad and a source pad formed on the first main surface, A first passivation film formed on the gate pad and the source pad, A second passivation film formed on the first passivation film, It has, The first passivation membrane is The first insulating separation portion between the gate pad and the source pad, The gate pad is exposed, and a first opening having a first edge is provided, The source pad is exposed, and a second opening having a second edge is provided, It has, Furthermore, A first plating film formed on the gate pad inside the first opening, The second plating film formed on the source pad inside the second opening, It has, The second passivation film is also formed on the first plating film and the second plating film. The aforementioned second passivation membrane is A second insulating separation portion covers the first insulating separation portion, The first plating film is exposed, and a third opening having a third edge is provided, The second plating film is exposed, and a fourth opening having a fourth edge is provided, It has, When viewed from a plane perpendicular to the first principal surface, The first edge is outside the third edge, The second edge is outside the fourth edge, A silicon carbide semiconductor device, wherein, when viewed from a plane perpendicular to the first main surface, the first distance between the first end of the source pad closest to the gate pad and the second edge is 30 μm or less.
6. The silicon carbide substrate is An active region containing multiple unit cells, A terminal region provided around the active region, It has, The silicon carbide semiconductor device according to claim 1, claim 2, claim 3, or claim 5, wherein, when viewed from a plan view in a direction perpendicular to the first main surface, the second edge is separated from the plurality of unit cells.
7. The silicon carbide substrate is An active region containing multiple unit cells, A terminal region provided around the active region, It has, The silicon carbide semiconductor device according to claim 1, claim 2, claim 3, or claim 5, wherein the termination region is covered by both the first passivation film and the second passivation film.
8. The first passivation film is an inorganic film, The silicon carbide semiconductor device according to claim 1, claim 2, claim 3, or claim 5, wherein the second passivation film is an organic film.