Semiconductor equipment

Abstract

To improve the power generation efficiency of on-chip solar cells.SOLUTION: A semiconductor device 100 includes a first region and a second region, the first region is provided with an integrated circuit and a light shielding portion SU that covers the integrated circuit in a two-dimensional manner, and the second region is provided with a light receiving region of a solar cell. Here, in the first region, below the light shielding portion SU, a metal electrode PE and a metal electrode NE are formed which are electrically connected to the light receiving region of the solar cell.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a technology that is effective when applied to a semiconductor device that combines an integrated circuit and a solar cell. [Background technology]

[0002] Non-patent document 1 describes a technology for combining integrated circuits and solar cells. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Fumio Horiguchi, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59.NO 6. JUNE 2012 [Overview of the project] [Problems that the invention aims to solve]

[0004] For example, in Fig. 1(b) of Non-Patent Document 1, in a semiconductor device that combines an integrated circuit and a solar cell, an electrode with light-shielding properties is placed in the light-receiving region of the solar cell. In this case, the electrode blocks a portion of the sunlight incident on the light-receiving region, thus hindering the improvement of the solar cell's power generation efficiency. Therefore, improvements to the electrode arrangement are desired in order to improve the power generation efficiency of the solar cell. [Means for solving the problem]

[0005] In one embodiment, the semiconductor device has a first region and a second region. The first region is provided with an integrated circuit and a light-shielding portion that covers the integrated circuit in a planar manner, and the second region is provided with a light-receiving region for a solar cell. In the first region, an electrode is formed below the light-shielding portion that is electrically connected to the light-receiving region for the solar cell. [Effects of the Invention]

[0006] According to one embodiment, the power generation efficiency of solar cells can be improved. [Brief explanation of the drawing]

[0007] [Figure 1] This is a schematic perspective view showing the configuration of a semiconductor device in its implemented form. [Figure 2] This is a top view showing the schematic configuration of a semiconductor device. [Figure 3] This is a cross-sectional view taken along line AA in Figure 2. [Figure 4] This is a schematic diagram showing the simulation model in the comparative example. [Figure 5] This is a schematic diagram showing the simulation model in the embodiment. [Figure 6] These graphs show the IV characteristics of on-chip solar cells in both the comparative example and the example. [Modes for carrying out the invention]

[0008] In all the drawings illustrating the embodiments, the same reference numeral is used for identical components, and repeated explanations of them are omitted. Hatching may be used even in plan views to improve clarity.

[0009] <On-chip solar cells> For example, an integrated circuit formed on a semiconductor chip operates by receiving power from an external source. In other words, an external power supply or battery is necessary to operate the integrated circuit.

[0010] In this regard, on-chip solar cells have attracted attention in recent years. An on-chip solar cell is a solar cell that can be integrated on the same semiconductor chip as an integrated circuit. With this on-chip solar cell, the solar cell that supplies power to the integrated circuit can be formed on the same semiconductor chip as the integrated circuit, thus eliminating the need to supply power to the integrated circuit from outside the semiconductor chip. Furthermore, by driving the integrated circuit with an on-chip solar cell, the maintenance of charging and replacing batteries becomes unnecessary, which is another advantage.

[0011] Therefore, for example, by using on-chip solar cells, it is possible to realize a system that operates autonomously on a single semiconductor chip. Here, the system referred to in this specification is, for example, a system that incorporates an on-chip solar cell, an integrated circuit, a DC / DC converter, an oscillator, and an on-chip antenna on the same semiconductor chip. Because such a system with an on-chip solar cell can operate autonomously, it is expected to be used in applications such as sensor networks and IoT.

[0012] <Consideration of improvements> On-chip solar cells are manufactured using standard CMOS technology because they are integrated with integrated circuits that have field-effect transistors. In this regard, for example, in the on-chip solar cell described in Non-Patent Document 1, as shown in Fig. 1(b) of Non-Patent Document 1, electrodes with light-shielding properties are placed in the light-receiving region of the solar cell. In this case, as a result of the electrodes blocking a portion of the sunlight incident on the light-receiving region, the electrodes hinder the improvement of the solar cell's power generation efficiency. Therefore, the on-chip solar cell described in Non-Patent Document 1 has room for improvement from the standpoint of improving the solar cell's power generation efficiency, and improvements regarding the arrangement of electrodes are desired in on-chip solar cells to improve the solar cell's power generation efficiency.

[0013] Therefore, in the present embodiment, in an on-chip solar cell, in order to improve the power generation efficiency of the solar cell, the arrangement of the electrodes is devised. Hereinafter, the technical idea in the present embodiment with this devise will be described.

[0014] <Basic Idea in the Embodiment> The basic idea in the present embodiment is an idea of providing an electrode of an on-chip solar cell in an integrated circuit region covered with a light-shielding portion instead of providing the electrode in a light-receiving region of the on-chip solar cell in an on-chip solar cell mixed-mounted with an integrated circuit. According to this basic idea, since an electrode having light-shielding property is not arranged in the light-receiving region of the on-chip solar cell, it is possible to suppress that a part of sunlight incident on the light-receiving region is shielded by the electrode. As a result, according to the basic idea, the power generation efficiency of the on-chip solar cell can be improved.

[0015] Hereinafter, an embodiment mode embodying the basic idea will be described.

[0016] <Embodiment Mode> <<Configuration of Semiconductor Device>> FIG. 1 is a perspective view schematically showing the configuration of a semiconductor device 100 in an embodiment mode.

[0017] In FIG. 1, the semiconductor device 100 has, for example, a semiconductor substrate SUB made of p ,

[0018] , , , - , , ,

[0017] -type silicon, and an n-type well region NWL is formed in this semiconductor substrate SUB. As a result of forming a pn junction by the semiconductor substrate SUB and the n-type well region NWL, an on-chip solar cell composed of a pn junction diode is formed.

[0018] And, on a part of the surface of the semiconductor substrate SUB, a metal electrode PE electrically connected to the semiconductor substrate SUB is provided, while on a part of the surface of the n-type well region NWL, a metal electrode NE electrically connected to the n-type well region NWL is provided. The metal electrode PE and the metal electrode NE are extraction electrodes for extracting the power generated by the solar cell.

[0019] Next, above the semiconductor substrate SUB, a light-shielding portion SU is provided, which has the function of blocking light, such as sunlight. This light-shielding portion SU is made of metal, for example, and an opening OP is formed in the light-shielding portion SU.

[0020] Here, if we refer to the area covered by the light-shielding portion SU as the "first region," this first region includes the integrated circuit region where the integrated circuit is formed. On the other hand, if we refer to the region located below the aperture OP as the "second region," this second region includes the light-receiving region of the on-chip solar cell.

[0021] In other words, the semiconductor device 100 has a semiconductor substrate SUB on which an integrated circuit and an on-chip solar cell are formed. The integrated circuit region is located in an area covered by a light-shielding portion SU provided above the semiconductor substrate SUB, thus blocking sunlight, while the light-receiving region of the on-chip solar cell is located in an area that is irradiated with sunlight through an opening OP provided in the light-shielding portion SU.

[0022] In this case, the first region, the integrated circuit region, surrounds the second region, the light-receiving region of the on-chip solar cell, in a planar manner. In other words, the light-receiving region of the on-chip solar cell is surrounded in a planar manner by the integrated circuit region. As shown in Figure 1, the metal electrodes PE and NE are provided in the first region, which is the integrated circuit region, and not in the second region, which is the light-receiving region of the on-chip solar cell. Here, the metal electrode NE is composed of a ring shape that surrounds the second region, which is the light-receiving region of the on-chip solar cell, in a planar manner, and the metal electrode PE is composed of a ring shape that further surrounds the metal electrode NE, which surrounds the light-receiving region of the on-chip solar cell, from the outside.

[0023] Figure 2 is a schematic top view showing the configuration of the semiconductor device 100.

[0024] As shown in Figure 2, the light-shielding portion SU is provided with an opening OP, and the insulating film IF is exposed in a second region located below the opening OP. Although not shown in Figure 2, the light-receiving region of the on-chip solar cell is located beneath the insulating film IF. Therefore, based on this and Figure 2, the metal electrode NE is provided so as to surround the light-receiving region of the on-chip solar cell located beneath the insulating film IF. The metal electrode PE is provided so as to surround the metal electrode NE from the outside in a planar manner.

[0025] In this configuration, the metal electrodes PE and NE are positioned in the region covered by the light-shielding portion SU. That is, the metal electrodes PE and NE are positioned in the integrated circuit region covered by the light-shielding portion SU. The metal electrodes PE and NE configured in this way are made of, for example, a metal that has light-shielding properties against sunlight.

[0026] Next, Figure 3 is a cross-sectional view taken along line AA in Figure 2.

[0027] In Figure 3, the semiconductor device 100 is, for example, p - It has a semiconductor substrate SUB made of silicon, and an on-chip solar cell and integrated circuit are formed on the semiconductor substrate SUB.

[0028] Below, we will first explain the configuration of on-chip solar cells.

[0029] An on-chip solar cell has a semiconductor substrate SUB, which is a semiconductor substrate of a first conductivity type (e.g., p-type), and an n-type well region NWL formed on the semiconductor substrate SUB and having a second conductivity type (e.g., n-type). As a result, a pn junction is formed between the semiconductor substrate SUB and the n-type well region NWL, and an on-chip solar cell consisting of a pn junction diode is formed on the semiconductor substrate SUB.

[0030] And, on a part of the surface of the semiconductor substrate SUB, p + A type semiconductor region PR is formed, and this p +A metal electrode PE is disposed on the p-type semiconductor region PR. On the other hand, on a part of the surface of the n-type well region NWL, an n + -type semiconductor region NR is formed, and a metal electrode NE is disposed on this n + -type semiconductor region NR. Here, the p + -type semiconductor region PR is formed to achieve ohmic contact with the metal electrode PE. Similarly, the n+-type semiconductor region NR is formed to achieve ohmic contact with the metal electrode NE.

[0031] Thus, the metal electrode PE is electrically connected to the semiconductor substrate SUB through the p + -type semiconductor region PR. In contrast, the metal electrode NE is electrically connected to the n-type well region NWL through the n + -type semiconductor region NR. These metal electrodes PE and metal electrode NE function as extraction electrodes for extracting the electric power (electromotive force) generated in the on-chip solar cell.

[0032] Note that, as shown in FIG. 3, an insulating film IF is formed on the surface of the semiconductor substrate SUB in which the n-type well region NWL is formed, together with the metal electrode PE and the metal electrode NE.

[0033] Subsequently, the configuration of the integrated circuit will be described.

[0034] The integrated circuit has, for example, a plurality of field effect transistors and multilayer wirings.

[0035] As a specific example, FIG. 3 shows a field effect transistor Q1 disposed in the left region of the on-chip solar cell and a field effect transistor Q2 disposed in the right region of the on-chip solar cell. Further, a multilayer wiring MW disposed above the field effect transistor Q1 or the field effect transistor Q2 is shown.

[0036] In Figure 3, the left region of the on-chip solar cell is provided with an n-type well region NWL1 formed on the semiconductor substrate SUB, and a p-type well region PWL1 enclosed within the n-type well region NWL1. A field-effect transistor Q1 is formed extending from the inside to the top of the p-type well region PWL1. Above this field-effect transistor Q1, for example, a first layer wiring W1A and a second layer wiring W2A are arranged. These first layer wiring W1A and second layer wiring W2A constitute a multilayer wiring MW.

[0037] Although not shown in Figure 3, the multilayer wiring MW is electrically connected to the field-effect transistor Q1 via a plug, thereby forming an integrated circuit.

[0038] In Figure 3, the right-hand region of the on-chip solar cell is provided with an n-type well region NWL2 formed on the semiconductor substrate SUB, and a p-type well region PWL2 enclosed within the n-type well region NWL2. A field-effect transistor Q2 is formed extending from the inside to the top of the p-type well region PWL2. Above this field-effect transistor Q2, for example, a first layer wiring W1B and a second layer wiring W2B are arranged. These first layer wiring W1B and second layer wiring W2B constitute a multilayer wiring MW.

[0039] Although not shown in Figure 3, the multilayer wiring MW is electrically connected to the field-effect transistor Q2 via a plug, thereby forming an integrated circuit.

[0040] Based on the above, for example, the integrated circuit is configured to include a field-effect transistor Q1, a field-effect transistor Q2, and multilayer wiring MW.

[0041] Furthermore, in the semiconductor device 100 shown in Figure 3, a light-shielding portion SU is provided so as to cover the integrated circuit. An opening OP is provided in this light-shielding portion SU, and below the opening OP, through an insulating film IF, lies the light-receiving region of the on-chip solar cell.

[0042] As a result, sunlight irradiated from above the semiconductor device 100 can enter the light-receiving region of the on-chip solar cell through the opening OP and insulating film IF formed in the light-shielding portion SU, while the semiconductor device 100 is configured such that sunlight is blocked in the integrated circuit region where the integrated circuit is formed.

[0043] Here, as shown in Figure 3, the region where the light-shielding portion SU exists is the first region, and this first region is provided with an integrated circuit including a field-effect transistor Q1, a field-effect transistor Q2, and multilayer wiring MW, as well as the light-shielding portion SU that covers the integrated circuit in a planar manner.

[0044] On the other hand, as shown in Figure 3, the region located below the opening OP formed in the light-shielding portion SU is the second region, and the light-receiving region of the on-chip solar cell is provided in the second region.

[0045] Furthermore, as shown in Figure 3, in the first region, metal electrodes PE and NE are provided below the light-shielding portion SU, which are electrically connected to the light-receiving region of the on-chip solar cell. That is, the planar size of the light-shielding portion SU is larger than the planar size of the integrated circuit, and the metal electrodes PE and NE are provided in the region of the first region where the light-shielding portion SU exists that does not overlap planarly with the integrated circuit. These metal electrodes PE and NE are formed in the same layer as, for example, the gate electrodes of field-effect transistor Q1 and field-effect transistor Q2. Above the metal electrodes PE and NE, there is a space region SP, in which wiring and capacitors can be placed.

[0046] As described above, the semiconductor device 100 in the embodiment is configured.

[0047] <<Semiconductor device operation>> Next, the operation of the semiconductor device 100 will be described.

[0048] First, in Figure 3, when sunlight, including visible light and infrared light, is irradiated from above the semiconductor device 100, the sunlight is blocked by the light-shielding portion SU in the first region where the light-shielding portion SU is located. As a result, sunlight is prevented from irradiating the integrated circuit in the integrated circuit region (first region), thereby protecting the integrated circuit from malfunctions caused by light irradiation.

[0049] On the other hand, in the second region located below the aperture OP formed in the light-shielding portion SU, sunlight is irradiated onto the light-receiving region of the on-chip solar cell through the aperture OP and the insulating film IF.

[0050] In this embodiment, as shown in Figure 3, the semiconductor device 100 does not have metal electrodes PE and NE located in the region below the opening OP.

[0051] As a result, not a portion of the sunlight incident through the aperture OP is blocked by the metal electrodes PE and NE. Therefore, in the implemented semiconductor device 100, the amount of sunlight incident on the light-receiving area of ​​the on-chip solar cell can be increased.

[0052] Next, of the sunlight incident on the light-receiving region, light with a light energy greater than the silicon band gap is absorbed. Specifically, electrons in the valence band receive light energy supplied from sunlight and are excited to the conduction band. As a result, electrons accumulate in the conduction band and holes are generated in the valence band. In this way, when sunlight is irradiated onto the on-chip solar cell contained in the semiconductor device 100, light with a light energy greater than the silicon band gap contained in the sunlight is absorbed, electrons are excited to the conduction band, and holes are generated in the valence band.

[0053] As a result, electrons accumulate in the n-type well region NWL, while holes accumulate in the semiconductor substrate SUB. This generates an electromotive force between the metal electrode NE, which is electrically connected to the n-type well region NWL, and the metal electrode PE, which is electrically connected to the semiconductor substrate SUB. By supplying the electromotive force generated by the on-chip solar cell included in the semiconductor device 100 to the integrated circuit included in the semiconductor device 100, the integrated circuit can be operated.

[0054] However, in reality, the output voltage from an on-chip solar cell is low (approximately 500mV). Therefore, it can be difficult to operate an integrated circuit with the output voltage from an on-chip solar cell. To address this, for example, by incorporating a DC / DC converter, which is a boost circuit, into the semiconductor device 100, the output voltage from the on-chip solar cell can be boosted to 1V or higher, and then this boosted voltage can be supplied to the integrated circuit to operate it. By configuring the semiconductor device 100 in this way, it is possible to provide a semiconductor device 100 that can handle a variety of applications. In particular, according to the implemented form of the semiconductor device 100, a system that operates autonomously with a single semiconductor chip can be realized, making the semiconductor device 100 useful in a wide range of applications such as sensor networks and IoT.

[0055] <<Characteristics of the Embodiment>> Next, I will explain the characteristic features of the embodiment.

[0056] The first characteristic feature of the embodiment is that, for example, as shown in Figures 1 to 3, in an on-chip solar cell that is integrated with an integrated circuit, the metal electrodes PE and NE of the on-chip solar cell are not provided in the light-receiving region (second region) of the on-chip solar cell, but rather in the integrated circuit region (first region) covered by the light-shielding portion SU. As a result, according to the first characteristic feature, since the light-shielding metal electrodes PE and NE are not placed in the light-receiving region of the on-chip solar cell, the blocking of a portion of the sunlight incident on the light-receiving region by the metal electrodes PE and NE is suppressed. As a result, according to the first characteristic feature, the power generation efficiency of the on-chip solar cell can be improved.

[0057] For example, the integrated circuit formed in the integrated circuit region (first region) includes field-effect transistors Q1 and Q2 formed on a semiconductor substrate SUB, and multilayer wiring MW positioned above either field-effect transistor Q1 or Q2. Above the multilayer wiring MW, a light-shielding section SU is provided to block light from entering the integrated circuit region. In other words, when light enters the integrated circuit region, unintended carriers (charges) are generated by the photoelectric effect, and these carriers can cause malfunctions in the field-effect transistors that make up the integrated circuit. For this reason, a light-shielding section SU is provided in the integrated circuit region to cover the integrated circuit in a planar manner and prevent light from entering the integrated circuit.

[0058] Therefore, at the first feature point, metal electrodes PE and NE, which are electrically connected to the light-receiving region of the on-chip solar cell, are placed in the integrated circuit region covered by the light-shielding portion SU. Typically, the planar size of the light-shielding portion SU is larger than the planar size of the integrated circuit, and there is a space region in the integrated circuit region covered by the light-shielding portion SU where the integrated circuit is not formed. For this reason, at the first feature point, for example, metal electrodes PE and NE, which are electrically connected to the light-receiving region of the on-chip solar cell, are placed in the space region covered by the light-shielding portion SU.

[0059] According to the first feature, by effectively utilizing the space area covered by the light-shielding portion SU, it is possible to realize a configuration in which metal electrodes PE and NE are placed in locations other than the light-receiving area of ​​the on-chip solar cell. As a result, according to the first feature, in an on-chip solar cell mounted on an integrated circuit, the amount of light received by the light-receiving area of ​​the on-chip solar cell can be increased, thereby improving the power generation efficiency of the on-chip solar cell.

[0060] This first characteristic is particularly effective because it is an on-chip solar cell integrated with an integrated circuit. In other words, the presence of an integrated circuit integrated with the on-chip solar cell makes it possible to place metal electrodes PE and NE, which are electrically connected to the light-receiving region of the on-chip solar cell, below the light-shielding portion SU that covers the integrated circuit in a planar manner, thus allowing the metal electrodes PE and NE to be placed in locations other than the light-receiving region.

[0061] Next, a second characteristic feature of the embodiment is that, for example, as shown in Figure 3, wiring or a capacitor is placed in the space region SP located above the metal electrodes PE and NE provided in the integrated circuit region (first region) covered by the light-shielding portion SU.

[0062] For example, according to the first feature point described above, metal electrodes PE and NE, which are electrically connected to the light-receiving area of ​​the on-chip solar cell, are placed in the space area covered by the light-shielding portion SU. These metal electrodes PE and NE are formed on the surface (directly above) the semiconductor substrate SUB. As a result, as shown in Figure 3, a space area SP exists above the metal electrodes PE and NE. Therefore, in the second feature point, wiring and capacitors are placed in this space area SP. Thus, according to the second feature point, the space area SP can be effectively utilized.

[0063] Next, a third characteristic feature of the embodiment is that, for example, as shown in Figures 1 and 2, the metal electrodes PE and NE provided in the integrated circuit region (first region) covered by the light-shielding portion SU are each ring-shaped. As a result, the contact area of ​​each of the metal electrodes PE and NE can be increased, thereby reducing the parasitic resistance of the on-chip solar cell.

[0064] <<Manufacturing Method for Semiconductor Devices>> Next, a description will be given of a method for manufacturing the semiconductor device 100 in an embodiment.

[0065] In the implemented embodiment, the semiconductor device 100 is manufactured using general standard CMOS technology, since the on-chip solar cell is integrated with an integrated circuit having a field-effect transistor. Here, the main change in the manufacturing method of the semiconductor device 100 from a general standard CMOS technology manufacturing method lies in the patterning to realize the arrangement and shape changes of the metal electrodes PE and NE, which are characteristic features of the implemented embodiment. The semiconductor device 100 in the implemented embodiment can be manufactured by basically using general standard CMOS technology for all other processes.

[0066] <<Variation>> Next, I will explain variations.

[0067] The basic concept in this embodiment can be broadly applied not only to the device structure described in the embodiment (see Figure 3), but also to on-chip solar cells employing device structures such as FFE (Front Floating Emitter) structures and FSF (Front Surface Field) structures.

[0068] <Verification of effectiveness> Next, we will explain the verification results that support the claim that the power generation performance of on-chip solar cells can be improved according to the basic concept of this embodiment. Here, a simulation was conducted to verify that the power generation performance of on-chip solar cells can be improved, so the following will explain the results of this simulation.

[0069] Figure 4 shows the simulation model 10 in the comparative example.

[0070] In Figure 4, a metal electrode NE is positioned in the light-receiving region of the on-chip solar cell, located below the opening OP in the light-shielding section SU. As a result, a portion of the sunlight that shines onto the light-receiving region of the on-chip solar cell through the opening OP in the light-shielding section SU is blocked by the metal electrode NE provided in the light-receiving region.

[0071] In contrast, Figure 5 shows the simulation model 20 in the embodiment.

[0072] In Figure 5, the metal electrode NE is not positioned in the light-receiving region of the on-chip solar cell located below the opening OP in the light-shielding section SU. Instead, the metal electrode NE is positioned on the surface of the semiconductor substrate SUB covered by the light-shielding section SU, thus realizing the basic concept. As a result, sunlight irradiated onto the light-receiving region of the on-chip solar cell through the opening OP in the light-shielding section SU is not blocked by the metal electrode NE.

[0073] Next, we will explain the simulation results based on simulation model 10 shown in Figure 4 and simulation model 20 shown in Figure 5.

[0074] Figure 6 is a graph showing the IV characteristics (current density-voltage characteristics) of on-chip solar cells in the comparative example and the example, respectively.

[0075] As shown in Figure 6, the embodiment shows that both the short-circuit current density and the open-circuit voltage are higher compared to the comparative example. This indicates that the power generation performance of the on-chip solar cell is superior to that of the comparative example. From these results, it can be seen that the power generation efficiency in the embodiment is improved by approximately 12% compared to the comparative example.

[0076] The above simulation results confirm that the basic concept of this embodiment can improve the power generation performance of on-chip solar cells.

[0077] The present invention has been described in detail above based on its embodiments, but it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence. [Explanation of symbols]

[0078] 100 Semiconductor Devices IF insulating film MW multilayer wiring NE metal electrode NR n + Semiconductor domain NWL n-type well region NWL1 n-type well region NWL2 n-type well region OP opening PE metal electrode PR p + Semiconductor domain PWL1 p-type well region PWL2 p-type well region Q1 Field-effect transistor Q2 Field-effect transistor SP Space Area SU light-shielding part SUB Semiconductor Substrate W1A 1st layer wiring W1B 1st layer wiring W2A Layer 2 Wiring W2B (Layer 2 Wiring)

Claims

1. It has a first region and a second region, The first region includes, Integrated circuits and A light-shielding portion that covers the aforementioned integrated circuit in a planar manner, A system was established, The semiconductor device is provided with a light-receiving region for a solar cell in the second region, In the first region, below the light-shielding portion, an electrode is formed that is electrically connected to the light-receiving region of the solar cell. In the light-receiving region of the solar cell provided in the second region, no electrodes electrically connected to the light-receiving region of the solar cell are formed. The light-receiving region of the solar cell provided in the second region is A first-type conductive semiconductor substrate and A well region formed on the semiconductor substrate and having a second conductivity type, It has, Multiple electrodes exist, Multiple electrodes are, A first electrode electrically connected to the semiconductor substrate, A second electrode electrically connected to the well region, It has, The first electrode and the second electrode function as extraction electrodes that extract the electromotive force generated in the light-receiving region of the solar cell. A semiconductor device in which the first electrode and the second electrode are not short-circuited.

2. In the semiconductor device described in claim 1, The planar size of the light-shielding portion is larger than the planar size of the integrated circuit. A semiconductor device in which the electrodes are provided in a region of the first region where the light-shielding portion exists, that does not overlap in a planar manner with the integrated circuit.

3. In the semiconductor device described in claim 1, The first region includes, The field-effect transistor constituting the aforementioned integrated circuit, A multilayer wiring provided above the field-effect transistor, Formed, The electrode is located in the same layer as the gate electrode of the field-effect transistor in the semiconductor device.

4. In the semiconductor device described in claim 3, A semiconductor device having wiring or a capacitor provided above the aforementioned electrode.

5. In the semiconductor device described in claim 1, The first region encloses the second region in a planar manner. The first electrode is configured in a ring shape surrounding the second region, The semiconductor device is configured such that the second electrode is formed from a ring shape surrounding the second region.

6. In the semiconductor device described in claim 1, The first conductivity type is p-type, The semiconductor device wherein the second conductivity type is n-type.

7. In the semiconductor device described in claim 1, The electrode is a semiconductor device that has light-shielding properties against sunlight.

8. In the semiconductor device described in claim 1, The aforementioned light-shielding portion is made of metal, and is a semiconductor device.

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