Sacrificial cap layer for contact etching

Abstract

The method includes providing a substrate having source / drain regions and an etch stop layer over the source / drain regions. A plasma etching process is performed using an etching gas to remove the etch stop layer and form a sacrificial oxide cap layer over the source / drain regions. The sacrificial oxide cap layer is then removed from the source / drain regions.

Description

[Technical Field]

[0001] Cross-reference of related applications This disclosure claims priority to and benefits from U.S. Provisional Patent Application No. 63 / 195,436 filed June 1, 2021, and U.S. Patent Application No. 17 / 721,620 filed April 15, 2022, which are incorporated herein by reference in their entirety.

[0002] The present invention relates, in general terms, to the manufacture of semiconductor devices, and more specifically, to a method for forming a sacrificial cap layer for contact etching. [Background technology]

[0003] Advances in semiconductor technology depend on continuous improvements in manufacturing techniques. Innovations in semiconductor technology have introduced new types of structures, such as FinFET devices and multilayer structures (e.g., 3D NAND devices). However, these new structures require new manufacturing schemes to overcome the challenge of manufacturing decline under conventional methods. For example, contacts can be opened using dry etching processes such as reactive ion etching (RIE) within a conventional middle-of-line (MOL) processing flow. Often, dry etching processes can be extremely aggressive to some layers in a semiconductor processing flow. Typically, dry etching processes have a plasma source that generates a huge number of ions that are accelerated to cause ion explosions against the sensitive device layer. As a result, plasma etching can cause damage to the underlying material, which can then lead to uncontrollable variability in the electrical performance of the device, as well as a decrease in yield. [Overview of the project] [Means for solving the problem]

[0004] This disclosure relates to semiconductor devices and methods for manufacturing semiconductor devices.

[0005] Embodiment (1) provides a method comprising providing a substrate having a source / drain region and an etching stop layer on the source / drain region. Plasma etching is performed using an etching gas that removes the etching stop layer and forms a sacrificial oxide cap layer on the source / drain region. The sacrificial oxide cap layer is then removed from the source / drain region.

[0006] Embodiment (2) comprises the method of Embodiment (1), wherein the substrate includes a metal gate stack separated from the source / drain region by a spacer, and the etching stop layer is a conformal layer having a first portion covering the source / drain region and a second portion covering the spacer and the metal gate stack.

[0007] Embodiment (3) comprises the method of Embodiment (2), wherein the plasma etching process is performed to completely remove the first portion of the etching stop layer to expose the source / drain region before completely removing the second portion of the etching stop layer. A sacrificial oxide cap layer is formed on the exposed source / drain region while the second portion of the etching stop layer is completely removed.

[0008] Embodiment (4) includes the method of Embodiment (1), wherein the source / drain region includes Si, Ge, or both Si and Ge.

[0009] Embodiment (5) includes the method of Embodiment (1), wherein the plasma etching process is performed on SiO2, GeO2, or SiGeO2. x This includes forming a sacrificial oxide cap layer containing the following:

[0010] Embodiment (6) includes the method of Embodiment (1), wherein the etching stop layer includes a nitride layer.

[0011] Embodiment (7) includes the method of Embodiment (1), wherein the etching stop layer includes SiN.

[0012] Embodiment (8) includes the method of Embodiment (1), wherein the plasma etching process is performed using an etching gas that includes a fluorocarbon-containing gas and an oxygen-containing gas.

[0013] Embodiment (9) includes the method of Embodiment (8), wherein the fluorocarbon-containing gas includes a fluorocarbon gas, a hydrofluorocarbon gas, or a combination thereof.

[0014] Embodiment (10) includes the method of Embodiment (8), wherein the oxygen-containing gas includes O2, O3, CO, CO2, SO2, or a combination thereof.

[0015] Embodiment (11) includes the method of Embodiment (1), wherein removing the sacrificial cap layer includes performing a wet etching process on the substrate.

[0016] Embodiment (12) includes the method of Embodiment (1), wherein removing the sacrificial cap layer is performed by performing a dry etching process on the substrate.

[0017] Another embodiment (13) provides a method comprising providing a substrate including a source / drain region and a SiN etching stop layer on the source / drain region, wherein the source / drain region comprises Si, Ge, or both Si and Ge. The plasma etching process is performed using an etching gas containing a fluorocarbon-containing gas and an oxygen-containing gas to remove the SiN etching stop layer and form a sacrificial oxide cap layer on the source / drain region. The sacrificial oxide cap layer is removed from the source / drain region using a wet or dry etching process.

[0018] Embodiment (14) includes the method of Embodiment (13), wherein the substrate includes a metal gate stack separated from the source / drain region by a spacer, and the SiN etching stop layer is a conformal layer having a first portion covering the source / drain region and a second portion covering the spacer and the metal gate stack.

[0019] Embodiment (15) comprises the method of Embodiment (14), wherein performing a plasma etching process includes completely removing a first portion of the etching stop layer to expose the source / drain region before completely removing a second portion of the etching stop layer. A sacrificial oxide cap layer is formed on the exposed source / drain region while the second portion of the etching stop layer is completely removed.

[0020] Embodiment (16) includes the method of Embodiment (13), wherein the sacrificial oxide cap layer is SiO2, GeO2, or SiGeO x Includes.

[0021] Embodiment (17) includes the method of Embodiment (13), wherein the fluorocarbon-containing gas includes a fluorocarbon gas, a hydrofluorocarbon gas, or a combination thereof.

[0022] Embodiment (18) includes the method of Embodiment (13), wherein the oxygen-containing gas includes O2, O3, CO, CO2, SO2, or a combination thereof.

[0023] Another embodiment (19) provides a method comprising providing a substrate including a source / drain region and a SiN etching stop layer on the source / drain region, wherein the source / drain region comprises Si, Ge, or both Si and Ge. The plasma etching process is performed using an etching gas comprising CH3F gas and O2 gas to remove the SiN etching stop layer and form a sacrificial oxide cap layer on the source / drain region, wherein the sacrificial oxide cap layer is SiO2, GeO2, or SiGeO x This includes the sacrificial oxide cap layer, which is removed from the source / drain region using wet or dry etching.

[0024] Aspect (20) includes the method of aspect (19), wherein the substrate includes a metal gate stack separated from the source / drain regions by spacers, and the SiN etch stop layer is a conformal layer having a first portion covering the source / drain regions and a second portion covering the spacers and the metal gate stack. Performing the plasma etching process includes completely removing the first portion of the etch stop layer to expose the source / drain regions before completely removing the second portion of the etch stop layer. The sacrificial oxide cap layer is formed on the exposed source / drain regions while the second portion of the etch stop layer is being completely removed.

[0025] Note that this "Summary of the Invention" section does not specify all embodiments or stepwise novel aspects of the disclosure of the present disclosure or the claims. Rather, the "Summary of the Invention" merely provides a preliminary explanation of various embodiments and the corresponding novel points over the prior art. For additional details and / or expected aspects of the present disclosure and embodiments, the reader is referred to the "Detailed Description of the Invention" section of the present disclosure and the corresponding drawings, which are further discussed below.

[0026] Multiple aspects of the present disclosure will be better understood by reviewing the following detailed description in conjunction with the accompanying drawings. Note that various features are not drawn to scale in accordance with industry standard practice. In fact, the dimensions of various features may be increased or decreased to clarify the discussion.

Brief Description of the Drawings

[0027] [Figure 1A] A fin partial cross-sectional view of a semiconductor device during manufacturing, along the direction of the fin, is shown. [Figure 1B] A gate cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention, along a direction orthogonal to the direction of the fin, is shown. [Figure 1C] A top view of a semiconductor according to an exemplary embodiment of the present disclosure is shown. [Figure 2A]The following shows a cross-sectional view of the fins of a semiconductor device in a subsequent manufacturing stage according to an exemplary embodiment of the present disclosure. [Figure 2B] The gate cross-section of a semiconductor device in a subsequent manufacturing stage according to an exemplary embodiment of the present disclosure is shown. [Figure 3A] The following shows a cross-sectional view of the fins of a semiconductor device in a subsequent manufacturing stage according to an exemplary embodiment of the present disclosure. [Figure 3B] The gate cross-section of a semiconductor device in a subsequent manufacturing stage according to an exemplary embodiment of the present disclosure is shown. [Figure 4A] The following shows a cross-sectional view of the fins of a semiconductor device in a subsequent manufacturing stage according to an exemplary embodiment of the present disclosure. [Figure 4B] The gate cross-section of a semiconductor device in a subsequent manufacturing stage according to an exemplary embodiment of the present disclosure is shown. [Figure 5A] The following shows a cross-sectional view of the fins of a semiconductor device in a subsequent manufacturing stage according to an exemplary embodiment of the present disclosure. [Figure 5B] The gate cross-section of a semiconductor device in a subsequent manufacturing stage according to an exemplary embodiment of the present disclosure is shown. [Figure 6A] The following shows a cross-sectional view of the fins of a semiconductor device in a subsequent manufacturing stage according to an exemplary embodiment of the present disclosure. [Figure 6B] The gate cross-section of a semiconductor device in a subsequent manufacturing stage according to an exemplary embodiment of the present disclosure is shown. [Figure 7A] The following shows a cross-sectional view of the fins of a semiconductor device in a subsequent manufacturing stage according to an exemplary embodiment of the present disclosure. [Figure 7B] The gate cross-section of a semiconductor device in a subsequent manufacturing stage according to an exemplary embodiment of the present disclosure is shown. [Figure 8A] The experimental results of substrate processing according to an embodiment of the present invention, compared with conventional methods, are shown. [Figure 8B] The experimental results of substrate processing according to an embodiment of the present invention, compared with conventional methods, are shown. [Modes for carrying out the invention]

[0028] The following disclosure provides numerous diverse embodiments or examples for realizing various features of the subject matter provided. For the sake of brevity, specific examples of components and arrangements are described below. Naturally, these are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, or it may include embodiments in which an additional feature is formed between the first and second features so that they are not in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in various embodiments. This repetition is for the sake of brevity and clarity and does not in itself refer to the relationships between the various embodiments and / or configurations discussed. Furthermore, for the sake of brevity, the specification may use spatially relative terms such as “top,” “bottom,” “below,” “downward,” “lower,” “above,” and “upper” to describe the relationship of one element or feature to another, as shown in the figures. Spatially relative terminology is intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the figure. The device may be in other orientations (rotated 90 degrees, or otherwise), and spatially relative descriptors used herein may be interpreted accordingly.

[0029] As described in the background section above, damage to epitaxial source / drain materials induced by contact open etching is one of the MOL challenges in the fabrication of FinFETs for logic ICs. This type of damage leads to uncontrollable variability in electrical performance within the device. Embodiments of the present invention provide a novel approach to protect epitaxial source / rain materials from damage by forming a thin sacrificial cap layer in situ on the epitaxial source / rain material during contact open etching. The sacrificial cap layer can then be removed using a gentle process that does not damage the epitaxial source / rain material and provides high etching selectivity between the sacrificial cap layer and the epitaxial source / rain material.

[0030] Embodiments of the present invention disclose a method for preventing damage to a semiconductor region during plasma etching. In the proposed integration scheme, a sacrificial cap layer is used, which is formed directly on the top of the semiconductor region to be protected. This sacrificial cap layer is designed to protect the semiconductor region during plasma etching, which would otherwise damage the semiconductor region. This sacrificial cap layer can be removed later in the process using a gentle dry or wet cleaning process.

[0031] Embodiments of the present invention can be applied to various types of devices, such as fin transistors and stacked memory devices. Specific embodiments of the above process will be described below.

[0032] Figure 1A shows a partial cross-sectional view of a semiconductor device under manufacture along the direction of the fins, Figure 1B shows a cross-sectional view of the semiconductor device along a direction perpendicular to the direction of the fins, and Figure 1C shows a top view showing the cutting line 1A-1A shown in Figure 1A and the cutting line 1B-1B shown in Figure 1B, all of which are embodiments of the present invention. Figure 1A is a partial cross-sectional view and does not show the underlying fins and substrate.

[0033] As shown in Figures 1A to 1C, at this processing stage, the semiconductor device 100 has already undergone a substantial part of front-end-of-line (FEOL) manufacturing. For example, as shown in Figure 1B, a transistor structure with multiple fins 109 is formed on the substrate 111.

[0034] In various embodiments, the substrate 111 may include silicon, silicon germanium, silicon carbide, and compound semiconductors such as gallium nitride, gallium arsenide, indium arsenide, indium phosphide, and others. The substrate 111 may include a semiconductor wafer that may include semiconductor epitaxial layers including heteroepitaxial layers. For example, in one or more embodiments, one or more heteroepitaxial layers including compound semiconductors may be formed on the semiconductor substrate. In various embodiments, part or all of the substrate 111 may be amorphous, polycrystalline, or single-crystal. In various embodiments, the substrate 111 may be doped, undoped, or include both doped and undoped regions.

[0035] Multiple fins 109 can be formed by epitaxial growth from the substrate 111, or alternatively, by an etch-back process that leaves multiple fins 109. Multiple fins 109 can be separated from each other by shallow isolation regions 112. Thus, the shallow isolation regions 112 and the multiple fins 109 can form an alternating pattern.

[0036] In one embodiment, a shallow separation region 112 may be formed by patterning a plurality of fins 109 and then depositing an oxide packing material, which is then planarized, for example, using a chemical mechanical planarization process. After planarization, the shallow separation region 112 may be recessed to raise the plurality of fins 109.

[0037] Multiple dummy gates 102 are formed on the substrate 111 and multiple fins 109. In one embodiment, the multiple dummy gates 102 can be formed by patterning a layer of amorphous silicon or polysilicon deposited on the multiple fins 109.

[0038] Next, multiple spacers 101 are formed on the sidewalls of multiple dummy gates 102. The multiple spacers 101 may be formed by the deposition of an insulating layer, followed by an anisotropic etching process. For example, a reactive ion etching (RIE) process may be used to form the spacers 101. The insulating layer material is selected so as not to be selectively etched during the removal of the multiple dummy gates 102 later in the process, and so as not to be affected by etching by chemicals such as TMAH or NH4OH. In one example, the spacers 101 may include a low dielectric constant material.

[0039] Next, the epitaxial region 103 is grown on the portions of the fins 109 located between the dummy gates 102 to form a raised source / drain region. As shown, the upper surface of the raised source / drain region can form a faceted surface due to the growth pattern of the corresponding epitaxial material. In some embodiments, the source / drain region includes Si, Ge, or both Si and Ge.

[0040] In one or more embodiments, the epitaxial region 103 may be formed by a single epitaxial growth process. In other embodiments, the growth of the epitaxial region 103 may consist of a multi-step process. For example, a multi-step process may begin by growing an initial epitaxial layer having a first doping on a plurality of fins 109 to a predetermined thickness, followed by growing a second layer having a second doping. For example, the second doping may be a higher doping than the first doping. Similarly, the different layers may have different compositions, for example, germanium or other compounds. The epitaxial growth process may use any type of epitaxial process, including molecular beam epitaxy (MBE), or various types of chemical vapor deposition (CVD).

[0041] In one or more embodiments, the epitaxial region 103 may be grown to introduce strain into a plurality of fins 109, for example, due to lattice mismatch.

[0042] In one or more embodiments, the source / drain (S / D) region may be formed by doping the fin region and the epitaxial region 103, for example, in a doping / annealing process.

[0043] Figures 2A and 2B show cross-sectional views of the semiconductor device 100 in subsequent manufacturing stages after an etching stop layer (ESL) 105 has been formed on the semiconductor device 100. Figure 2A shows the same cutting lines as Figure 1A, while Figure 2B shows the same cutting lines as Figure 1B.

[0044] ESL105 can be conformally deposited across the entire wafer surface. In various embodiments, ESL105 comprises silicon nitride (SiN) or silicon oxynitride (SiON). In various embodiments, ESL105 may have a thickness in the range of 0.5 nm to about 10 nm. In one embodiment, ESL105 may have a thickness in the range of 2 nm to about 5 nm.

[0045] Figures 3A and 3B show partial cross-sectional views of a semiconductor device 100 during manufacturing after deposition of oxide 106 according to an embodiment of the present invention. Figure 3A shows the same cutting lines as Figure 1A, while Figure 3B shows the same cutting lines as Figure 1B.

[0046] Referring to Figures 3A and 3B, the oxide 106 is packed between the multiple dummy gates 102. The oxide 106 is overpacked above the top surface of the ESL 105 and on top of the multiple dummy gates 102.

[0047] In various embodiments of the semiconductor device 100, the oxide 106 may be a fluid oxide including spin-on glass. For example, a layer containing borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), borosilicate glass (BSG), arsenic silicon glass (ArSG), or other types of glass may be deposited and heated to reflow. In one or more embodiments, the oxide 106 may also include oxides such as tetraethyloxysilane (TEOS), fluorinated TEOS (FTEOS), organic silicate glass (OSG), fluorinated silicate glass (FSG), or spin-on glass (SOG).

[0048] Figures 4A and 4B show cross-sectional views of a semiconductor device 100 during manufacturing after the formation of a substitution metal gate (RMG) according to an embodiment of the present invention. Figure 4A shows the same cutting line as Figure 1A, while Figure 4B shows the same cutting line as Figure 1B.

[0049] As shown in Figures 4A and 4B, the oxide 106 is planarized to expose the underlying ESL 105. The ESL 105 can be removed using anisotropic etching to expose the multiple dummy gates 102. The multiple dummy gates 102 are then removed, for example, by wet etching or alternatively by plasma etching. The spacer 101 maintains the shape of the gate stack during the removal of the multiple dummy gates 102. During etching, the oxide 106 protects the underlying region of the epitaxial region 103.

[0050] After removing the multiple dummy gates 102, the inner walls of the multiple spacers 101 are exposed, leaving cavities. These cavities are filled with replacement gate material 107. After the replacement gate material 107 is in place, contact caps 108 are formed. The contact caps 108 may be formed using a self-aligning process so as to be selectively formed only on the replacement gate material 107.

[0051] The replacement gate material 107, together with the contact cap 108, forms a replacement metal gate (RMG) stack 102'. The RMG stack 102' helps to set the work function of the gate and forms the final gate electrode of the semiconductor device 100.

[0052] Figures 5A and 5B show partial cross-sectional views of the semiconductor device 100 in the next manufacturing step after etching of oxide 106, according to an embodiment of the present invention. Figure 5A shows the same cutting lines as Figure 1A, while Figure 5B shows the same cutting lines as Figure 1B.

[0053] As shown in Figure 5A, etching of the oxide 106 leaves empty, unfilled trenches or concave features. In various embodiments, the oxide etching process may be a wet etching process, a dry etching process such as reactive ion etching (RIE), or any process currently known in the field of semiconductor manufacturing. Etching of the oxide 106 exposes the ESL 105 remaining between the multiple spacers 101 backing the replacement gate material 107 and the contact cap 108.

[0054] Figures 6A and 6B show partial cross-sectional views of the semiconductor device 100 in the next manufacturing step after performing ESL etching according to an embodiment of the present invention. Figure 6A shows the same cutting lines as in Figure 1A, while Figure 6B shows the same cutting lines as in Figure 1B.

[0055] ESL etching involves performing plasma etching using an etching gas that removes ESL 105 and forms a sacrificial oxide capping layer 113 on the source / drain region. During plasma etching, once ESL 105 is removed and the epitaxial region 103 is exposed, the presence of oxygen-containing gases in the etching gas reacts with the epitaxial region 103 to form a thin sacrificial capping layer 113 on the epitaxial region 103. The presence of the thin sacrificial capping layer 113 protects the epitaxial region 103 from plasma damage caused by other reactive gases in the etching gas. ESL etching is performed until ESL 105 is completely removed from the semiconductor device 100. This requires protection of the epitaxial region 103 by the sacrificial oxide capping layer 113, as ESL etching may be performed to remove any remaining ESL 105 from regions other than the epitaxial region 103. The sacrificial oxide capping layer 113 is resistant to other reactive gases in the etching gas. Protection of the epitaxial region 103 prevents or reduces material loss, chemical doping, and damage to the bulk crystal structure of the epitaxial region 103. In some embodiments, the sacrificial oxide cap layer 113 is made of SiO2, GeO2, or SiGeO2. x Includes.

[0056] In various embodiments, the sacrificial cap layer 113 may have a thickness in the range of 0.5 nm to about 5 nm on the top of the epitaxial region 103. In one embodiment, the sacrificial cap layer 113 may have a thickness in the range of 1 nm to about 3 nm, and may be about 2 nm.

[0057] In various embodiments, the etching gas in the ESL etching process may include a fluorocarbon-containing gas and an oxygen-containing gas. The etching gas may further include argon (Ar) gas as a diluent. The fluorocarbon-containing gas may include a fluorocarbon gas, a hydrofluorocarbon gas, or a combination thereof. The fluorocarbon gas is C x X yhaving the chemical formula, where C and X each represent carbon and halogen, and x and y are integers. The hydrofluorocarbon gas is C x X y H z having the chemical formula, where C, X, and H each represent carbon, halogen, and hydrogen, and x, y, and z are integers. The oxygen-containing gas may include, for example, O2, O3, CO, CO2, SO2, or a combination thereof.

[0058] In one example, the etching gas includes CH3F, O2, and Ar. An exemplary gas flow includes about 10 to 100 sccm of CH3F, about 10 to 100 sccm of O2, and about 50 to 200 sccm of Ar. In one example, the plasma etching process can be performed in a processing chamber including an upper electrode and a lower electrode, and the lower electrode supports the substrate to be processed. Exemplary processing conditions may include a substrate temperature of about 20 to 100 °C, a gas pressure of about 5 to 100 mTorr, an RF power of about 50 to 500 W to the upper electrode, and an RF power of about 50 to 500 W to the lower electrode.

[0059] Figures 7A - 7B show partial cross-sectional views of the semiconductor device 100 in the next manufacturing stage after removing the sacrificial oxide cap layer from the source / drain regions according to an embodiment of the present invention. Figure 7A shows a cutting line similar to that in Figure 1A, while Figure 7B shows a cutting line similar to that in Figure 1B.

[0060] The removal of the sacrificial cap layer 113 can be performed by an etching process that is efficient and does not damage the epitaxial region 103, such as dry etching or wet etching. In one example, wet etching may include exposing the substrate to dilute hydrofluoric acid (DHF). In one example, dry etching may include a chemical oxide removal process (COR) that includes exposing the substrate to HF gas and NH3 gas, followed by a heat treatment to desorb reaction by-products from the substrate.

[0061] Figures 8A and 8B show experimental results of substrate processing according to embodiments of the present invention. Figure 8A shows a transmission electron microscope (TEM) image after removing SiN ESL from a SiGe substrate using a plasma-excited etching gas containing CH3F, O2, and Ar. Following the removal of SiN ESL, a sacrificial cap layer containing SiGeOx and having a thickness of approximately 2 nm was formed on the SiGe substrate. The TEM in Figure 8A clearly shows that the crystal structure of the SiGe substrate was not damaged by the plasma etching process. In contrast, Figure 8B shows a TEM after removing SiN ESL from a SiGe substrate using a plasma-excited etching gas containing CH3F, H2, and Ar. Because there was no oxygen-containing gas in the etching gas, no sacrificial cap layer was formed on the SiGe substrate following the removal of SiN ESL. The TEM in Figure 8B clearly shows that the crystal structure of the SiGe substrate was severely damaged by the plasma etching process. Chemical analysis further showed that high levels of hydrogen were incorporated into the SiGe substrate. Therefore, the results in Figures 8A to 8B clearly demonstrate how the sacrificial cap layer can protect the crystal structure of the SiGe substrate within the semiconductor device.

[0062] In the preceding description, specific details have been provided, including the particular geometric shape of the processing system and descriptions of the various components and processes used. However, it should be understood that the techniques described herein may be implemented in other embodiments different from these specific details, and that such details are for illustrative purposes only and not to limit the scope. Multiple embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for illustrative purposes, certain numbers, materials, and configurations have been shown to ensure thorough understanding. However, multiple embodiments may be implemented without such specific details. In some cases, redundant descriptions have been omitted because elements having substantially identical functional structures are indicated by similar reference numerals.

[0063] To aid in understanding various embodiments, various techniques have been described as multiple operations. The order of description should not be interpreted as meaning that these operations are necessarily order-dependent. In fact, these operations do not have to be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments, and / or the described operations may be omitted.

[0064] As used herein, “substrate” or “wafer” generally refers to an object processed according to the present invention. A substrate may include any material portion or structure of a device, in particular a semiconductor or other electronic device, and may be, for example, a base substrate structure such as a semiconductor wafer, a reticle, or a layer that rests on or covers a base substrate structure such as a thin film. Accordingly, a substrate is not limited to any specific base structure, patterned or unpatterned underlayer or coating layer, but is intended to include any such layer or base structure, and any combination of multiple layers and / or base structures. The description herein may refer to certain types of substrates, but this is for illustrative purposes only.

[0065] Those skilled in the art will understand that many modifications can be made to the operation of the technology described above while achieving the same objectives as the present invention. Such modifications are intended to be within the scope of this disclosure. Thus, the above description of multiple embodiments of the present invention is not intended to be limiting. Rather, the limitations on multiple embodiments of the present invention are shown in the following claims.

Claims

1. A step of providing a substrate including an epitaxial source / drain region and an etching stop layer on the epitaxial source / drain region, A step of performing a plasma etching process using an etching gas, wherein the etching gas removes the etching stop layer and forms a sacrificial oxide cap layer on the epitaxial source / drain region, A step of removing the sacrificial oxide cap layer from the epitaxial source / drain region using an etching process, wherein the epitaxial source / drain region below the sacrificial oxide cap layer is not damaged. A method having.

2. The substrate includes a metal gate stack separated from the source / drain region by a spacer, The method according to claim 1, wherein the etching stop layer is a conformal layer having a first portion that covers the epitaxial source / drain region and a second portion that covers the spacer and the metal gate stack.

3. The step of performing the aforementioned plasma etching process is: Before completely removing the second portion of the etching stop layer, the first portion of the etching stop layer is completely removed to expose the epitaxial source / drain region. The steps include: forming the sacrificial oxide cap layer in the exposed epitaxial source / drain region while completely removing the second portion of the etching stop layer; The method according to claim 2, having the following characteristics.

4. The method according to claim 1, wherein the epitaxial source / drain region comprises Si, Ge, or both Si and Ge.

5. The step of performing the aforementioned plasma etching process is SiO ２ , GeO ２ , or SiGeO ｘ The method according to claim 1, comprising the step of forming a sacrificial oxide cap layer containing the following:

6. The method according to claim 1, wherein the etching stop layer includes a nitride layer.

7. The method according to claim 1, wherein the etching stop layer includes SiN.

8. The method according to claim 1, wherein the step of performing the plasma etching process includes the step of using an etching gas containing a fluorocarbon-containing gas and an oxygen-containing gas.

9. The method according to claim 8, wherein the fluorocarbon-containing gas includes a fluorocarbon gas, a hydrofluorocarbon gas, or a combination thereof.

10. The oxygen-containing gas is O ２ , O ３ CO, CO ２ SO ２ The method according to claim 8, including, or a combination thereof.

11. The method according to claim 1, wherein the step of removing the sacrificial oxide cap layer comprises the step of performing a wet etching treatment on the substrate.

12. The method according to claim 1, wherein the step of removing the sacrificial oxide cap layer comprises the step of performing a dry etching treatment on the substrate.

13. A step of providing a substrate including an epitaxial source / drain region and a SiN etching stop layer on the epitaxial source / drain region, wherein the epitaxial source / drain region includes Si, Ge, or both Si and Ge. A step of performing a plasma etching process using an etching gas, wherein the etching gas includes a fluorocarbon-containing gas and an oxygen-containing gas, the SiN etching stop layer is removed, and a sacrificial oxide cap layer is formed in the epitaxial source / drain region. A step of removing the sacrificial oxide cap layer from the epitaxial source / drain region using a wet or dry etching process, wherein the epitaxial source / drain region beneath the sacrificial oxide cap layer is not damaged. A method having.

14. The substrate includes a metal gate stack separated from the epitaxial source / drain region by a spacer. The method according to claim 13, wherein the SiN etching stop layer is a conformal layer having a first portion that covers the epitaxial source / drain region and a second portion that covers the spacer and the metal gate stack.

15. The step of performing the plasma etching process includes, before completely removing the second portion of the etching stop layer, completely removing the first portion of the etching stop layer to expose the epitaxial source / drain region, The steps include: forming the sacrificial oxide cap layer in the exposed epitaxial source / drain region while completely removing the second portion of the etching stop layer; The method according to claim 14, having the following characteristics.

16. The sacrificial oxide cap layer is SiO ２ , GeO ２ , or SiGeO ｘ , the method according to claim 13, comprising.

17. The method according to claim 13, wherein the fluorocarbon-containing gas includes a fluorocarbon gas, a hydrofluorocarbon gas, or a combination thereof.

18. The oxygen-containing gas is O ２ , O ３ CO, CO ２ SO ２ The method according to claim 13, including, or a combination thereof.

19. A step of providing a substrate including an epitaxial source / drain region and a SiN etching stop layer on the epitaxial source / drain region, wherein the epitaxial source / drain region includes Si, Ge, or both Si and Ge. CH ３ F gas and O ２ A step of performing a plasma etching process using an etching gas containing gas, wherein the SiN etching stop layer is removed, a sacrificial oxide cap layer is formed in the epitaxial source / drain region, and the sacrificial oxide cap layer is SiO ２ , GeO ２ , or SiGeO ｘ Steps including, A step of removing the sacrificial oxide cap layer from the epitaxial source / drain region using a wet or dry etching process, wherein the epitaxial source / drain region beneath the sacrificial oxide cap layer is not damaged. A method having.

20. The substrate includes a metal gate stack separated from the epitaxial source / drain region by a spacer. The SiN etching stop layer is a conformal layer having a first portion that covers the epitaxial source / drain region and a second portion that covers the spacer and the metal gate stack. The step of performing the aforementioned plasma etching process is: Before completely removing the second portion of the etching stop layer, the first portion of the etching stop layer is completely removed to expose the epitaxial source / drain region. The steps include: forming the sacrificial oxide cap layer in the exposed epitaxial source / drain region while completely removing the second portion of the etching stop layer; The method according to claim 19, comprising:

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