Semiconductor equipment

Abstract

To provide a semiconductor device capable of improving electrical characteristics.SOLUTION: A semiconductor device 61 includes: a substrate 2; an output region 6 (device region) provided in the substrate 2; a source terminal 26 (terminal) covering the output region 6 in planar view; a plurality of pseudo-bumps 75 densely arranged on the source terminal 26 in a state of being opened from a wire; and at least one genuine bump 90 arranged more sparsely than the plurality of pseudo-bumps 75 on the source terminal 26 in a state of being connected to the wire.SELECTED DRAWING: Figure 9

Description

Technical Field

[0004] ,

[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a semiconductor device including an electrode for wire bonding formed near active elements such as a microcomputer and a power transistor.

Prior Art Document

Patent Document

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] [Figure 1] Figure 1 is a plan view showing a semiconductor chip according to the first embodiment. [Figure 2] Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. [Figure 3] Figure 3 is a circuit diagram showing an example of the electrical configuration of the semiconductor chip shown in Figure 1. [Figure 4] Figure 4 is a plan view showing the layout of the output area. [Figure 5] Figure 5 is a cross-sectional view along the VV line shown in Figure 4. [Figure 6] Figure 6 is a cross-sectional view along the line VI-VI shown in Figure 4. [Figure 7] Figure 7 is a cross-sectional view along the line VII-VII shown in Figure 4. [Figure 8] Figure 8 is a perspective view showing a semiconductor device equipped with the semiconductor chip shown in Figure 1. [Figure 9] Figure 9 is a plan view showing the internal structure of the semiconductor device shown in Figure 8, along with a pseudo-bump related to the first layout example. [Figure 10] Figure 10 is a cross-sectional view along the line XX shown in Figure 9. [Figure 11] Figure 11 is a cross-sectional view along the line XI-XI shown in Figure 9. [Figure 12] Figure 12 is a plan view showing a pseudo-bump related to the first layout example. [Figure 13] Figure 13 is a cross-sectional view along the line XIII-XIII shown in Figure 12. [Figure 14] Figure 14 is a cross-sectional view along the line XIV-XIV shown in Figure 12. [Figure 15] Figure 15 is a plan view showing a pseudo-bump related to the second layout example. [Figure 16] Figure 16 is a cross-sectional view along the line XVI-XVI shown in Figure 15. [Figure 17] FIG. 17 is a plan view showing the internal structure of a semiconductor device together with dummy bumps according to a third layout example. [Figure 18] FIG. 18 is a plan view showing dummy bumps according to a third layout example. [Figure 19] FIG. 19 is a cross-sectional view taken along line XIX-XIX shown in FIG. 18. [Figure 20] FIG. 20 is a cross-sectional view taken along line XX-XX shown in FIG. 18. [Figure 21] FIG. 21 is a plan view showing a semiconductor chip according to a second embodiment. [Figure 22] FIG. 22 is a plan view showing a semiconductor device on which the semiconductor chip shown in FIG. 21 is mounted together with dummy bumps according to a first layout example. [Figure 23] FIG. 23 is a cross-sectional view taken along line XXIII-XXIII shown in FIG. 22. [Figure 24] FIG. 24 is a plan view showing the internal structure of a semiconductor device according to a first modification together with dummy bumps according to a first layout example. [Figure 25] FIG. 25 is a cross-sectional view taken along line XXV-XXV shown in FIG. 24. [Figure 26] FIG. 26 is a plan view showing the internal structure of a semiconductor device according to a second modification together with dummy bumps according to a first layout example. [Figure 27] FIG. 27 is a cross-sectional view taken along line XXVII-XXVII shown in FIG. 26. [Figure 28] FIG. 28 is a plan view showing a modification example of dummy bumps according to a first layout example. [Figure 29] FIG. 29 is a plan view showing a modification example of dummy bumps according to a second layout example. [Figure 30] FIG. 30 is a plan view showing a modification example of dummy bumps according to a third layout example.

MODE FOR CARRYING OUT THE INVENTION

[0009] The embodiments will now be described in detail with reference to the attached drawings. The attached drawings are schematic diagrams and not strictly accurate; the scale and other aspects may not necessarily match. Corresponding structures in the attached drawings are given the same reference numerals, and redundant descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the description given before the omission or simplification applies.

[0010] In descriptions where a comparison target exists, when phrases such as "substantially equal" are used, this phrase includes not only numerical values ​​(forms) that are equal to the numerical value (form) of the comparison target, but also numerical errors (form errors) within a range of ±10% based on the numerical value (form) of the comparison target. In the embodiments, phrases such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of explanation and are not intended to limit the names of each structure.

[0011] Figure 1 is a plan view showing a semiconductor chip 1A according to the first embodiment. Figure 2 is a cross-sectional view along the line II-II shown in Figure 1. Figure 3 is a circuit diagram showing an example of the electrical configuration of the semiconductor chip 1A shown in Figure 1. Figure 3 shows an example in which an inductive load L is connected to the output terminal (source terminal 26).

[0012] Referring to Figures 1 and 2, the semiconductor chip 1A in this embodiment includes a substrate 2 formed in the shape of a rectangular parallelepiped. The substrate 2 is made of a Si single crystal substrate. The substrate 2 may be made of a wide-bandgap semiconductor single crystal substrate (for example, a SiC single crystal substrate). The substrate 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4.

[0013] The first principal surface 3 and the second principal surface 4 are formed in a quadrilateral shape in a plan view (hereinafter simply referred to as "plan view") taken from their normal direction Z. The first principal surface 3 is the device surface on which a functional device is formed. The second principal surface 4 is a non-device surface. The first side surface 5A and the second side surface 5B extend in a first direction X along the first principal surface 3 and face a second direction Y that intersects (specifically orthogonal to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in a second direction Y and face the first direction X.

[0014] The first to fourth sides 5A to 5D may each have a length of 0.1 mm or more and 10 mm or less in a plan view. The lengths of the first to fourth sides 5A to 5D may be 0.1 mm or more and 0.5 mm or less, 0.5 mm or more and 1 mm or less, 1 mm or more and 2.5 mm or less, 2.5 mm or more and 5 mm or less, 5 mm or more and 7.5 mm or less, or 7.5 mm or more and 10 mm or less.

[0015] The semiconductor chip 1A includes an output region 6, a current detection region 7, a control region 8, a first temperature measurement region 9, and a second temperature measurement region 10, which are provided on the first main surface 3. The output region 6, the current detection region 7, the control region 8, the first temperature measurement region 9, and the second temperature measurement region 10 may also be referred to as the "first device region," "second device region," "third device region," "fourth device region," and "fifth device region," respectively.

[0016] The output region 6 is a region having a functional device configured to generate an output signal that is output to the outside (outside the semiconductor chip 1A). In this embodiment, the output region 6 is demarcated on the first main surface 3 in the region on the first side surface 5A side. The output region 6 may be demarcated in a rectangular shape in a plan view, or it may be demarcated in a polygonal shape other than a rectangle. The position, size, and planar shape of the output region 6 are arbitrary and not limited to a particular form.

[0017] The current detection region 7 is a region having a functional device configured to generate a monitor signal for monitoring the output signal. Preferably, the current detection region 7 is adjacent to the output region 6. In this embodiment, the current detection region 7 has a planar area less than the planar area of ​​the output region 6 and is located in the interior part of the output region 6.

[0018] In other words, the current detection region 7 is arranged to be surrounded by the output region 6. "Surrounded" here includes configurations where the current detection region 7 is surrounded by the output region 6 all around, as well as configurations where the current detection region 7 is adjacent to the output region 6 in at least two directions. In this configuration, the functional device of the current detection region 7 is formed using a portion of the functional device of the output region 6.

[0019] The control region 8 is a region having multiple functional devices configured to generate control signals for controlling the functional devices of the output region 6. In this embodiment, the control region 8 is partitioned in the region on the second side 5B side relative to the output region 6 and faces the output region 6 in the second direction Y. The control region 8 may be partitioned in a rectangular shape in a plan view, or it may be partitioned in a polygonal shape other than a rectangle. The position, size, and planar shape of the control region 8 are arbitrary and are not limited to a particular form.

[0020] The control area 8 preferably has a flat area less than or equal to the flat area of ​​the output area 6. The area ratio of the control area 8 to the flat area of ​​the output area 6 may be 0.1 or more and 2 or less. The area ratio of the control area 8 to the flat area of ​​the output area 6 may be 0.1 or more and 0.25 or less, 0.25 or more and 0.5 or less, 0.5 or more and 0.75 or less, 0.75 or more and 1 or less, 1 or more and 1.25 or less, 1.25 or more and 1.5 or less, 1.5 or more and 1.75 or less, or 1.75 or more and 2 or less. The area ratio is preferably less than 1.

[0021] The first temperature measurement area 9 is an area having a functional device configured to generate a temperature measurement signal for monitoring the temperature of the output area 6. Preferably, the first temperature measurement area 9 is adjacent to the output area 6. In this embodiment, the first temperature measurement area 9 has a planar area less than the planar area of ​​the output area 6 and is located in the interior part of the output area 6.

[0022] In other words, the first temperature measurement area 9 is surrounded by the output area 6. The term "surrounded" here includes not only the configuration in which the first temperature measurement area 9 is surrounded all around by the output area 6, but also the configuration in which the first temperature measurement area 9 is adjacent to the output area 6 in at least two directions.

[0023] The second temperature measurement area 10 is an area having a functional device configured to generate a temperature measurement signal for monitoring the temperature of the control area 8. Preferably, the second temperature measurement area 10 is adjacent to the control area 8. In this embodiment, the second temperature measurement area 10 has a planar area less than the planar area of ​​the control area 8 and is located in the interior part of the control area 8.

[0024] In other words, the second temperature measurement area 10 is surrounded by the control area 8. The term "surrounded" here includes not only the configuration in which the second temperature measurement area 10 is surrounded by the control area 8 all around, but also the configuration in which the second temperature measurement area 10 is adjacent to the control area 8 in at least two directions.

[0025] Referring to Figures 1 and 3, the semiconductor chip 1A includes an n-system insulated-gate main transistor 11 formed in the output region 6, where "n" is 2 or greater (n≧2). Figure 3 illustrates two main transistors 11. The main transistor 11 may also be called a "gate-splitting transistor". The main transistor 11 includes n (n-number) first gates FG, one first drain FD, and one first source FS.

[0026] The main transistor 11 is configured such that n identical or different gate signals (gate voltages) are input to n first gates FG at arbitrary timings. Each gate signal includes an ON signal that controls a portion of the main transistor 11 to an ON state, and an OFF signal that controls a portion of the main transistor 11 to an OFF state.

[0027] The main transistor 11 generates a single output current IO (output signal) in response to n gate signals. In other words, the main transistor 11 consists of a multi-input single-output switching device. The output current IO is the drain-source current flowing between the first drain FD and the first source FS. The output current IO is output outside the substrate 2.

[0028] The main transistor 11 includes n system transistors 12. Figure 3 illustrates the first system transistor 12A and the second system transistor 12B. The n system transistors 12 are aggregated into a single output region 6 and are configured to be electrically controlled to be on and off independently of each other.

[0029] Specifically, the n system transistors 12 are connected in parallel to each other so that n gate signals are individually input to them. In other words, the n main transistors 11 are configured so that on-state system transistors 12 and off-state system transistors 12 can coexist at any given time.

[0030] Each of the n system transistors 12 includes a second gate SG, a second drain SD, and a second source SS. Each of the n second gates SG constitutes a n first gate FG. Each of the n second drains SD constitutes a single first drain FD. Each of the n second sources SS constitutes a single first source FS.

[0031] Each of the n system transistors 12 generates a system current IS in response to a corresponding gate signal. The system current IS is the drain-source current flowing between the second drain SD and the second source SS of the system transistor 12. The n system currents IS may be different values ​​from each other or may be equal values. The n system currents IS are added together between the first drain FD and the first source FS. This generates a single output current IO consisting of the sum of the n system currents IS.

[0032] Referring to Figures 1 and 3, the semiconductor chip 1A includes an m-system insulated-gate type monitor transistor 13 formed in the current sensing region 7, where "m" is 1 or greater (m≧1). Figure 3 illustrates two systems of monitor transistors 13. The monitor transistors 13 are connected in parallel to the main transistor 11 and are configured to monitor part or all of the output current IO. That is, the monitor transistors 13 are connected in parallel to at least one system transistor 12 and monitor at least one system current IS.

[0033] The monitor transistor 13 is preferably connected in parallel to multiple system transistors 12 and configured to monitor multiple system currents IS. In this configuration, the monitor transistor 13 consists of n systems (m=n) of monitor transistors 13 connected in parallel to n system transistors 12 to monitor n system currents IS. In the following description, "m systems" will be replaced with "n systems" and "m units" will be replaced with "n units" as needed.

[0034] In this configuration, the monitor transistor 13 includes n first monitor gates FMG, one first monitor drain FMD, and one first monitor source FMS. Each of the n first monitor gates FMG is configured to receive n monitor gate signals (monitor gate voltages) individually.

[0035] The first monitored drain FMD is electrically connected to the first drain FD. The first monitored source FMS is electrically separated from the first source FS. The same or different n monitored gate signals are input to the n first monitored gates FMG at any timing. Each monitored gate signal includes an on signal for controlling a part of the monitor transistor 13 to be in the on state and an off signal for controlling a part of the monitor transistor 13 to be in the off state.

[0036] In this form, the monitor transistor 13 generates a single monitor current IM (monitor signal) that monitors n system currents IS (output currents IO) in response to the n monitored gate signals. That is, the monitor transistor 13 consists of a multi-input single-output type switching device. The monitor current IM is the drain-source current flowing between the first monitored drain FMD and the first monitored source FMS.

[0037] In this form, the n first monitored gates FMG are electrically connected to the corresponding n first gates FG in a one-to-one correspondence. Therefore, the n first monitored gates FMG are configured such that the monitored gate signals consisting of gate signals are individually input. That is, the monitor transistor 13 is turned on and off at the same timing as the main transistor 11, and generates a monitor current IM that increases and decreases in conjunction with the increase and decrease of the output current IO.

[0038] The monitor current IM is output outside the output region 6 through a current path that is electrically independent of the current path of the output current IO. The monitor current IM is less than or equal to the output current IO (IM≦IO). Preferably, the monitor current IM is less than the output current IO (IM<IO). The current ratio IM / IO of the monitor current IM to the output current IO is arbitrary. The current ratio IM / IO may be 1 / 10000 or more and 1 or less (preferably less than 1).

[0039] The monitor transistor 13 contains m (n in this configuration) system monitor transistors 14. Figure 3 illustrates the first system monitor transistor 14A and the second system monitor transistor 14B. The number of systems in the monitor transistor 13 is adjusted by the number of system monitor transistors 14.

[0040] In other words, when m-system monitor transistors 13 monitor at least one system current IS, at least one system monitor transistor 14 is electrically connected (specifically, in parallel) to at least one system transistor 12. Also, when m-system monitor transistors 13 monitor multiple system current IS, multiple system monitor transistors 14 are electrically connected to multiple system transistors 12. In this configuration, n system monitor transistors 14 are electrically connected to n system transistors 12.

[0041] The n system monitor transistors 14 are configured to be electrically controlled to be on and off independently of each other. Specifically, the n system monitor transistors 14 are connected in parallel to each other so that n monitor gate signals are individually input to them. In other words, the monitor transistor 13 is configured so that the on-state system monitor transistors 14 and the off-state system monitor transistors 14 can coexist at any given time.

[0042] Each of the n system monitor transistors 14 includes a second monitor gate SMG, a second monitor drain SMD, and a second monitor source SMS. Each of the n second monitor gate SMGs constitutes a n first monitor gate FMG. Each of the n second monitor drain SMDs constitutes a first monitor drain FMD. Each of the n second monitor source SMSs constitutes a first monitor source FMS.

[0043] The n second monitor gate SMGs are input to n identical or different monitor gate signals at arbitrary timings. The n system monitor transistors 14 each generate a system monitor current ISM (system monitor signal) that monitors the system current IS of the corresponding system transistor 12 in response to the corresponding monitor gate signal.

[0044] The system monitor current ISM is the drain-source current flowing between the second monitor drain SMD and the second monitor source SMS of the system monitor transistor 14. The n system monitor currents ISM are added together between the first monitor drain FMD and the first monitor source FMS. This generates a single monitor current IM, which consists of the sum of the n system monitor currents ISM.

[0045] In this configuration, the n system monitor transistors 14 are electrically connected to their corresponding system transistors 12 in a one-to-one correspondence and are controlled in conjunction with the corresponding system transistors 12. Specifically, the n system monitor transistors 14 are connected in parallel to their respective system transistors 12 such that the system monitor current ISM is output to a current path electrically independent of the system current IS current path.

[0046] Each of the n second monitor gates SMG is electrically connected to its corresponding first gate FG in a one-to-one correspondence. In other words, in this configuration, monitor gate signals consisting of gate signals are input to each of the n second monitor gates SMG. The second monitor drain SMD is electrically connected to the first drain FD. The second monitor source SMS is electrically isolated from the first source FS.

[0047] As a result, the n system monitor transistors 14 are controlled to be switched on and off at the same timing as the corresponding system transistors 12, and each generates a system monitor current ISM that increases or decreases in conjunction with the increase or decrease of the corresponding system current IS. The system monitor current ISM is taken from the second monitor source SMS, electrically independent of the system current IS.

[0048] Each system monitor current ISM is less than or equal to the corresponding system current IS (ISM ≦ IS). Preferably, each system monitor current ISM is less than the corresponding system current IS (ISM < IS). The current ratio ISM / IS of the system monitor current ISM to the system current IS is arbitrary. The current ratio ISM / IS may be 1 / 10000 or more and 1 or less (preferably less than 1).

[0049] Hereinafter, control examples of two system main transistors 11 and two system monitor transistors 13 will be described. When gate signals (that is, off signals) less than the gate threshold voltage are input to all of the n first gates FG, the first system transistor 12A and the second system transistor 12B are turned off. This control is applied during the off operation of the main transistor 11. On the other hand, in the monitor transistor 13, the first system monitor transistor 14A and the second system monitor transistor 14B are turned off in conjunction with the main transistor 11.

[0050] When gate signals (that is, on signals) greater than or equal to the gate threshold voltage are input to all of the n first gates FG, the first system transistor 12A and the second system transistor 12B are turned on. As a result, the main transistor 11 generates an output current IO including the system current IS of the first system transistor 12A and the system current IS of the second system transistor 12B. In this case, the channel utilization rate of the main transistor 11 relatively increases, and the on-resistance relatively decreases. This control is applied during the normal operation of the main transistor 11.

[0051] On the other hand, in the monitor transistor 13, the first system monitor transistor 14A and the second system monitor transistor 14B are turned on in conjunction with the main transistor 11. The monitor transistor 13 generates a monitor current IM including the system monitor current ISM of the first system monitor transistor 14A and the system monitor current ISM of the second system monitor transistor 14B. In this case, the channel utilization rate of the monitor transistor 13 relatively increases, and the on-resistance relatively decreases.

[0052] When a gate signal (i.e., an ON signal) greater than or equal to the gate threshold voltage is input to the first gate FG of the first system transistor 12A, and a gate signal (i.e., an OFF signal) less than the gate threshold voltage is input to the first gate FG of the second system monitor transistor 14B, the first system transistor 12A turns ON and the second system monitor transistor 14B turns OFF.

[0053] As a result, the main transistor 11 generates an output current IO that includes the system current IS of the first system transistor 12A. In this case, the channel utilization of the main transistor 11 decreases relatively, and the on-resistance increases relatively. This control is applied when the main transistor 11 is in active clamp operation.

[0054] Meanwhile, in the monitor transistor 13, the first system monitor transistor 14A is turned on and the second system monitor transistor 14B is turned off in conjunction with the main transistor 11. The monitor transistor 13 generates a monitor current IM that includes the system monitor current ISM of the first system monitor transistor 14A. In this case, the channel utilization rate of the monitor transistor 13 decreases relatively, and the on-resistance increases relatively.

[0055] Referring to Figures 1 and 3, the semiconductor chip 1A includes a first temperature-sensing diode 15 as an example of a first temperature sensor formed in the first temperature-sensing region 9. The first temperature-sensing diode 15 has a temperature characteristic that varies with respect to the forward voltage according to the temperature of the output region 6, and generates a first temperature-sensing signal ST1 for detecting the temperature of the output region 6. The forward voltage may have a negative temperature characteristic that decreases linearly as the temperature of the output region 6 rises.

[0056] Referring to Figures 1 and 3, the semiconductor chip 1A includes a second temperature-sensing diode 16 as an example of a second temperature sensor formed in the second temperature-sensing region 10. The second temperature-sensing diode 16 has a temperature characteristic that varies with respect to the forward voltage according to the temperature of the control region 8, and generates a second temperature-sensing signal ST2 for detecting the temperature of the control region 8. The forward voltage may have a negative temperature characteristic that decreases linearly as the temperature of the control region 8 rises.

[0057] The second temperature-sensing diode 16 preferably has substantially the same configuration as the first temperature-sensing diode 15, and preferably has substantially the same electrical characteristics as the first temperature-sensing diode 15. When the main transistor 11 is generating the output current IO, the temperature of the control region 8 is less than the temperature of the output region 6. Therefore, when generating the output current IO, the forward voltage of the second temperature-sensing diode 16 is greater than the forward voltage of the first temperature-sensing diode 15.

[0058] The semiconductor chip 1A includes a control circuit 17 formed in the control region 8. The control circuit 17 may also be called a "Control Integrated Circuit (Control IC)". The control circuit 17, together with the main transistor 11, constitutes an Intelligent Power Device (IPD). The IPD may also be called an "Intelligent Power Module (IPM)". The control circuit 17 includes multiple functional circuits that realize various functions in response to electrical signals input from an external source.

[0059] In this configuration, the control circuit 17 includes a gate drive circuit 18, an active clamp circuit 19, an overcurrent protection circuit 20, and an overtemperature protection circuit 21. The overcurrent protection circuit 20 may be referred to as the "OCP (Over Current Protection) circuit," and the overtemperature protection circuit 21 may be referred to as the "TSD (Thermal Shutdown) circuit." The aforementioned monitor transistor 13, first temperature-sensing diode 15, and second temperature-sensing diode 16 constitute part of the control circuit 17.

[0060] The gate drive circuit 18 is electrically connected to the first gate FG of the main transistor 11 and the first monitor gate FMG of the monitor transistor 13, and generates gate signals that control the main transistor 11 and the monitor transistor 13 in response to an external electrical signal.

[0061] The active clamp circuit 19 is electrically connected to the main transistor 11 and the gate drive circuit 18. Specifically, the active clamp circuit 19 is electrically connected to some (but not all) of the first gate FG, the first drain FD, and the gate drive circuit 18.

[0062] The active clamp circuit 19 may include a first diode stage 19a, a second diode stage 19b, and an n-channel type MISFET 19c. The first diode stage 19a includes one or more Zener diodes forming a forward series circuit. The cathode of the first diode stage 19a is electrically connected to the first drain FD.

[0063] The second diode stage 19b includes one or more pn junction diodes that form a forward series circuit. The anode of the second diode stage 19b is reverse-biased to the anode of the first diode stage 19a. The cathode of the second diode stage 19b is electrically connected to the gate drive circuit 18.

[0064] The gate of MISFET19c is electrically connected to the cathode of the second diode stage 19b. The back gate of MISFET19c is electrically connected to the first source FS. The drain of MISFET19c is connected to the first drain FD. The source of MISFET19c is electrically connected to part (but not all) of the first gate FG.

[0065] The active clamp circuit 19 works in cooperation with the gate drive circuit 18 to limit (clamp) the output voltage when a back electromotive force is input to the main transistor 11 due to energy stored in the inductive load L, thereby protecting the main transistor 11 from the back electromotive force. In other words, the active clamp circuit 19 is configured to limit the output voltage until the back electromotive force is consumed by causing the main transistor 11 to perform an active clamp operation when a back electromotive force is input.

[0066] Specifically, during active clamp operation, the active clamp circuit 19 works in cooperation with the gate drive circuit 18 to control a portion of the main transistor 11 (for example, the first system transistor 12A) to the ON state and a portion of the main transistor 11 (for example, the second system transistor 12B) to the OFF state.

[0067] Furthermore, during active clamp operation, the active clamp circuit 19 works in cooperation with the gate drive circuit 18 to control a portion of the monitor transistor 13 (for example, the first system monitor transistor 14A) to the ON state and a portion of the monitor transistor 13 (for example, the second system monitor transistor 14B) to the OFF state.

[0068] The active clamp circuit 19 may be configured to control the on / off state of n system transistors 12 (system monitor transistors 14) when the first source FS of the main transistor 11 falls below a predetermined voltage (for example, a predetermined negative voltage).

[0069] The overcurrent protection circuit 20 is electrically connected to the monitor transistor 13 and the gate drive circuit 18. The overcurrent protection circuit 20 is electrically connected to the first monitor source FMS of the monitor transistor 13 and is configured to receive some or all (in this configuration, all) of the monitor current IM as input. The overcurrent protection circuit 20 works in cooperation with the gate drive circuit 18 to control the gate signal and protect the main transistor 11 from overcurrent.

[0070] The overcurrent protection circuit 20 may be configured to generate an overcurrent detection signal SC when the monitor current IM exceeds a predetermined threshold and to output the overcurrent detection signal SC to the gate drive circuit 18. The overcurrent detection signal SC is a signal for limiting some or all of the n gate signals generated in the gate drive circuit 18 to a predetermined value or less (for example, off).

[0071] The gate drive circuit 18 responds to the overcurrent detection signal SC by limiting some or all of the n gate signals to suppress the overcurrent flowing through the main transistor 11. When the monitor current IM falls below a predetermined threshold, the overcurrent protection circuit 20 switches the gate drive circuit 18 (main transistor 11) to normal control.

[0072] The overheat protection circuit 21 is electrically connected to the first temperature-sensing diode 15, the second temperature-sensing diode 16, and the gate drive circuit 18. The overheat protection circuit 21 is configured to cooperate with the gate drive circuit 18 to control the gate signal and protect the main transistor 11 from overheating. The overheat protection circuit 21 receives a first temperature detection signal ST1 from the first temperature-sensing diode 15 and a second temperature detection signal ST2 from the second temperature-sensing diode 16.

[0073] The overheat protection circuit 21 may be configured to generate an overheat detection signal SH when the difference between the first temperature measurement signal ST1 and the second temperature measurement signal ST2 exceeds a predetermined threshold, and to output the overheat detection signal SH to the gate drive circuit 18. The overheat detection signal SH is a signal used to limit some or all of the n gate signals generated in the gate drive circuit 18 to be turned off.

[0074] The gate drive circuit 18 controls some or all of the main transistor 11 to an off state in response to the overheat detection signal SH, thereby suppressing the temperature rise in the output region 6. The gate drive circuit 18 also controls some or all of the monitor transistor 13 to an off state in response to the overheat detection signal SH, thereby suppressing the temperature rise in the current detection region 7 (output region 6). When the difference value falls below a threshold, the overheat protection circuit 21 switches the gate drive circuit 18 to normal control.

[0075] Referring to Figure 2, the semiconductor chip 1A includes an interlayer insulating film 24 covering the first main surface 3. The interlayer insulating film 24 collectively covers the output region 6, the current detection region 7, the control region 8, the first temperature detection region 9, and the second temperature detection region 10. In this embodiment, the interlayer insulating film 24 has a multilayer wiring structure including a plurality of insulating films stacked on the first main surface 3 and a plurality of wirings arranged on any of the insulating films.

[0076] Each insulating film may include at least one of a silicon oxide film and a silicon nitride film. Each wiring may include at least one of a pure Al layer (Al layer with a purity of 99% or higher), a Cu layer (Cu layer with a purity of 99% or higher), an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer.

[0077] Referring to Figures 1 and 2, the semiconductor chip 1A includes multiple terminals 25-30. The number and layout of the multiple terminals 25-30 are adjusted as appropriate according to the specifications of the main transistor 11 and the control circuit 17. In this configuration, the multiple terminals 25-30 include a drain terminal 25 (power terminal), a source terminal 26 (output terminal), a first control terminal 27, a second control terminal 28, a third control terminal 29, and a fourth control terminal 30.

[0078] The drain terminal 25 covers the second main surface 4 of the substrate 2 and is electrically connected to the second main surface 4. The drain terminal 25 may include at least one of the Ti layer, Ni layer, Au layer, Ag layer, and Al layer. The drain terminal 25 may have a laminated structure in which at least two of the Ti layer, Ni layer, Au layer, Ag layer, and Al layer are stacked in any manner. The drain terminal 25 is electrically connected to the first drain FD of the main transistor 11 and transmits the power supply potential.

[0079] The source terminal 26 is positioned on the interlayer insulating film 24. The source terminal 26 covers the output region 6 such that the control region 8 is exposed in a plan view. The layout of the source terminal 26 is adjusted by the layout of the output region 6 and is not limited to a particular configuration. In this configuration, the source terminal 26 is formed in a rectangular shape (specifically, a rectangle extending in the first direction X) in a plan view. Of course, the source terminal 26 may be formed in a polygonal shape other than a rectangle in a plan view.

[0080] In this embodiment, the source terminal 26 has a rectangular notch 26a that exposes the first temperature sensing area 9 (first temperature sensing diode 15). The source terminal 26 is electrically connected to the first source FS of the main transistor 11 and transmits the output current IO to the outside. The source terminal 26 may include either or both of an Al-based metal layer and a Cu-based metal layer. The source terminal 26 may include at least one of a pure Al layer, a pure Cu layer, an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer.

[0081] The first to fourth control terminals 27 to 30 are located on the interlayer insulating film 24. The first to fourth control terminals 27 to 30 may be, for example, input terminals for supplying input signals to the control circuit 17, enable terminals for supplying enable signals to the control circuit 17, self-diagnosis output terminals for outputting electrical signals to diagnose the state of the control circuit 17, and ground terminals for supplying ground potential to the control circuit 17.

[0082] The first to fourth control terminals 27 to 30 each cover the area outside the output area 6 (specifically, the control area 8) in a plan view. Each of the first to fourth control terminals 27 to 30 has a planar area less than the planar area of ​​the source terminal 26. The first to fourth control terminals 27 to 30 may contain at least one of the following: a pure Al layer, a pure Cu layer, an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer.

[0083] The configuration of output region 6 will be explained below with reference to Figures 4 to 7. Figure 4 is a plan view showing the layout of output region 6. Figure 5 is a cross-sectional view along the VV line shown in Figure 4. Figure 6 is a cross-sectional view along the VI-VI line shown in Figure 4. Figure 7 is a cross-sectional view along the VII-VII line shown in Figure 4.

[0084] The semiconductor chip 1A includes an n-type (first conductivity type) first semiconductor region 31 formed on the surface layer of the first main surface 3 of the substrate 2. The first semiconductor region 31 forms the first drain FD of the main transistor 11 and the first monitor drain FMD of the monitor transistor 13. The first semiconductor region 31 may also be referred to as a "drift region".

[0085] The first semiconductor region 31 is formed over the entire surface layer of the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. The thickness of the first semiconductor region 31 may be 5 μm or more and 30 μm or less. Preferably, the thickness of the first semiconductor region 31 is 10 μm or more and 20 μm or less. In this embodiment, the first semiconductor region 31 is formed by an n-type epitaxial layer (Si epitaxial layer).

[0086] The semiconductor chip 1A includes an n-type second semiconductor region 32 formed on the surface layer of the second main surface 4 of the substrate 2. The second semiconductor region 32, together with the first semiconductor region 31, forms the first drain FD of the main transistor 11 and the first monitor drain FMD of the monitor transistor 13. The second semiconductor region 32 may also be referred to as the "drain region".

[0087] The second semiconductor region 32 is formed over the entire surface layer of the second main surface 4 so as to be electrically connected to the first semiconductor region 31, and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. The second semiconductor region 32 is thicker than the first semiconductor region 31. The thickness of the second semiconductor region 32 may be 10 μm or more and 450 μm or less. Preferably, the thickness of the second semiconductor region 32 is 50 μm or more and 150 μm or less. In this embodiment, the second semiconductor region 32 is formed from an n-type semiconductor substrate (Si semiconductor substrate).

[0088] The semiconductor chip 1A includes a p-type (second conductivity type) body region 33 formed on the surface of the first semiconductor region 31 of the output region 6 and the current detection region 7. The body region 33 is formed with a gap from the bottom of the first semiconductor region 31 toward the first main surface 3 and faces the second semiconductor region 32 with a portion of the first semiconductor region 31 in between.

[0089] The semiconductor chip 1A includes a plurality of trench structures 35 formed on the first main surface 3 in the output region 6. The trench structures 35 may also be referred to as "trench gate structures". The plurality of trench structures 35 include a plurality of trench structures 35 for the main transistor 11 formed in the output region 6, and a plurality of trench structures 35 for the monitor transistor 13 formed in the current sensing region 7. The number of trench structures 35 for the monitor transistor 13 is less than the number of trench structures 35 for the main transistor 11.

[0090] The multiple trench structures 35 are arranged at intervals in the first direction X in a plan view and are each formed in a strip shape extending in the second direction Y. The multiple trench structures 35 penetrate the body region 33 so as to reach the first semiconductor region 31. The multiple trench structures 35 are formed at intervals from the bottom of the first semiconductor region 31 toward the first main surface 3 and face the second semiconductor region 32 with a portion of the first semiconductor region 31 in between.

[0091] Each trench structure 35 has a first width W1 and a first depth D1. The first width W1 is the width in a direction perpendicular to the direction in which the trench structure 35 extends. The first width W1 may be 0.5 μm or more and 2 μm or less. Preferably, the first width W1 is 0.5 μm or more and 1.5 μm or less. The first depth D1 may be 1 μm or more and 10 μm or less. Preferably, the first depth D1 is 2 μm or more and 6 μm or less. The bottom wall of each trench structure 35 is preferably spaced 1 μm or more and 5 μm or less from the bottom of the first semiconductor region 31.

[0092] Multiple trench structures 35 are arranged in the first direction X with a trench spacing IT. The trench spacing IT may be 0.25 to 1.5 times the first width W1. Preferably, the trench spacing IT is less than or equal to the first width W1. The trench spacing IT may be 0.5 μm to 2 μm.

[0093] The configuration of one trench structure 35 is described below. The trench structure 35 has a multi-electrode structure including a trench 36, a first insulating film 37, a second insulating film 38, a first electrode 39, a second electrode 40, and a third insulating film 41. In other words, the trench structure 35 includes an electrode (gate electrode) embedded in the trench 36 with an insulator (gate insulator) in between. The insulator is composed of the first insulating film 37, the second insulating film 38, and the third insulating film 41. The electrode is composed of the first electrode 39 and the second electrode 40.

[0094] The trench 36 is excavated downward from the first main surface 3 towards the second main surface 4, and partitions the wall surface of the trench structure 35. The first insulating film 37 covers the upper wall surface of the trench 36 in a film-like manner. Specifically, the first insulating film 37 covers the upper wall surface located in the region of the trench 36 that is on the opening side relative to the bottom of the body region 33.

[0095] The first insulating film 37 has a portion that crosses the boundary between the first semiconductor region 31 and the body region 33 and covers the first semiconductor region 31. The first insulating film 37 may contain a silicon oxide film. Preferably, the first insulating film 37 contains a silicon oxide film made of the oxide of the substrate 2. The first insulating film 37 is formed as a gate insulating film.

[0096] The second insulating film 38 coats the lower wall surface of the trench 36 in a film-like manner. Specifically, the second insulating film 38 coats the lower wall surface located in the region of the trench 36 on the bottom wall side relative to the bottom of the body region 33. The second insulating film 38 coats the first semiconductor region 31. The second insulating film 38 may contain a silicon oxide film. Preferably, the second insulating film 38 contains a silicon oxide film made of the oxide of the substrate 2. Preferably, the second insulating film 38 is thicker than the first insulating film 37.

[0097] The first electrode 39 is embedded in the upper (opening) side of the trench 36, with the first insulating film 37 in between. In a plan view, the first electrode 39 is embedded in a strip shape extending in the second direction Y. The first electrode 39 faces the body region 33 and the first semiconductor region 31, with the first insulating film 37 in between. The first electrode 39 may contain conductive polysilicon. The first electrode 39 is formed as a gate electrode. A gate signal is input to the first electrode 39.

[0098] The second electrode 40 is embedded in the lower (bottom wall) side of the trench 36, with the second insulating film 38 in between. The second electrode 40 is embedded in a strip shape extending in the second direction Y in a plan view. The second electrode 40 may have a thickness (length) that exceeds the thickness (length) of the first electrode 39 with respect to the depth direction of the trench 36.

[0099] The second electrode 40 faces the first semiconductor region 31 across the second insulating film 38. The second electrode 40 has an upper end that protrudes from the second insulating film 38 toward the first main surface 3. The upper end of the second electrode 40 is aligned with the bottom of the second electrode 40 and faces the first insulating film 37 in a lateral direction along the first main surface 3, with the bottom of the second electrode 40 in between.

[0100] The second electrode 40 may contain conductive polysilicon. In this embodiment, the second electrode 40 is formed as a gate electrode and fixed at the same potential as the first electrode 39. That is, the same gate signal is applied to the second electrode 40 simultaneously with the first electrode 39. As a result, the voltage drop between the first electrode 39 and the second electrode 40 is suppressed, and electric field concentration between the first electrode 39 and the second electrode 40 is suppressed. In addition, the carrier density near the trench 36 increases, resulting in a decrease in the on-resistance of the substrate 2 (particularly the first semiconductor region 31).

[0101] The third insulating film 41 is interposed between the first electrode 39 and the second electrode 40, electrically insulating the first electrode 39 and the second electrode 40. The third insulating film 41 covers the portion of the second electrode 40 that is exposed from the second insulating film 38 and is connected to the first insulating film 37 and the second insulating film 38. The third insulating film 41 may contain a silicon oxide film. Preferably, the third insulating film 41 contains a silicon oxide film made of the oxide of the second electrode 40. Preferably, the third insulating film 41 is thinner than the second insulating film 38.

[0102] The semiconductor chip 1A includes a plurality of trench connection structures 45 formed on the first main surface 3 in the output region 6. The plurality of trench connection structures 45 are formed in the region on one end side of the plurality of trench structures 35 and in the region on the other end side of the plurality of trench structures 35, respectively. Figure 4 shows the region on one end side of the plurality of trench structures 35.

[0103] Each of the multiple trench connection structures 45 is formed in a strip shape extending in a second direction Y so as to connect one end of at least two (two in this embodiment) adjacent trench structures 35 in a first direction X. Each of the multiple trench connection structures 45 is formed in a strip shape extending in a second direction Y so as to connect the other ends of at least two (two in this embodiment) adjacent trench structures 35 in a first direction X.

[0104] The multiple trench connection structures 45, in a plan view, each constitute a single annular or ladder-shaped unit trench structure together with the multiple trench structures 35. The multiple trench connection structures 45 are formed at intervals from the bottom of the first semiconductor region 31 toward the first main surface 3, and face the second semiconductor region 32 with a portion of the first semiconductor region 31 in between.

[0105] The trench connection structure 45 on the other side has the same structure as the trench connection structure 45 on the one side, except that it is connected to the other end of the multiple trench structures 35. The configuration of one trench connection structure 45 on the one side will be described below, and the description of the trench connection structure 45 on the other side will be omitted.

[0106] The trench connection structure 45 has a first trench portion 45a extending in a first direction X and a plurality (two in this embodiment) of second trench portions 45b extending in a second direction Y. The first trench portion 45a faces a plurality of ends in a plan view. The plurality of second trench portions 45b extend from the first trench portion 45a toward a single end of the plurality of trench structures 35 and are connected to that single end.

[0107] The trench connection structure 45 has a second width W2 and a second depth D2. The second width W2 is the width in a direction perpendicular to the direction in which the trench connection structure 45 extends. Preferably, the second width W2 is approximately equal to the first width W1 of the trench structure 35. Preferably, the second depth D2 is approximately equal to the first depth D1 of the trench structure 35. Preferably, the bottom wall of the trench connection structure 45 is spaced at a distance of 1 μm to 5 μm from the bottom of the first semiconductor region 31.

[0108] The trench connection structure 45 has a single-electrode structure including a connection trench 46, a connection insulating film 47, and a connection electrode 48. The connection trench 46 is excavated from the first main surface 3 toward the second main surface 4 and demarcates the wall surface of the trench connection structure 45. The side walls and bottom walls of the connection trench 46 are connected to the side walls and bottom walls of the trench 36 of the trench structure 35.

[0109] The connecting insulating film 47 coats the wall surface of the connecting trench 46 in a film-like manner. The connecting insulating film 47 is connected to the first insulating film 37 and the second insulating film 38 at the communication portion between the trench 36 and the connecting trench 46. The connecting insulating film 47 may contain a silicon oxide film. Preferably, the connecting insulating film 47 contains a silicon oxide film made of the oxide of the substrate 2. Preferably, the connecting insulating film 47 is thicker than the first insulating film 37. The thickness of the connecting insulating film 47 may be approximately equal to the thickness of the second insulating film 38.

[0110] The connecting electrode 48 is embedded in the connecting trench 46 with a connecting insulating film 47 in between. The connecting electrode 48 may contain conductive polysilicon. The connecting electrode 48 extends in a first direction X in the first trench portion 45a and in a second direction Y in the second trench portion 45b. The connecting electrode 48 is connected to the second electrode 40 at the communication portion between the trench 36 and the connecting trench 46, and faces the first electrode 39 with a third insulating film 41 in between. The same gate signal is applied to the connecting electrode 48 simultaneously with the first electrode 39 and the second electrode 40.

[0111] The semiconductor chip 1A includes multiple n-type source regions 51 formed in the surface layer of the body region 33 of the output region 6 and the current detection region 7, along the regions of multiple trench structures 35. The n-type impurity concentration in the multiple source regions 51 is higher than that in the first semiconductor region 31. The multiple source regions 51 are arranged on both sides of each trench structure 35 and spaced apart along each trench structure 35. The multiple source regions 51 are formed spaced apart from the bottom of the body region 33 toward the first main surface 3 and face the first electrode 39 across the corresponding first insulating film 37.

[0112] It is preferable that the multiple source regions 51 along one trench structure 35 are arranged offset in the second direction Y relative to the multiple source regions 51 along the other trench structure 35. In other words, it is preferable that the multiple source regions 51 along one trench structure 35 are facing the region between the multiple source regions 51 along the other trench structure 35 in the first direction X.

[0113] The semiconductor chip 1A includes multiple p-type contact regions 52 formed along multiple trench structures 35 in the surface layer of the body region 33 of the output region 6 and the current detection region 7. The p-type impurity concentration in the multiple contact regions 52 is higher than that in the body region 33.

[0114] Multiple contact regions 52 are positioned on both sides of each trench structure 35 and are spaced apart along each trench structure 35. The multiple contact regions 52 are formed spaced apart from the bottom of the body region 33 toward the first main surface 3 and face the first electrode 39 with the corresponding first insulating film 37 in between.

[0115] Multiple contact regions 52 are arranged alternately with multiple source regions 51 on both sides of each trench structure 35. Preferably, the multiple contact regions 52 along one trench structure 35 are offset in the second direction Y relative to the multiple contact regions 52 along the other trench structure 35. In other words, preferably, the multiple contact regions 52 along one trench structure 35 are facing the region between the multiple contact regions 52 along the other trench structure 35 (i.e., the source region 51) in the first direction X.

[0116] The semiconductor chip 1A includes n gate wirings 53 arranged electrically independently of each other within the aforementioned interlayer insulating film 24. The n gate wirings 53 include n gate wirings 53 for the main transistor 11 and n gate wirings 53 for the monitor transistor 13. The n gate wirings 53 are selectively electrically connected to at least one corresponding trench structure 35 via a plurality of first via electrodes 54 in the output region 6 and the current sensing region 7, and are electrically connected to the control circuit 17 (gate drive circuit 18) in the control region 8. The plurality of first via electrodes 54 may contain tungsten.

[0117] Specifically, the n gate wires 53 for the main transistor 11 are electrically connected in the output region 6 to at least one (or more in this configuration) trench structures 35 and at least one (or more in this configuration) trench connection structures 45, which should be systematized (grouped) as system transistors 12 via a plurality of first via electrodes 54.

[0118] Here, an example is described in which n gate wirings 53 for the main transistor 11 include a first gate wiring 53A for the first system transistor 12A and a second gate wiring 53B for the second system transistor 12B. The first gate wiring 53A is electrically connected in the output region 6 to multiple unit trench structures (multiple trench structures 35 and multiple trench connection structures 45) that should be systematized (grouped) as the first system transistor 12A via multiple first via electrodes 54.

[0119] The second gate wiring 53B is located within the interlayer insulating film 24, electrically independent of the first gate wiring 53A. The second gate wiring 53B is electrically connected in the output region 6 to a plurality of unit trench structures (a plurality of trench structures 35 and a plurality of trench connection structures 45) that should be systematized (grouped) as the second system transistor 12B via a plurality of first via electrodes 54. In this configuration, the plurality of unit trench structures for the second system transistor 12B are systematized alternately with the plurality of unit trench structures for the first system transistor 12A.

[0120] On the other hand, the n gate wires 53 for the monitor transistor 13 are electrically connected in the current detection region 7 to at least one (or more in this configuration) trench structures 35 and at least one (or more in this configuration) trench connection structures 45, respectively, which should be systematized (grouped) as a system monitor transistor 14 via a plurality of first via electrodes 54. The number of trench structures 35 (or trench connection structures 45) constituting the system monitor transistor 14 is less than the number of trench structures 35 (or trench connection structures 45) constituting the system transistor 12.

[0121] Here, an example is described in which n gate wirings 53 for the monitor transistor 13 include a first gate wiring 53A for the first system monitor transistor 14A and a second gate wiring 53B for the second system monitor transistor 14B. The first gate wiring 53A is electrically connected in the current sensing region 7 to at least one trench structure 35 and at least one trench connection structure 45 to be systematized as the first system monitor transistor 14A via a plurality of first via electrodes 54.

[0122] The second gate wiring 53B is located within the interlayer insulating film 24, electrically independent of the first gate wiring 53A. The second gate wiring 53B is electrically connected in the current detection region 7 to at least one trench structure 35 and at least one trench connection structure 45 to be systematized as a second system monitor transistor 14B via a plurality of first via electrodes 54. The trench structure 35 for the second system monitor transistor 14B may be adjacent to the trench structure 35 for the first system monitor transistor 14A.

[0123] The first gate wiring 53A for the monitor transistor 13 may be formed integrally with the first gate wiring 53A for the main transistor 11. Similarly, the second gate wiring 53B for the monitor transistor 13 may be formed integrally with the second gate wiring 53B for the main transistor 11.

[0124] The semiconductor chip 1A includes a plurality of source connections 55 arranged within an interlayer insulating film 24. The plurality of source connections 55 include a first source connection 55A for the main transistor 11 and a second source connection 55B for the monitor transistor 13. The first source connection 55A covers the output region 6 within the interlayer insulating film 24 and is electrically connected to a plurality of source regions 51 and a plurality of contact regions 52 via a plurality of second via electrodes 56. The plurality of second via electrodes 56 may contain tungsten.

[0125] The second source wiring 55B is selectively routed within the interlayer insulating film 24 to the region between the current detection region 7 and the control region 8. The second source wiring 55B is electrically connected to a plurality of source regions 51 and a plurality of contact regions 52 via a plurality of second via electrodes 56 in the current detection region 7, and is electrically connected to the control circuit 17 (overcurrent protection circuit 20) in the control region 8.

[0126] The semiconductor chip 1A includes the aforementioned source terminal 26 positioned on the interlayer insulating film 24. In this embodiment, the source terminal 26 overlaps with a plurality of source wirings 55 (first source wiring 55A and second source wiring 55B) in a plan view and covers all trench structures 35 and all trench connection structures 45.

[0127] The source terminal 26 is electrically connected to the first source wiring 55A via a plurality of third via electrodes 57 arranged within the interlayer insulating film 24. The plurality of third via electrodes 57 are located in the region between the plurality of second via electrodes 56 in both plan and cross-sectional views. In other words, in this embodiment, the plurality of third via electrodes 57 do not face the second via electrodes 56 across the first source wiring 55A. Of course, the plurality of third via electrodes 57 may face the second via electrodes 56 across the first source wiring 55A.

[0128] The source terminal 26 preferably has a greater thickness than the source wiring 55. The thickness of the source terminal 26 preferably has a greater thickness than the first depth D1 of the multiple trench structures 35 (the second depth D2 of the trench connection structure 45). The thickness of the source terminal 26 preferably has a greater thickness than the interlayer insulating film 24. The thickness of the source terminal 26 may be 1 μm or more and 25 μm or less.

[0129] The thickness of the source terminal 26 may be 1 μm to 5 μm, 5 μm to 10 μm, 10 μm to 15 μm, 15 μm to 20 μm, or 20 μm to 25 μm. If the source terminal 26 mainly contains Al-based metal, the thickness of the source terminal 26 may be 1 μm to 10 μm. If the source terminal 26 mainly contains Cu-based metal, the thickness of the source terminal 26 may be 10 μm to 25 μm.

[0130] Figure 8 is a perspective view showing a semiconductor device 61 on which the semiconductor chip 1A shown in Figure 1 is mounted. Figure 9 is a plan view showing the internal structure of the semiconductor device 61 shown in Figure 8, along with a pseudo-bump 75 relating to the first layout example. Figure 10 is a cross-sectional view along the line XX shown in Figure 9. Figure 11 is a cross-sectional view along the line XI-XI shown in Figure 9. Figure 12 is a plan view showing the pseudo-bump 75 relating to the first layout example. Figure 13 is a cross-sectional view along the line XIII-XIII shown in Figure 12. Figure 14 is a cross-sectional view along the line XIV-XIV shown in Figure 12.

[0131] Referring to Figures 8 to 14, the semiconductor device 61 may also be referred to as a "semiconductor package" or "semiconductor module." The package type of the semiconductor device 61 can take various forms depending on the operating environment, the object to be mounted, the form of the semiconductor chip 1A, etc. Here, a form in which the semiconductor device 61 consists of an 8-pin SOP (Small Outline Package) is given as an example.

[0132] The semiconductor device 61 includes a rectangular parallelepiped package body 62. The package body 62 includes a matrix resin and a plurality of fillers. The matrix resin may be a thermosetting resin (e.g., epoxy resin). The plurality of fillers may be insulating spherical objects (e.g., silica particles).

[0133] The package body 62 has a first surface 63 on one side, a second surface 64 on the other side, and first to fourth side walls 65A to 65D connecting the first surface 63 and the second surface 64. The first surface 63 is the mounting surface, and the second surface 64 is the non-mounting surface. The first surface 63 and the second surface 64 are formed in a rectangular shape (in this form, a rectangle extending in the first direction X) when viewed from above.

[0134] The first side wall 65A and the second side wall 65B extend in a first direction X along the first main surface 3 and face the second direction Y. The first side wall 65A and the second side wall 65B form the long side of the package body 62. The third side wall 65C and the fourth side wall 65D extend in a second direction Y and face the first direction X. The third side wall 65C and the fourth side wall 65D form the short side of the package body 62.

[0135] The semiconductor device 61 includes a rectangular parallelepiped-shaped metal plate 66 disposed within a package body 62. The metal plate 66 may also be referred to as a metal "die pad". The metal plate 66 has a first plate surface 67 on one side, a second plate surface 68 on the other side, and first to fourth plate side walls 69A to 69D connecting the first plate surface 67 and the second plate surface 68.

[0136] The first plate surface 67 and the second plate surface 68 are formed in a rectangular shape (in this embodiment, a rectangle extending in the first direction X) when viewed from above. The second plate surface 68 is exposed from the second surface 64 of the package body 62. Of course, the metal plate 66 may be placed inside the package body 62 so that the second plate surface 68 is not exposed from the second surface 64.

[0137] The first plate sidewall 69A and the second plate sidewall 69B extend in a first direction X along the first main surface 3 and face the second direction Y. The first plate sidewall 69A and the second plate sidewall 69B form the long side of the metal plate 66. The third plate sidewall 69C and the fourth plate sidewall 69D extend in a second direction Y and face the first direction X. The third plate sidewall 69C and the fourth plate sidewall 69D form the short side of the metal plate 66.

[0138] The semiconductor device 61 includes at least one (or more in this embodiment) extensions 70 drawn out from the metal plate 66 within the package body 62 toward at least one of the first to fourth side walls 65A to 65D. The multiple extensions 70 include a first extension 70A and a second extension 70B.

[0139] The first extension 70A is drawn out in a strip shape from the third plate side wall 69C toward the third side wall 65C. In this embodiment, the first extension 70A has a bent portion that is bent toward the first surface 63 and is exposed at the third side wall 65C from the middle of the thickness range of the package body 62. The second extension 70B is drawn out in a strip shape from the fourth plate side wall 69D toward the fourth side wall 65D. In this embodiment, the second extension 70B has a bent portion that is bent toward the first surface 63 and is exposed at the fourth side wall 65D from the middle of the thickness range of the package body 62.

[0140] The semiconductor device 61 includes metal first to eighth lead terminals 71A to 71H, which are positioned inside the package body 62 at a distance from the metal plate 66 so as to be drawn out from inside the package body 62 to the outside. The first to fourth lead terminals 71A to 71D are arranged at a distance from each other in the first direction X on the first side wall 65A side and are each formed in a strip shape extending in the second direction Y. The fifth to eighth lead terminals 71E to 71H are arranged at a distance from each other in the first direction X on the second side wall 65B side and are each formed in a strip shape extending in the second direction Y.

[0141] The first to eighth lead terminals 71A to 71H each have an inner end, a strip portion, and an outer end. The inner end is positioned in the middle of the thickness range of the package body 62 so as to be on the first surface 63 side with respect to the height of the metal plate 66. The planar shape of the inner end is arbitrary. The strip portion extends from the inner end to the outside of the package body 62 and is bent towards the second surface 64 side outside the package body 62. The strip portion extends to a height position that crosses the second surface 64 of the package body 62. The outer end extends approximately parallel to the second surface 64 at a height position below the second surface 64 of the package body 62.

[0142] The semiconductor device 61 includes a semiconductor chip 1A disposed on a metal plate 66 (first plate surface 67) within the package body 62. The semiconductor chip 1A is disposed on the metal plate 66 with its drain terminal 25 facing the metal plate 66 (first plate surface 67).

[0143] The semiconductor device 61 includes a conductive bonding material 72 interposed between the semiconductor chip 1A and the metal plate 66 within the package body 62. Specifically, the conductive bonding material 72 is interposed between the drain terminal 25 and the metal plate 66, electrically and mechanically connecting the drain terminal 25 and the metal plate 66. The conductive bonding material 72 may contain solder or metal paste. The solder may be lead-free solder. The metal paste may contain at least one of Au, Ag, and Cu. The Ag paste may consist of Ag sintered paste.

[0144] The semiconductor device 61 includes a plurality of pseudo-bumps 75 positioned above the source terminals 26 within the package body 62, free from the wires. Each of the plurality of pseudo-bumps 75 consists of a metal mass formed using a wire bonding process to the source terminals 26. The wire bonding process is carried out using the capillary (wire supply device) of the bonding apparatus.

[0145] In the wire bonding process, first, a wire is supplied to the inner bore of the capillary, and an initial ball is formed at the tip of the capillary by electrical discharge machining of the wire. Next, the initial ball is brought into contact with the source terminal 26, and a load toward the source terminal 26 is applied to the initial ball, while ultrasonic vibrations are applied to the initial ball simultaneously. As a result, the initial ball is crushed and simultaneously pressed against the source terminal 26. After that, the wire is separated from the crushed initial ball, and a pseudo-bump 75 consisting of a bump-shaped (for example, roughly cylindrical) metal mass is formed.

[0146] Multiple pseudo-bumps 75 are densely arranged on the source terminal 26. Here, "densely" means that the area occupied by the multiple pseudo-bumps 75 on the source terminal 26 is large compared to other structures connected to the source terminal 26 (the true bumps 90 described later). The multiple pseudo-bumps 75 are arranged on the source terminal 26 with a first occupied area per unit square area.

[0147] Each of the multiple pseudo-bumps 75 has a first size S1 in plan view. The first size S1 is defined by the length of the widest part of the pseudo-bump 75 in plan view. The first size S1 may be between 50 μm and 250 μm.

[0148] The first size S1 may be 50 μm to 75 μm, 75 μm to 100 μm, 100 μm to 125 μm, 125 μm to 150 μm, 150 μm to 175 μm, 175 μm to 200 μm, 200 μm to 225 μm, or 225 μm to 250 μm. The first size S1 is preferably 75 μm to 200 μm. The first size S1 is particularly preferably 100 μm to 180 μm.

[0149] Multiple pseudo-bumps 75 are arranged on the source terminal 26 at a first pitch P1 in a plan view. The first pitch P1 is defined by the distance between the centers of the multiple pseudo-bumps 75. The multiple pseudo-bumps 75 may be arranged so as to be in contact with each other at the first pitch P1, or they may be arranged with a gap between them at the first pitch P1. It is preferable that the multiple pseudo-bumps 75 are arranged with a gap between them.

[0150] The first pitch P1 is preferably 1 to 2.5 times the first size S1. The ratio P1 / S1 of the first pitch P1 to the first size S1 may be 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, or 2.25 to 2.5. The ratio P1 / S1 is preferably greater than 1. The ratio P1 / S1 is particularly preferably 1.25 to 1.75.

[0151] The first pitch P1 may be 50 μm or more and 250 μm or less. The first pitch P1 may be 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, 100 μm or more and 125 μm or less, 125 μm or more and 150 μm or less, 150 μm or more and 175 μm or less, 175 μm or more and 200 μm or less, 200 μm or more and 225 μm or less, or 225 μm or more and 250 μm or less. It is preferable that the first pitch P1 is 75 μm or more and 200 μm or less. It is particularly preferable that the first pitch P1 is 100 μm or more and 180 μm or less.

[0152] The spacing I between multiple pseudo-bumps 75 may be 0 μm or more and 100 μm or less. The spacing I may be 0 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or more and 100 μm or less. It is preferable that the spacing I is 10 μm or more. It is particularly preferable that the spacing I is 30 μm or more and 60 μm or less.

[0153] Each of the multiple pseudo-bumps 75 has a first thickness T1. The first thickness T1 is defined by the thickness of the thickest part of the pseudo-bump 75 in a cross-sectional view. Preferably, the first thickness T1 is greater than the first depth D1 of the multiple trench structures 35. Preferably, the first thickness T1 is greater than the thickness of the source terminal 26. Preferably, the first thickness T1 is greater than the thickness of the first semiconductor region 31. The first thickness T1 may be greater than the thickness of the substrate 2. Of course, the first thickness T1 may also be less than the thickness of the substrate 2.

[0154] The first thickness T1 may be 10 μm to 150 μm or less. The first thickness T1 may be 10 μm to 25 μm, 25 μm to 50 μm, 50 μm to 75 μm, 75 μm to 100 μm, 100 μm to 125 μm, or 125 μm to 150 μm. The first thickness T1 is preferably 25 μm to 100 μm. The first thickness T1 is particularly preferably 50 μm or more.

[0155] It is preferable that at least three pseudo-bumps 75 are arranged on the source terminal 26 as a pseudo-bump group 76. In this case, it is preferable that the at least three pseudo-bumps 75 are arranged in a layout that is located at the vertices of an isosceles triangle in a plan view. It is particularly preferable that the isosceles triangle is an equilateral triangle.

[0156] It is preferable that at least seven pseudo-bumps 75 are arranged on the source terminal 26 as a pseudo-bump group 76. In this case, it is preferable that six pseudo-bumps 75 are arranged around one pseudo-bump 75 in a plan view. It is preferable that the six pseudo-bumps 75 are arranged in concentric circles centered on the central part of one pseudo-bump 75 in a plan view.

[0157] It is preferable that six pseudo-bumps 75 are arranged in a layout where they are located at the vertices of a hexagon in a plan view, and one pseudo-bump 75 is located at the center of the hexagon in a plan view. In other words, it is preferable that the multiple pseudo-bumps 75 are joined to the source terminal 26 in a layout that forms a hexagonal close-packed arrangement (i.e., a honeycomb arrangement) in a plan view. In this case, it is most preferable that the hexagon is a regular hexagon.

[0158] In this configuration, a group of pseudo-bumps 76, including 28 pseudo-bumps 75 arranged in a hexagonally close-packed layout, is joined to the source terminal 26. The number of pseudo-bumps 75 joined to the source terminal 26 is arbitrary, but it is preferable that a group of pseudo-bumps 76 containing at least 3 pseudo-bumps 75, and / or a group of pseudo-bumps 76 containing at least 7 pseudo-bumps 75, is joined to the source terminal 26. Of course, multiple groups of pseudo-bumps 76 may be joined to the source terminal 26 at a distance greater than the first pitch P1 (spacing I).

[0159] The bonding locations of the multiple pseudo-bumps 75 (pseudo-bump group 76) to the source terminal 26 may be set based on the temperature distribution of the semiconductor chip 1A. For example, the high-temperature and low-temperature regions of the output region 6 may be analyzed using thermography or simulation tools, and multiple pseudo-bumps 75 (pseudo-bump group 76) may be bonded to the portion of the source terminal 26 that covers the high-temperature region of the output region 6.

[0160] For example, the temperature of the inner part of the output region 6 (e.g., the central part) tends to rise more easily than the peripheral part of the output region 6. Therefore, multiple pseudo-bumps 75 (pseudo-bump group 76) may be joined to the source terminal 26 in a layout that is dense in the inner part of the source terminal 26 (e.g., the central part) and sparse at the peripheral part of the source terminal 26. The configuration in which the multiple pseudo-bumps 75 are "sparse" includes a configuration in which no pseudo-bumps 75 exist. In this configuration, one pseudo-bump 75 is arranged along each of the three sides of the peripheral part of the source terminal 26.

[0161] The temperature of the control region 8 is lower than the temperature of the output region 6. In this configuration, the source terminal 26 covers the output region 6 so as to expose the control region 8, and multiple pseudo-bumps 75 (pseudo-bump group 76) are arranged in a region that overlaps with the output region 6 in a plan view. In other words, the multiple pseudo-bumps 75 (pseudo-bump group 76) are arranged in a position that overlaps with the main transistor 11 in a plan view, and are not arranged in a region that overlaps with the control region 8 in a plan view.

[0162] Some of the multiple pseudo-bumps 75 (pseudo-bump group 76) may face the monitor transistor 13 in a plan view. In other words, the multiple pseudo-bumps 75 (pseudo-bump group 76) may face the multiple trench structures 35 for the main transistor 11 and the multiple trench structures 35 for the monitor transistor 13. Of course, the multiple pseudo-bumps 75 (pseudo-bump group 76) may be arranged on the source terminal 26 so as not to face the multiple trench structures 35 for the monitor transistor 13.

[0163] Each pseudo-bump 75 may face 10 to 200 trench structures 35. The number of trench structures 35 facing each pseudo-bump 75 may be 10 to 25, 25 to 50, 50 to 75, 75 to 100, 100 to 125, 125 to 150, 150 to 175, or 175 to 200. Preferably, the number of trench structures 35 facing each pseudo-bump 75 is 25 to 100.

[0164] The specific shape of one pseudo-bump 75 will be described below with reference to Figure 13. In this embodiment, the pseudo-bump 75 includes a first bump body 77 and a first bump metal film 78. The first bump body 77 includes a first metal. The first metal includes at least one of Cu-based metals, Al-based metals, Au-based metals, and Ag-based metals.

[0165] The Cu-based metal may contain pure Cu or a Cu alloy. The Al-based metal may contain pure Al or an Al alloy. The Au-based metal may contain pure Au or an Au alloy. The Ag-based metal may contain pure Ag or an Ag alloy. In this embodiment, the first bump body 77 contains pure Cu.

[0166] The first bump body 77 includes a first body portion 79 and a first neck portion 80. The first body portion 79 consists of a wide portion connected to the source terminal 26. The first body portion 79 is formed in a substantially cylindrical shape with side walls that curve outward in cross-sectional view. The first body portion 79 has a first body size SB1 that forms the first size S1 of the pseudo-bump 75 in plan view.

[0167] The first body portion 79 may have a first body thickness TB1 that is 0.1 times or more and 0.9 times or less the first thickness T1 of the pseudo-bump 75. Preferably, the first body thickness TB1 is greater than the thickness of the first semiconductor region 31. The first body thickness TB1 may also be greater than the thickness of the substrate 2. Of course, the first body thickness TB1 may also be less than the thickness of the substrate 2.

[0168] The thickness ratio T1 / TB1 of the first body thickness TB1 to the first thickness T1 may be 0.1 or more and 0.2 or less, 0.2 or more and 0.3 or less, 0.3 or more and 0.4 or less, 0.4 or more and 0.5 or less, 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, or 0.8 or more and 0.9 or less. A thickness ratio T1 / TB1 of 0.4 or more and 0.7 or less is preferred. A thickness ratio T1 / TB1 of 0.5 or more is particularly preferred.

[0169] The first neck portion 80 consists of a portion that protrudes from the first body portion 79 toward the opposite side of the source terminal 26 and is narrower than the first body portion 79. The first neck portion 80 is formed in a substantially cylindrical shape in cross-section. In this embodiment, the first neck portion 80 has a first upper end portion 81 that slopes downward diagonally. Specifically, the first upper end portion 81 may have an upper end top portion 82, an upper end base portion 83, and an inclined portion 84 in cross-section.

[0170] The upper end vertex 82 is formed on one side of the peripheral edge of the first upper end portion 81 in a cross-sectional view. The upper end base portion 83 is formed on the other side of the peripheral edge of the first upper end portion 81 in a cross-sectional view and is located on the first body portion 79 side with respect to the height position of the upper end vertex 82. The inclined portion 84 slopes diagonally downward from the upper end vertex 82 toward the upper end base portion 83 in a cross-sectional view. The first upper end portion 81 may have an upper end projection 85 that protrudes from the upper end base portion 83 toward the side opposite to the first body portion 79. The tip of the upper end projection 85 may be formed at a height position on the first body portion 79 side with respect to the height position of the tip of the upper end vertex 82.

[0171] The first neck portion 80 has a first neck size SN1 that is less than the first body size SB1 in a plan view. The first neck size SN1 may be 0.1 times or more and 0.9 times or less the first body size SB1 (first size S1).

[0172] The size ratio SN1 / SB1, which is the ratio of the first neck size SN1 to the first body size SB1, may be 0.1 to 0.2, 0.2 to 0.3, 0.3 to 0.4, 0.4 to 0.5, 0.5 to 0.6, 0.6 to 0.7, 0.7 to 0.8, or 0.8 to 0.9. A size ratio SN1 / SB1 of 0.5 to 0.7 is preferred. A size ratio SN1 / SB1 greater than 0.5 is particularly preferred.

[0173] The first bump metal film 78 contains a second metal different from the first metal of the first bump body 77 and covers at least a portion of the outer surface of the first bump body 77. The first bump metal film 78 covers the area outside the upper end top 82 of the outer surface of the first bump body 77 so as to expose the upper end top 82.

[0174] Figure 13 shows a configuration in which the first bump metal film 78 covers the entire area outside the upper top portion 82, but the first bump metal film 78 does not necessarily have to have this configuration. Furthermore, the configuration of the first bump metal film 78 between multiple pseudo-bumps 75 is indeterminate and does not settle into a fixed configuration.

[0175] For example, the first bump metal film 78 only needs to cover at least a portion of the outer surface of the first bump body 77 such that the first bump body 77 (first metal) is partially exposed in the region outside the upper end top portion 82, and a portion of the first bump metal film 78 may be located inside the first bump body 77.

[0176] For example, a portion of the first bump metal film 78 may be fused into the interior of the first bump body 77. For example, the covering area of ​​the first bump metal film 78 over the first bump body 77 may be less than the exposed area of ​​the first bump body 77 over the first bump metal film 78. Of course, the covering area of ​​the first bump metal film 78 over the first bump body 77 may be greater than or equal to the exposed area of ​​the first bump body 77 over the first bump metal film 78.

[0177] The first bump metal film 78 is preferably made of a plated film. The first bump metal film 78 is preferably made of at least one of a Ni plated film, a Pd plated film, and an Au plated film. For example, the first bump metal film 78 may have a laminated structure in which a Ni plated film, a Pd plated film, and an Au plated film are laminated in this order from the first bump body 77.

[0178] For example, the first bump metal film 78 may have a laminated structure including a Ni plating film and a Pd plating film laminated in that order from the first bump body 77. For example, the first bump metal film 78 may have a single-layer structure consisting of a Ni plating film, a Pd plating film, or an Au plating film.

[0179] The semiconductor device 61 includes at least one (in this embodiment, more than one) first bonding wire 89 located within the package body 62. The multiple first bonding wires 89 electrically connect the source terminal 26 to at least one connection target selected from the first to eighth lead terminals 71A to 71H (in this embodiment, the first to fourth lead terminals 71A to 71D). The number of first bonding wires 89 can be one or more, and is not limited to a specific number.

[0180] In this configuration, four first bonding wires 89 are connected to the source terminal 26 and the first lead terminal 71A, four first bonding wires 89 are connected to the source terminal 26 and the second lead terminal 71B, four first bonding wires 89 are connected to the source terminal 26 and the third lead terminal 71C, and four first bonding wires 89 are connected to the source terminal 26 and the fourth lead terminal 71D.

[0181] Each of the multiple first bonding wires 89 includes a true bump 90, a wire loop 91, and a wire tail 92. The true bump 90 is a metal block joined to the source terminal 26 while connected to a wire (wire loop 91). The wire loop 91 is a wire portion that extends in an arch shape in the region between the true bump 90 and the object to be connected. The wire tail 92 is the wire end joined to the object to be connected. The multiple first bonding wires 89 are formed through a wire bonding process using a capillary (wire supply device) of a bonding apparatus.

[0182] In the wire bonding process, first, a wire is supplied to the inner bore of the capillary, and an initial ball is formed at the tip of the capillary by electrical discharge machining of the wire. Next, the initial ball is brought into contact with the source terminal 26, and a load toward the source terminal 26 is applied to the initial ball, while ultrasonic vibrations are applied to the initial ball simultaneously. As a result, the initial ball is crushed and pressed against the source terminal 26. In addition, a true bump 90 made of a bump-shaped (for example, roughly cylindrical) metal block is formed.

[0183] Next, the capillary is moved from the true bump 90 to the object to be connected, while pulling out the wire. This forms an arched wire loop 91 between the true bump 90 and the object to be connected. Then, a portion of the wire loop 91 comes into contact with the object to be connected, and a load directed toward the object is applied to the wire loop 91, while ultrasonic vibrations are applied to the wire loop 91. This causes a portion of the wire loop 91 to be crushed and crimped to the object to be connected. After that, the wire is detached from the crimped portion of the wire loop 91, and a wire tail 92 is formed.

[0184] The following describes several configurations of genuine bumps 90. The multiple genuine bumps 90 are arranged on the source terminal 26 at intervals from the multiple pseudo-bumps 75 (pseudo-bump group 76). In this configuration, the multiple genuine bumps 90 are arranged on the periphery of the source terminal 26 at intervals along its edge. The placement of the multiple genuine bumps 90 is not limited to a specific location, but is possible in any available space between the periphery of the source terminal 26 and the multiple pseudo-bumps 75 (pseudo-bump group 76).

[0185] Multiple genuine bumps 90 are spaced more sparsely on the source terminal 26 than multiple pseudo-bumps 75. Here, "sparsely" means that the area occupied by the multiple genuine bumps 90 on the source terminal 26 is smaller than the area occupied by the multiple pseudo-bumps 75 on the source terminal 26.

[0186] Even when only a single genuine bump 90 is placed on the source terminal 26, and the area occupied by that single genuine bump 90 is smaller than the area occupied by multiple pseudo-bumps 75, the genuine bumps 90 are included in the "sparsely arranged" configuration. In other words, it is sufficient that one or more genuine bumps 90 are placed on the source terminal 26 with a second area occupied per unit area that is less than the first area occupied by multiple pseudo-bumps 75.

[0187] Each of the multiple true bumps 90 has a second size S2 in plan view. The second size S2 is defined by the length of the widest part of the true bump 90 in plan view. The second size S2 may be between 50 μm and 250 μm.

[0188] The second size S2 may be 50 μm to 75 μm, 75 μm to 100 μm, 100 μm to 125 μm, 125 μm to 150 μm, 150 μm to 175 μm, 175 μm to 200 μm, 200 μm to 225 μm, or 225 μm to 250 μm. The second size S2 is preferably 75 μm to 200 μm. The second size S2 is particularly preferably 100 μm to 180 μm.

[0189] The second size S2 may be greater than or equal to the first size S1 of the pseudo-bump 75, or less than the first size S1. Preferably, the second size S2 is approximately equal to the first size S1. With this configuration, the pseudo-bump 75 and the true bump 90 can be formed under the same manufacturing conditions with respect to size.

[0190] Multiple genuine bumps 90 are arranged on the source terminal 26 at a second pitch P2 greater than or equal to the first pitch P1 of the pseudo-bumps 75 in a plan view. The second pitch P2 is defined by the distance between the centers of two adjacent genuine bumps 90. Preferably, the multiple genuine bumps 90 are arranged with a gap of the second pitch P2 between them so that they do not come into contact with each other.

[0191] The second pitch P2 can take any value as long as the entire true bump 90 is located within the range surrounded by the periphery of the source terminal 26 and is greater than or equal to the first pitch P1. For example, the pitch ratio P2 / P1 of the second pitch P2 to the first pitch P1 may be between 1 and 20. The pitch ratio P2 / P1 may be between 1 and 2, between 2 and 5, between 5 and 10, between 10 and 15, or between 15 and 20. It is preferable that the pitch ratio P2 / P1 is greater than 1.

[0192] Multiple true bumps 90 are positioned above the source terminal 26 at a third pitch P3 relative to one adjacent pseudo-bump 75. The third pitch P3 is defined by the distance between the central portions of the adjacent pseudo-bumps 75 and true bumps 90. Preferably, the third pitch P3 is greater than or equal to the first pitch P1 of the pseudo-bump 75. Preferably, at least one true bump 90 is positioned at a third pitch P3 greater than the first pitch P1. In this embodiment, all true bumps 90 are positioned at a third pitch P3 greater than the first pitch P1.

[0193] The third pitch P3 can take any value as long as the entire true bump 90 is located within the range surrounded by the periphery of the source terminal 26 and is greater than or equal to the first pitch P1. For example, the pitch ratio P3 / P1 of the third pitch P3 to the first pitch P1 may be between 1 and 20. The pitch ratio P2 / P1 may be between 1 and 2, between 2 and 5, between 5 and 10, between 10 and 15, or between 15 and 20.

[0194] Each of the multiple true bumps 90 has a second thickness T2. The second thickness T2 is defined by the thickness of the thickest part of the true bump 90 in a cross-sectional view. Preferably, the second thickness T2 is greater than the first depth D1 of the multiple trench structures 35. Preferably, the second thickness T2 is greater than the thickness of the source terminal 26. Preferably, the second thickness T2 is greater than the thickness of the first semiconductor region 31. The second thickness T2 may be greater than the thickness of the substrate 2. Of course, the second thickness T2 may also be less than the thickness of the substrate 2.

[0195] The second thickness T2 may be 10 μm to 150 μm or less. The second thickness T2 may be 10 μm to 25 μm, 25 μm to 50 μm, 50 μm to 75 μm, 75 μm to 100 μm, 100 μm to 125 μm, or 125 μm to 150 μm. The second thickness T2 is preferably 25 μm to 100 μm. The second thickness T2 is particularly preferably 50 μm or more.

[0196] The second thickness T2 may be greater than or equal to the first thickness T1 of the pseudo-bump 75, or less than the first thickness T1. Preferably, the second thickness T2 is approximately equal to the first thickness T1. With this configuration, the pseudo-bump 75 and the true bump 90 can be formed under the same manufacturing conditions with respect to thickness.

[0197] The multiple true bumps 90 are positioned in a region that overlaps with the output region 6 in a plan view. In other words, the multiple true bumps 90 are positioned in a location that overlaps with the main transistor 11 in a plan view, and are not positioned in a region that overlaps with the control region 8 in a plan view. Some of the multiple true bumps 90 may face the monitor transistor 13 in a plan view.

[0198] In other words, the multiple true bumps 90 may face the multiple trench structures 35 for the main transistor 11 and the multiple trench structures 35 for the monitor transistor 13. Of course, the multiple true bumps 90 may be positioned above the source terminal 26 so as not to face the multiple trench structures 35 for the monitor transistor 13.

[0199] Each true bump 90 may face 10 to 200 trench structures 35. The number of trench structures 35 facing each true bump 90 may be 10 to 25, 25 to 50, 50 to 75, 75 to 100, 100 to 125, 125 to 150, 150 to 175, or 175 to 200. Preferably, the number of trench structures 35 facing each true bump 90 is 25 to 100.

[0200] The specific shape of one true bump 90 will be described below with reference to Figure 14. In this embodiment, the true bump 90 includes a second bump body 97 and a second bump metal film 98. The second bump body 97 includes a first metal. The first metal includes at least one of Cu-based metals, Al-based metals, Au-based metals, and Ag-based metals.

[0201] Cu-based metals may include pure Cu or Cu alloys. Al-based metals may include pure Al or Al alloys. Au-based metals may include pure Au or Au alloys. Ag-based metals may include pure Ag or Ag alloys. In this embodiment, the second bump body 97 contains pure Cu. Preferably, the second bump body 97 contains the same metal as the first bump body 77 of the pseudo-bump 75. Of course, the second bump body 97 may contain a different metal than the first bump body 77.

[0202] The second bump body 97 includes a second body portion 99 and a second neck portion 100. The second body portion 99 consists of a wide portion connected to the source terminal 26. The second body portion 99 is formed in a substantially cylindrical shape with side walls that curve outward in cross-sectional view. The second body portion 99 has a second body size SB2 that forms the second size S2 of the true bump 90 in plan view.

[0203] The second body portion 99 may have a second body thickness TB2 that is 0.1 times or more and 0.9 times or less the second thickness T2 of the true bump 90. Preferably, the second body thickness TB2 is greater than the thickness of the first semiconductor region 31. The second body thickness TB2 may also be greater than the thickness of the substrate 2. Of course, the second body thickness TB2 may also be less than the thickness of the substrate 2.

[0204] The thickness ratio T2 / TB2 of the second body thickness TB2 to the second thickness T2 may be 0.1 to 0.2, 0.2 to 0.3, 0.3 to 0.4, 0.4 to 0.5, 0.5 to 0.6, 0.6 to 0.7, 0.7 to 0.8, or 0.8 to 0.9. A thickness ratio T2 / TB2 of 0.4 to 0.7 is preferred. A thickness ratio T2 / TB2 of 0.5 or higher is particularly preferred. The second body thickness TB2 may be approximately equal to the first body thickness TB1 of the pseudo-bump 75.

[0205] The second neck portion 100 consists of a portion that protrudes from the second body portion 99 toward the opposite side of the source terminal 26 and is narrower than the second body portion 99. The second neck portion 100 is formed in a substantially cylindrical shape in cross-section. The second neck portion 100 has a second upper end portion 101 connected to the wire loop 91. Unlike the first upper end portion 81 of the first neck portion 80, the second upper end portion 101 does not have an upper end top portion 82, an upper end base portion 83, and an inclined portion 84.

[0206] The second neck portion 100 has a second neck size SN2 that is less than the second body size SB2 in a plan view. The second neck size SN2 may be 0.1 times or more and 0.9 times or less the second body size SB2 (first size S1).

[0207] The size ratio SN2 / SB2, which is the ratio of the second neck size SN2 to the second body size SB2, may be 0.1 to 0.2, 0.2 to 0.3, 0.3 to 0.4, 0.4 to 0.5, 0.5 to 0.6, 0.6 to 0.7, 0.7 to 0.8, or 0.8 to 0.9. A size ratio SN2 / SB2 of 0.5 to 0.7 is preferred. A size ratio SN2 / SB2 greater than 0.5 is particularly preferred. The second neck size SN2 may be approximately equal to the first neck size SN1 of the pseudo-bump 75.

[0208] The second bump metal film 98 contains a second metal different from the first metal of the second bump body 97 and covers at least a portion of the outer surface of the second bump body 97. The second bump metal film 98 also covers at least a portion of the outer surface of the wire loop 91 and at least a portion of the outer surface of the wire tail 92.

[0209] Figure 14 shows a configuration in which the second bump metal film 98 covers the entire outer surface of the second bump body 97, but the second bump metal film 98 does not necessarily have to have this configuration. Furthermore, the configuration of the second bump metal film 98 between multiple true bumps 90 is indeterminate and does not settle into a fixed configuration.

[0210] For example, the second bump metal film 98 only needs to cover at least a portion of the outer surface of the second bump body 97 (first metal) so as to partially expose the second bump body 97, and a portion of the second bump metal film 98 may be located inside the second bump body 97.

[0211] For example, a portion of the second bump metal film 98 may be fused into the interior of the second bump body 97. For example, the covering area of ​​the second bump metal film 98 over the second bump body 97 may be less than the exposed area of ​​the second bump body 97 over the second bump metal film 98. Of course, the covering area of ​​the second bump metal film 98 over the second bump body 97 may be greater than or equal to the exposed area of ​​the second bump body 97 over the second bump metal film 98.

[0212] The second bump metal film 98 is preferably made of a plated film. The second bump metal film 98 is preferably made of at least one of a Ni plated film, a Pd plated film, and an Au plated film. For example, the second bump metal film 98 may have a laminated structure in which a Ni plated film, a Pd plated film, and an Au plated film are laminated in this order from the second bump body 97.

[0213] For example, the second bump metal film 98 may have a laminated structure including a Ni plating film and a Pd plating film laminated in this order from the second bump body 97. For example, the second bump metal film 98 may have a single-layer structure consisting of a Ni plating film, a Pd plating film, or an Au plating film. It is preferable that the second bump metal film 98 has the same configuration as the first bump metal film 78 of the pseudo-bump 75.

[0214] Referring to Figures 13 and 14, the semiconductor device 61 includes a plurality of first thin film portions 111, a plurality of second thin film portions 112, and a thick film portion 113 formed on the source terminal 26. Each of the plurality of first thin film portions 111 consists of a portion of the source terminal 26 that has sunk due to the bonding of the plurality of pseudo-bumps 75, and is formed at the bonding portion of the plurality of pseudo-bumps 75 on the source terminal 26.

[0215] The multiple second thin film portions 112 each consist of parts of the source terminal 26 that have settled due to the bonding of the multiple true bumps 90, and are formed at the bonding points of the multiple true bumps 90 on the source terminal 26. The thick film portion 113 consists of parts that have escaped settlement due to the bonding of the multiple pseudo-bumps 75 and the multiple true bumps 90, and is formed in the region outside the bonding points of the multiple pseudo-bumps 75 and the bonding points of the multiple true bumps 90 on the source terminal 26.

[0216] The maximum thickness of the thick film portion 113 is greater than the minimum thickness of the first thin film portion 111 (second thin film portion 112), and may be 2.5 times or less the minimum thickness of the first thin film portion 111 (second thin film portion 112). The thickness ratio of the maximum thickness to the minimum thickness may be greater than 1 and be 1.25 or less, 1.25 or more and 1.5 or less, 1.5 or more and 1.75 or less, 1.75 or more and 2 or less, 2 or more and 2.25 or less, or 2.25 or more and 2.5 or less.

[0217] The semiconductor device 61 includes a plurality of first raised portions 114 formed on the source terminal 26. The plurality of first raised portions 114 are formed on the bonding edges of a plurality of pseudo-bumps 75 on the source terminal 26, and a portion of the source terminal 26 is thicker than the thick film portion 113. Each first raised portion 114 extends in an annular shape along the edge (bonding edge) of each pseudo-bump 75 in a plan view. At least a portion of each first raised portion 114 faces the peripheral edge of each pseudo-bump 75 in the thickness direction.

[0218] The portion along the edge of each pseudo-bump 75 in the source terminal 26 is thicker than the first thin film portion 111 (second thin film portion 112) due to the thick film portion 113 and the first raised portion 114. Furthermore, the portion located between the multiple pseudo-bumps 75 in the source terminal 26 is thicker than the multiple first thin film portions 111 (second thin film portion 112) due to the thick film portion 113 and the multiple first raised portions 114.

[0219] The portion of the source terminal 26 located between the multiple pseudo-bumps 75 is preferably facing the multiple trench structures 35. In other words, in the region between the multiple pseudo-bumps 75, the thick film portion 113 and the multiple first raised portions 114 are preferably facing the multiple trench structures 35.

[0220] Each first raised portion 114 faces at least one trench structure 35 in the thickness direction. In this embodiment, each first raised portion 114 is formed to face a plurality of trench structures 35 in the thickness direction. Preferably, the raised height of at least one first raised portion 114 with respect to the thick film portion 113 is greater than the first depth D1 of the trench structure 35. The raised height of at least one first raised portion 114 may be greater than the thickness of the first semiconductor region 31. Of course, the raised height of at least one first raised portion 114 may be less than or equal to the first depth D1 of the trench structure 35.

[0221] The first total thickness of the thick film portion 113 and the first raised portion 114 is preferably greater than the thickness of the interlayer insulating film 24. The first total thickness is greater than 1 times the minimum thickness of the first thin film portion 111 (second thin film portion 112) and may be 10 times or less the minimum thickness of the first thin film portion 111 (second thin film portion 112). The thickness ratio of the first total thickness to the minimum thickness may be greater than 1 and 2 or less, 2 or more and 4 or less, 4 or more and 6 or less, 6 or more and 8 or less, or 8 or more and 10 or less. The thickness ratio is preferably 2 or more and 6 or less.

[0222] A first raised portion 114 formed on one pseudo-bump 75 side may be integrated with a first raised portion 114 formed on the other pseudo-bump 75 side. In other words, the portion of the source terminal 26 located between the multiple pseudo-bumps 75 may be thicker than the multiple first thin film portions 111 (second thin film portions 112) by a first raised portion 114 that can be considered as one. Preferably, the first raised portion 114 that can be considered as one faces the multiple trench structures 35.

[0223] The semiconductor device 61 includes a plurality of second raised portions 115 formed on the source terminal 26. The plurality of second raised portions 115 are formed on the bonding edges of a plurality of true bumps 90 on the source terminal 26, and consist of a portion of the source terminal 26 that is thicker than the thick film portion 113. Each second raised portion 115 extends in an annular shape along the edge (bonding edge) of each true bump 90 in a plan view. At least a portion of each second raised portion 115 faces the peripheral edge of each true bump 90 in the thickness direction.

[0224] The portion along the edge of each genuine bump 90 in the source terminal 26 is thicker than the first thin film portion 111 (second thin film portion 112) due to the thick film portion 113 and the second raised portion 115. Also, the portion located between the multiple genuine bumps 90 in the source terminal 26 is thicker than the first thin film portion 111 (second thin film portion 112) due to the thick film portion 113 and the multiple second raised portions 115. Furthermore, the portion located between the pseudo bump 75 and the genuine bump 90 in the source terminal 26 is thickened by the thick film portion 113 and the multiple second raised portions 115. At least a portion of each second raised portion 115 faces the peripheral edge of each genuine bump 90 in the thickness direction.

[0225] Each second ridge 115 faces at least one trench structure 35 in the thickness direction. In this embodiment, each second ridge 115 is formed to face multiple trench structures 35 in the thickness direction. Preferably, the ridge height of at least one second ridge 115 with respect to the thick film portion 113 is greater than the first depth D1 of the trench structure 35. The ridge height of at least one second ridge 115 may be greater than the thickness of the first semiconductor region 31. Of course, the ridge height of at least one second ridge 115 may be less than or equal to the first depth D1 of the trench structure 35.

[0226] The second total thickness of the thick film portion 113 and the second raised portion 115 is preferably greater than the thickness of the interlayer insulating film 24. The second total thickness is greater than 1 times the minimum thickness of the first thin film portion 111 (second thin film portion 112) and may be 10 times or less the minimum thickness of the first thin film portion 111 (second thin film portion 112). The thickness ratio of the second total thickness to the minimum thickness may be greater than 1 and 2 or less, 2 or more and 4 or less, 4 or more and 6 or less, 6 or more and 8 or less, or 8 or more and 10 or less. The thickness ratio is preferably 2 or more and 6 or less.

[0227] The semiconductor device 61 includes at least one (in this embodiment, more than one) second bonding wire 119 located within the package body 62. The multiple second bonding wires 119 electrically connect the first to fourth control terminals 27 to 30 to at least one connection target selected from the first to eighth lead terminals 71A to 71H (in this embodiment, the fifth to eighth lead terminals 71E to 71H).

[0228] The number of second bonding wires 119 connected to the first to fourth control terminals 27 to 30 can be one or more, and is not limited to a specific number. In this configuration, one second bonding wire 119 is connected to the first control terminal 27 and the fifth lead terminal 71E, one second bonding wire 119 is connected to the second control terminal 28 and the sixth lead terminal 71F, one second bonding wire 119 is connected to the third control terminal 29 and the seventh lead terminal 71G, and one second bonding wire 119 is connected to the fourth control terminal 30 and the eighth lead terminal 71H.

[0229] Each of the multiple second bonding wires 119 includes a true bump 90, a wire loop 91, and a wire tail 92, similar to the first bonding wire 89. Furthermore, each of the multiple second bonding wires 119 includes a second bump body 97 and a second bump metal film 98 in the true bump 90, similar to the first bonding wire 89.

[0230] It is preferable that the true bump 90 is joined to the first to fourth control terminals 27 to 30 and the wire tail 92 is joined to the fifth to eighth lead terminals 71E to 71H. Of course, the true bump 90 may be joined to the fifth to eighth lead terminals 71E to 71H and the wire tail 92 may be joined to the first to fourth control terminals 27 to 30. Further description of the second bonding wire 119 is omitted, as the description of the first bonding wire 89 applies.

[0231] As described above, the semiconductor device 61 includes a substrate 2, an output region 6 (device region), a source terminal 26 (terminal), a plurality of pseudo-bumps 75, and at least one true bump 90. The output region 6 is provided on the substrate 2. The source terminal 26 covers the output region 6 in a plan view. The plurality of pseudo-bumps 75 are densely arranged on the source terminal 26, free from wires. At least one true bump 90 is connected to wires and is more sparsely arranged on the source terminal 26 than the plurality of pseudo-bumps 75.

[0232] In other words, multiple pseudo-bumps 75 are arranged on the source terminal 26 with a first occupied area per unit square area, and at least one true bump 90 is arranged on the source terminal 26 with a second occupied area less than the first occupied area per unit square area. With this configuration, the heat generated in the output region 6 can be absorbed by the multiple pseudo-bumps 75. This suppresses the temperature rise in the output region 6 and suppresses the deterioration of the electrical characteristics of the output region 6 caused by the temperature rise. Thus, a semiconductor device 61 with improved electrical characteristics can be provided.

[0233] The placement locations of the multiple pseudo-bumps 75 on the source terminal 26 may be determined based on the temperature distribution of the semiconductor chip 1A. For example, the high-temperature and low-temperature regions of the output region 6 may be analyzed using thermography or simulation tools, and multiple pseudo-bumps 75 may be densely arranged in the portion of the source terminal 26 that covers the high-temperature region of the output region 6, and multiple pseudo-bumps 75 may be sparsely arranged in the portion of the source terminal 26 that covers the low-temperature region of the output region 6. At least one true bump 90 is placed in the portion where the multiple pseudo-bumps 75 are sparsely arranged.

[0234] For example, the temperature of the inner part of the output region 6 tends to be higher than that of the peripheral part of the output region 6. Therefore, the multiple pseudo-bumps 75 may be joined to the source terminal 26 in a layout in which they are densely packed in the inner part of the source terminal 26 and sparsely packed at the peripheral part of the source terminal 26. The configuration in which the multiple pseudo-bumps 75 are "sparse" also includes the configuration in which the pseudo-bumps 75 do not exist.

[0235] Another means of absorbing the heat generated in the device region is to deposit a relatively thick plated terminal film (for example, a Cu plated film of 10 μm to 25 μm) on or as the source terminal 26 during the wafer stage.

[0236] In this case, not only are costs increased due to the equipment required for depositing the plating terminal film (deposition equipment, plating solution, etc.), but the plating terminal film itself causes warping of the wafer. The electrical and physical properties of the wafer are degraded by the warping. For example, if cracks or crystal defects occur in the wafer due to warping, the electrical properties of the device region will fluctuate. Furthermore, wafer warping can also cause problems in processes such as dicing.

[0237] In contrast, the semiconductor device 61 can bond multiple pseudo-bumps 75 to the semiconductor chip 1A during the packaging process of the semiconductor chip 1A after it has been separated from the wafer through the dicing process. Therefore, it does not require the equipment necessary for forming the plating terminal film. Furthermore, since wafer warping at the wafer stage can be suppressed, a semiconductor chip 1A with suppressed cracks and crystal defects can be obtained. In addition, relatively thick pseudo-bumps 75 can be formed using the relatively inexpensive wire bonding process used in the formation process of true bumps 90. Thus, electrical characteristics can be improved while keeping costs down.

[0238] Of course, the pseudo-bumps 75 may be bonded to a plated terminal film formed on the terminal (source terminal 26) or to a plated terminal film formed as the terminal (source terminal 26). In this case, the heat absorption effect of multiple pseudo-bumps 75 can be added to the heat absorption effect of the plated terminal film. However, it should be noted that if the amount of heat that can be absorbed by the plated terminal film is already saturated, there is little benefit in bonding multiple pseudo-bumps 75 to the plated terminal film.

[0239] It is preferable that the multiple pseudo-bumps 75 are thicker than the source terminal 26. With this configuration, the source terminal 26 can be thinned by forming multiple relatively thick pseudo-bumps 75. Therefore, heat can be transferred to the multiple pseudo-bumps 75 via the relatively thin source terminal 26, while simultaneously reducing the formation cost of the source terminal 26.

[0240] For example, by employing multiple relatively thick pseudo-bumps 75, a source terminal 26 containing a Cu-based metal film or an Al-based metal film and having a thickness of 1 μm to 10 μm can be used. Since such a source terminal 26 can be formed by sputtering, it can be composed of an electrode film other than a plating film.

[0241] It is preferable that multiple genuine bumps 90 are sparsely arranged on the source terminal 26. In other words, it is preferable that the design rule of dense arrangement is not imposed on multiple genuine bumps 90. With this configuration, multiple genuine bumps 90 can be connected to appropriate positions on the source terminal 26. Multiple pseudo bumps 75 may be arranged on the source terminal 26 at a first pitch P1. In this case, it is preferable that multiple genuine bumps 90 are arranged on the source terminal 26 at a second pitch P2 greater than or equal to the first pitch P1.

[0242] It is preferable that at least three pseudo-bumps 75 are densely arranged above the source terminal 26. It is preferable that the at least three pseudo-bumps 75 are arranged in a layout that forms the vertices of an isosceles triangle in a plan view. In this case, it is particularly preferable that the isosceles triangle is an equilateral triangle. With these configurations, multiple pseudo-bumps 75 can be appropriately densely arranged. In addition, the pseudo-bump group 76, which includes multiple pseudo-bumps 75, can absorb the heat generated in the output region 6.

[0243] It is preferable that at least seven pseudo-bumps 75 are densely arranged on the source terminal 26. In this case, it is preferable that six pseudo-bumps 75 are arranged around one pseudo-bump 75. It is preferable that the six pseudo-bumps 75 are arranged in concentric circles centered on the central part of one pseudo-bump 75 in a plan view. It is preferable that the six pseudo-bumps 75 are arranged in a layout where they are located at the vertices of a hexagon in a plan view, and one pseudo-bump 75 is located at the center of the hexagon in a plan view.

[0244] In other words, it is preferable that the multiple pseudo-bumps 75 are joined to the source terminal 26 in a layout that forms a hexagonal close-packed arrangement (i.e., a honeycomb arrangement) in a plan view. In this case, it is particularly preferable that the hexagons are regular hexagons. With these configurations, the multiple pseudo-bumps 75 can be arranged appropriately and densely. In addition, the pseudo-bump group 76, which includes the multiple pseudo-bumps 75, can absorb the heat generated in the output region 6.

[0245] The semiconductor device 61 preferably includes a first thin film portion 111 formed at the junction of the pseudo-bump 75 at the source terminal 26. With this configuration, heat generated in the output region 6 can be transferred to the pseudo-bump 75 via the first thin film portion 111. The semiconductor device 61 preferably includes a thick film portion 113 formed in the region outside the junction of the pseudo-bump 75 at the source terminal 26. With this configuration, heat generated in the output region 6 can be absorbed by the thick film portion 113 in the region outside the junction of the pseudo-bump 75. The heat absorbed by the thick film portion 113 is transferred to the pseudo-bump 75.

[0246] The semiconductor device 61 preferably includes a first raised portion 114 at the bonding edge of the pseudo-bump 75 at the source terminal 26, where a part of the source terminal 26 is thicker than the thick film portion 113. In other words, it is preferable that the portion of the source terminal 26 along the edge of the pseudo-bump 75 is thicker than the first thin film portion 111 due to the thick film portion 113 and the first raised portion 114.

[0247] Furthermore, the portion of the source terminal 26 located between the multiple pseudo-bumps 75 is thicker than the multiple first thin film portions 111 due to the thick film portion 113 and the multiple first raised portions 114. With these configurations, the heat generated in the output region 6 can be absorbed by the thick film portion 113 and the first raised portions 114 in the region outside the junction of the pseudo-bumps 75.

[0248] The pseudo-bump 75 may include a first bump body 77 containing a first metal, and a first bump metal film 78 containing a second metal different from the first metal and covering at least a portion of the outer surface of the first bump body 77. The pseudo-bump 75 may also include a wide first body portion 79 connected to the source terminal 26, and a first neck portion 80 that protrudes from the first body portion 79 toward the opposite side from the source terminal 26 and is narrower than the first body portion 79.

[0249] The semiconductor device 61 may include a plurality of trench structures 35 formed on the first main surface 3 of the output region 6. In this case, it is preferable that the pseudo-bumps 75 overlap the plurality of trench structures 35 in a plan view. With this configuration, the heat generated in the plurality of trench structures 35 and / or in the vicinity of the plurality of trench structures 35 can be absorbed by the pseudo-bumps 75 directly above them.

[0250] The pseudo-bumps 75 preferably have a thickness greater than the depth of each trench structure 35. If a first raised portion 114 is formed near the joint edge of the pseudo-bumps 75, it is preferable that the first raised portion 114 faces at least one trench structure 35 in the thickness direction. The height of the raised portion 114 relative to the thick film portion 113 is preferably greater than the depth of the trench structure 35.

[0251] The semiconductor device 61 preferably has an insulated gate type main transistor 11 that includes a plurality of trench structures 35 in the output region 6. With this configuration, the temperature rise caused by the back electromotive force of the inductive load L during the active clamp operation of the main transistor 11 can be suppressed by the plurality of pseudo-bumps 75. This improves the active clamp withstand capability.

[0252] The main transistor 11 is preferably an n-gate splitting transistor containing n first gates FG, each receiving n gate signals individually. With this configuration, the main transistor 11 is controlled to switch between a fully on state where all first gates FG are on, a partially on state where some first gates FG are on (some gates are off), and a fully off state where all first gates FG are off. In the main transistor 11, the on-resistance value in the partially on state is higher than the on-resistance value in the fully on state.

[0253] With the n-series main transistor 11, during active clamp operation, the output voltage of the main transistor 11 can be clamped by controlling some of the first gates FG of the main transistor 11 to the ON state and some of the first gates FG of the main transistor 11 to the OFF state. This protects the main transistor 11 from the back electromotive force of the inductive load L and improves the active clamp withstand capability.

[0254] The semiconductor device 61 preferably includes a control region 8 provided on the first main surface 3. The semiconductor device 61 preferably includes a control circuit 17 formed in the control region 8 to generate gate signals applied to a plurality of trench structures 35. In this case, the source terminal 26 preferably covers the output region 6 such that the control region 8 is exposed in a plan view.

[0255] Preferably, the semiconductor device 61 includes a first temperature sensing region 9 provided on the first main surface 3 adjacent to the output region 6, and a second temperature sensing region 10 provided on the first main surface 3 adjacent to the control region 8. Preferably, the semiconductor device 61 includes a first temperature sensing diode 15 (first temperature sensor) formed in the first temperature sensing region 9 to detect the temperature of the output region 6, and a second temperature sensing diode 16 (second temperature sensor) formed in the second temperature sensing region 10 to detect the temperature of the control region 8.

[0256] In this case, the control circuit 17 may be configured to generate a gate signal based on a first temperature measurement signal ST1 (electrical signal) from the first temperature sensing diode 15 and a second temperature measurement signal ST2 (electrical signal) from the second temperature sensing diode 16. With this configuration, the temperature rise in the output region 6 can be suppressed by multiple pseudo-bumps 75, and at the same time, the temperature rise in the output region 6 can be suppressed by utilizing the control of the control circuit 17.

[0257] Figure 15 is a plan view showing a pseudo-bump 75 in the second layout example. Figure 16 is a cross-sectional view along the line XVI-XVI shown in Figure 15. In Figures 15 and 16, a layout in which multiple pseudo-bumps 75 are arranged to abut each other is shown as the second layout example.

[0258] Each pseudo-bump 75 may have at least one notch 120 at the periphery of the first neck portion 80 that is recessed toward the center of the first neck portion 80. The notch 120 is formed when a plurality of pseudo-bumps 75 are arranged at a narrow pitch using a capillary, by the tip of the capillary contacting the first neck portion 80 of the already placed pseudo-bumps 75.

[0259] The indented portion 120 is formed in the portion of the first neck portion 80 that faces an adjacent pseudo-bump 75. Therefore, one pseudo-bump 75 adjacent to two pseudo-bumps 75 includes two indented portions 120 in the first neck portion 80. Also, one pseudo-bump 75 surrounded by six pseudo-bumps 75 includes six indented portions 120 in the first neck portion 80. A portion of the first upper end portion 81 (upper end top portion 82, upper end base portion 83, and inclined portion 84) may be lost due to the indented portion 120.

[0260] The aforementioned first raised portion 114 is formed at the joining edge of each pseudo-bump 75 in the source terminal 26. The first raised portion 114 formed on one pseudo-bump 75 side may be integrated with the first raised portion 114 formed on the other pseudo-bump 75 side. In other words, the portion of the source terminal 26 located between the multiple pseudo-bumps 75 may be thicker than the multiple first thin film portions 111 (second thin film portions 112) due to the first raised portion 114 which can be considered as one.

[0261] The portion of the source terminal 26 located between the multiple pseudo-bumps 75 is preferably facing the multiple trench structures 35. In other words, in the region between the multiple pseudo-bumps 75, the first raised portion 114, which can be considered as one, is preferably facing the multiple trench structures 35.

[0262] Figure 17 is a plan view showing the internal structure of the semiconductor device 61 along with the pseudo-bumps 75 according to the third layout example. Figure 18 is a plan view showing the pseudo-bumps 75 according to the third layout example. Figure 19 is a cross-sectional view along the line XIX-XIX shown in Figure 18. Figure 20 is a cross-sectional view along the line XX-XX shown in Figure 18.

[0263] Referring to Figures 17 to 20, the pseudo-bump 75 in the third layout example has a relatively large first size S11 in plan view and includes at least one (or more in this embodiment) large pseudo-bumps 75a densely arranged above the source terminal 26 when detached from the wire. The first size S11 is defined in plan view by the length of the widest portion of the large pseudo-bumps 75a.

[0264] Here, "dense" means that the area occupied by one large pseudo-bump 75a relative to the source terminal 26 is larger compared to that of another structure relative to the source terminal 26 (such as one small pseudo-bump 75b or one genuine bump 90, which will be described later). The large pseudo-bump 75a is positioned on the source terminal 26 with a first-largest area per unit square area.

[0265] The first size S11 may be 100 μm or more and 1000 μm or less. The first size S11 may be 100 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, 400 μm or more and 500 μm or less, 500 μm or more and 600 μm or less, 600 μm or more and 700 μm or less, 700 μm or more and 800 μm or less, 800 μm or more and 900 μm or less, or 900 μm or more and 1000 μm or less.

[0266] Each of the multiple large pseudo-bumps 75a has a first thickness T11. The first thickness T11 is defined by the thickness of the thickest part of the large pseudo-bump 75a in a cross-sectional view. Preferably, the first thickness T11 is greater than the first depth D1 of the multiple trench structures 35. Preferably, the first thickness T11 is greater than the thickness of the source terminal 26. Preferably, the first thickness T11 is greater than the thickness of the first semiconductor region 31. The first thickness T11 may be greater than the thickness of the substrate 2. Of course, the first thickness T11 may also be less than the thickness of the substrate 2.

[0267] The first thickness T11 may be 50 μm to 500 μm or less. The first thickness T11 may be 50 μm to 100 μm, 100 μm to 150 μm, 150 μm to 200 μm, 200 μm to 250 μm, 250 μm to 300 μm, 300 μm to 350 μm, 350 μm to 400 μm, 400 μm to 450 μm, or 450 μm to 500 μm.

[0268] The placement of the multiple large pseudo-bumps 75a is arbitrary. In this embodiment, the multiple large pseudo-bumps 75a are arranged with spacing in the first direction X. Preferably, the multiple large pseudo-bumps 75a are placed on the portion of the source terminal 26 that covers the high-temperature region of the output region 6.

[0269] It is preferable that the multiple large pseudo-bumps 75a are arranged on the source terminal 26 in a layout that is dense in the inner part (for example, the central part) of the source terminal 26 and sparse in the peripheral part of the source terminal 26. The configuration in which the large pseudo-bumps 75a are "sparse" includes a configuration in which the large pseudo-bumps 75a are absent.

[0270] A plurality of large pseudo bumps 75a are arranged at positions overlapping the main transistor 11 in a plan view, and are not arranged in a region overlapping the control region 8 in the plan view. A part of at least one large pseudo bump 75a may face the monitor transistor 13 in the plan view. That is, the plurality of large pseudo bumps 75a may face the plurality of trench structures 35 of the main transistor 11 and the plurality of trench structures 35 for the monitor transistor 13.

[0271] Each large pseudo bump 75a may face 50 or more and 200 or less trench structures 35. The number of trench structures 35 facing each large pseudo bump 75a may be 50 or more and 75 or less, 75 or more and 100 or less, 100 or more and 125 or less, 125 or more and 150 or less, 150 or more and 175 or less, or 175 or more and 200 or less.

[0272] The pseudo bump 75 according to the third layout example has a second size S12 smaller than the first size S11 of the large pseudo bump 75a in a plan view, and includes at least one small pseudo bump 75b arranged around the large pseudo bump 75a in a state separated from a wire. The second size S12 is defined by the length of the widest part of the small pseudo bumps 75b in the plan view. The presence or absence of the small pseudo bumps 75b is arbitrary, and a structure without the small pseudo bumps 75b may be adopted.

[0273] The second size S12 may be 0.05 times or more and 0.8 times or less the first size S11. The size ratio of the second size S12 to the first size S11 may be 0.05 or more and 0.075 or less, 0.075 or more and 0.1 or less, 0.1 or more and 0.2 or less, 0.2 or more and 0.3 or less, 0.3 or more and 0.4 or less, 0.3 or more and 0.4 or less, 0.4 or more and 0.5 or less, 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, or 0.7 or more and 0.8 or less. The size ratio may be less than 0.5. That is, the planar area of the small pseudo bumps 75b may be less than 1 / 2 of the planar area of the large pseudo bump 75a.

[0274] The second size S12 may be 50 μm or more and 250 μm or less. The second size S12 may be 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, 100 μm or more and 125 μm or less, 125 μm or more and 150 μm or less, 150 μm or more and 175 μm or less, 175 μm or more and 200 μm or less, 200 μm or more and 225 μm or less, or 225 μm or more and 250 μm or less. The second size S12 is preferably 75 μm or more and 200 μm or less. The second size S12 is particularly preferably 100 μm or more and 180 μm or less.

[0275] The plurality of small pseudo bumps 75b each have a second thickness T12. The second thickness T12 is defined by the thickness of the thickest part among the small pseudo bumps 75b in a cross-sectional view. The second thickness T12 is smaller than the first thickness T11 of the large pseudo bump 75a. The second thickness T12 is preferably larger than the first depth D1 of the plurality of trench structures 35. The second thickness T12 is preferably larger than the thickness of the source terminal 26. The second thickness T1,2 is preferably larger than the thickness of the first semiconductor region 31. The second thickness T12 may be larger than the thickness of the substrate 2. Of course, the second thickness T12 may be smaller than the thickness of the substrate 2.

[0276] The second thickness T12 may be 10 μm or more and 150 μm or less. The second thickness T12 may be 10 μm or more and 25 μm or less, 25 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, 100 μm or more and 125 μm or less, or 125 μm or more and 150 μm or less.

[0277] The small pseudo-bumps 75b, when placed alongside the large pseudo-bumps 75a, increase the area occupied by the pseudo-bumps 75 relative to the source terminal 26. Preferably, at least one small pseudo-bump 75b is arranged around each large pseudo-bump 75a, and together with the corresponding large pseudo-bump 75a, they constitute a pseudo-bump group 76. In this embodiment, multiple small pseudo-bumps 75b are arranged around each large pseudo-bump 75a, and together with the corresponding large pseudo-bump 75a, they constitute a pseudo-bump group 76.

[0278] The configuration within one pseudo-bump group 76 is described below. Multiple small pseudo-bumps 75b may include two small pseudo-bumps 75b arranged around a large pseudo-bump 75a. In this case, it is preferable that the two small pseudo-bumps 75b are arranged in concentric circles centered on the central part of the large pseudo-bump 75a.

[0279] The two small pseudo-bumps 75b may be positioned opposite each other in a first direction X or a second direction Y, with the large pseudo-bump 75a in between. One small pseudo-bump 75b may be positioned offset from the large pseudo-bump 75a in the first direction X, and the other small pseudo-bump 75b may be positioned offset from the large pseudo-bump 75a in the second direction Y.

[0280] One small pseudo-bump 75b may be positioned at a predetermined angle (absolute value) offset from the other small pseudo-bump 75b along the circumferential direction of the large pseudo-bump 75a. The predetermined angle is the angle formed between the line connecting the center of the large pseudo-bump 75a and the center of one small pseudo-bump 75b and the line connecting the center of the large pseudo-bump 75a and the center of the other small pseudo-bump 75b.

[0281] The specified angle may be between 10 degrees and 180 degrees. The specified angle may also be between 10 degrees and 30 degrees, between 30 degrees and 45 degrees, between 45 degrees and 60 degrees, between 60 degrees and 75 degrees, between 75 degrees and 90 degrees, between 90 degrees and 105 degrees, between 105 degrees and 120 degrees, between 120 degrees and 135 degrees, between 135 degrees and 150 degrees, between 150 degrees and 165 degrees, or between 165 degrees and 180 degrees.

[0282] The multiple small pseudo-bumps 75b may include x (x≧3) small pseudo-bumps 75b arranged around the large pseudo-bump 75a. Preferably, the x small pseudo-bumps 75b are arranged at equal intervals around the large pseudo-bump 75a along its circumferential direction in a plan view. Preferably, the x small pseudo-bumps 75b are arranged on concentric circles centered on the central part of the large pseudo-bump 75a in a plan view.

[0283] It is particularly preferable that x small pseudobumps 75b are placed at the vertices of a regular x-gon, and a large pseudobump 75a is placed at the center of the regular x-gon. For example, when x=3, three small pseudobumps 75b are placed at the vertices of an equilateral triangle, and a large pseudobump 75a is placed at the center of the equilateral triangle. For example, when x=4, four small pseudobumps 75b are placed at the vertices of a square, and a large pseudobump 75a is placed at the center of the square.

[0284] For example, when x=5, five small pseudobumps 75b are placed at each vertex of the regular pentagon, and a large pseudobump 75a is placed at the center of the regular pentagon. For example, when x=6, six small pseudobumps 75b are placed at each vertex of the regular hexagon, and a large pseudobump 75a is placed at the center of the regular hexagon.

[0285] Reducing the value of x reduces the number of steps in the wire bonding process, but increases the area of ​​the empty space formed around the large pseudo-bump 75a. On the other hand, increasing the value of x increases the number of steps, and at the same time reduces the diameter of the small pseudo-bumps 75b, decreasing the heat absorption effect of each small pseudo-bump 75b.

[0286] For example, the amount of heat absorbed when 40 small pseudo-bumps 75b with reduced diameter are arranged in a concentric circle is almost the same as the amount of heat absorbed when 20 small pseudo-bumps 75b with increased diameter are arranged in the same concentric circle. Therefore, it is preferable that the value of x is set to 4 or more and 20 or less, and that the second size S12 of the small pseudo-bumps 75b is adjusted accordingly.

[0287] This configuration allows for the placement of multiple smaller pseudo-bumps 75b surrounding a large pseudo-bump 75a from at least four directions, while suppressing the burden of man-hours. It is particularly preferable that the value of x be set to between 6 and 12. In this form, x=8, and eight smaller pseudo-bumps 75b are placed at the vertices of a regular octagon, with the large pseudo-bump 75a placed at the center of the regular octagon.

[0288] Multiple small pseudo-bumps 75b are arranged on the source terminal 26 with a first pitch P11 relative to one large pseudo-bump 75a. The first pitch P11 is defined by the distance between the centers of the large pseudo-bump 75a and the small pseudo-bumps 75b. The multiple small pseudo-bumps 75b may be arranged so as to be in contact with the large pseudo-bump 75a with a first pitch P11, or they may be arranged with a gap between them with a first pitch P11.

[0289] It is preferable that the multiple small pseudo-bumps 75b are arranged at intervals from the large pseudo-bump 75a. When the multiple small pseudo-bumps 75b are in contact with the large pseudo-bump 75a, at least one notch 120 may be formed on either or both of the first body portion 79 and the first neck portion 80 of the large pseudo-bump 75a (see also Figures 15 and 16). Of course, a configuration without the notch 120 may also be adopted.

[0290] The first interval I1 between the small pseudo-bump 75b and the large pseudo-bump 75a may be 0 μm or more and 100 μm or less. The first interval I1 may be 0 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or more and 100 μm or less. It is preferable that the first interval I1 is 10 μm or more. It is particularly preferable that the first interval I1 is 30 μm or more and 60 μm or less.

[0291] Multiple small pseudo-bumps 75b are arranged around a large pseudo-bump 75a at a second pitch P12 in a plan view. The second pitch P12 is defined by the distance between the centers of the multiple small pseudo-bumps 75b. The multiple small pseudo-bumps 75b may be arranged so as to be in contact with each other at the second pitch P12, or they may be arranged with a gap between them at the second pitch P12.

[0292] The second pitch P12 may be greater than or equal to the first pitch P11. Preferably, the second pitch P12 is less than the first pitch P11. The second interval I2 between multiple small pseudo-bumps 75b may be 0 μm or greater and is not limited to a specific value. Preferably, the multiple small pseudo-bumps 75b are arranged at equal intervals with respect to the second pitch P12 (second interval I2). The second pitch P12 (second interval I2) is adjusted by the number of small pseudo-bumps 75b, their placement, the second size S12, etc.

[0293] The pseudo-bump 75 may include one or more small pseudo-bumps 75b that do not belong to the pseudo-bump group 76. The small pseudo-bumps 75b that do not belong to the pseudo-bump group 76 may be located in any available area of ​​the source terminal 26. The small pseudo-bumps 75b that do not belong to the pseudo-bump group 76 may be located, for example, in the area between multiple adjacent pseudo-bump groups 76.

[0294] The plurality of large pseudo bumps 75a include a first bump body 77 and a first bump metal film 78, similar to the case of the first layout example. The first bump body 77 includes a first body portion 79 and a first neck portion 80. The plurality of small pseudo bumps 75b include a first bump body 77 and a first bump metal film 78, similar to the case of the first layout example. The first bump body 77 includes a first body portion 79 and a first neck portion 80. Regarding these descriptions, the foregoing descriptions are applied and thus omitted.

[0295] Each of the aforementioned true bumps 90 is arranged more sparsely on the source terminal 26 than one large pseudo bump 75a. The term "sparse" here means that the occupied area of one true bump 90 with respect to the source terminal 26 is smaller than the occupied area of one large pseudo bump 75a with respect to the source terminal 26. That is, each true bump 90 is arranged on the source terminal 26 with a second occupied area less than the first occupied area of one large pseudo bump 75a per unit plane area.

[0296] Also, the plurality of true bumps 90 are arranged more sparsely than the pseudo bump group 76. That is, each true bump 90 is arranged on the source terminal 26 with an occupied area less than the occupied areas of the large pseudo bumps 75a and the small pseudo bumps 75b per unit plane area. When comparing the occupied area of one large pseudo bump 75a with the occupied areas of two adjacent true bumps 90, the occupied areas of the two true bumps 90 may be less than the occupied area of one large pseudo bump 75a.

[0297] The plurality of true bumps 90 each have a third size S13 smaller than the first size S11 of the large pseudo bumps 75a in a plan view. The third size S13 is defined by the length of the widest part of the true bump 90 in a plan view. The third size S13 may be not less than 0.05 times and not more than 0.8 times the first size S11.

[0298] The size ratio of the third size S13 to the first size S11 may be 0.05 to 0.075, 0.075 to 0.1, 0.1 to 0.2, 0.2 to 0.3, 0.3 to 0.4, 0.3 to 0.4, 0.4 to 0.5, 0.5 to 0.6, 0.6 to 0.7, or 0.7 to 0.8. The size ratio may also be less than 0.5. In other words, the flat area of ​​the true bump 90 may be less than half the flat area of ​​the large pseudo-bump 75a.

[0299] The third size S13 may be 50 μm or more and 250 μm or less. The third size S13 may be 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, 100 μm or more and 125 μm or less, 125 μm or more and 150 μm or less, 150 μm or more and 175 μm or less, 175 μm or more and 200 μm or less, 200 μm or more and 225 μm or less, or 225 μm or more and 250 μm or less.

[0300] The third size S13 is preferably 75 μm or more and 200 μm or less. The third size S13 is particularly preferably 100 μm or more and 180 μm or less. The third size S13 may be larger than or equal to the second size S12 of the small pseudo-bump 75b, or it may be smaller than the second size S12. The third size S13 is preferably approximately equal to the second size S12. With this configuration, small pseudo-bumps 75b and true bumps 90 can be formed under the same manufacturing conditions in terms of size.

[0301] Each of the multiple true bumps 90 has a third thickness T13. The third thickness T13 is defined by the thickness of the thickest part of the true bump 90 in a cross-sectional view. The third thickness T13 is smaller than the first thickness T11 of the large pseudo-bump 75a. Preferably, the third thickness T13 is larger than the first depth D1 of the multiple trench structures 35. Preferably, the third thickness T13 is larger than the thickness of the source terminal 26. Preferably, the third thickness T13 is larger than the thickness of the first semiconductor region 31. The third thickness T13 may be larger than the thickness of the substrate 2. Of course, the third thickness T13 may also be smaller than the thickness of the substrate 2.

[0302] The third thickness T13 may be 10 μm to 150 μm or less. The third thickness T13 may be 10 μm to 25 μm, 25 μm to 50 μm, 50 μm to 75 μm, 75 μm to 100 μm, 100 μm to 125 μm, or 125 μm to 150 μm.

[0303] The third thickness T13 may be greater than or equal to the second thickness T12 of the miniature pseudo-bump 75b, or less than the second thickness T12. Preferably, the third thickness T13 is approximately equal to the second thickness T12. With this configuration, the miniature pseudo-bump 75b and the true bump 90 can be formed under the same manufacturing conditions in terms of thickness.

[0304] Multiple true bumps 90 are positioned on the source terminal 26 at an arbitrary third pitch P13 in a plan view. The third pitch P13 is defined by the distance between the centers of two adjacent true bumps 90. The third pitch P13 can take any value as long as the entire true bump 90 is located within the area enclosed by the periphery of the source terminal 26. The third pitch P13 may be greater than or equal to the first pitch P11, or less than the first pitch P11. The third pitch P13 may be greater than or equal to the second pitch P12, or less than the second pitch P12.

[0305] The third interval I3 between the closest genuine bump 90 and the small pseudo-bump 75b is preferably greater than or equal to the first interval I1 between the large pseudo-bump 75a and the small pseudo-bump 75b. The third interval I3 is particularly preferably greater than the first interval I1. As an example, the ratio of the third interval I3 to the first interval I1 may be between 1 and 20. The ratio may be between 1 and 2, between 2 and 5, between 5 and 10, between 10 and 15, or between 15 and 20.

[0306] The multiple true bumps 90 include the second bump body 97 and the second bump metal film 98 described above. The second bump body 97 includes the second body portion 99 and the second neck portion 100 described above. Details of these are omitted as the above-mentioned details apply.

[0307] In this embodiment, the semiconductor device 61 includes a plurality of first thin film portions 121, a plurality of second thin film portions 122, a plurality of third thin film portions 123, and a thick film portion 124 formed on the source terminal 26. The plurality of first thin film portions 121 are each formed at the junctions of a plurality of large pseudo-bumps 75a on the source terminal 26. The plurality of second thin film portions 122 are each formed at the junctions of a plurality of small pseudo-bumps 75b on the source terminal 26. The minimum thickness of the plurality of second thin film portions 122 may be greater than the minimum thickness of the plurality of first thin film portions 121.

[0308] Multiple third thin film portions 123 are formed at the joints of multiple true bumps 90 at the source terminal 26. The minimum thickness of the multiple third thin film portions 123 may be greater than the minimum thickness of the multiple first thin film portions 121. Thick film portions 124 are formed in the regions outside the joints of multiple large pseudo-bumps 75a, multiple small pseudo-bumps 75b, and multiple true bumps 90 at the source terminal 26.

[0309] The maximum thickness of the thick film portion 124 is greater than the minimum thickness of the first thin film portion 121, and may be three times or less the minimum thickness of the first thin film portion 121. The thickness ratio of the maximum thickness to the minimum thickness may be greater than 1 and be 1.25 or less, 1.25 or more and 1.5 or less, 1.5 or more and 1.75 or less, 1.75 or more and 2 or less, 2 or more and 2.25 or less, 2.25 or more and 2.5 or less, 2.5 or more and 2.75 or less, or 2.75 or more and 3 or less.

[0310] The semiconductor device 61 includes a plurality of first raised portions 125 formed on the source terminal 26. The plurality of first raised portions 125 are formed on the bonding edges of a plurality of large pseudo-bumps 75a on the source terminal 26, and a portion of the source terminal 26 consists of a part that is thicker than the thick film portion 124. Each first raised portion 125 extends in an annular shape along the edge (bonding edge) of each large pseudo-bump 75a in a plan view. At least a portion of each first raised portion 125 faces the peripheral edge of each large pseudo-bump 75a in the thickness direction.

[0311] The portion along the edge of each large pseudo-bump 75a in the source terminal 26 is thicker than the first thin film portion 121 by the thick film portion 124 and the first raised portion 125. Each first raised portion 125 faces at least one trench structure 35 in the thickness direction. In this embodiment, each first raised portion 125 is formed to face multiple trench structures 35 in the thickness direction.

[0312] The height of at least one first raised portion 125 relative to the thick film portion 124 is preferably greater than the first depth D1 of the trench structure 35. The height of at least one first raised portion 125 may also be greater than the thickness of the first semiconductor region 31. Of course, the height of at least one first raised portion 125 may be less than or equal to the first depth D1 of the trench structure 35. The first total thickness of the thick film portion 124 and the first raised portion 125 is preferably greater than the thickness of the interlayer insulating film 24.

[0313] The first total thickness is greater than 1 times the minimum thickness of the first thin film portion 121, and may be 10 times or less the minimum thickness of the first thin film portion 121. The thickness ratio of the first total thickness to the minimum thickness may be greater than 1 and 2 or less, 2 to 4, 4 to 6, 6 to 8, or 8 to 10. The thickness ratio is preferably 2 to 6.

[0314] The semiconductor device 61 includes a plurality of second raised portions 126 formed on the source terminal 26. The plurality of second raised portions 126 are formed on the bonding edges of a plurality of small pseudo-bumps 75b on the source terminal 26, and a portion of the source terminal 26 is thicker than the thick film portion 124. Each second raised portion 126 extends in an annular shape along the edge (bonding edge) of each small pseudo-bump 75b in a plan view. At least a portion of each second raised portion 126 faces the peripheral edge of each small pseudo-bump 75b in the thickness direction.

[0315] The portion along the edge of each small pseudo-bump 75b in the source terminal 26 is thicker than the second thin film portion 122 due to the thick film portion 124 and the second raised portion 126. Furthermore, the portion along the edge of each small pseudo-bump 75b is thicker than the first thin film portion 121. In addition, the portion located between the large pseudo-bump 75a and the small pseudo-bump 75b in the source terminal 26 is thicker than the first thin film portion 121 and the second thin film portion 122 due to the thick film portion 124, the first raised portion 125, and the second raised portion 126.

[0316] Each second ridge 126 faces at least one trench structure 35 in the thickness direction. In this embodiment, each second ridge 126 is formed to face multiple trench structures 35 in the thickness direction. Preferably, the ridge height of at least one second ridge 126 relative to the thick film portion 124 is smaller than the ridge height of the first ridge 125.

[0317] Preferably, the height of at least one second raised portion 126 is greater than the first depth D1 of the trench structure 35. The height of at least one second raised portion 126 may also be greater than the thickness of the first semiconductor region 31. Of course, the height of at least one second raised portion 126 may be less than or equal to the first depth D1 of the trench structure 35. Preferably, the second total thickness of the thick film portion 124 and the second raised portion 126 is greater than the thickness of the interlayer insulating film 24.

[0318] The second total thickness may be greater than 1 times the minimum thickness of the second thin film portion 122, and less than or equal to 10 times the minimum thickness of the second thin film portion 122. The thickness ratio of the second total thickness to the minimum thickness may be greater than 1 and less than or equal to 2, 2 to 4, 4 to 6, 6 to 8, or 8 to 10. The thickness ratio is preferably 2 to 6.

[0319] The second raised portion 126 formed on the side of the small pseudo-bump 75b may be integrated with the first raised portion 125 formed on the side of the large pseudo-bump 75a. In other words, the portion of the source terminal 26 located between the large pseudo-bump 75a and the small pseudo-bump 75b may be thicker than the multiple first thin film portions 121 (second thin film portions 122) by the first raised portion 125 (second raised portion 126) which can be considered as one. It is preferable that the first raised portion 125 (second raised portion 126) which can be considered as one faces the multiple trench structures 35.

[0320] The semiconductor device 61 includes a plurality of third raised portions 127 formed on the source terminal 26. The plurality of third raised portions 127 are formed on the bonding edges of a plurality of true bumps 90 on the source terminal 26, and consist of a portion of the source terminal 26 that is thicker than the thick film portion 124. Each third raised portion 127 extends in an annular shape along the edge (bonding edge) of each true bump 90 in a plan view. At least a portion of each third raised portion 127 faces the peripheral edge of each true bump 90 in the thickness direction.

[0321] The portion along the edge of each true bump 90 in the source terminal 26 is thicker than the third thin film portion 123 due to the thick film portion 124 and the third raised portion 127. In addition, the portion located between the small pseudo-bump 75b and the true bump 90 in the source terminal 26 is thicker than the second thin film portion 122 and the third thin film portion 123 due to the thick film portion 124, the second raised portion 126 and the third raised portion 127.

[0322] Each third ridge 127 faces at least one trench structure 35 in the thickness direction. In this embodiment, each third ridge 127 is formed to face multiple trench structures 35 in the thickness direction. Preferably, the ridge height of at least one third ridge 127 relative to the thick film portion 124 is smaller than the ridge height of the first ridge 125.

[0323] Preferably, the height of at least one third raised portion 127 is greater than the first depth D1 of the trench structure 35. The height of at least one third raised portion 127 may also be greater than the thickness of the first semiconductor region 31. Of course, the height of at least one third raised portion 127 may be less than or equal to the first depth D1 of the trench structure 35. Preferably, the third total thickness of the thick film portion 124 and the third raised portion 127 is greater than the thickness of the interlayer insulating film 24.

[0324] The third total thickness may be greater than 1 times the minimum thickness of the third thin film portion 123, and may be 10 times or less the minimum thickness of the third thin film portion 123. The thickness ratio of the third total thickness to the minimum thickness may be greater than 1 and 2 or less, 2 to 4 or less, 4 to 6 or less, 6 to 8 or less, or 8 to 10 or less. The thickness ratio is preferably 2 to 6 or less.

[0325] As described above, the semiconductor device 61 includes a substrate 2, an output region 6 (device region), a source terminal 26 (terminal), a large pseudo-bump 75a, and a true bump 90. The output region 6 is provided on the substrate 2. The source terminal 26 covers the output region 6 in a plan view. The large pseudo-bump 75a is positioned on the source terminal 26, free from the wires. The true bump 90 is positioned on the source terminal 26, connected to the wires, and has a smaller size than the large pseudo-bump 75a.

[0326] With this configuration, the heat generated in the output region 6 can be absorbed by the large pseudo-bumps 75a, which are larger than the true bumps 90. The amount of heat absorbed is adjusted by the size of the large pseudo-bumps 75a. This suppresses the temperature rise in the output region 6 and prevents the deterioration of the electrical characteristics of the output region 6 caused by the temperature rise. Therefore, a semiconductor device 61 with improved electrical characteristics can be provided.

[0327] The large pseudo-bump 75a is preferably thicker than the source terminal 26. With this configuration, the source terminal 26 can be thinned by forming a relatively thick large pseudo-bump 75a. Therefore, heat can be transferred to the large pseudo-bump 75a via the relatively thin source terminal 26, while simultaneously reducing the formation cost of the source terminal 26.

[0328] For example, by employing a relatively thick, large pseudo-bump 75a, a source terminal 26 containing a Cu-based metal film or an Al-based metal film and having a thickness of 1 μm to 10 μm can be used. Since such a source terminal 26 can be formed by sputtering, it can be composed of an electrode film other than a plating film.

[0329] The semiconductor device 61 may include a small pseudo-bump 75b that is smaller in size than the large pseudo-bump 75a and is positioned around the large pseudo-bump 75a on the source terminal 26, while being free from wires. With this configuration, the heat generated in the output region 6 can be absorbed by the large pseudo-bump 75a and the small pseudo-bump 75b.

[0330] The small pseudo-bump 75b is preferably thicker than the source terminal 26. With this configuration, the source terminal 26 can be thinned by forming a relatively thick small pseudo-bump 75b. Therefore, heat can be transferred to the small pseudo-bump 75b via the relatively thin source terminal 26, while simultaneously reducing the formation cost of the source terminal 26.

[0331] It is preferable that x (x≧2) small pseudo-bumps 75b are arranged around the large pseudo-bump 75a. With this configuration, the heat generated in the output region 6 can be absorbed by the large pseudo-bump 75a and the x (x≧2) small pseudo-bumps 75b. It is preferable that the value of x is 3 or greater (x≧3). It is preferable that the value of x is 4 or greater (x≧4). It is preferable that the value of x is 20 or less (x≦20).

[0332] The value of x is preferably between 6 and 12. The x small pseudobumps 75b may be arranged at equal intervals along the circumferential direction of the large pseudobump 75a. The x small pseudobumps 75b may be arranged on concentric circles centered on the central part of the large pseudobump 75a in a plan view. If the value of x is 3 or greater (x≧3), the x small pseudobumps 75b may be placed at the vertices of a regular x-gon. In this case, the large pseudobump 75a may be placed at the center of the regular x-gon.

[0333] Multiple genuine bumps 90 may be arranged on the source terminal 26. In this case, it is preferable that each genuine bump 90 is arranged on the source terminal 26 with an area occupied less than the area occupied by the large pseudo-bump 75a and the small pseudo-bump 75b per unit area. The area occupied by two adjacent genuine bumps 90 per unit area may be less than the area occupied by one large pseudo-bump 75a. In other words, the area of ​​one genuine bump 90 may be less than half the area of ​​one large pseudo-bump 75a.

[0334] The semiconductor device 61 preferably includes a first thin film portion 121 formed at the junction of the large pseudo-bump 75a at the source terminal 26. With this configuration, heat generated in the output region 6 can be transferred to the large pseudo-bump 75a via the first thin film portion 121.

[0335] The semiconductor device 61 preferably includes a second thin film portion 122 formed at the junction of the small pseudo-bump 75b at the source terminal 26. With this configuration, heat generated in the output region 6 can be transferred to the small pseudo-bump 75b via the second thin film portion 122. The second thin film portion 122 may be thicker than the first thin film portion 121.

[0336] The semiconductor device 61 preferably includes a thick film portion 124 formed in the region outside the junction of the large pseudo-bump 75a at the source terminal 26. With this configuration, the heat generated in the output region 6 can be absorbed by the thick film portion 124 in the region outside the junction of the large pseudo-bump 75a. The heat absorbed by the thick film portion 124 is then transferred to the large pseudo-bump 75a.

[0337] The semiconductor device 61 preferably includes a first raised portion 125 at the bonding edge of the large pseudo-bump 75a at the source terminal 26, where a portion of the source terminal 26 is thicker than the thick film portion 124. In other words, it is preferable that the portion of the source terminal 26 along the edge of the large pseudo-bump 75a is thicker than the first thin film portion 121 due to the thick film portion 124 and the first raised portion 125. With this configuration, the heat generated in the output region 6 can be absorbed by the thick film portion 124 and the first raised portion 125 in the region outside the bonding area of ​​the large pseudo-bump 75a.

[0338] The semiconductor device 61 preferably includes a second raised portion 126 at the bonding edge of the small pseudo-bump 75b at the source terminal 26, where a portion of the source terminal 26 is thicker than the thick film portion 124. In other words, it is preferable that the portion of the source terminal 26 along the edge of the small pseudo-bump 75b is thicker than the second thin film portion 122 due to the thick film portion 124 and the second raised portion 126. With this configuration, the heat generated in the output region 6 can be absorbed by the thick film portion 124 and the second raised portion 126 in the region outside the bonding area of ​​the small pseudo-bump 75b.

[0339] The large pseudo-bump 75a may include a first bump body 77 containing a first metal, and a first bump metal film 78 containing a second metal different from the first metal and covering at least a portion of the outer surface of the first bump body 77. The large pseudo-bump 75a may also include a wide first body portion 79 connected to the source terminal 26, and a first neck portion 80 that protrudes from the first body portion 79 toward the opposite side from the source terminal 26 and is narrower than the first body portion 79.

[0340] The miniature pseudo-bump 75b may include a first bump body 77 containing a first metal, and a first bump metal film 78 containing a second metal different from the first metal and covering at least a portion of the outer surface of the first bump body 77. The miniature pseudo-bump 75b may also include a wide first body portion 79 connected to the source terminal 26, and a first neck portion 80 that protrudes from the first body portion 79 toward the opposite side from the source terminal 26 and is narrower than the first body portion 79.

[0341] The semiconductor device 61 may include a plurality of trench structures 35 formed on the first main surface 3 of the output region 6. In this case, it is preferable that the large pseudo-bump 75a overlaps the plurality of trench structures 35 in a plan view. With this configuration, the heat generated in and / or near the plurality of trench structures 35 can be absorbed by the large pseudo-bump 75a directly above it.

[0342] The large pseudo-bump 75a preferably has a thickness greater than the depth of each trench structure 35. If a first raised portion 125 is formed near the joint edge of the large pseudo-bump 75a, the first raised portion 125 preferably faces at least one trench structure 35 in the thickness direction. The raised height of the first raised portion 125 with respect to the thick film portion 124 preferably has a height greater than the depth of the trench structure 35.

[0343] The semiconductor device 61 preferably has an insulated gate type main transistor 11 that includes a plurality of trench structures 35 in the output region 6. With this configuration, the temperature rise caused by the back electromotive force of the inductive load L during the active clamp operation of the main transistor 11 can be suppressed by the plurality of pseudo-bumps 75. This improves the active clamp withstand capability.

[0344] The main transistor 11 is preferably an n-gate splitting transistor containing n first gates FG, each receiving n gate signals individually. With this configuration, the main transistor 11 is controlled to switch between a fully on state where all first gates FG are on, a partially on state where some first gates FG are on (some gates are off), and a fully off state where all first gates FG are off. In the main transistor 11, the on-resistance value in the partially on state is higher than the on-resistance value in the fully on state.

[0345] With the n-series main transistor 11, during active clamp operation, the output voltage of the main transistor 11 can be clamped by controlling some of the first gates FG of the main transistor 11 to the ON state and some of the first gates FG of the main transistor 11 to the OFF state. This protects the main transistor 11 from the back electromotive force of the inductive load L and improves the active clamp withstand capability.

[0346] The semiconductor device 61 preferably includes a control region 8 provided on the first main surface 3. In this case, the semiconductor device 61 preferably includes a control circuit 17 formed in the control region 8 to generate gate signals applied to a plurality of trench structures 35. In this case, the source terminal 26 preferably covers the output region 6 such that the control region 8 is exposed in a plan view.

[0347] The semiconductor device 61 preferably includes a first temperature sensing region 9 provided on the first main surface 3 adjacent to the output region 6, and a second temperature sensing region 10 provided on the first main surface 3 adjacent to the control region 8. In this case, the semiconductor device 61 preferably includes a first temperature sensing diode 15 (first temperature sensor) formed in the first temperature sensing region 9 to detect the temperature of the output region 6, and a second temperature sensing diode 16 (second temperature sensor) formed in the second temperature sensing region 10 to detect the temperature of the control region 8.

[0348] In this case, the control circuit 17 may be configured to generate a gate signal based on a first temperature measurement signal ST1 (electrical signal) from the first temperature sensing diode 15 and a second temperature measurement signal ST2 (electrical signal) from the second temperature sensing diode 16. With this configuration, the temperature rise in the output region 6 can be suppressed by multiple pseudo-bumps 75, and at the same time, the temperature rise in the output region 6 can be suppressed by utilizing the control of the control circuit 17.

[0349] Figure 21 is a plan view showing a semiconductor chip 1B according to a second embodiment. Referring to Figure 21, semiconductor chip 1B has an embodiment in which the layout of the output region 6 of semiconductor chip 1A has been changed. In this embodiment, the output region 6 is partitioned in an L-shape in a plan view. Specifically, the output region 6 has a first region 6A that extends in a strip shape along the first direction X in the region on the first side surface 5A side, and a second region 6B that extends in a strip shape along the second direction Y in the region on the third side surface 5C side.

[0350] In this configuration, the control region 8 is located in the region on the second side surface 5B side, in the area demarcated by the periphery of the first main surface 3, the first region 6A of the output region 6, and the second region 6B of the output region 6. The current detection region 7 may be located in either the first region 6A of the output region 6 or the second region 6B of the output region 6, or both. In this configuration, the current detection region 7 is located in the first region 6A.

[0351] The first temperature measurement area 9 may be provided adjacent to either or both of the first area 6A and the second area 6B of the output area 6. In this embodiment, the first temperature measurement area 9 is provided adjacent to the first area 6A. The second temperature measurement area 10 is provided adjacent to the control area 8, as in the first embodiment.

[0352] In this configuration, the source terminal 26 is divided into an L-shape in a plan view. Specifically, the source terminal 26 has a first terminal portion 26A that extends in a strip shape along a first direction X to cover a first region 6A of the output region 6, and a second terminal portion 26B that extends in a strip shape along a second direction Y to cover a second region 6B of the output region 6. In this configuration, the source terminal 26 has a notch portion 26a that is cut out in a rectangular shape in the first terminal portion 26A to expose the first temperature measurement region 9.

[0353] The first to fourth control terminals 27 to 30 are located in the area on the second side surface 5B side, within the region demarcated by the periphery of the first main surface 3, the first terminal portion 26A of the source terminal 26, and the second terminal portion 26B of the source terminal 26.

[0354] Figure 22 is a plan view showing a semiconductor device 61 on which the semiconductor chip 1B shown in Figure 21 is mounted, along with a pseudo-bump 75 according to the first layout example. Figure 23 is a cross-sectional view along the line XXIII-XXIII shown in Figure 22. Referring to Figures 22 and 23, the semiconductor device 61 includes semiconductor chip 1B in place of semiconductor chip 1A.

[0355] The aforementioned multiple pseudo-bumps 75 may be positioned on either or both of the first terminal portion 26A and the second terminal portion 26B of the source terminal 26. In this embodiment, the multiple pseudo-bumps 75 are positioned on the intersection 26C of the first terminal portion 26A and the second terminal portion 26B. In this embodiment, the intersection 26C is also the portion of the source terminal 26 that covers the high-temperature region of the output region 6.

[0356] The explanation of the layout of multiple pseudo-bumps 75 and the relationship between the layout of the genuine bump 90 and the layout of multiple pseudo-bumps 75 is omitted as it has been explained above. Of course, the pseudo-bumps 75 according to the second layout example may be placed on the source terminal 26. Also, the pseudo-bumps 75 according to the third layout example (large pseudo-bump 75a and small pseudo-bump 75b) may be placed on the source terminal 26.

[0357] Figure 24 is a plan view showing the internal structure of the semiconductor device 61 according to the first modification, together with the pseudo-bumps 75 according to the first layout example. Figure 25 is a cross-sectional view along the line XXV-XXV shown in Figure 24. Referring to Figures 24 and 25, the semiconductor device 61 according to the first modification includes a first semiconductor chip 1C and a second semiconductor chip 1D instead of semiconductor chip 1A. The first semiconductor chip 1C and the second semiconductor chip 1D are configured to perform the same function as semiconductor chip 1A together.

[0358] Specifically, the first semiconductor chip 1C includes a substrate 2, an output region 6, a current detection region 7, a first temperature measurement region 9, a main transistor 11 (with multiple trench structures 35), a monitor transistor 13 (with multiple trench structures 35), a first temperature sensing diode 15, an interlayer insulating film 24, a drain terminal 25, a source terminal 26, gate wiring 53, source wiring 55, and multiple first function terminals 131-133, but does not include a control region 8, a second temperature measurement region 10, a second temperature sensing diode 16, and a control circuit 17.

[0359] The multiple first function terminals 131-133 include n (here, 2) first gate terminals 131, at least one (here, 1) first monitor terminal 132, and at least one (here, 1) first temperature measurement terminal 133. The n first gate terminals 131 are electrically connected to the first gates FG (multiple trench structures 35) of n (here, 2) main transistors 11 via n gate wirings 53, and transmit n (here, 2) gate signals input from the outside to the first gates FG.

[0360] The first monitor terminal 132 is electrically connected to the first monitor source FMS of the monitor transistor 13 via the source wiring 55 and outputs the monitor current IM from the monitor transistor 13 to the outside. The first temperature detection terminal 133 is electrically connected to the first temperature sensing diode 15 and outputs the first temperature detection signal ST1 from the first temperature sensing diode 15 to the outside.

[0361] On the other hand, the second semiconductor chip 1D includes a substrate 2, a control region 8, a second temperature sensing region 10, a second temperature sensing diode 16, a control circuit 17 (gate drive circuit 18, active clamp circuit 19, overcurrent protection circuit 20 and overheat protection circuit 21), an interlayer insulating film 24, a drain terminal 25, first to fourth control terminals 27 to 30, gate wiring 53, source wiring 55 and a plurality of second function terminals 134 to 136, but does not include an output region 6, a current detection region 7, a first temperature sensing region 9, a main transistor 11 (multiple trench structures 35), a monitor transistor 13 (multiple trench structures 35), or a first temperature sensing diode 15.

[0362] The multiple second function terminals 134-136 include n (here, 2) second gate terminals 134, at least one (here, 1) second monitor terminal 135, and at least one (here, 1) second temperature measurement terminal 136. The n second gate terminals 134 are electrically connected to the control circuit 17 (gate drive circuit 18) via n gate wirings 53, and output n gate signals generated by the control circuit 17 to the outside.

[0363] The second monitor terminal 135 is electrically connected to the control circuit 17 (overcurrent protection circuit 20) via source wiring 55, and the monitor current IM from the monitor transistor 13 is input. The second temperature detection terminal 136 is electrically connected to the control circuit 17 (overheat protection circuit 21), and the first temperature detection signal ST1 from the first temperature sensing diode 15 is input.

[0364] The semiconductor device 61 includes a first conductive bonding material 137 interposed between a first semiconductor chip 1C and a metal plate 66 within a package body 62. Specifically, the first conductive bonding material 137 is interposed between the drain terminal 25 of the first semiconductor chip 1C and the metal plate 66, electrically and mechanically connecting the drain terminal 25 of the first semiconductor chip 1C and the metal plate 66. The first conductive bonding material 137 may contain solder or metal paste. The solder may be lead-free solder. The metal paste may contain at least one of Au, Ag, and Cu. The Ag paste may consist of Ag sintered paste.

[0365] The semiconductor device 61 includes a second conductive bonding material 138 interposed between the second semiconductor chip 1D and the metal plate 66 within the package body 62. Specifically, the second conductive bonding material 138 is interposed between the drain terminal 25 of the second semiconductor chip 1D and the metal plate 66, electrically and mechanically connecting the drain terminal 25 of the second semiconductor chip 1D and the metal plate 66. The second conductive bonding material 138 may contain solder or metal paste. The solder may be lead-free solder. The metal paste may contain at least one of Au, Ag, and Cu. The Ag paste may consist of Ag sintered paste.

[0366] The semiconductor device 61 according to the first modified example includes at least one (or more in this embodiment) third bonding wires 139 arranged within the package body 62. The multiple third bonding wires 139 electrically connect multiple first functional terminals 131 to 133 to multiple second functional terminals 134 to 136, respectively.

[0367] Each of the multiple third bonding wires 139 includes a true bump 90, a wire loop 91, and a wire tail 92, similar to the first bonding wire 89. Furthermore, each of the multiple third bonding wires 139 includes a second bump body 97 and a second bump metal film 98 in the true bump 90, similar to the first bonding wire 89.

[0368] It is preferable that the true bump 90 is joined to the first functional terminals 131-133 and the wire tail 92 is joined to the second functional terminals 134-136. Of course, the true bump 90 may be joined to the second functional terminals 134-136 and the wire tail 92 may be joined to the first functional terminals 131-133. Further description of the third bonding wire 139 is omitted, as the description of the first bonding wire 89 applies.

[0369] In the semiconductor device 61 according to the first modified example, the electrical configuration of semiconductor chip 1A is realized by a first semiconductor chip 1C and a second semiconductor chip 1D. Since the manufacturing process for the second semiconductor chip 1D is omitted in the manufacturing process for the first semiconductor chip 1C, the manufacturing difficulty of the first semiconductor chip 1C is reduced, and the manufacturing time of the first semiconductor chip 1C can be shortened. Similarly, since the manufacturing process for the first semiconductor chip 1C is omitted in the manufacturing process for the second semiconductor chip 1D, the manufacturing difficulty of the second semiconductor chip 1D is reduced, and the manufacturing time of the second semiconductor chip 1D can be shortened.

[0370] Figure 26 is a plan view showing the internal structure of the semiconductor device 61 according to the second modification, together with the pseudo-bumps 75 according to the first layout example. Figure 27 is a cross-sectional view along the line XXVII-XXVII shown in Figure 26. The semiconductor device 61 according to the second modification has a form in which the form of the first semiconductor chip 1C and the form of the second semiconductor chip 1D according to the first modification are changed.

[0371] Specifically, the first semiconductor chip 1C includes a pad terminal 140 positioned on the interlayer insulating film 24 at a distance from the source terminal 26. The position of the pad terminal 140 is arbitrary. In this embodiment, the pad terminal 140 is positioned opposite the source terminal 26, flanking a plurality of first functional terminals 131 to 133. Preferably, the pad terminal 140 covers an area outside the output region 6 in a plan view.

[0372] The second semiconductor chip 1D is smaller in size than the first semiconductor chip 1C and is positioned on top of the first semiconductor chip 1C. The second semiconductor chip 1D is positioned on top of the pad terminal 140 with the drain terminal 25 facing the pad terminal 140. In addition, in a plan view, the second semiconductor chip 1D is positioned so that multiple second function terminals 134 to 136 face the multiple first function terminals 131 to 133.

[0373] In this configuration, the aforementioned second conductive bonding material 138 is interposed between the second semiconductor chip 1D and the pad terminals 140 within the package body 62. Specifically, the second conductive bonding material 138 is interposed between the drain terminal 25 and the pad terminals 140 of the second semiconductor chip 1D, electrically and mechanically connecting the drain terminal 25 and the pad terminals 140 of the second semiconductor chip 1D. The aforementioned multiple third bonding wires 139 electrically connect multiple first functional terminals 131 to 133 to multiple second functional terminals 134 to 136 on the first semiconductor chip 1C.

[0374] Hereinafter, with reference to the plan views in Figures 28 to 30, modified examples of the pseudo-bumps 75 according to the first to third layout examples are shown. Referring to Figure 28, in the multiple pseudo-bumps 75 according to the first layout example, at least one pseudo-bump 75 may be replaced with a real bump 90. Referring to Figure 29, in the multiple pseudo-bumps 75 according to the second layout example, at least one pseudo-bump 75 may be replaced with a real bump 90.

[0375] Referring to Figure 30, in the third layout example, at least one of the small pseudo-bumps 75b may be replaced with a true bump 90. In the first to third layout examples, the placement and number of pseudo-bumps 75 replaced with true bumps 90 are arbitrary. A detailed explanation of the layouts in Figures 28 to 30 can be obtained by replacing "pseudo-bump 75" with "true bump 90" in the above explanation of "pseudo-bump 75".

[0376] The embodiments described above can be implemented in other forms. For example, in the embodiments described above, one main transistor 11 may be used. In this case, all trench structures 35 for the main transistor 11 are controlled to turn on and off simultaneously. For example, in the embodiments described above, one monitor transistor 13 may be used. In this case, all trench structures 35 for the monitor transistor 13 are controlled to turn on and off simultaneously.

[0377] For example, in the embodiment described above, a current detection region 7 may be provided in a region outside the output region 6 (for example, within the control region 8). For example, in the embodiment described above, a structure may be adopted in which a first active clamp circuit 19 is connected to the main transistor 11 and a second active clamp circuit 19 is connected to the monitor transistor 13.

[0378] For example, in the embodiment described above, the monitor transistor 13 may include at least one system monitor transistor 14 that is electrically independent from the n system transistors 12. For example, in the embodiment described above, multiple system monitor transistors 14 may be connected to one system transistor 12. For example, in the embodiment described above, at least one second monitor source SMS may be electrically isolated from the first monitor source FMS to form an independent current path.

[0379] For example, in the embodiment described above, a structure may be adopted in which a first gate drive circuit 18 is connected to the main transistor 11 and a second gate drive circuit 18 is connected to the monitor transistor 13. In this case, the monitor transistor 13 may be controlled to operate in conjunction with the main transistor 11, or it may be controlled not to operate in conjunction with it.

[0380] In the above-described embodiment, an example was shown in which the second electrode 40 was fixed at the same potential as the first electrode 39. However, a potential different from that of the first electrode 39 may be applied to the second electrode 40. In this case, the source potential may be applied to the second electrode 40. This structure reduces parasitic capacitance between the substrate 2 and the second electrode 40 and improves the switching speed.

[0381] In the embodiments described above, the third insulating film 41 may be removed, and the first electrode 39 and the second electrode 40 may be formed integrally. Furthermore, the second insulating film 38 may have a thickness approximately equal to that of the first insulating film 37. In other words, the trench structure 35 may have a single electrode structure including a single electrode embedded in the trench 36 with the insulating film in between.

[0382] In the above-described embodiment, an example was shown in which a trench-gate type main transistor 11 is formed in the output region 6. However, a planar-gate type main transistor 11 may also be formed in the output region 6. In this case, a planar-gate type monitor transistor 13 may be formed in the current detection region 7.

[0383] In the embodiment described above, an example was shown in which the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type may be p-type and the second conductivity type may be n-type. In this case, the specific configuration can be obtained by replacing the n-type region with a p-type region and the p-type region with an n-type region, as shown in the description above and the attached drawings.

[0384] The following are examples of features extracted from this specification and the accompanying drawings. The alphanumeric characters in parentheses below represent the corresponding components in the embodiments described above, but this is not intended to limit the scope of each item (Clause) to the embodiments.

[0385] [A1] A semiconductor device (61) comprising a substrate (2), a device region (6) provided on the substrate (2), a terminal (26) covering the device region (6) in a plan view, a plurality of pseudo-bumps (75, 75a, 75b) densely arranged on the terminal (26) while free from wires, and at least one true bump (90) connected to wires and more sparsely arranged on the terminal (26) than the plurality of pseudo-bumps (75, 75a, 75b).

[0386] [A2] The semiconductor device (61) according to A1, wherein the plurality of pseudo-bumps (75, 75a, 75b) are arranged on the terminal (26) with a first occupied area per unit square area, and at least one true bump (90) is arranged on the terminal (26) with a second occupied area less than the first occupied area per unit square area.

[0387] [A3] The semiconductor device (61) according to A1 or A2, wherein a plurality of the true bumps (90) are sparsely arranged on the terminal (26).

[0388] [A4] The semiconductor device (61) according to A3, wherein a plurality of the pseudo bumps (75, 75a, 75b) are arranged on the terminal (26) at a first pitch (P1), and a plurality of the true bumps (90) are arranged on the terminal (26) at a second pitch (P2) which is larger than the first pitch (P1).

[0389] [A5] A semiconductor device (61) according to any one of A1 to A4, wherein at least three of the pseudo-bumps (75, 75a, 75b) are densely arranged on the terminal (26).

[0390] [A6] The semiconductor device (61) according to A5, wherein at least three of the pseudobumps (75, 75a, 75b) are arranged in a layout that is at the vertices of an isosceles triangle in a plan view.

[0391] [A7] A semiconductor device (61) according to any one of A1 to A6, wherein at least seven of the pseudo-bumps (75, 75a, 75b) are densely arranged on the terminal (26).

[0392] [A8] The semiconductor device (61) according to A7, wherein six of the pseudo-bumps (75, 75a, 75b) are arranged around one of the pseudo-bumps (75, 75a, 75b).

[0393] [A9] The semiconductor device (61) according to A8, wherein six of the pseudo-bumps (75, 75a, 75b) are arranged in a layout where they are located at the vertices of a hexagon in a plan view, and one of the pseudo-bumps (75, 75a, 75b) is arranged in a layout where it is located at the center of the hexagon in a plan view.

[0394] [A10] A semiconductor device (61) according to any one of A1 to A9, further comprising: thin film portions (111, 121, 122) formed at the joints of each of the pseudo-bumps (75, 75a, 75b) at the terminal (26); and thick film portions (113, 124) formed in the region outside the joints of each of the pseudo-bumps (75, 75a, 75b) at the terminal (26).

[0395] [A11] The semiconductor device (61) according to A10, wherein at the bonding edge of each of the pseudo-bumps (75, 75a, 75b) on the terminal (26), a portion of the terminal (26) further includes raised portions (114, 125, 126) that are thicker than the thick film portions (113, 124).

[0396] [A12] Each of the pseudo-bumps (75, 75a, 75b) includes a wide body portion (79) connected to the terminal (26), and a neck portion (80) that protrudes from the body portion (79) toward the opposite side from the terminal (26) and is narrower than the body portion (79), wherein the semiconductor device (61) is as described in any one of A1 to A11.

[0397] [A13] The semiconductor device (61) according to A12, wherein each of the pseudo-bumps (75, 75a, 75b) includes at least one recess (120) in the neck portion (80) toward the center of the neck portion (80).

[0398] [A14] Each pseudo-bump (75, 75a, 75b) comprises a bump body (77) containing a first metal, and a metal film (78) containing a second metal different from the first metal, which covers at least a portion of the outer surface of the bump body (77), according to any one of A1 to A13, wherein the semiconductor device (61) is as described above.

[0399] [A15] A semiconductor device (61) according to any one of A1 to A14, further comprising a plurality of trench structures (35) formed in the device region (6) on the substrate (2), wherein each of the pseudo-bumps (75, 75a, 75b) overlaps the plurality of trench structures (35) in a plan view.

[0400] [A16] The semiconductor device (61) according to A15, wherein each of the pseudo-bumps (75, 75a, 75b) has a thickness greater than the depth of each of the trench structures (35).

[0401] [A17] A semiconductor device (61) according to A15 or A16, further comprising transistors (11, 13) having a plurality of trench structures (35).

[0402] [A18] The semiconductor module (1D) according to A17, wherein the transistors (11, 13) include a plurality of individually controlled system transistors (12, 14), and the gate-divided transistors (11, 13) generate a single output signal (IO, IM) by selective control of the plurality of system transistors (12, 14).

[0403] [A19] The semiconductor module (1D) described in A18, wherein the transistors (11, 13) are configured such that their on-resistance changes by individual control of a plurality of the system transistors (12, 14).

[0404] [A20] A semiconductor device (61) according to any one of A1 to A19, further comprising a control region (8) provided on the substrate (2), wherein the terminal (26) covers the device region (6) such that the control region (8) is exposed in a plan view.

[0405] [A21] The semiconductor device (61) according to A20, further comprising: a first temperature measurement area (9) provided on the substrate (2) adjacent to the output area (6); a second temperature measurement area (10) provided on the substrate (2) adjacent to the control area (8); a first temperature sensor (15) formed in the first temperature measurement area (9); and a second temperature sensor (16) formed in the second temperature measurement area (10).

[0406] [B1] A semiconductor device (61) comprising a substrate (2), a device region (6) provided on the substrate (2), a terminal (26) covering the device region (6) in a plan view, a pseudo-bump (75a) positioned on the terminal (26) while free from wires, and a true bump (90) positioned on the terminal (26) while connected to wires and having a size (S13) smaller than the size (S11) of the pseudo-bump (75a).

[0407] [B2] The semiconductor device (61) described in B1, wherein the pseudo-bump (75a) is thicker than the terminal (26).

[0408] [B3] The semiconductor device (61) according to B1 or B2, further comprising a miniature pseudo-bump (75b) positioned around the pseudo-bump (75a) on the terminal (26) in a state free from wires, and having a size (S12) smaller than the size (S11) of the pseudo-bump (75a).

[0409] [B4] The small pseudo-bump (75b) is thicker than the terminal (26) of the semiconductor device (61) described in B3.

[0410] [B5] The semiconductor device (61) according to B3 or B4, wherein x (x≧2) of the small pseudo-bumps (75b) are arranged around the pseudo-bump (75a).

[0411] [B6] The semiconductor device (61) described in B5, wherein the value of x is 3 or greater (x≧3).

[0412] [B7] The semiconductor device (61) described in B5 or B6, wherein the value of x is 4 or greater (x≧4).

[0413] [B8] The semiconductor device (61) described in any one of B5 to B7, wherein the value of x is 20 or less (x ≤ 20).

[0414] [B9] The semiconductor device (61) described in any one of B5 to B8, wherein the value of x is 6 or more and 12 or less (6 ≤ x ≤ 12).

[0415] [B10] The semiconductor device (61) according to any one of B5 to B9, wherein x of the small pseudo-bumps (75b) are arranged at equal intervals along the circumferential direction of the pseudo-bump (75a) in a plan view.

[0416] [B11] The semiconductor device (61) according to any one of B5 to B10, wherein x of the small pseudo-bumps (75b) are arranged in concentric circles centered on the central part of the pseudo-bump (75a) in a plan view.

[0417] [B12] The semiconductor device (61) described in any one of B5 to B11, wherein x (x≧3) of the small pseudo-bumps (75b) are each arranged at the vertices of a regular x-gon in a plan view.

[0418] [B13] The semiconductor device (61) according to B12, wherein the pseudo-bump (75a) is located at the center of the regular x-gon in a plan view.

[0419] [B14] A semiconductor device (61) according to any one of B1 to B13, wherein a plurality of the true bumps (90) are arranged on the terminal (26).

[0420] [B15] The semiconductor device (61) according to any one of B1 to B14, wherein the pseudo-bump (75a) includes a wide body portion (79) connected to the terminal (26), and a neck portion (80) that protrudes from the body portion (79) toward the opposite side from the terminal (26) and is narrower than the body portion (79).

[0421] [B16] The semiconductor device (61) according to any one of B1 to B15, wherein the pseudo-bump (75a) includes a bump body (77) containing a first metal, and a metal film (78) containing a second metal different from the first metal and covering at least a portion of the outer surface of the bump body (77).

[0422] [B17] A semiconductor device (61) according to any one of B1 to B16, further comprising: a thin film portion (121) formed at the joint of the pseudo-bump (75a) at the terminal (26); and a thick film portion (124) formed in the region of the pseudo-bump (75a) outside the joint at the terminal (26).

[0423] [B18] The semiconductor device (61) according to B17, wherein at the bonding edge of the pseudo-bump (75a) on the terminal (26), a raised portion (125) is further included in which a part of the terminal (26) is thicker than the thick film portion (124).

[0424] [B19] A semiconductor device (61) according to any one of B1 to B18, further comprising a plurality of trench structures (35) formed in the device region (6) on the substrate (2), wherein the pseudo-bump (75a) overlaps the plurality of trench structures (35) in a plan view.

[0425] [B20] The semiconductor device (61) according to B19, wherein the pseudo-bumps (75a) have a thickness greater than the depth of each of the trench structures (35).

[0426] [B21] A semiconductor device (61) according to any one of B1 to B20, further comprising a control region (8) provided on the substrate (2), wherein the terminal (26) covers the device region (6) such that the control region (8) is exposed in a plan view.

[0427] [B22] The semiconductor device (61) according to B21, further comprising: a first temperature measurement area (9) provided on the substrate (2) adjacent to the output area (6); a second temperature measurement area (10) provided on the substrate (2) adjacent to the control area (8); a first temperature sensor (15) formed in the first temperature measurement area (9); and a second temperature sensor (16) formed in the second temperature measurement area (10).

[0428] Although embodiments have been described in detail, these are merely specific examples used to clarify the technical content, and the present invention should not be interpreted as being limited to these specific examples. The scope of the present invention is limited by the appended claims. [Explanation of symbols]

[0429] 1A Semiconductor Chip 1B Semiconductor Chip 1C First Semiconductor Chip 2 circuit boards 6. Device Area 8 Control Domain 9. First temperature measurement area 10. Second temperature measurement area 15. First temperature-sensitive diode 16. Second temperature-sensitive diode 17 Control circuits 26 Source terminals 35 Trench structure 61 Semiconductor Equipment 75 Pseudo Bump 75a Large simulated bump 75b Small pseudo-bump 77. First Bump Body 78 First Bump Metal Film 79. First Body Section 80 First neck section 90 Genuine Bump 111 First thin film section 113 Thick film portion 114 1st protuberance 120 Gouged area 121 First thin film section 122 Second Thin Film Section 124 Thick film portion 125 1st protuberance 126 Second bulge P1 First Pitch P2, 2nd pitch S11 1st size S12 2nd size S13 3rd size

Claims

1. circuit board and A device region provided on the aforementioned substrate, A terminal that covers the device area in a plan view, Multiple pseudo-bumps are densely arranged on the terminal while detached from the wire, Includes, while connected to a wire, at least one true bump that is spaced more widely apart than the plurality of pseudo bumps on the terminal, Multiple of the aforementioned pseudo-bumps are arranged on the terminals at a first pitch, At least one of the true bumps is positioned on the terminal at a third pitch with respect to one adjacent pseudo-bump, A semiconductor device wherein the third pitch is greater than or equal to the first pitch.

2. Multiple pseudo-bumps are arranged on the terminal with a first occupied area per unit square area. The semiconductor device according to claim 1, wherein at least one of the true bumps is located on the terminal with a second occupied area less than the first occupied area per unit area.

3. The semiconductor device according to claim 1, wherein a plurality of the true bumps are sparsely arranged on the terminal.

4. The semiconductor device according to claim 3, wherein the plurality of true bumps are arranged on the terminals at a second pitch that is larger than the first pitch.

5. The semiconductor device according to claim 1, wherein at least three of the pseudo-bumps are densely arranged on the terminal.

6. The semiconductor device according to claim 5, wherein at least three of the pseudo-bumps are arranged in a layout that is located at the vertices of an isosceles triangle in a plan view.

7. The semiconductor device according to claim 1, wherein at least seven of the pseudo-bumps are densely arranged on the terminal.

8. The semiconductor device according to claim 7, wherein six of the pseudo-bumps are arranged around one of the pseudo-bumps.

9. The six pseudo-bumps are arranged in a layout that positions them at the vertices of a hexagon in a plan view. The semiconductor device according to claim 8, wherein one of the pseudo-bumps is arranged in a layout where it is located at the center of the hexagon in a plan view.

10. A thin film portion formed at the joint of each of the pseudo bumps in the terminal, A semiconductor device according to any one of claims 1 to 9, further comprising: a thick film portion formed in the region outside the joint of each of the pseudo bumps at the terminal.

11. The semiconductor device according to claim 10, wherein at the bonding edge of each pseudo-bump in the terminal, a portion of the terminal further includes a raised portion that is thicker than the thick film portion.

12. Each of the pseudo-bumps includes a wide body portion connected to the terminal, and a neck portion that protrudes from the body portion toward the opposite side from the terminal, narrower than the body portion, according to any one of claims 1 to 9.

13. The semiconductor device according to claim 12, wherein each of the pseudo-bumps includes at least one recessed portion in the neck portion toward the center of the neck portion.

14. Each pseudo-bump comprises a bump body containing a first metal, and a metal film containing a second metal different from the first metal, which covers at least a portion of the outer surface of the bump body, according to any one of claims 1 to 9.

15. The substrate further includes a plurality of trench structures formed in the device region, The semiconductor device according to any one of claims 1 to 9, wherein each of the pseudo-bumps overlaps with a plurality of trench structures in a plan view.

16. The semiconductor device according to claim 15, wherein each of the pseudo-bumps has a thickness greater than the depth of each of the trench structures.

17. The substrate further includes a control region provided on the substrate, The semiconductor device according to any one of claims 1 to 9, wherein the terminals cover the device area such that the control area is exposed in a plan view.

18. circuit board and A device region provided on the aforementioned substrate, A terminal that covers the device area in a plan view, A pseudo-bump positioned on the terminal while detached from the wire, A genuine bump, which is placed on the terminal while connected to a wire and has a size smaller than the size of the pseudo-bump, is included. The pseudo-bump is positioned on the terminal at a first pitch, The genuine bump is positioned on the terminal at a third pitch with respect to one adjacent pseudo-bump, A semiconductor device wherein the third pitch is greater than or equal to the first pitch.

19. The semiconductor device according to claim 18, further comprising a miniature pseudo-bump positioned around the pseudo-bump on the terminal, free from wires, and having a size smaller than the size of the pseudo-bump.

20. The semiconductor device according to claim 19, wherein a plurality of the small pseudo-bumps are arranged around the pseudo-bumps.

21. A substrate and A device region provided on the aforementioned substrate, A terminal that covers the device area in a plan view, Multiple pseudo-bumps are densely arranged on the terminal while detached from the wire, Includes, while connected to a wire, at least one true bump that is spaced more widely apart than the plurality of pseudo bumps on the terminal, The device region includes a high-temperature region that becomes relatively hotter due to the temperature rise, and a low-temperature region that remains relatively lower than the high-temperature region. A semiconductor device in which the plurality of pseudo-bumps are joined to the portion of the terminal that covers the high-temperature region.

22. A substrate and A device region provided on the aforementioned substrate, A terminal that covers the device area in a plan view, A pseudo-bump positioned on the terminal while detached from the wire, A genuine bump, which is placed on the terminal while connected to a wire and has a size smaller than the size of the pseudo-bump, is included. The device region includes a high-temperature region that becomes relatively hotter due to the temperature rise, and a low-temperature region that remains relatively lower than the high-temperature region. The pseudo-bump is bonded to the portion of the terminal that covers the high-temperature region in the semiconductor device.

23. The semiconductor device according to claim 21, wherein the plurality of pseudo-bumps are joined to the portion of the terminal covering the high-temperature region and the low-temperature region, and at least one true bump is joined to the portion of the terminal covering the low-temperature region.

24. The semiconductor device according to claim 22, wherein the pseudo-bump is joined to the portion of the terminal covering the high-temperature region and the low-temperature region, and the true bump is joined to the portion of the terminal covering the low-temperature region.

25. The high-temperature region is the inner part of the device region, The semiconductor device according to any one of claims 21 to 24, wherein the low-temperature region is the peripheral edge of the device region.

Images