Semiconductor equipment

Abstract

To reduce an on-resistance while maintaining a channel length and suppressing a reduction of a threshold voltage.SOLUTION: A semiconductor device according to the present embodiment includes: a first electrode; a first semiconductor region of a first conductivity type disposed above the first electrode; a second semiconductor region of a second conductivity type disposed on the first semiconductor region; a third semiconductor region of the first conductivity type disposed on the second semiconductor region; an insulating film disposed in the first semiconductor region, the second semiconductor region, and the third semiconductor region; and a second electrode disposed in the insulating film so as to be adjacent to the second semiconductor region via the insulating film. The second semiconductor region includes a boundary region that is in contact with the insulating film and faces the second electrode. The boundary region has a high-concentration region including a peak of an impurity concentration of the second conductivity type. The insulating film includes a first region in contact with the high-concentration region and a second region in contact with a low-concentration region of the boundary region, the low-concentration region being different from the high-concentration region. A thickness of the second region is smaller than a thickness of the first region.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] A semiconductor device having a trench gate structure in which a gate electrode is embedded in a groove formed in a semiconductor layer is known. In such a semiconductor device, channel resistance is one of the main factors affecting the on-resistance (Ron). To reduce channel resistance, design measures such as lowering the threshold voltage Vth or shortening the length of the base region (channel length) can be considered.

[0003] However, lowering the threshold voltage Vth increases the risk of semiconductor device malfunction. Also, shortening the channel length causes short-channel effects, degrading the reliability of the semiconductor device. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2002-299619 [Patent Document 2] Japanese Patent Publication No. 2012-204377 [Patent Document 3] Japanese Patent Publication No. 2003-17696 [Patent Document 4] Japanese Patent Publication No. 2018-56463 [Patent Document 5] Japanese Patent Publication No. 2012-216675 [Overview of the project] [Problems that the invention aims to solve]

[0005] Embodiments of the present invention provide a semiconductor device that can reduce on-resistance while maintaining channel length and suppressing a decrease in threshold voltage. [Means for solving the problem]

[0006] The semiconductor device according to this embodiment includes a first electrode, a first semiconductor region of a first conductivity type disposed above the first electrode, a second semiconductor region of a second conductivity type disposed above the first semiconductor region, a third semiconductor region of a first conductivity type disposed above the second semiconductor region, an insulating film disposed within the first semiconductor region, the second semiconductor region, and the third semiconductor region, a second electrode disposed in the insulating film so as to be adjacent to the second semiconductor region via the insulating film, and a third electrode electrically connected to the third semiconductor region. The second semiconductor region includes a boundary region in contact with the insulating film and facing the second electrode, the boundary region having a high-concentration region including a peak in the impurity concentration of the second conductivity type, the insulating film includes a first region in contact with the high-concentration region and a second region in contact with a low-concentration region of the boundary region that is different from the high-concentration region, and the thickness of the second region is smaller than the thickness of the first region. [Brief explanation of the drawing]

[0007] [Figure 1A] This is a cross-sectional view of the semiconductor device according to the first embodiment. [Figure 1B] This diagram illustrates the shape of the gate insulating film provided in the semiconductor device according to the first embodiment. [Figure 1C] This figure shows an example of the relationship between threshold voltage and on-resistance in a semiconductor device according to the first embodiment. [Figure 2A] This figure illustrates the shape of the gate insulating film provided in a semiconductor device according to a modified example 1 of the first embodiment. [Figure 2B] This figure shows an example of the relationship between threshold voltage and on-resistance in a semiconductor device according to Modification 1 of the First Embodiment. [Figure 3A] This figure illustrates the shape of the gate insulating film provided in a semiconductor device according to a modified example 2 of the first embodiment. [Figure 3B] This figure shows an example of the relationship between threshold voltage and on-resistance in a semiconductor device according to a modified example 2 of the first embodiment. [Figure 4]It is a diagram for explaining the shape of the gate insulating film included in the semiconductor device according to Modification Example 3 of the First Embodiment. [Figure 5] It is a diagram for explaining the shape of the gate insulating film included in the semiconductor device according to Modification Example 4 of the First Embodiment. [Figure 6A] It is a cross-sectional view for explaining an example of the steps of the manufacturing method of the semiconductor device according to the First Embodiment. [Figure 6B] It is a cross-sectional view for explaining an example of the steps of the manufacturing method of the semiconductor device according to the First Embodiment, following FIG. 6A. [Figure 6C] It is a cross-sectional view for explaining an example of the steps of the manufacturing method of the semiconductor device according to the First Embodiment, following FIG. 6B. [Figure 6D] It is a cross-sectional view for explaining an example of the steps of the manufacturing method of the semiconductor device according to the First Embodiment, following FIG. 6C. [Figure 6E] It is a cross-sectional view for explaining an example of the steps of the manufacturing method of the semiconductor device according to the First Embodiment, following FIG. 6D. [Figure 6F] It is a cross-sectional view for explaining an example of the steps of the manufacturing method of the semiconductor device according to the First Embodiment, following FIG. 6E. [Figure 6G] It is a cross-sectional view for explaining an example of the steps of the manufacturing method of the semiconductor device according to the First Embodiment, following FIG. 6F. [Figure 7A] It is a cross-sectional view of the semiconductor device according to the Second Embodiment. [Figure 7B] It is a diagram for explaining the shape of the gate insulating film included in the semiconductor device according to the Second Embodiment. [Figure 8A] It is a cross-sectional view for explaining an example of the steps of the manufacturing method of the semiconductor device according to the Second Embodiment. [Figure 8B] It is a cross-sectional view for explaining an example of the steps of the manufacturing method of the semiconductordevice according to the Second Embodiment, following FIG. 8A. [Figure 8C] It is a cross-sectional view for explaining an example of the steps of the manufacturing method of the semiconductor device according to the Second Embodiment, following FIG.http: / / www.8B. [Figure 8D]Figure 8C is a cross-sectional view illustrating an example of the steps for manufacturing a semiconductor device according to the second embodiment. [Figure 9A] This is a cross-sectional view of the semiconductor device according to the third embodiment. [Figure 9B] This figure illustrates the shape of the gate insulating film provided in the semiconductor device according to the third embodiment. [Figure 10A] This is a cross-sectional view illustrating an example of the steps for manufacturing a semiconductor device according to the third embodiment. [Figure 10B] This is a cross-sectional view illustrating an example of the steps for manufacturing a semiconductor device according to the third embodiment, following Figure 10A. [Figure 10C] Figure 10B is a cross-sectional view illustrating an example of the steps for manufacturing a semiconductor device according to the third embodiment. [Figure 10D] Figure 10C is a cross-sectional view illustrating an example of the steps for manufacturing a semiconductor device according to the third embodiment. [Figure 10E] Figure 10D is a cross-sectional view illustrating an example of the steps for manufacturing a semiconductor device according to the third embodiment. [Figure 11A] This is a cross-sectional view of a semiconductor device according to the fourth embodiment. [Figure 11B] This figure illustrates the shape of the gate insulating film provided in the semiconductor device according to the fourth embodiment. [Modes for carrying out the invention]

[0008] Embodiments of the present invention will be described below with reference to the drawings. These embodiments are not intended to limit the present invention. The drawings are schematic or conceptual, and the proportions of each part may not necessarily be the same as those of actual objects. In the specification and drawings, elements similar to those described above are denoted by the same reference numerals with respect to previously shown drawings, and detailed explanations are omitted as appropriate.

[0009] For the sake of convenience in explanation, an XYZ orthogonal coordinate system is adopted. The Z-axis direction is the stacking direction (thickness direction) of the semiconductor device. Also, in the Z-axis direction, the source electrode side is also referred to as "up", and the drain electrode side is also referred to as "down". However, this expression is for convenience and has nothing to do with the direction of gravity.

[0010] In addition, in the following description, in order to represent the relative levels of impurity concentrations in each conductivity type, n - , [[ID=e]]n, n - and p + p, p - notations may be used. That is, n + indicates that the n-type impurity concentration is relatively higher than that of n, and n - [[ID=1e]]indicates that the n-type impurity concentration is relatively lower than that of n. Also, p <d000007>indicates that the p-type impurity concentration is relatively higher than that of p, and p - indicates that the p-type impurity concentration is relatively lower than that of p. The n-type, n <00000d9>type and n - type are an example of the first conductivity type in the claims. The p-type, p + type and p - type are an example of the second conductivity type in the claims. In the following description, the n-type and the p-type may be reversed. That is, the first conductivity type may be the p-type.

[0011] (First Embodiment) Referring to FIG. 1A, the semiconductor device 1 according to the first embodiment will be described. In this embodiment, the semiconductor device 1 is configured as a vertical MOSFET having a trench gate structure.

[0012] As shown in FIG. 1A, the semiconductor device 1 includes a drain electrode 2, a semiconductor region 3, a gate electrode 4, a gate insulating film 5, a field plate electrode (FP electrode) 6, a barrier metal 7, and a source electrode 8.

[0013] [[ID=41*] The drain electrode 2 is an electrode that functions as the drain electrode of the MOSFET. The drain electrode 2 is located beneath the semiconductor region 3. The drain electrode 2 is electrically connected to the drain region 31 contained within the semiconductor region 3. The drain electrode 2 is made of a metal such as titanium (Ti), tungsten (W), or aluminum (Al). The drain electrode 2 is an example of the first electrode in the claims.

[0014] The semiconductor region 3 is positioned on the drain electrode 2. The semiconductor region 3 includes, for example, a drain region 31, a drift region 32, a base region 33, a contact region 34, and a source region 35.

[0015] The semiconductor region 3 may be an epitaxial layer, a semiconductor substrate, or a semiconductor substrate with an epitaxial layer disposed thereon. In this embodiment, the semiconductor region 3 is, for example, silicon (Si). In this case, n-type impurities may include, for example, arsenic (As), phosphorus (P), or antimony (Sb). Also, p-type impurities may include, for example, boron (B). The semiconductor region 3 may also be made of a compound semiconductor such as silicon carbide (SiC) or gallium nitride (GaN).

[0016] The drain region 31 is a semiconductor region that functions as the drain of the MOSFET. The drain region 31 is located on top of the drain electrode 2 and is electrically connected to the drain electrode 2. The drain region 31 is also located between the drain electrode 2 and the drift region 32. The drain region 31 is, for example, n + This is a semiconductor region of a certain shape. The drain region 31 is an example of a fourth semiconductor region in the claims.

[0017] The drift region 32 is a semiconductor region that functions as the drift region of the MOSFET. The drift region 32 is located above the drain region 31 (above the drain electrode 2). The drift region 32 is, for example, n -This is a semiconductor region of a certain shape. The drift region 32 is an example of the first semiconductor region in the claims.

[0018] The base region 33 is a semiconductor region that functions as the base of the MOSFET. The base region 33 is located on the drift region 32 and is adjacent to the gate electrode 4 via the gate insulating film 5. The base region 34 is located between the drift region 32 and the source region 35. When a voltage is applied to the gate electrode 4, the base region 33 forms a channel, allowing carriers to flow between the drain region 31 and the source region 35. The base region 33 is, for example, p - This is a semiconductor region of a certain shape. The base region 33 is an example of a second semiconductor region in the claims.

[0019] The contact region 34 is located between the drift region 32 and the barrier metal 7. The contact region 34 is located below the barrier metal 7. The contact region 34 is, for example, p + This is a semiconductor region of a certain shape. The contact region 34 is positioned to prevent the generation of a potential difference between the base region 33 and the barrier metal 7 when a reverse voltage is applied to the MOSFET, thereby suppressing device failure by parasitic transistors.

[0020] The source region 35 is a semiconductor region that functions as the source of the MOSFET. The source region 35 is located on top of the base region 33. The source region 35 is also located in the region between the gate insulating film 5 and the barrier metal 7. The source region 35 is electrically connected to the source electrode 8 via the barrier metal 7. The source region 35 is, for example, n + This is a semiconductor region of a certain shape. Source region 35 is an example of a third semiconductor region in the claims.

[0021] The gate electrode 4 is an electrode that functions as the gate electrode of the MOSFET. The gate electrode 4 is located in the gate insulating film 5. In the Y-axis direction, the gate electrode 4 is positioned adjacent to (facing) the base region 33 via the gate insulating film 5. In this embodiment, as shown in Figure 1A, the gate electrode 4 has an H-shaped cross-section with a small central thickness (width in the Y-axis direction). The gate electrode 4 is made of, for example, polysilicon. The gate electrode 4 is an example of the second electrode in the claims.

[0022] The gate insulating film 5 is positioned within the drift region 32, the base region 33, and the source region 35, electrically insulating the gate electrode 4 from the semiconductor region 3 and the barrier metal 7. The gate insulating film 5 also electrically insulates the FP electrode 6 from the semiconductor region 3. In this embodiment, the gate insulating film 5 is an insulating film embedded in a gate trench extending from the source region 35 to partway through the drift region 32. The gate insulating film 5 is composed of an insulating material such as silicon oxide or silicon nitride. The gate insulating film 5 is an example of an insulating film within the claims.

[0023] The FP electrode 6 is positioned below the gate electrode 4 within the gate insulating film 5. The FP electrode 6 is electrically connected to the source electrode 8. The FP electrode 6 is positioned to increase the breakdown voltage by mitigating the concentration of the reverse electric field between the gate electrode 4 and the drain electrode 9. The FP electrode 6 is made of, for example, polysilicon. The FP electrode 6 is an example of the fourth electrode in the claims.

[0024] The barrier metal 7 is used to prevent reaction between the metallic material used in the source electrode 8 and the semiconductor material used in the semiconductor region 3. The barrier metal 7 is in contact with the base region 33, the contact region 34, and the source region 35. The barrier metal 7 includes, for example, titanium, titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN).

[0025] The source electrode 8 is an electrode that functions as the source electrode of the MOSFET. The source electrode 8 is electrically connected to the barrier metal 7 and electrically connected to the source region 35. The source electrode 8 is made of, for example, copper, aluminum, or the like. The source electrode 8 is an example of the third electrode in the claims.

[0026] In the above description, it was assumed that the semiconductor device 1 is a vertical MOSFET, but the semiconductor device 1 may also be configured as an insulated-gate bipolar transistor (IGBT) having a similar structure, namely a trench-gate structure. If the semiconductor device 1 is an IGBT, the drain region 31 is, for example, p + The collector region may be changed to a different type, or a collector region may be added and placed between the drain region 31 and the drain electrode 2. Otherwise, it is the same as the vertical MOSFET described in this embodiment. Note that if the semiconductor device 1 is an IGBT, the source region 35 becomes the emitter region. This collector region is an example of the fifth semiconductor region in the claims.

[0027] <Shape of gate insulating film 5> Here, the shape of the gate insulating film 5 will be explained with reference to Figure 1B. Figure 1B is a diagram illustrating the relationship between the thickness of the portion 5a sandwiched between the base region 33 and the gate electrode 4 of the gate insulating film 5 and the impurity concentration of the boundary region 33a. Here, the thickness of portion 5a refers to the width of portion 5a in the Y-axis direction, which corresponds to the distance between the base region 33 and the gate electrode 4 in the Y-axis direction. The right-hand side of Figure 1B is an enlarged view of region A shown in Figure 1A.

[0028] As shown in Figure 1B, the base region 33 includes a boundary region 33a that is in contact with the gate insulating film 5 (part 5a) and faces the gate electrode 4. The graph shown in Figure 1B (left figure) shows the concentration distribution of impurity concentration p in the boundary region 33a.

[0029] As shown in Figure 1B, the impurity concentration p in the boundary region 33a is not uniform and is biased in the Z-axis direction. The maximum value of the impurity concentration p is the peak p maxThe boundary region 33a has a region with a relatively high impurity concentration p (high-concentration region H) that includes the peak, and a low-concentration region L other than the high-concentration region H. The high-concentration region H is the region within the boundary region 33a where the impurity concentration p is the value at the peak p max A predetermined proportion α or greater (i.e., the impurity concentration p is αp) max ~p max This is the domain of ).

[0030] As shown in Figure 1B, the thickness of portion 5a changes according to the impurity concentration p in the boundary region 33a. The gate insulating film 5 (portion 5a) includes region A1, which is in contact with the high-concentration region H, and region A2, which is the region (other than region A1) in contact with the low-concentration region L. In this embodiment, region A2 is the entire region of portion 5a excluding region A1.

[0031] Furthermore, the thickness T2 of region A2 is smaller than the thickness T1 of region A1. In this embodiment, the shape (thickness) of portion 5a described above is achieved by the gate electrode 4 having an H-shaped cross-section.

[0032] In Figure 1B, the high-concentration region H is located near the center of the boundary region 33a, so region A2 is located above and below region A1. However, the high-concentration region H may include the upper or lower edge of the boundary region 33a. In other words, the high-concentration region H may be in contact with the drift region 32 or the source region 35. In that case, region A2 will be located either above or below region A1.

[0033] <Simulation Results> Referring to Figure 1C, the effect of changing the thickness of portion 5a of the insulating film 5 according to the impurity concentration p in the boundary region 33a, as described above, will be explained.

[0034] Figure 1C is a graph showing an example of the relationship between the threshold voltage Vth and the on-resistance Ron of the semiconductor device 1 according to this embodiment, obtained by simulation, when the thickness T2 is changed. In the simulation of this embodiment, a predetermined ratio α = 0.5 was set, and the thickness T1 was always 40 nm.

[0035] Figure 1C also shows the relationship between the threshold voltage Vth and the on-resistance Ron of the semiconductor device in the comparative example, obtained by simulation. In the comparative example, the thickness of the gate insulating film 5 in contact with the boundary region 33a is constant (i.e., T1 = T2). The numbers next to each plot indicate the magnitude of the thickness T2 in each plot.

[0036] As can be seen from the comparative example shown in Figure 1C, if the thickness of section 5a is uniformly reduced to lower the on-resistance Ron (channel resistance) (i.e., if T1 and T2 are reduced together), the threshold voltage Vth also decreases. In other words, there is a trade-off relationship between on-resistance Ron and threshold voltage Vth.

[0037] In contrast, in this embodiment, the thickness T2 of region A2, which is in contact with the low-concentration region L and has little effect on the threshold voltage Vth, is made smaller than the thickness T1 of region A1, which is in contact with the high-concentration region H. This makes it possible to reduce the channel resistance while suppressing the decrease in the threshold voltage Vth, and thus reduce the on-resistance Ron. In other words, the trade-off relationship between on-resistance Ron and threshold voltage Vth can be improved.

[0038] In the above simulation, the predetermined ratio α was set to 0.5, but the effective value of α depends on the impurity concentration profile in the boundary region 33a of the base region 33 and the film thickness of portion 5a of the gate insulating film 5, etc. For example, the predetermined ratio α may be between 0.7 and 0.95.

[0039] Furthermore, in this embodiment, only the thickness of portion 5a of the gate insulating film 5 is changed, and the base length is not changed, thus preventing short-channel effects.

[0040] Thus, according to this embodiment, since the thickness of region A1 in contact with the high-concentration region H is greater than the thickness of region A2 in contact with the low-concentration region L, it is possible to provide a semiconductor device that can reduce on-resistance while maintaining the channel length and suppressing the reduction of the threshold voltage.

[0041] In the description of the first embodiment above, region A2 was defined as the region of the insulating film 5a other than region A1. That is, as shown in Figure 1B, if the high-density region H is not in contact with the drift region 32 and the source region 35, region A2 will be located above and below region A1. However, if it is sufficient to improve the trade-off relationship between on-resistance Ron and threshold voltage Vth to some extent, region A2 does not necessarily have to be all regions of the boundary region 33a other than region A1. That is, region A2 only needs to be in contact with either of the low-density regions L located above or below the high-density region H. In that case, some steps can be omitted in the manufacturing method of the semiconductor device 1, which will be described later.

[0042] From the above perspective, two modified examples (Modification 1 and Modification 2) according to the first embodiment will be described below.

[0043] (Variation 1) Figure 2A is an enlarged view of region A of the semiconductor device 1 according to Modification 1 of the first embodiment. There are no changes to the parts other than region A. In Modification 1, as shown in Figure 2A, region A2 is located below region A1, and the region above region A1 has the same thickness (thickness T1) as region A1.

[0044] <Simulation Results> Referring to Figure 2B, the effect of the shape of part 5a of the semiconductor device 1 according to Modification 1 will be explained. Figure 2B is a graph showing an example of the relationship between the threshold voltage Vth and the on-resistance Ron of the semiconductor device 1 according to Modification 1 when the thickness T2 is changed, as obtained by simulation. The comparative example shown in Figure 2B is the same as the comparative example shown in Figure 1C. In the simulation of this modification as well, the predetermined ratio α = 0.5 was set, and T1 was always assumed to be 40 nm.

[0045] As can be seen from Figure 2B, although the reduction in on-resistance is not as significant as in the first embodiment, this modified example also improves the trade-off relationship between on-resistance Ron and threshold voltage Vth.

[0046] (Modification 2) Figure 3A is an enlarged view of region A of the semiconductor device 1 according to Modification 2 of the First Embodiment. There are no changes to the parts other than region A. In Modification 2, as shown in Figure 3A, region A2 is located above region A1, and the region below region A1 has the same thickness (thickness T1) as region A1.

[0047] <Simulation Results> Referring to Figure 3B, the effect of the shape of part 5a of semiconductor device 1 in Modification 2 will be explained. Figure 3B is a graph showing an example of the relationship between the threshold voltage Vth and the on-resistance Ron of semiconductor device 1 in Modification 2 when the thickness T2 is changed, as obtained by simulation. The comparative example shown in Figure 3B is the same as the comparative example shown in Figure 1C. In the simulation of this modification as well, the predetermined ratio α = 0.5 was set, and T1 was always 40 nm.

[0048] As can be seen from Figure 3B, although the reduction in on-resistance is not as significant as in the first embodiment, this modified example also improves the trade-off relationship between on-resistance Ron and threshold voltage Vth.

[0049] As shown in the first embodiment, modification example 1, and modification example 2 above, in order to improve the trade-off relationship between on-resistance Ron and threshold voltage Vth, region A2 can be any region of portion 5a that is different from region A1. In other words, in the examples shown in Figures 2A and 2B, region A2 can be at least one of the regions above and below region A1.

[0050] (Variation 3) By the way, in the above explanation, there was only one high-concentration region H, but depending on the distribution of impurity concentration p in the boundary region 33a, there may be multiple high-concentration regions H. Figure 4 is an enlarged view of region A of the semiconductor device 1 according to modification 3 of the first embodiment. There are no changes to the parts other than region A. As shown in Figure 4, in this modification, the high-concentration regions H are located spaced apart in the Z-axis direction. In such cases, region A1 is also located spaced apart in the Z-axis direction in accordance with the high-concentration regions H.

[0051] As shown in this modified example, even when there are multiple high-concentration regions H, the trade-off relationship between on-resistance Ron and threshold voltage Vth can be improved by arranging regions A1 and A2 of different thicknesses corresponding to the high-concentration regions H.

[0052] (Modification 4) Figure 5 is an enlarged view of region A of the semiconductor device 1 according to modification 4 of the first embodiment. There are no changes to the parts other than region A. As shown in Figure 5, in this modification, the gate electrode 4 has partial electrodes 4a, 4b, and 4c that are spaced apart from each other. Each of the partial electrodes 4a, 4b, and 4c is electrically connected to each other by a metal plug (not shown) that penetrates the partial electrodes 4a, 4b, and 4c in the Z-axis direction, and is at the same potential. The metal plug is located in a gate contact portion provided locally along the X-axis direction. Partial electrode 4b is adjacent to a high-concentration region H via region A1. Partial electrodes 4a and 4c are adjacent to a low-concentration region L via region A2. Partial electrodes 4a and 4b are examples of the first and second partial electrodes in the claims, respectively.

[0053] In this modified example, by arranging regions A1 and A2 of different thicknesses corresponding to the high-concentration region H and the low-concentration region L, the trade-off relationship between on-resistance Ron and threshold voltage Vth can be improved.

[0054] <Manufacturing method for semiconductor devices> Next, an example of a method for manufacturing the semiconductor device 1 will be described with reference to Figures 6A to 6H. Figures 6A to 6H are cross-sectional views illustrating the process for manufacturing the semiconductor device 1. Here, the process of manufacturing the gate insulating film 5 will be explained in detail, and other processes will be omitted or simplified as appropriate.

[0055] First, as shown in Figure 6A, a trench T is provided in the drift region 32 formed on the semiconductor wafer, and a gate insulating film 5 is placed inside the trench T. The trench T is partially filled with the gate insulating film 5, forming a recess RE1. The gate insulating film 5 is made of, for example, silicon oxide. In this embodiment, an FP electrode 6 is embedded inside the gate insulating film 5, but it is not necessary to provide the FP electrode 6.

[0056] Next, as shown in Figure 6B, a gate electrode 4 is formed in the recess RE1. The gate electrode 4 is formed, for example, by depositing a conductive material such as polysilicon to fill the recess RE1, and then etching back the excess conductive material.

[0057] Next, as shown in Figure 6C, an insulating material is deposited in the recess RE1 by physical vapor deposition (PVD) or chemical vapor deposition (CVD). As a result, the gate electrode 4 is embedded in the gate insulating film 5. Also, the width of the recess RE1 is reduced. The insulating material is, for example, silicon oxide.

[0058] Next, as shown in Figure 6D, a portion of the gate insulating film 5 is removed, for example, by a combination of a resist mask and RIE (Reactive Ion Etching), so that the gate electrode 4 is exposed on the bottom surface of the recess RE1. At this time, the width of the recess RE1 is made to be approximately the same as the width in the previous step.

[0059] Next, as shown in Figure 6E, for example, after laminating conductive material to fill the recess RE1, the gate electrode 4 is extended upward by etching back the excess conductive material.

[0060] Next, as shown in Figure 6F, the width of the recess RE1 above the gate electrode 4 is widened by removing a portion of the gate insulating film 5, for example, by wet etching.

[0061] Next, as shown in Figure 6G, for example, after laminating conductive material to fill the recess RE1, the excess conductive material is etched back to extend the gate electrode 4 upward. This forms a gate electrode 4 with an H-shaped cross-section. Furthermore, the shape of portion 5a of the gate insulating film 5 is determined by the shape of the gate electrode 4.

[0062] Subsequently, although not shown in the diagram, the base region 33 and the source region 35 are formed by ion implantation of impurity ions of the second and first conductivity types into the drift region 32. The base region 33 is formed using ion implantation or other methods such that the region adjacent to the portion of the insulating film 5a with a thickness T1 in the boundary region 33a becomes a high-concentration region H. Then, insulating material is deposited in the recess RE1 by methods such as PVD or CVD, and the gate electrode 4 is embedded in the gate insulating film 5.

[0063] Subsequently, a contact trench is provided on the inner wall (not shown) in which a base region 33 and a source region 35 are exposed. Then, a contact region 34 is formed by ion implantation of ions of a second conductivity type into the bottom of the contact trench. After that, a barrier metal 7 is formed by depositing a first metallic material to fill the contact trench. The first metallic material includes, for example, titanium, tungsten, or nickel. Then, a source electrode 8 is formed by depositing a second metallic material on top of the barrier metal 7. The second metallic material includes, for example, copper or aluminum. Furthermore, a drain region 31 is formed by ion implantation into the lower surface of the drift region 32, and a drain electrode 2 is formed by depositing the second metallic material in the drain region 31. For the deposition of the first metallic material and / or the second metallic material, for example, a vapor deposition method or a sputtering method may be used.

[0064] The semiconductor device 1 according to the first embodiment is manufactured through the above process. Note that the above description is merely one example of a method for manufacturing the semiconductor device 1, and it is possible to manufacture the semiconductor device 1 by other methods as well. For example, the drain region 31 may be formed before the formation of the gate electrode 4.

[0065] Furthermore, in the above manufacturing method, the thickness of portion 5a of the gate insulating film 5 is varied by first forming the lower part of the gate electrode 4 (see Figures 6A and 6B), then separately forming the central part of the gate electrode 4 (see Figures 6C-6E), and finally separately forming the upper part of the gate electrode 4 (see Figures 6F and 6G).

[0066] As described above, in the case of Modification 1 and 2, some of the above manufacturing methods can be omitted or modified. Specifically, in Modification 1, since the width of the upper and central parts of the gate electrode 4 is constant, the step of separately forming the upper part of the gate electrode 4 (see Figures 6F and 6G) ​​can be omitted. Similarly, in Modification 2, since the width of the lower and central parts of the gate electrode 4 is constant, the step of separately forming the central part of the gate electrode 4 (see Figures 6C-6E) can be omitted. In this way, in both Modification 1 and 2, the manufacturing method can be simplified and manufacturing costs can be reduced.

[0067] (Second Embodiment) Next, the semiconductor device 1A according to the second embodiment will be described with reference to Figures 7A and 7B. Figure 7A is a cross-sectional view of the semiconductor device 1A according to the second embodiment. Figure 7B is an enlarged view of area A shown in Figure 7A. In Figures 7A and 7B, elements with the same names or functions as those described in the previously described embodiments are denoted by the same reference numerals. Hereafter, descriptions will be omitted except for changes or additions.

[0068] In the first embodiment, the shape (width) of the gate electrode 4 was changed to vary the thickness of portion 5a of the insulating film 5. In contrast, in the second embodiment, as shown in Figures 7A and 7B, the width of the gate electrode 4 is constant, and instead the thickness of portion 5a is changed by changing the shape of the semiconductor region 3. Specifically, as shown in Figure 7B, the high-density region H is recessed relative to the gate electrode 4.

[0069] In this embodiment, the region above the high-concentration region H is also recessed relative to the gate electrode 4. Region A2 is located below region A1. The region above region A1 has the same thickness (thickness T1) as region A1. The arrangement of regions A1 and A2 is the same as in Modification 1 of the first embodiment. Note that only the high-concentration region H may be recessed relative to the gate electrode 4 so that regions A1 and A2 are arranged in the same way as in the first embodiment.

[0070] Therefore, in the second embodiment, as in the first embodiment, the trade-off relationship between on-resistance Ron and threshold voltage Vth can be improved. Also, in this embodiment, since the base length is not changed, short-channel effects can be prevented.

[0071] <Manufacturing method for semiconductor devices> Next, an example of a manufacturing method for the semiconductor device 1A according to the second embodiment will be described with reference to Figures 8A to 8E. Figures 8A to 8E are cross-sectional views illustrating the manufacturing process for the semiconductor device 1A. Here, the process of creating the gate insulating film 5 will be explained in detail, and other processes will be omitted or simplified as appropriate.

[0072] First, as shown in Figure 8A, a trench T is provided in the drift region 32 formed on the semiconductor wafer, and a gate insulating film 5 is placed inside the trench T. The gate insulating film 5 is made of, for example, silicon oxide. In this embodiment, an FP electrode 6 is embedded inside the gate insulating film 5, but it is not necessary to provide the FP electrode 6.

[0073] Next, as shown in Figure 8B, ion implantation damage is inflicted on the upper part of the trench T by ion implanting, for example, argon. This creates the damaged area D.

[0074] Next, as shown in Figure 8C, the inside of the trench T is thermally oxidized. At this time, the damaged area D oxidizes faster and is oxidized more deeply. This process determines the final shape of portion 5a. As a result, in a subsequent process, by forming the base region 33 so that the high-concentration region H is adjacent to the area of ​​portion 5a with a large thickness, the high-concentration region H can be set back relative to the gate electrode 4.

[0075] Next, as shown in Figure 8D, a gate electrode 4 is formed in the trench T. The gate electrode 4 is formed, for example, by depositing a conductive material such as polysilicon to fill the trench T, and then etching back the excess conductive material.

[0076] Subsequently, the base region 33, source region 35, gate insulating film 5, contact region 34, barrier metal 7, source electrode 8, drain region 31, and drain electrode 2 are formed in the same manner as in the manufacturing method of the semiconductor device 1 according to the first embodiment.

[0077] Through the above process, the semiconductor device 1A according to the first embodiment is manufactured. Note that the above description is merely one example of a method for manufacturing the semiconductor device 1, and the semiconductor device 1A can also be manufactured by other methods. For example, after thermal oxidation of the inner wall of the trench, the trench may be vertically excavated using RIE or the like, and the inner wall of the trench may be thermally oxidized again. As a result, the oxide film (insulating film) becomes thicker in the portion that has been thermally oxidized twice (upper part of the trench) compared to the portion that has been thermally oxidized once (lower part of the trench). Therefore, in a later step, the base region 33 (including the high-concentration region H) adjacent to the portion that has been thermally oxidized twice can be recessed relative to the gate electrode 4.

[0078] (Third embodiment) Next, the semiconductor device 1B according to the third embodiment will be described with reference to Figures 9A and 9B. Figure 9A is a cross-sectional view of the semiconductor device 1B according to the third embodiment. Figure 9B is an enlarged view of area A shown in Figure 9A. In Figures 9A and 9B, elements with the same names or functions as those described in the previously described embodiments are denoted by the same reference numerals. Hereafter, descriptions will be omitted except for changes or additions.

[0079] In the first and second embodiments, the thickness of portion 5a of the insulating film 5 changed discontinuously. That is, the thickness changed discontinuously at the boundary between region A1 and region A2. Also, the thickness T1 was constant within region A1, and the thickness T2 was constant within region A2. In this embodiment, the thickness of the gate insulating film 5 changes continuously. That is, the thickness changes continuously at the boundary between region A1 and region A2, and the thickness is not constant within region A1 and region A2.

[0080] In this embodiment, as shown in Figure 9A, a gate trench GT having a bowing-shaped cross-section is provided. The gate trench GT extends from the source region 35 through the base region 34 to the drift region 32. The gate insulating film 5 fills the gate trench GT. The gate electrode 4 is positioned within the gate insulating film 5. The gate electrode 4 has a constant width (size in the Y-axis direction). Thus, in this third embodiment, the thickness (width) of the gate electrode 4 is constant, and because the gate trench GT has a bowing-shaped cross-section, the thickness of portion 5a changes continuously, as shown in Figure 9B.

[0081] As in this embodiment, even if the thickness of portion 5a of the insulating film 5 changes continuously, the thickness of region A1 in contact with the high-concentration region H is greater than the thickness of region A2 in contact with the low-concentration region L, thus improving the trade-off relationship between on-resistance Ron and threshold voltage Vth. Furthermore, in this embodiment as well, the base length is not changed, thus preventing short-channel effects.

[0082] Note that thicknesses T1 and T2 may be the thickness of the thickest parts of regions A1 and A2, respectively, or they may be the average thickness.

[0083] In the first and second embodiments, separate processes are required to discontinuously change the thickness of portion 5a, that is, to form region A1 and region A2. Therefore, the manufacturing process involves a relatively large number of steps. In contrast, in the third embodiment, by utilizing a bowing-shaped gate trench GT, the thickness of portion 5a of the insulating film 5 can be continuously changed. Therefore, region A1, which is in contact with the high-concentration region H, and region A2, which is in contact with the low-concentration region L, can be formed in a single process. This reduces the number of manufacturing steps for the semiconductor device 1B, thereby lowering costs.

[0084] <Manufacturing method for semiconductor devices> An example of a manufacturing method for semiconductor device 1B will be described with reference to Figures 10A to 10F. Figures 10A to 10F are cross-sectional view diagrams illustrating the manufacturing process for semiconductor device 1B. Here, the manufacturing process for the gate insulating film 5 will be explained in detail, and other processes will be omitted or simplified as appropriate.

[0085] First, as shown in Figure 10A, a gate trench GT having a bowing-shaped cross-section is provided in the drift region 32 formed on the semiconductor wafer. When etching the drift region 32, for example by RIE, the gate trench GT having a bowing-shaped cross-section can be formed with high reproducibility by adjusting various conditions such as the gas flow rate.

[0086] Next, as shown in Figure 10B, an insulating material is deposited on the inner wall of the gate trench GT and the drift region 32 by a method such as PVD or CVD to form a gate insulating film 5.

[0087] Next, as shown in Figure 10C, a portion of the gate insulating film 5 is removed by anisotropic etching such as RIE. At this time, the gate insulating film 5 is removed except for the portion that has a wider cross-sectional area than the opening of the gate trench GT when viewed in the thickness direction (Z-axis direction) of the drift region 32. As a result, the thickness of portion 5a changes continuously because the remaining gate insulating film 5 has an arc-shaped cross-section. Consequently, when the base region 33 is formed in a later step, the region A1 in contact with the high-concentration region H and the region A2 in contact with the low-concentration region L will have different thicknesses.

[0088] Next, as shown in Figure 10D, insulating material is deposited on the inner wall of the gate trench GT, on the gate insulating film 5, and on the drift region 32 by a method such as PVD or CVD, thereby thickening the gate insulating film 5. This forms the recess RE2.

[0089] Next, as shown in Figure 10E, a gate electrode 4 is formed in the recess RE2. The gate electrode 4 is formed, for example, by laminating a conductive material such as polysilicon to fill the recess RE2, and then etching back the excess conductive material.

[0090] Subsequently, the base region 33, source region 35, gate insulating film 5, contact region 34, barrier metal 7, source electrode 8, drain region 31, and drain electrode 2 are formed in the same manner as in the manufacturing method of the semiconductor device 1 according to the first embodiment.

[0091] The semiconductor device 1B according to the third embodiment is manufactured through the above process. Note that the above description is merely one example of a method for manufacturing the semiconductor device 1B, and it is possible to manufacture the semiconductor device 1B by other methods as well.

[0092] According to this manufacturing method, an insulating film 5 including regions A1 and A2 can be formed in a single step, thus simplifying the manufacturing process and reducing manufacturing costs.

[0093] (Fourth Embodiment) Next, the semiconductor device 1C according to the fourth embodiment will be described with reference to Figures 11A and 11B. Figure 11A is a cross-sectional view of the semiconductor device 1C. Figure 11B is an enlarged view of area A shown in Figure 11A. In Figures 11A and 11B, elements with the same names or functions as those described in the previously described embodiments are denoted by the same reference numerals. Hereafter, descriptions will be omitted except for changes or additions.

[0094] In the first, second, and third embodiments, the trade-off relationship between on-resistance Ron and threshold voltage Vth was improved by changing the thickness of the gate insulating film 5. In contrast, in this embodiment, the trade-off relationship between on-resistance Ron and threshold voltage Vth is improved by replacing a part of portion 5a with a low dielectric constant portion 51 having a lower dielectric constant than the gate insulating film 5.

[0095] As shown in Figure 11B, the gate insulating film 5 includes a low dielectric constant portion 51 within region A1. In other words, the low dielectric constant portion 51 is located in part or all of region A1. The dielectric constant of the low dielectric constant portion 51 is lower than that of the gate insulating film 5. As a result, region A2 has a higher dielectric constant than region A1, and the same effect as if region A2 were thinner than region A1 can be obtained without changing the thickness of regions A1 and A2. Therefore, in this embodiment, the width of the gate electrode 4 is constant, and the high-density region H is not recessed relative to the gate electrode 4.

[0096] The low dielectric constant portion 51 is made of a low-k material such as fluorinated silicon oxide (SiOF). When the gate insulating film 5 is made of silicon oxide, for example, the low dielectric constant portion 51 made of SiOF is formed by adding fluorine to a part of the gate insulating film 5.

[0097] As described above, in the fourth embodiment, by arranging an insulating film portion 51 with a lower dielectric constant than the gate insulating film 5 in part or all of the region A1 that is in contact with the high-concentration region H of the base region 33, the trade-off relationship between the on-resistance Ron and the threshold voltage Vth can be improved without changing the physical thickness of portion 5a. Furthermore, in this embodiment as well, the base length is not changed, so the short-channel effect can be prevented.

[0098] While embodiments of the present invention have been described, these embodiments and examples are presented as examples only and are not intended to limit the scope of the invention. These embodiments and examples can be carried out in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and examples and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0099] 1, 1A, 1B, 1C Semiconductor devices 2 Drain electrodes 3. Semiconductor Domain 4 gate 4a, 4b partial electrodes 5 Gate insulating film 5a part 51 Low dielectric constant part 6. Field plate electrodes (FP electrodes) 7 Barrier Metal 8 Source electrodes 9 Drain electrode 31 Drain area 32 Drift region 33 Base area 33a Boundary area 34 Contact Area 35 Source Area Area A A1, A2 area D Damaged area T Trench GT Gate Trench H High concentration area L Low concentration area RE1 recess RE2 recess

Claims

1. First electrode and, A first semiconductor region of a first conductivity type is positioned above the first electrode, A second semiconductor region of a second conductivity type is disposed on the first semiconductor region, A third semiconductor region of a first conductivity type is disposed on the second semiconductor region, An insulating film disposed in the first semiconductor region, the second semiconductor region, and the third semiconductor region, A second electrode is disposed in the insulating film so as to be adjacent to the second semiconductor region via the insulating film, A third electrode electrically connected to the aforementioned third semiconductor region, Equipped with, The second semiconductor region includes a boundary region that is in contact with the insulating film and facing the second electrode. The boundary region of the second semiconductor region has a high-concentration region including a peak in the impurity concentration of the second conductivity type. The insulating film includes a first region in contact with the high-concentration region of the boundary region, a second region positioned above the first region and in contact with a low-concentration region of the boundary region that is different from the high-concentration region, and a third region positioned below the first region and in contact with a low-concentration region of the boundary region that is different from the high-concentration region. The thickness of the second region is smaller than the thickness of the first region and smaller than the thickness of the third region. Semiconductor equipment.

2. The high-concentration region is a region where the impurity concentration is equal to or greater than a predetermined percentage of the value at the peak. The semiconductor device according to claim 1.

3. The first electrode and A first semiconductor region of a first conductivity type is positioned above the first electrode, A second semiconductor region of a second conductivity type is disposed on the first semiconductor region, A third semiconductor region of a first conductivity type is disposed on the second semiconductor region, An insulating film disposed in the first semiconductor region, the second semiconductor region, and the third semiconductor region, A second electrode is disposed in the insulating film so as to be adjacent to the second semiconductor region via the insulating film, A third electrode electrically connected to the aforementioned third semiconductor region, Equipped with, The second semiconductor region includes a boundary region that is in contact with the insulating film and facing the second electrode. The boundary region of the second semiconductor region has a high-concentration region including a peak in the impurity concentration of the second conductivity type. The insulating film includes a first region in contact with the high-concentration region of the boundary region, and a second region in contact with a low-concentration region of the boundary region that is different from the high-concentration region. The thickness of the second region is smaller than the thickness of the first region. The second electrode has a first partial electrode and a second partial electrode that are spaced apart from each other. The first partial electrode is adjacent to the high-concentration region via the first region, and the second partial electrode is adjacent to the low-concentration region via the second region. Semiconductor equipment.

4. The width of the second electrode is constant, The high-concentration region is recessed relative to the second electrode. The semiconductor device according to claim 1.

5. The first electrode and A first semiconductor region of a first conductivity type is positioned above the first electrode, A second semiconductor region of a second conductivity type is disposed on the first semiconductor region, A third semiconductor region of a first conductivity type is disposed on the second semiconductor region, An insulating film disposed in the first semiconductor region, the second semiconductor region, and the third semiconductor region, A second electrode is disposed in the insulating film so as to be adjacent to the second semiconductor region via the insulating film, A third electrode electrically connected to the aforementioned third semiconductor region, Equipped with, The second semiconductor region includes a boundary region that is in contact with the insulating film and facing the second electrode. The boundary region of the second semiconductor region has a high-concentration region including a peak in the impurity concentration of the second conductivity type. The insulating film includes a first region in contact with the high-concentration region of the boundary region, and a second region in contact with a low-concentration region of the boundary region that is different from the high-concentration region. The thickness of the second region is smaller than the thickness of the first region. The width of the second electrode is constant, The insulating film fills trenches having a bowing-shaped cross-section. Semiconductor equipment.

6. The present invention further comprises a fourth semiconductor region of a first conductivity type disposed between the first electrode and the first semiconductor region, The semiconductor device is configured as a vertical MOSFET. A semiconductor device according to any one of claims 1 to 5.

7. The insulating film further comprises a fourth electrode positioned below the second electrode and electrically connected to the third electrode. The semiconductor device according to claim 6.

8. The present invention further comprises a fifth semiconductor region of a second conductivity type disposed between the first electrode and the first semiconductor region, The semiconductor device is configured as an insulated-gate bipolar transistor. A semiconductor device according to any one of claims 1 to 5.

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