Voltage regulation module design for underfill use

Abstract

A voltage regulation module design is provided. In one aspect, the voltage regulation module (VRM) includes a first layer configured to output a regulated voltage based on a step-down voltage, a second layer stacked with the first layer, and a plurality of contacts, such as a ball grid array (BGA), on the first layer. The second layer includes a plurality of active components configured to provide the step-down voltage to the first layer. The first and second layers have overlapping recesses, the recess of the first layer having a larger footprint than the recess of the second layer. The plurality of VRMs can be arranged to form an opening including a counterbore. A fastener, such as a bolt, can be disposed in the opening. The first layer can have a larger clearance from a fastener disposed in the opening than the second layer.

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims the benefit of U.S. Provisional Patent Application No. 63 / 140,547, filed on January 22, 2021, entitled "VOLTAGE REGULATING MODULE DESIGN FOR UNDERFILL", the disclosure of which is hereby incorporated by reference in its entirety for all purposes.

[0002] This disclosure generally relates to electronic devices, and more specifically to a voltage regulating module (VRM).

Background Art

[0003] A multi - chip module can include a plurality of application - specific integrated circuit (ASIC) devices and a plurality of VRMs configured to supply power to each of the ASICs. A given VRM can be electrically coupled to one of the ASIC devices via a ball grid array (BGA). To protect the BGA, underfill can be used to encapsulate the BGA.

Summary of the Invention

Means for Solving the Problems

[0004] In one embodiment, a voltage regulation module (VRM) is provided, comprising: a first layer having a first recess, configured to output a regulated voltage based on a step-down voltage; a second layer stacked with the first layer, the second layer comprising a plurality of active components configured to receive a voltage, generate a step-down voltage based on the voltage, and provide the step-down voltage to the first layer, the second layer having a second recess that overlaps with the first recess, the first recess having a larger mounting area than the second recess; and a plurality of contacts located on the first layer and configured to output a regulated voltage.

[0005] Multiple contacts can include a ball grid array.

[0006] Ball grid arrays can be encapsulated with underfill.

[0007] The VRM may further include a third layer stacked with the first and second layers, and the third layer may include multiple active components.

[0008] The third layer may have a third recess having an area that is substantially the same as the area of ​​the second recess.

[0009] The first layer may comprise a plurality of discrete components configured to multiply the step-down voltage current.

[0010] Individual components may include passive circuit elements.

[0011] In another embodiment, a multichip module is provided, comprising a plurality of integrated circuit (IC) dies and a voltage regulation module (VRM) array, wherein the VRM array is arranged such that openings include counterbore holes between groups of adjacent VRMs in the VRM array, and each VRM of the VRM is stacked with each IC die of the plurality of IC dies, and fasteners are positioned in the openings between groups of adjacent VRMs of the VRM array.

[0012] Each VRM in the VRM array may contain a ball grid array enclosed in underfill.

[0013] Each VRM in the VRM group may have a first layer and a second layer, where the gap from the fastener is greater in the first layer than in the second layer, the first layer includes passive components and the second layer includes active components.

[0014] In yet another embodiment, the multichip module comprises a plurality of integrated circuit (IC) dies, a plurality of voltage regulation modules (VRMs), each VRM of the VRM being stacked with each of the plurality of IC dies, and a plurality of fasteners arranged in the openings between the VRMs of the plurality of VRMs, wherein the first VRM of the plurality of VRMs is a first layer configured to output a regulated voltage based on a step-down voltage, the first layer having a first recess, and a second layer stacked with the first layer, the second layer receiving a voltage and stepping down the voltage to the first layer. The device comprises a plurality of active components configured to supply, the second layer having a second recess that overlaps with the first recess, the gap from the first fastener of the plurality of fasteners being larger in the first layer than in the second layer, the first fastener being positioned in the first opening of the opening, the first opening being at least partially defined by the first and second recesses, and a plurality of contacts located on the first layer and electrically connected to the first IC die of the plurality of IC dies stacked with the first VRM, the contacts configured to provide an adjustment voltage to the first IC die.

[0015] Multiple contacts can include a ball grid array.

[0016] Ball grid arrays can be encapsulated with underfill.

[0017] The gaps in the first layer may be configured to prevent or stop the underfill from filling the first recess.

[0018] The underfill may form a fillet extending from the edge of the first layer toward the fastener.

[0019] The distance that the fillet extends from the edge of the first layer toward the fastener can be smaller than the distance between the gap of the first layer and the gap of the second layer.

[0020] The first layer can include a plurality of passive circuit elements configured to multiply the current of the step-down voltage.

[0021] The fastener can include a bolt.

[0022] [[ID=|18]]The multi-chip module can further include a cooling system configured to actively cool the VRM.

[0023] A system on wafer (SoW) can include an IC die.

[0024] The multi-chip module can further include a heat dissipation structure formed on a side surface of the SoW facing the first layer and the second layer.

Brief Description of the Drawings

[0025] [Figure 1] It is a side cross-sectional block diagram showing an embodiment of a multi-chip module configured according to an aspect of the present disclosure.

[0026] [Figure 2A] It is a diagram showing a processing system according to an aspect of the present disclosure. [Figure 2B] It is a diagram showing a processing system according to an aspect of the present disclosure.

[0027] [Figure 3] It is a partial cross-sectional view of the system on wafer module of FIGS. 2A and 2B.

[0028] [Figure 4A] This is a partial plan view of a VRM including a recess for a bolt according to an aspect of the present disclosure. [Figure 4B] This is a partial plan view of a VRM including a recess for a bolt according to an aspect of the present disclosure.

[0029] [Figure 4C] This is a plan view of a plurality of VRMs arranged in an array according to an aspect of the present disclosure.

[0030] [Figure 5A] This is a cross-sectional view of a VRM design for underfill according to an aspect of this disclosure. [Figure 5B] This is a cross-sectional view of a VRM design for underfill according to an aspect of this disclosure.

[0031] [Figure 6] This is a cross-sectional view of a VRM attached to an ASIC according to an aspect of the present disclosure. [Modes for carrying out the invention]

[0032] The following descriptions of embodiments for carrying out the invention present various descriptions of specific embodiments. However, the technological innovations described herein can be carried out in numerous different ways, for example, as defined and encompassed by the claims. In this description, similar reference numbers and / or terms refer to drawings where identical or functionally similar elements may be shown. It will be understood that the elements shown in the drawings are not necessarily drawn to scale. Furthermore, it will be understood that a particular embodiment may include more elements and / or subsets of elements shown in the drawings than those shown. In addition, some embodiments may incorporate any suitable combination of features from two or more drawings.

[0033] In certain embodiments, the mechanical architecture of a system on a substrate includes a high-density mounting of voltage regulation modules (VRMs) on the substrate, in addition to multiple application-specific integrated circuit (ASIC) devices. There are several design trade-offs and / or challenges that affect the size, layout, density, and spacing of the VRMs on the substrate. One particular challenge concerns allocating space within the VRM's inner layers for active and passive components, stepped bolts for fastening the VRM to the substrate, and underfill. This disclosure provides technical solutions to such challenges.

[0034] Aspects of this disclosure relate to a VRM design having a recessed area on the bottom ball grid array (BGA) mounting layer of the VRM. A particular advantage of this design is that it helps save physical space within the VRM layout so that the VRM can meet underfill and bolt clearance specifications, which are critical factors enabling the backend assembly process. Furthermore, aspects of this disclosure can also maintain the specifications of the VRM internal layer space, particularly for active components, and the overall VRM mounting density on the substrate is not significantly affected.

[0035] Previous-generation BGA-type VRMs lack the flexibility to enable high mounting density. Manufacturing challenges are numerous, ranging from tool alignment to true position tolerances of drilled holes. In contrast, the design according to the embodiments of this disclosure is unique and has not been used to solve the aforementioned problems.

[0036] Aspects of this disclosure relate to a VRM architecture that can be integrated into a product that includes a backend assembly having a relatively high mounting density. The architecture can be integrated into a product where components are placed in close proximity. In certain embodiments, the VRM can be formed from a material that can withstand machining to achieve dimensional stability. Non-limiting examples of materials that can be used for the VRM include printed circuit boards (PCBs), organic substrates, and / or PCBs or organic substrates overmolded with engineering mold compounds. The VRM architecture may include recessed counterbore mechanisms that can improve component placement and / or enable backend assembly. The mechanical architecture of the VRM is one aspect that can affect power delivery for enhancing and / or optimizing ASIC performance. For example, a low mounting density of the VRM can significantly degrade ASIC performance.

[0037] A VRM can include multiple layers, including at least a first and second layer. One or more of these layers can include active components such as transistors. Active components can step down the received voltage and output the stepped-down voltage. Another layer of the VRM can include passive components such as capacitors and / or inductors. This layer can output a regulated voltage to electrical contacts on it, such as a ball grid array. The regulated voltage is based on the stepped-down voltage.

[0038] A layer containing passive components has recesses that overlap with the recesses of one or more layers containing active components. The recesses of the layers containing passive components may have a larger mounting area than the corresponding recesses of the layers containing active components. Thus, the mounting area of ​​the recesses of the layers containing passive components is greater than the mounting area of ​​the recesses of the layers containing active components, over which the components are located. The recesses of the layers containing passive components can provide a larger clearance from fasteners, such as bolts, placed in openings at least partially defined by the recesses of the layers of the VRM. An array of such VRMs can be included in a multi-chip module. For example, the VRMs can be stacked with each ASIC and supply regulating voltages to each ASIC. The openings for fasteners, at least partially defined by the corners of the VRMs and the recesses between adjacent VRMs, can each form a counterbore mechanism. For example, the recesses at the corners of four VRMs can define an opening. As another example, the corner recesses of four VRMs and one or more intervening structures can define an opening. A layer of VRM having a passive component with a recess having a larger fastener gap can at least partially define a counterbore mechanism. The counterbore mechanism allows for dense mounting of the VRM without sacrificing the area of ​​one or more VRM layers containing the active component.

[0039] Embodiments of this disclosure relate to VRM designs for multichip modules. In some embodiments, the multichip module can be mounted on a system-on-wafer (SoW) redistribution layer or an integrated fan-out (InFO) package. In one embodiment, the multichip module includes a modular direct clamp structure that allows mounting of multiple ICs or sockets mounted on and mechanically coupled to a heat dissipation structure for thermal cooling of integrated circuit (IC) dies within the multichip module. In one embodiment, the IC dies or sockets are mounted on the side of the InFO substrate away from the heat dissipation structure.

[0040] For mounting multi-chip modules onto InFO substrates and / or heat dissipation structures, frames configured to hold multiple chips can be used. For example, the frame can be sized and shaped to hold 2, 4, 6, 8, 10, 12, or more IC dies, as will be described in more detail below. In yet another embodiment, 16, 25, or 36 IC dies may be supported by the frame. In one embodiment, the frame is rectangular or square, enclosing each side of the IC dies and providing a stable mounting system or means for the multi-chip module. Each corner of the IC dies in the module may have a through-retaining portion within the frame to allow mounting pins, screws, or other fasteners to attach the frame to the substrate and cooling system. As shown in the figure, one or more corner clamps can be used to secure the multi-chip module frame to the rest of the package.

[0041] Figure 1 is a side cross-sectional view showing a processing system 100 configured according to an aspect of the present disclosure. The processing system 100 can be a multi-chip module. The processing system 100 in Figure 1 includes a plurality of high-power VRMs 102 mounted on a substrate structure 104. The VRMs 102 are supplied by a direct current (DC) supply voltage 108, for example, 40 volts, 48 ​​volts, or another relatively high voltage, and provide a regulated voltage to each of the plurality of IC dies 106, respectively. In some embodiments, each of the plurality of VRMs 102 generates an output of about 0.8 volts, supplying power of about 600 watts or more to each of the plurality of IC dies 106. However, the aspects of the present disclosure are not limited thereto, and the VRMs 102 can generate outputs in the range of about 0.6 to 1.3 volts, in the range of 0.8 to 1.1 volts, or within another suitable voltage range depending on the embodiment. Thus, in certain embodiments, each of the plurality of VRMs 102 generates a current of more than about 100 amperes to the plurality of IC dies 106. For specific applications, the VRM can supply currents ranging from 400 amperes to 800 amperes to multiple IC dies 106.

[0042] Figures 2A and 2B show a processing system 200 according to an aspect of the present disclosure. Figure 2A is an exploded view of the processing system 200. Figure 2B is an assembled view of the processing system 200. Features of the present disclosure can be implemented in the processing system 200 and / or any other suitable processing system. The processing system 200 can have a high computational density and can dissipate the heat generated by the processing system 200. The processing system 200 can perform trillions of operations per second in a particular application. The processing system 200 can be used in and / or specifically configured for high-performance computing and / or computationally intensive applications such as neural network training and / or processing, machine learning, and artificial intelligence. In one embodiment, the processing system 200 can be used for neural network training. The processing system 200 can provide redundancy. In some applications, the processing system 200 can be used for neural network training to generate data used in an autopilot system for a vehicle (e.g., an automobile).

[0043] As shown in Figure 2A, the processing system 200 includes a heat dissipation structure 202, a SoW 204, an edge reinforcement 206, a VRM 208, a cooling system 210, and a control broad 212. Figure 2B shows the processing system 200 upside down compared to Figure 2A. In Figure 2B, the processing system 200 is shown without the control board 212.

[0044] The heat dissipation structure 202 can dissipate heat from the SoW 204. The heat dissipation structure 202 may include a heat spreader. Such a heat spreader may include a metal plate. Alternatively or additionally, the heat dissipation structure may include a heat sink. The heat dissipation structure 202 may include metals such as copper and / or aluminum. The heat dissipation structure 202 may, alternatively or additionally, include any other suitable material having the desired heat dissipation properties. In certain applications, the heat dissipation structure 202 may include a copper heat spreader and an aluminum heat sink. A thermal interface material may be included between the heat dissipation structure 202 and the SoW 204 to reduce and / or minimize heat transfer resistance.

[0045] SoW204 can include an array of IC dies. The IC dies can be embedded in the molding material. SoW204 can have a high computation density. The IC dies may be semiconductor dies such as silicon dies. The array of IC dies can include any appropriate number of IC dies. For example, the array of IC dies can include 16 IC dies, 25 IC dies, 36 IC dies, or 49 IC dies. SoW204 can be, for example, an InFO wafer. An InFO wafer can include multiple routing layers on the array of IC dies. For example, an InFO wafer can include 4, 5, 6, 8, or 10 routing layers in a particular application. The routing layers of the InFO wafer can provide signal connections between IC dies and / or to external components. SoW204 can have a relatively large diameter, for example, in the range of 10 to 15 inches. As an example, SoW204 can have a diameter of 12 inches.

[0046] The edge reinforcement member 206 can contribute to the structural integrity of the processing system 200. The edge reinforcement member 206 can support the VRM 208 and hold the VRM 208 in place.

[0047] The VRM208 can be arranged so that each VRM is stacked with the IC die of the SoW204. In the processing system 200, there is a high-density implementation of the VRM208. Therefore, the VRM208 can consume a considerable amount of power. The VRM208 is configured to receive a direct current (DC) supply voltage and supply a lower output voltage to the corresponding IC die of the SoW204.

[0048] The cooling system 210 can provide active cooling to the VRM 208. The cooling system 210 can provide active cooling to the control board 212. The cooling system 210 may include a metal having channels for heat transfer fluid to flow through. As an example, the cooling system 210 may include a machined metal such as copper. The cooling system 210 may include a brazed fin array for high cooling efficiency. In the assembled processing system 200, the cooling system 210 can be bolted to the heat dissipation structure 202. This can provide structural support for the SoW 204 and / or reduce the possibility of failure of the SoW 204. A thermal interface material may be included between the cooling system 210 and the control board 212 to reduce and / or minimize heat transfer resistance.

[0049] The control board 212 may include electrical components. The electronics of the control board 212 may provide control signals for the VRM208. The control board 212 may include electronics for controlling the operation of the SoW204.

[0050] Figure 3 is a partial cross-sectional view of the SoW module 200 shown in Figures 2A and 2B. Referring to Figure 3, the SoW module 200 includes a heat dissipation structure 202, a SoW 204, a VRM 208, and a cooling system 210. The SoW module 200 further includes a thermal interface structure 214 between the VRM 208 and the cooling system 210, and a number of bolts 216 configured to fasten the VRM 208 in place.

[0051] Figures 4A and 4B show partial plan views of a VRM 302 including a recess 308 for a bolt 306 according to an aspect of the present disclosure. Figure 4C shows a plan view of a plurality of VRM 302 arranged in an array 300 according to an aspect of the present disclosure. As shown in Figure 4C, four adjacent VRM 302 recesses 308 can form a bolt hole 310 in which a bolt can be placed. The bolt hole 310 is at least partially defined by the four VRM 302 recesses 308 in Figure 4C. The bolt hole 310 is an example of an opening at least partially defined by the VRM 302 recesses 308. Such an opening can be formed by the space between the VRM 302 recesses 308. Such an opening can be formed by the space between one or more intervening structures within the VRM 302 recesses 308.

[0052] Referring to Figures 4A and 4B, the recess 308 defines a keep-out zone to provide clearance for inserting a bolt 306 adjacent to one or more VRMs 302 and securing the VRMs 302 in place. For example, the keep-out zone may be defined by the minimum distance or gap D between the edge of the VRM 302 and the bolt 306. As shown, the bolt 306 can be a stepped bolt. Any other suitable fastener can be used instead of the bolt.

[0053] As shown in Figure 4A, the BGA304 is provided at one end of the VRM302 to provide an electrical connection to the SoW204 (see Figures 2A to 3). As shown, the BGA304 may be spaced at a minimum distance or gap E from the edge of the VRM302, and the pitch F between balls in the BGA304 in the diagonal direction may be defined. As described above, the BGA304 may be fitted with an underfill configured to enclose the BGA304 when it is installed on the SoW204, provide structural support to the BGA304, and thereby prevent damage to the BGA304. In one embodiment, the gap D may be about 600 μm, the gap E may be about 500 μm, and the pitch F may be about 550 μm. However, in other embodiments, each of these distances may be larger or smaller.

[0054] Several competing design considerations may exist that could affect the size of the keep-out zone, which is defined by the gap D between the bolt 306 and the edge of the VRM 302. For example, to protect the ball of the BGA 304 adjacent to the recess 308, underfill may occupy a certain amount of space between the BGA 304 and the bolt 306. In some embodiments, the underfill may include a molding material or polymer that is applied in liquid form and solidifies to enclose the BGA 304. If there is insufficient space (e.g., a keep-out zone or gap D) between the edge of the VRM 302 and the bolt 306, the underfill may clog the recess 308, which may make it difficult or impossible to insert the bolt 306 through the bolt hole 310 formed by one or more recesses 308. In certain embodiments, it may be specified to provide a keep-out zone defined by a gap D of about 1.1 mm. The gap D can be 1.1 mm + / - about 3%. The keep-out zone may be larger or smaller depending on the implementation.

[0055] One option for increasing the size of the keep-out zone is to provide additional spacing between adjacent VRM302s. However, this may have the drawback of increasing the overall area occupied by the VRM302s. In certain embodiments, the area in which VRM302s can be placed (e.g., within the edge reinforcement 206) is fixed, and therefore the spacing between VRM302s cannot be increased without reducing the size of individual VRM302s or the number of VRM302s that can be included in the multi-chip module. For example, as shown in Figure 4C, a certain multi-chip module may include an array of ASICs, each coupled to a VRM302. As illustrated, Figure 4C has 25 ASICs and 25 VRMs. To maintain the size of the VRM302s and provide a sufficiently large keep-out zone so that underfill does not clog the recess 308, the number of ASICs and VRM302s can be reduced to 16 in a 4x4 array. This reduction significantly impacts the overall performance of the multi-chip module.

[0056] Referring to Figure 4B, the size of the keep-out zone can be increased by removing the three rows of balls closest to the recess 308 from the BGA304 in Figure 4A, thereby increasing the gap D. However, reducing the size of individual VRM302s or the number of VRM302s without sacrificing some of the functionality of the VRM302 may be difficult or impractical. For example, the components of the VRM302 may be packed so tightly that the components do not all fit within the reduced area of ​​the VRM302 in order to provide a keep-out zone large enough to avoid clogging of the recess 308 by underfill. For example, reducing the size of VRM302s or the number of VRM302s may reduce the amount of power that can be supplied to the ASIC, which may lead to a decrease in ASIC performance. In some embodiments, the gap D may be 1.1 mm ± approximately 3%, and the gap E may be approximately 550 microns ± approximately 20%.

[0057] Aspects of this disclosure relate to a design for VRM 302 that can prevent or substantially prevent clogging of recesses 308 by underfill without increasing the spacing between VRM 302 and without sacrificing the functionality of VRM 302. Figures 5A and 5B show cross-sectional views of a VRM 400 design for underfill according to an aspect of this disclosure. The layer of VRM 400 closest to the BGA can have larger recesses than the active layer of VRM 400. Thus, the BGA can be protected by sufficient gaps in the layer closest to the BGA, and the active layer can maintain a higher density with smaller recesses than the layer closest to the BGA.

[0058] Referring to Figure 5A, the VRM400 includes a first layer 402, a second layer 404, a third layer 406, and a BGA408. The VRM400 further includes a plurality of recesses 412 formed at the corners of the VRM400. Multiple adjacent recesses 412 of the VRM400 can form bolt holes, for example, as shown in Figure 4C. The second layer 404 and the third layer 406 may each include active components (e.g., silicon components such as transistors) configured to step down and / or repeat the input voltage to a voltage usable by the SoW204. Thus, the second layer 404 and the third layer 406 can be called active layers. In certain embodiments, at least a portion of the second layer 404 and / or the third layer 406 can be implemented by stepping down the input voltage using an ASIC device, which imposes limitations on the form factor of these layers 404 and 406. In particular, the use of ASIC devices may be limited to specific mounting areas for the second layer 404 and the third layer 406.

[0059] In one example, the VRM400 can receive an input voltage of 48V and provide an output of 0.8V or 1.1V to the SoW204. Depending on the implementation, any other suitable input and / or output voltages can be used. Thus, the second layer 404 and the third layer 406 may be configured to function as step-down transformers. In some embodiments, the second layer 404 and the third layer 406 may include one or more current dividers and / or one or more current multipliers configured to step down the input voltage received by the VRM400.

[0060] The first layer 402 may include multiple current multiplier components, which may be discrete components rather than active components included in the second layer 404 and the third layer 406. Discrete components can be passive circuit elements. For example, discrete components in the first layer 402 may include one or more resistors, one or more capacitors, one or more inductors, or any suitable combination thereof. Discrete components offer more flexibility in placement than active components, thereby allowing for greater flexibility in the layout design of components in the first layer 402 compared to the second layer 404 and the third layer 406. The area of ​​the first layer 402 can be reduced by the specific placement of discrete components. Thus, the area of ​​the first layer 402 can be reduced without significantly affecting the functionality of the VRM 400.

[0061] Figure 5B shows an enlarged view of portion 410 near recess 412 of the VRM 400 in Figure 5A. Referring to Figure 5B, a step or notch 414 can be provided in recess 412 to increase the size of the keep-out zone around the bolts adjacent to the BGA 408 without reducing the size of the second layer 404 and the third layer 406, without adjusting the size of the second layer 404 and the third layer 406. The recess of the first layer 402 has a larger mounting area than the recesses of the second layer 404 and the third layer 406. The recess of the first layer 402 can provide a larger bolt clearance than the recesses of the second layer 404 and the third layer 406. Together, the notch 414 formed by the recess of the first layer 402, along with the recesses of the second layer 404 and the third layer 406 of the adjacent VRM 400 (see, for example, Figure 4C), can form a counterbore. Thus, an underfill (see, for example, the underfill 502 shown in Figure 6) can be provided to protect the BGA 408, and by increasing the size of the keep-out zone provided by the notch 414 of the first layer 402, it is possible to prevent the underfill from clogging the recess 412. Also, since the underfill is applied to protect the BGA 408 adjacent to the first layer 402, there is little or no risk of the underfill reaching these layers 404 and 406, so the sizes of the second layer 404 and the third layer 406 can be maintained. Therefore, in order to ensure that the performance of VRM400 and the density of the second layer 404 and the third layer 406 are maintained, the size of the second layer 404 and the third layer 406 having active components can be maintained.

[0062] The underfill may form a fillet extending from the edge of the first layer 402 toward the bolt. In some embodiments, the distance the fillet extends from the edge of the first layer 402 toward the center of the bolt hole formed by the recess 412 and a similar recess in the adjacent VRM is less than the distance between the gap in the recess 412 in the second layer 404 and the third layer 406 and the gap in the recess 412 in the first layer 402. That is, the fillet does not need to extend toward the center of the bolt hole any further than the distance the second layer 404 and the third layer 406 extend toward the center of the bolt hole. However, in some other embodiments, the fillet may extend further toward the bolt than the second layer 404 and the third layer 406.

[0063] Figure 6 shows a cross-sectional view of a VRM400 mounted on an ASIC500 according to an aspect of the present disclosure. As shown in Figure 6, the VRM400 includes a BGA408 configured to provide a number of electrical connections between the VRM400 and the ASIC500. The BGA408 is enclosed by an underfill 502 that structurally supports and physically protects the BGA408. As shown in Figure 6, the underfill 502 forms a fillet that extends from the edge of the VRM400 along the ASIC500 toward the bolt holes formed by the recesses 412 at the corners of the VRM400. As described above, due to the presence of the notches 414, the fillet formed by the underfill 502 does not extend toward the center of the bolt holes as much as a similar VRM without the notches 414. conclusion

[0064] The foregoing disclosure is not intended to limit the disclosure to the exact form or specific field of use disclosed. Therefore, various alternative embodiments and / or modifications to the disclosure, whether expressly described or implied herein, are possible in light of the disclosure. While embodiments of the disclosure have been described in this manner, those skilled in the art will recognize that modifications to form and detail can be made without departing from the scope of the disclosure. Therefore, the disclosure is limited solely by the claims.

[0065] The above specification has described the disclosure with reference to specific embodiments. However, as those skilled in the art will understand, the various embodiments disclosed herein can be modified or implemented in various other ways without departing from the spirit and scope of the disclosure. Therefore, this description should be considered illustrative and is intended to teach those skilled in the art how to manufacture and use various embodiments of the disclosed ventilation assemblies. It should be understood that the forms of disclosure shown and described herein should be interpreted as representative embodiments. Equivalent elements, materials, processes, or steps may be substituted for those representatively illustrated and described herein. Furthermore, certain features of the disclosure can be utilized independently of the use of other features, all of which will be obvious to those skilled in the art after benefiting from this description of the disclosure. Expressions such as “including,” “comprising,” “incorporating,” “consisting of,” “have,” and “is” used to describe and claim the disclosure are intended to be interpreted in a non-exclusive manner, that is, allowing for the existence of items, components, or elements not expressly described. References to the singular form should be interpreted as also relating to the plural form.

[0066] Furthermore, the various embodiments disclosed herein should be interpreted in an illustrative and descriptive sense and not in any way as limiting the disclosure. All references to joining (e.g., mounting, fastening, joining, connection, etc.) are used solely to aid the reader's understanding of the disclosure and should not result in any limitation with respect to the location, orientation, or use of the systems and / or methods disclosed herein. Accordingly, where there is a reference to joining, it should be interpreted broadly. Furthermore, such references to joining do not necessarily mean that the two elements are directly connected to each other. In addition, all numerical terms, for example, but not limited to, “first,” “second,” “third,” “primary,” “secondary,” “main,” or any other common and / or numerical terms should also be taken solely as identifiers to aid the reader's understanding of the various elements, embodiments, variations, and / or modifications of the disclosure and should not result in any limitation with respect to the order or priority of any element, embodiment, variation, and / or modification to or compared with another element, embodiment, variation, and / or modification.

[0067] It should be understood that, depending on the specific application, one or more of the elements shown in the drawings / figures may also be implemented in a more separated or integrated manner, or in certain cases may be removed or disabled. (Note) [Configuration 1] A voltage regulation module (VRM), A first layer configured to output an adjustment voltage based on a step-down voltage, the first layer having a first recess, A second layer laminated with the first layer, the second layer comprising a plurality of active components configured to receive a voltage, generate the step-down voltage based on the voltage, and provide the step-down voltage to the first layer, wherein the second layer has a second recess that overlaps with the first recess, and the first recess has a larger mounting area than the second recess, A voltage regulation module (VRM) comprising a plurality of contacts located on the first layer and configured to output the adjustment voltage. [Configuration 2] The VRM according to configuration 1, wherein the plurality of contacts include a ball grid array. [Configuration 3] The VRM according to configuration 2, wherein the ball grid array is enclosed in underfill. [Structure 4] The VRM according to configuration 1, further comprising a third layer laminated with the first layer and the second layer, wherein the third layer comprises a plurality of active components. [Composition 5] The VRM according to configuration 4, wherein the third layer has a third recess having substantially the same area as the area of ​​the second recess. [Composition 6] The VRM according to configuration 1, wherein the first layer comprises a plurality of individual components configured to multiply the step-down voltage by the current. [Composition 7] The VRM according to configuration 6, wherein the aforementioned individual components include passive circuit elements. [Structure 8] It is a multi-chip module, Multiple integrated circuit (IC) dies, A voltage regulation module (VRM) array, wherein the VRM array is arranged such that openings include counterbore holes between adjacent groups of VRMs in the VRM array, and each VRM is stacked with each of the plurality of IC dies, A multichip module comprising: fasteners disposed in the openings between adjacent groups of VRMs in the VRM array. [Composition 9] The multi-chip module according to configuration 8, wherein each of the VRMs in the VRM array includes a ball grid array enclosed in underfill. [Configuration 10] The multichip module according to configuration 8, wherein each of the VRMs in the group of VRMs has a first layer and a second layer, the gap from the fastener is larger in the first layer than in the second layer, the first layer has passive components and the second layer has active components. [Composition 11] It is a multi-chip module, Multiple integrated circuit (IC) dies, Multiple voltage regulation modules (VRMs), wherein each VRM is stacked with each of the IC dies of the multiple IC dies, The system comprises a plurality of fasteners arranged in the openings between the VRMs of the plurality of VRMs, The first VRM among the aforementioned multiple VRMs, A first layer configured to output an adjustment voltage based on a step-down voltage, wherein the first layer has a first recess, A second layer laminated with the first layer, wherein the second layer comprises a plurality of active components configured to receive a voltage and supply the step-down voltage to the first layer, the second layer having a second recess that overlaps with the first recess, the gap from the first fastener of the plurality of fasteners being larger in the first layer than in the second layer, the first fastener being positioned in the first opening of the opening, and the first opening being at least partially defined by the first recess and the second recess, A multichip module comprising a plurality of contacts located on the first layer and electrically connected to a first IC die among a plurality of IC dies stacked with the first VRM, the plurality of contacts configured to provide the adjustment voltage to the first IC die. [Composition 12] The multi-chip module according to configuration 11, wherein the plurality of contacts include a ball grid array. [Composition 13] The multi-chip module according to configuration 12, wherein the ball grid array is enclosed in underfill. [Composition 14] The multichip module according to configuration 13, wherein the gap in the first layer is configured to prevent the underfill from filling the first recess. [Composition 15] The multi-chip module according to configuration 13, wherein the underfill forms a fillet extending from the edge of the first layer toward the fastener. [Composition 16] The multi-chip module according to configuration 15, wherein the distance the fillet extends from the edge of the first layer toward the fastener is smaller than the distance between the gap of the first layer and the gap of the second layer. [Composition 17] The multichip module according to configuration 11, wherein the first layer comprises a plurality of passive circuit elements configured to multiply the step-down voltage by the current. [Composition 18] The multi-chip module according to configuration 11, wherein the fastener includes a bolt. [Composition 19] The multi-chip module according to configuration 11, further comprising a cooling system configured to actively cool the VRM. [Configuration 20] A multi-chip module according to configuration 11, wherein the system-on-wafer (SoW) includes the IC die. [Composition 21] The multi-chip module according to configuration 20, further comprising a heat dissipation structure formed on the side surface of the SoW facing the first layer and the second layer.

Claims

1. A voltage regulation module (VRM), A first layer configured to output an adjustment voltage based on a step-down voltage, the first layer having a first recess, A second layer laminated with the first layer, the second layer comprising a plurality of active components configured to receive a voltage, generate the step-down voltage based on the voltage, and provide the step-down voltage to the first layer, wherein the second layer has a second recess that overlaps with the first recess, and the first recess has a larger mounting area than the second recess, A voltage adjustment module (VRM) comprising a plurality of contacts located on the first layer and configured to output the adjustment voltage.

2. The VRM according to claim 1, wherein the plurality of contacts include a ball grid array.

3. The VRM according to claim 2, wherein the ball grid array is sealed with underfill.

4. The VRM according to claim 1, further comprising a third layer laminated with the first layer and the second layer, wherein the third layer comprises a plurality of active components.

5. The VRM according to claim 4, wherein the third layer has a third recess having substantially the same area as the area of ​​the second recess.

6. The VRM according to claim 1, wherein the first layer comprises a plurality of individual components configured to multiply the current of the step-down voltage.

7. The VRM according to claim 6, wherein the individual components include passive circuit elements.

8. It is a multi-chip module, Multiple integrated circuit (IC) dies, Multiple voltage regulation modules (VRMs), wherein each VRM is stacked with each of the IC dies of the multiple IC dies, The system comprises a plurality of fasteners arranged in the openings between the VRMs of the plurality of VRMs, Of the aforementioned multiple VRMs, the first VRM is A first layer configured to output an adjustment voltage based on a step-down voltage, wherein the first layer has a first recess, A second layer laminated with the first layer, wherein the second layer comprises a plurality of active components configured to receive a voltage and supply the step-down voltage to the first layer, the second layer having a second recess that overlaps with the first recess, the gap from the first fastener among the plurality of fasteners being larger in the first layer than in the second layer, the first fastener being positioned in the first opening of the opening, and the first opening being at least partially defined by the first recess and the second recess, A multichip module comprising a plurality of contacts located on the first layer and electrically connected to a first IC die among a plurality of IC dies stacked with the first VRM, the plurality of contacts configured to provide the adjustment voltage to the first IC die.

9. The multi-chip module according to claim 8, wherein the plurality of contacts include a ball grid array.

10. The multi-chip module according to claim 9, wherein the ball grid array is enclosed in underfill.

11. The multi-chip module according to claim 10, wherein the gap in the first layer is configured to prevent the underfill from filling the first recess.

12. The multi-chip module according to claim 10, wherein the underfill forms a fillet extending from the edge of the first layer toward the fastener.

13. The multi-chip module according to claim 12, wherein the distance the fillet extends from the edge of the first layer toward the fastener is smaller than the distance between the gap of the first layer and the gap of the second layer.

14. The multichip module according to claim 8, wherein the first layer comprises a plurality of passive circuit elements configured to multiply the current of the step-down voltage.

15. The multi-chip module according to claim 8, wherein the fastener includes a bolt.

16. The multi-chip module according to claim 8, further comprising a cooling system configured to actively cool the VRM.

17. The multichip module according to claim 8, wherein the system-on-wafer (SoW) includes the IC die.

18. The multi-chip module according to claim 17, further comprising a heat dissipation structure formed on the side surface of the SoW facing the first layer and the second layer.

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