3D Vertical Spiral Inductor and Transformer

The 3D spiral inductor design addresses interference issues by eliminating shielding and keep-out zones, enhancing performance with higher Q and lower resistance.

JP7894384B2Active Publication Date: 2026-07-23QUALCOMM INC
View PDF 4 Cites 0 Cited by

Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
QUALCOMM INC
Filing Date
2022-02-08
Publication Date
2026-07-23

AI Technical Summary

Technical Problem

Conventional inductor structures require shielding and keep-out zones to mitigate adverse effects from magnetic flux, leading to design constraints and interference issues.

Method used

A 3D spiral inductor configuration with vertically oriented coils, utilizing multiple dielectric and conductive layers, eliminates the need for shielding and keep-out zones by reducing electromagnetic interference.

Benefits of technology

The 3D spiral inductor design achieves higher quality factor (Q) and lower resistance, minimizing interference and enabling more compact, efficient circuit designs.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure 0007894384000001
    Figure 0007894384000001
  • Figure 0007894384000002
    Figure 0007894384000002
  • Figure 0007894384000003
    Figure 0007894384000003
Patent Text Reader

Abstract

An apparatus is disclosed that includes a vertical spiral inductor. The vertical spiral inductor may include a plurality of dielectric layers formed on a substrate, a plurality of conductive layers, each of the plurality of conductive layers disposed on each of the plurality of dielectric layers, and a plurality of insulating layers, each of the plurality of insulating layers disposed on each of the plurality of conductive layers, each of the plurality of insulating layers separating each of the plurality of dielectric layers. A first spiral coil is disposed in a first plane perpendicular to the substrate, the first spiral coil being formed from a first portion of the plurality of conductive layers and a first set of vias of the plurality of vias configured to connect the first portion of the plurality of conductive layers.
Need to check novelty before this filing date? Find Prior Art