In-package passive inductive element for reflection reduction

Abstract

The packaged device comprises a first transceiver (110) comprising a first integrated circuit (IC) die and a transmit circuit (112), and a second transceiver (120) comprising a second IC die and a receive circuit (124). The receive circuit is coupled to the transmit circuit via a channel (140). The packaged device further comprises an interconnect device (130) connected to the first IC die and the second IC die. The interconnect device comprises a channel (140) connecting the transmit circuit to the receive circuit, and a passive inductive element (142) disposed along the channel external to the first IC die and the second IC die.

Description

Technical Field

[0001] Examples of the present disclosure generally relate to electronic circuits, and more particularly, to passive inductive elements for reducing reflections in received signals.

Background Art

[0002] Transceivers of different integrated circuit (IC) dies are connected via one or more channels. The channels include one or more traces. In Extra Short Reach (XSR) and Ultra Short Reach (USR) channels, ultra-low power transceivers are used. XSR and USR channels correspond to communication links having a length of about 5 mm to about 50 mm. Since XSR and USR channels use ultra-low power transceivers, decision feedback equalizers (DFEs) and feed forward equalizers (FFEs) are not normally available in the corresponding receiving circuits to reduce inter-symbol interference (ISI) due to reflections. In many cases, equalization techniques rely on on-die inductors (e.g., T coils). The on-die inductor can compensate for most of the parasitic capacitance between IC dies and reduce reflections. However, the on-die inductor cannot compensate for the capacitance between the bump pads of the IC die and the corresponding off-die bumps.

Summary of the Invention

[0003] Inductive elements are used within integrated circuit (IC) dies (e.g., on-die inductors) to mitigate the effects caused by capacitive components within the IC die. However, inductive elements within an IC die can only mitigate some of the reflections that may occur when transmitting a signal from a transmitting circuit to a receiving circuit. For example, inductive elements within an IC die do not mitigate the capacitance between an off-die bump and a bump pad on the IC die. In one example, a passive inductive element is placed outside the IC die, close to the bump, to mitigate the effect of bump-to-bump pad capacitance. The passive inductor may be contained within one or more layers of an interface element (e.g., a substrate, interposer, or one or more layers outside the IC die but connected to it).

[0004] In one example, the package device comprises a first transceiver having a first integrated circuit (IC) die and a transmitting circuit, and a second transceiver having a second IC die and a receiving circuit. The receiving circuit is coupled to the transmitting circuit via a channel. The package device further comprises an interconnection device connected to the first and second IC dies. The interconnection device comprises a channel connecting the transmitting circuit to the receiving circuit, and passive inductive elements arranged along the channel outside the first and second IC dies.

[0005] In one example, the interconnect device includes a channel configured to connect the transmitting circuit of a first integrated circuit (IC) die to the receiving circuit of a second IC die. The interconnect device is connected to the first IC die and the second IC die. The interconnect device further includes a passive inductive element positioned along the channel in close proximity to the second IC die.

[0006] In one example, the electronic device includes a package device. The package device comprises a first transceiver having a first integrated circuit (IC) die and a transmitting circuit, a second transceiver having a second IC die and a receiving circuit, and an interconnect device. The interconnect device is connected to the first IC die and the second IC die. The interconnect device comprises a body and a channel connecting the transmitting circuit to the receiving circuit. The channel is located within the interconnect device. The interconnect device further comprises a passive inductive element located in close proximity to the second IC die and along the channel within the interconnect device.

[0007] These and other embodiments may be understood by referring to the following "Modes for Carrying Out the Invention".

[0008] To ensure a detailed understanding of the above features, a more specific explanation, concisely summarized above, can be provided by referring to exemplary implementations, some of which are shown in the attached drawings. However, it should be noted that the attached drawings only show typical exemplary implementations and should therefore not be considered limiting in scope. [Brief explanation of the drawing]

[0009] [Figure 1] This is a block diagram illustrating exemplary packaging devices, one or more examples. [Figure 2] This is a side view of an exemplary package device, with one or more examples. [Figure 3] This is a side view of an exemplary package device, with one or more examples. [Figure 4] This is a graph of potential response errors in signals, using one or more examples. [Figure 5] This is a schematic diagram of a portion of an exemplary communication system, with one or more examples. [Figure 6] This graph shows the reduction in error in the received signal using one or more examples. [Figure 7]One or more examples of exemplary passive inductive elements are shown. [Figure 8] One or more examples of exemplary passive inductive elements are shown. [Figure 9] One or more examples of exemplary passive inductive elements are shown. [Figure 10] One or more examples of exemplary passive inductive elements are shown. [Figure 11] One or more examples of exemplary passive inductive elements are shown. [Figure 12] One or more examples of exemplary passive inductive elements are shown. [Modes for carrying out the invention]

[0010] For ease of understanding, the same reference numeral is used to indicate identical elements common to multiple drawings, where possible. It is intended that elements in one example may be usefully incorporated into others.

[0011] In short-range channels or links (e.g., channels less than approximately 15 mm), reflections are the dominant factor negatively affecting signals received by the receiving circuit of the short-range channel. In some examples, in short-range channel links, reflections occur within the 9th to 14th post-cursor. Intersymbol interference (ISI) can be mitigated by decision feedback equalizers (DFEs) and feedforward equalizers (FFEs) in the receiving circuit, although DFEs and FFEs are not included in low-power devices. Furthermore, transmitter finite impulse response (TXFIR) filters in the transmitting circuit and continuous-time linear equalizers (CTLEs) in the receiving circuit cannot mitigate ISI caused by reflections. Therefore, in low-power transceiver devices, ISI due to reflections negatively affects signal reception in the receiving circuit.

[0012] Inductive elements (or inductors) within an IC die (e.g., on-die inductors) mitigate the effects caused by capacitive components within the IC die. However, inductive elements within an IC die do not reduce reflections between the receiving and transmitting circuits of a transceiver device caused by capacitance outside the IC die. For example, inductive elements within an IC die do not mitigate the effect corresponding to the capacitance between the bumps and bump pads of the IC die. In one example, passive inductive elements are added outside the IC die, close to the bumps, to mitigate the effect of off-die bumps on the capacitance of on-die bump pads. Passive inductive elements may be contained within one or more layers of an interconnecting device. An interconnecting device is one or more redistribution layers located outside the substrate, interposer, or IC die but connected to it.

[0013] Figure 1 shows an exemplary package device 100 in one or more examples. The package device 100 includes transceivers 110 and 120. In one example, transceivers 110 and 120 form a serial communication system. For example, transceivers 110 and 120 are each serializer-deserializer (SerDes) devices. Transceivers 110 and 120 are part of a larger transmitting circuit. Transceivers 110 and 120 include IC dies. Furthermore, transceivers 110 and 120 may be application-specific ICs (ASICs) or field-programmable gate arrays (FPGAs).

[0014] Transceiver 110 includes a transmitting circuit 112 and a receiving circuit 114. Furthermore, transceiver 120 includes a transmitting circuit 122 and a receiving circuit 124. In one example, the transmitting circuit 112 of transceiver 110 is connected to the receiving circuit 124 of transceiver 120 via a channel 140. Transceivers 110 and 120 are mounted (or connected in some other way) on an interconnecting device 130 and communicatively coupled via the channel 140. The interconnecting device 130 is a substrate, interposer, package substrate, or other routing for a chip package. In another example, the interconnecting device 130 is a plurality of layers including conductive and non-conductive layers. Furthermore, the interconnecting device 130 includes, among other things, one or more organic materials and / or silicon materials. In one example, the interconnecting device 130 includes a body on which the channel 140 and passive inductive elements 142 reside.

[0015] The transceiver 110's transmitting circuit 112 generates a data signal at a certain data rate. In one example, the data signal is a serial data signal generated by the transmitting circuit 112 from a parallel data path (serialized). The transmitting circuit 112 drives the data signal on channel 140 using modulation techniques. For example, the transmitting circuit 112 can drive the data signal using pulse amplitude modulation (PAM) or another modulation technique. Channel 140 propagates electrical signals representing the symbols of the data signal (e.g., logical "1" and logical "0") toward the receiving circuit 124.

[0016] Channel 140 may also be called a communication medium, communication link, or link. In one example, channel 140 includes multiple traces or electrical paths. Channel 140 includes, among other things, traces and vias within the body of interconnect device 130, bumps between interconnect device 130 and the IC dies of transceivers 110 and 120, and bump pads between interconnect device 130 and the IC dies of transceivers 110 and 120. Channel 140 may also be a differential channel having two traces (e.g., wires) connecting the transmitting circuit 112 to the receiving circuit 124. In such an example, data on the differential channel is represented by using two electrical signals (e.g., a true signal and a complementary signal). In one example, logic "0" is represented by driving the first electrical signal to a lower voltage limit and the second electrical signal to an upper voltage limit. Logic "1" is represented by driving the first electrical signal to an upper voltage limit and the second electrical signal to a lower voltage limit. Therefore, the logical value of each transmitted symbol is based on the difference between the first electrical signal and the second electrical signal. The peak-to-peak difference between the true signal and the complementary signal is the voltage amplitude (e.g., the signal amplitude or amplitude). In one example, channel 140 includes a pair of matched transmission lines (traces), each having a characteristic impedance (Z0).

[0017] The transmit circuit 112 of the transceiver 110 may include, among other circuit elements, an FIR filter, a pre-driver, an output driver, and control logic. The transmit circuit 112 equalizes the serial data signal before transmitting it through channel 140. In one example, the FIR filter of the transmit circuit 112 mitigates the precursor ISI caused by channel 140. The output driver of the transmit circuit 112 couples the data signal to channel 140. The data signal may be a differential data signal.

[0018] In one example, when a data signal is transmitted via channel 140, the data signal degrades. For example, the data signal may undergo channel insertion loss. Channel insertion loss is a frequency-dependent degradation in the signal power of the transmitted data signal. As the data signal travels through channel 140, the high-frequency components of the transmitted data signal are attenuated more than the low-frequency components. Channel insertion loss increases as the frequency increases. The energy of the signal pulses in the transmitted data signal may spread from one symbol period to another when the data signal is transmitted over channel 140. The resulting distortion is sometimes referred to as inter-symbol interference (ISI). In various examples, ISI worsens as the speed at which the communication system operates increases.

[0019] The receiving circuit 124 of the transceiver 120 includes, among other things, an inductive element 132, an electrostatic discharge (ESD) circuit, a continuous-time linear equalizer (CTLE) circuit, an automatic gain control (AGC) circuit, an analog-to-digital (ADC) circuit, and a digital signal processing (DSP) circuit. The inductive element 132 minimizes the impact of the receiver's capacitance on the received data signal. In one example, the inductive element 132 is a T-coil circuit that includes one or more inductors and one or more capacitors within the IC die of the transceiver 120. The inductance of the inductive element 132 is approximately 100 pH. In other embodiments, the inductance of the inductive element 132 is greater than or less than 100 pH. Further, since the inductive element 132 is disposed within the IC die of the transceiver 120, the inductive element 132 is an on-die element. The inductive element 132 is disposed between the bump pad on the IC die of the transceiver 120 and the ESD circuit of the receiving circuit 124.

[0020] The output of the induction element 132 is provided to the CTLE circuit or the AGC circuit via the ESD circuit. The ESD circuit includes one or more diodes that reduce the impact of static electricity. The AGC circuit adjusts the gain of the data signal received from the channel 140. The CTLE circuit receives the gain-adjusted signal from the AGC circuit and operates as a high-pass filter that compensates for the low-pass characteristics of the channel 140. The CTLE circuit and the AGC circuit may be arranged in any order. The ADC circuit receives the output signal from the CTLE circuit or the AGC circuit and generates a digital signal. The digital signal is received by the DSP circuit, and the DSP circuit generates a processed digital signal output by the receiving circuit 124.

[0021] The channel 140 includes a passive induction element 142. The passive induction element 142 is disposed outside the IC die of the transceiver 120. Further, the passive induction element 142 includes one or more inductors formed from the traces constituting the channel 140. The passive induction element 142 compensates for the adverse effects caused by the bump pads of the interconnect device 130 and the capacitance of the associated bump pads. In one example, the passive induction element 142 reduces the reflection between the transmission circuit 112 and the receiving circuit 124. The passive induction element 142 is disposed in proximity to the bump pads of the interconnect device 130. Further, the passive induction element **********142 is formed from the traces forming the channel 140. The passive induction element 142 may be formed within one or more layers of the interconnect device 130. The passive induction element 142 is formed horizontally and / or vertically within the interconnect device 130.

[0022] The passive induction element 142 has an inductance value of approximately 100 pH. In other examples, the passive induction element 142 has an inductance value less than 100 pH or greater than 100 pH. The inductance of the passive induction element 142 corresponds to the capacitance of the bumps and bump pads between the IC die of the transceiver 120 and the interconnect device 130.

[0023] In one example, different passive inductive elements 142 may be arranged along two or more channels between the transmitting and receiving circuits of the communication system. In another example, the passive inductive elements 142 are arranged along the first trace of the first channel, and the second trace of the first channel and / or the trace of the second channel do not contain any passive inductive elements.

[0024] The package device 100 is part of the electronic device 102. For example, the package device 100 is mounted on the substrate of the electronic device 102 so that the transceivers 110 and 120 can communicate with other elements of the electronic device 102. The electronic device 102 may be, among other things, a computing device, a sensing device, or a communication device. The electronic device 102 may include one or more package devices and other circuit elements (e.g., passive and active components) each performing functions related to the operation of the electronic device 102.

[0025] Figure 2 shows a side view of a package device 200 mounted on a package substrate 250, in one or more examples. The IC die of the transceiver 110 is mounted on the substrate 230 via bump pads 211, 212 and bump 210. While the substrate 230 is described in relation to Figure 2, in other examples the substrate 230 is an interposer or other in-chip package routing that can form connections between multiple IC dies within a chip package. In one example the substrate 230 is a package substrate. Bump pad 211 is located on the surface of the IC die of the transceiver 110, and bump pad 212 is located on the surface of the body 231 of the substrate 230. Bump pad 211 is connected to the circuitry within the transceiver 110 (e.g., the transmitting circuit 112). Bump pad 212 is connected to the traces and vias within the body 231 of the substrate 230. The bump 210 forms a connection between the bump pad 211 and the bump pad 212 so that signals can be communicated to and from the transceiver 110 via traces and vias (e.g., 204, 202, and 218) in the substrate 230.

[0026] The transceiver 120 is mounted on the substrate 230 via bump pads 215 and 216 and bump 214. Bump pad 215 is located on the surface of the IC die of the transceiver 120, and bump pad 216 is located on the surface of the body 231 of the substrate 230. Bump pad 215 is connected to the circuitry within the transceiver 120 (e.g., the receiving circuit 124). Bump pad 216 is connected to the traces and vias (e.g., 204, 202, and 219) within the body 231 of the substrate 230. Bump 214 forms a connection between bump pad 215 and bump pad 216 so that signals can be communicated to and from the transceiver 120 via the traces and vias (e.g., 204, 202, and 219) within the body of the substrate 230.

[0027] In one example, bumps 210 and 214 may be referred to as C4 bumps. In the example shown in Figure 2, substrate 230 is mounted on package substrate 250 via bump 220 to form a chip package. The chip package may be included as part of a larger electronic device (e.g., electronic device 102).

[0028] Transceiver 110 is connected to transceiver 120 via channel 140. Channel 140 includes traces 202 and 204. Trace 202 is connected between bump pads 212a and 216a, and trace 204 is connected between bump pads 212b and 216b. Traces 202 and 204 are located within the body 231 of substrate 230. In one example, passive inductors 142 are formed within the body 231 of substrate 230 where trace 202 contacts bump pad 216a and trace 204 contacts bump pad 216b. Passive inductors 142 include passive inductors (e.g., passive inductors 242a and 242b) for each trace (e.g., traces 202 and 204) connecting the IC die of transceiver 110 to the IC die of transceiver 120. In one example, the passive inductor 242a is formed along trace 202, where trace 202 contacts a bump pad 216a within the body 231 of the substrate 230, and the passive inductor 242b is formed along trace 204, where trace 204 contacts a bump pad 216b within the body 231 of the substrate 230. The passive inductor element 142 is formed within the substrate 230, outside the IC die of the transceiver 120. For example, the passive inductors 242a and 242b of the passive inductor element 142 are formed within the body 231 of the substrate 230, and outside the IC die of the transceiver 120. The passive inductor element 142 is formed from traces 202 and 204. For example, the passive inductors 242a and 242b of the passive inductor element 142 are formed from traces 202 and 204, respectively. In one example, the passive inductor element 142 is formed horizontally (for example, in a single layer) within the body 231 of the substrate 230. For example, one or more of the passive inductors 242a and 242b are formed horizontally within the body 231 of the substrate 230. In another example, the passive inductor element 142 is formed both horizontally and vertically within the body 231 of the substrate 230, such that one or more layers within the substrate 230 are used to form the passive inductor element 142. For example, one or more of the passive inductors 242a and 242b are formed horizontally and vertically within the substrate 230.

[0029] The passive inductor 142 is located in close proximity to the bump pads 216a and 216b within the body 231 of the substrate 230. For example, the passive inductor 242a is located in close proximity to the bump pad 216a, and the passive inductor 242b within the body 231 of the substrate 230 is located in close proximity to the bump pad 216b within the body 231 of the substrate 230. In one example, the passive inductor 142 is connected to the bump pads 216a and 216b such that the passive inductor 142 terminates at the bump pads 216a and 216b within the body 231 of the substrate 230. In such an example, the passive inductor 242a is connected to the bump pad 216a and terminates at the bump pad 216a within the body 231 of the substrate 230, and the passive inductor 242b is connected to the bump pad 216b and terminates at the bump pad 216b within the body 231 of the substrate 230. In one example, there are no other elements between the passive inductive element 142 and the bump pads 216a and 216b. The passive inductive element 142 reduces the effect of capacitance between the bump and the bump pads (for example, the capacitance formed between the respective bump pads 216a and 216b of the bump 214).

[0030] Figure 3 shows a side view of the package device 300 in one or more examples. Compared to the example in Figure 2, in the example in Figure 3, the transceivers 110 and 120 are located on and connected to layer 330. Layer 330 includes conductive and non-conductive layers that can be used to form a channel 140. For example, channel 140 includes traces 302 and 304 located on different layers of layer 330. Layer 330 includes a redistribution layer (RDL) containing traces and vias. Channel 140 is formed from traces 304 and 302 and the corresponding vias in layer 330.

[0031] Layer 330 is mounted or placed on the package substrate 340. The package substrate 340 may be mounted within a larger electronic device (e.g., electronic device 102).

[0032] The transceiver 110 is connected to layer 330 via bump pads 311 and 312 and bump 310. Bump pad 311 is located on the surface of the IC die of the transceiver 110, and bump pad 312 is located on layer 330. Bump pad 311 is connected to the circuitry within the transceiver 110 (e.g., the transmitting circuit 112). Bump pad 312 is connected to the traces and vias within layer 330. Bump 310 forms a connection between bump pad 311 and bump pad 312 so that signals can be communicated to and from the transceiver 110 via the traces and vias within layer 330.

[0033] The transceiver 120 is mounted on layer 330 via bump pads 315 and 316 and bump 314. Bump pad 315 is located on the surface of the IC die of the transceiver 120, and bump pad 316 is located on layer 330. Bump pad 315 is connected to the circuitry within the transceiver 120 (e.g., the receiving circuit 124). Bump pad 316 is connected to the traces and vias within layer 330. Bump 314 forms a connection between bump pad 315 and bump pad 316 so that signals can be communicated to and from the transceiver 120 via the traces and vias within layer 330.

[0034] In one example, the trace density in layer 330 is greater than the trace density in substrate 230 in Figure 2. Furthermore, the traces in layer 330 are thinner than the traces in substrate 230, and the trace pitch in layer 330 is smaller than the trace pitch in substrate 230. For example, traces 302 and 304 are thinner than traces 202 and 204 in Figure 2. Bump pads 311, 312, 315, and 316 are smaller than bump pads 211, 212, 215, and 216. Furthermore, the width and / or height of bumps 310 and 314 are smaller than the width and / or height of bumps 210 and 214. In one example, bumps 310 and 314 are sometimes called microbumps.

[0035] As explained with respect to Figure 2, the passive inductors 242a and 242b of the passive inductor element 142 are formed at the ends of trace 302 and trace 304, respectively. Furthermore, the passive inductors 242a and 242b of the passive inductor element 142 are formed within one or more layers of layer 330. For example, the passive inductors 242a and 242b of the passive inductor element 142 are formed vertically and horizontally within layer 330. In one example, the passive inductors 242a and 242b of the passive inductor element 142 are formed from traces 302 and 304, respectively. Furthermore, the passive inductors 242a and 242b of the passive inductor element 142 are close to bump pads 316a and 316b, respectively. In one example, the passive inductors 242a and 242b of the passive inductor element 142 form connections between trace 302 of layer 330 and bump pad 316a, and between trace 304 of layer 330 and bump pad 316a. The passive inductors 242a and 242b of the passive inductor element 142 are connected to bump pads 316a and 316b so that the passive inductor element 142 is terminated at bump pads 316a and 316b.

[0036] In the examples in Figures 2 and 3, a differential channel 140 is described. In such examples, each trace of channel 140 includes a passive inductor of a passive inductor element 142 (e.g., passive inductor 242a or 242b). In other examples, channel 140 may include fewer or more than two traces. In such examples, passive inductor element 142 includes a passive inductor for each trace of channel 140. Alternatively, in such examples, passive inductor element 142 includes a passive inductor for at least one, but not all, traces of channel 140. Furthermore, in one or more examples, the package device 100 includes multiple channels. In such examples, two or more traces of the channels include passive inductors. In one example, each trace of two or more channels includes a passive inductor of the corresponding passive inductor element. In other examples, at least one, but not all, traces of each channel include a passive inductor.

[0037] Figure 4 shows a graph 400 of a single-bit response in one or more examples. Line 410 shows a single-bit response with a reflection 420. The reflection 420 is located at a distance of approximately 7 UI from the starting point 430. The reflection 420 appears as ISI in the receiving circuit 124 of transceiver 120. In one example, the reflection 420 triggers a pulse that travels from the receiving circuit 124 to the transmitting circuit 112 of transceiver 110 and then back to the receiving circuit 124. Filtering elements in the receiving circuit 124 (e.g., AGC circuit, CTLE circuit, and / or DSP circuit) cannot mitigate the interference (e.g., ISI) caused by the reflection 420. Therefore, additional filtering techniques are used to mitigate the effects of the reflection 420. For example, to mitigate the effects of the reflection 420, a passive inductive element (e.g., passive inductive element 142) is brought outside the IC die of transceiver 120.

[0038] Figure 5 shows a schematic block diagram of a portion of the package device 100 in one or more examples. In the example of Figure 5, the transceiver 110 is coupled to the transceiver 120 via the channel 140. The channel 140 includes traces 502 and 504, and a passive inductor 142. Traces 502 and 504 are configured similarly to traces 202 and 204 in Figure 2, and traces 302 and 304 in Figure 3.

[0039] In one example, the passive inductive element 142 is connected to bump connections 506 and 508. Each of the bump connections 506 and 508 includes two or more bump pads (e.g., 215 and 216, or 315 and 316) and a bump (e.g., 214 or 314).

[0040] The bump connections 506 and 508 are associated with capacitances, for example, capacitances 512 and 514. For example, capacitances 512 and 514 can be associated with the corresponding package bumps (or other connections). In one example, capacitances 512 and 514 are associated with bump 214 in Figure 2 or bump 314 in Figure 3. In one example, capacitances 512 and 514 have a value of approximately 30 fF. In another embodiment, capacitances 512 and 514 have a value greater than or less than 30 fF. The inductance value of the passive inductive element 142 can be selected to reduce the influence of capacitances 512 and 514.

[0041] The transceiver 120 is connected to connectors 506 and 508 and includes an inductive element 132. The inductive element 132 is contained within the IC die of the transceiver 120. Furthermore, the inductive element 132 is located within the IC die of the transceiver 120 and is connected to a bump pad (e.g., bump pad 215 or 315) of the IC die of the transceiver 120. The inductive element 132 reduces the influence of capacitances 522 and 524 on the received signal. Capacitors 522 and 524 are parasitic capacitances corresponding to circuit elements of the transceiver 120. For example, the parasitic capacitances correspond to one or more of the following: ESD circuitry, CTLE circuitry, AGC circuitry, ADC circuitry, and DSP circuitry.

[0042] The inductances of the passive inductor 142 and the inductor 132 are determined based on the impedance of the channel 140 and the downstream capacitance (e.g., the combined capacitance of capacitances 512 and 514). The inductances of the passive inductor 142 and the inductor 132 are determined from Z = sqrt(L_lump / C_lump), where Z is the impedance of the channel 140 and C_lump is the combined capacitance of capacitances 512, 514, 522, and 524. The inductance L_lump is divided between the passive inductor 142 and the inductor 132. The inductance L_lump may also be equally allocated between the passive inductor 142 and the inductor 132. In another example, the inductance L_lump is allocated based on the ratio of capacitances 512 and 514 to capacitances 522 and 524. In one example, the inductance L_lump is approximately 400 pH, the inductance value of the passive inductive element 142 is approximately 200 pH, and the inductance value of the inductive element 132 is approximately 200 pH.

[0043] Figure 6 includes graph 600 with one or more examples. Graph 600 includes line 610 showing time-domain reflectometry (TDR) measurements of transceivers that include internal inductors but do not include external inductors. Graph 600 further includes line 620 showing TDR measurements of transceivers that include both internal and external inductors, as shown in Figures 2, 3, and 5. As can be seen from lines 610 and 620, TDR measurements are improved in transceivers that include both internal and external inductors.

[0044] Figure 7 shows a portion of channel 700 in one or more examples. Channel 700 is configured similarly to channel 140 in Figures 1, 2, and 3. Channel 700 includes traces 702 and 704 connected to bump pads 716a and 716b. Channel 700 further includes a passive inductive element 706 formed from traces 702 and 704. The passive inductive element 706 includes passive inductors 706a and 706b formed from traces 702 and 704, respectively. In one example, the trace widths of traces 702 and 704 vary. For example, the widths (e.g., widths 722 and 724) of the portions of traces 702 and 704 that form the passive inductive element 706 (e.g., the first regions of traces 702 and 704) are smaller than the widths (e.g., widths 720 and 722) of the portions of traces 702 and 704 that do not form the passive inductive element 706 (e.g., the second regions of traces 702 and 704). Furthermore, in the passive inductive element 706, at least a portion of each path of traces 702 and 704 is nonlinear. Traces 702 and 704 include portions 730 and 732 that at least partially surround their respective bump pads 716a and 716b. In one example, portions 730 and 732 may be called helical or arc segments that rotate around their respective bump pads 716a and 716b. For example, with respect to the endpoint within the bump pad, portion 730 rotates clockwise and portion 732 rotates counterclockwise. Parts 730 and 732 rotate in opposite directions relative to each other. Parts 730 and 732 may also be mirror-symmetric with respect to each other. Each of traces 702 and 704 includes angled parts 734, 736 that reduce the distance between traces 702 and 704 at the beginning of parts 730 and 732. In one example, the passive inductor 706 is located within one or more layers (e.g., substrate 230 in Figure 2 or layer 330 in Figure 3) outside the IC die of a transceiver (e.g., transceiver 120). For example, parts 730 and 732 may extend through multiple layers of layer 330 in Figure 3. In such an example, the passive inductor 706 is a three-dimensional structure. In one example, the passive inductor 706 may include a helical shape that reduces the distance relative to bump pads 716a and 716b. In other examples, other three-dimensional shapes may be used.

[0045] The passive inductor element 706 is mirror-symmetric with respect to the center line 740. In other examples, the passive inductor element 706 is not symmetric with respect to the center line 740, such that one of the traces 702 and 704 differs in shape and / or thickness from the other of the traces 702 and 704.

[0046] The inductance of the passive inductor 706 is determined by varying the widths 722 and 724, the distance between traces 702 and 704, and the amount by which traces 702 and 704 surround boundary pads 716a and 716b. For example, the inductance of the passive inductor 706 can be increased or decreased by adjusting these characteristics. By forming the passive inductor 706 as described with respect to Figure 7, it is possible to form the passive inductor 706 within an interconnect device (e.g., a substrate, interposer, or one or more layers outside of an IC chip) and reduce reflections and other interference in the transmitted data signal. In one example, the shape and position of the passive inductor 706 provide an inductive load close to the corresponding bumps and bump pads, which increases the efficiency of compensating for the capacitive load between the bumps and bump pads.

[0047] Figure 8 shows a portion of channel 800 in one or more examples. Channel 800 is configured similarly to channel 140 in Figures 1, 2, and 3. Channel 800 includes traces 802 and 804 connected to bump pads 816a and 816b. Channel 800 further includes a passive inductor 806 formed from traces 802 and 804. Passive inductor 806 is configured similarly to passive inductor 706. For example, the width of traces 802 and 804 forming passive inductor 806 is smaller than the width of traces 802 and 804 outside of passive inductor 806. Furthermore, passive inductor 806 includes portions of traces 802 and 804 that at least partially surround bump pads 816a and 816b, similar to portions 730 and 732 shown in Figure 7. Passive inductor 806 includes passive inductors 806a and 806b. Furthermore, the passive inductive element 806 includes angled portions 834, 836 in which the distance between traces 802 and 804 is reduced. The passive inductive element 806 further includes one or more portions (e.g., 810 and 812) of traces 802 and 804 that extend perpendicular to the path 808, with traces 802 and 804 including at least one change of direction. In one example, traces 802 and 804 may extend vertically and / or horizontally. The path 808 represents the direction of the shortest distance that traces 802 and 804 travel to reach bump pads 816a and 816b. Portions 810 and 812 have a waveform (or waveform), such as a sinusoidal or square waveform, among other things. In the example of Figure 8, portions 810 and 812 of traces 802 and 804 include a plurality of extensions that extend perpendicular to the path 808. Furthermore, the extensions may extend horizontally and / or vertically. Although four extensions are shown in Figure 8, in other examples, portions 810 and 812 of traces 802 and 804 may include more or fewer than four extensions that extend perpendicular to path 808. The extensions may be of the same length, or one or more extensions may be longer than another or more extensions.

[0048] In one example, portions 810 and 812 are positioned between bump pads 816a and 816b and inclined portions 834 and 836, or angled portions 834 and 836 are positioned between bump pads 816a and 816b and portions 810 and 812.

[0049] The inductance of the passive inductor 806 is adjusted by changing the number of extensions in sections 810 and 812, the distance over which the extensions in sections 810 and 812 extend, the width of traces 802 and 804, and the amount to which traces 802 and 804 surround the bump pads 816a and 816b. For example, by adjusting these characteristics, the inductance of the passive inductor 806 can be increased or decreased. By forming the passive inductor 806 as described with respect to Figure 8, it is possible to form the passive inductor 806 within an interconnect device (e.g., a substrate, interposer, or one or more layers outside the IC chip) to reduce reflections and other interference in the transmitted data signal. Furthermore, with respect to the passive inductor 706 in Figure 7, the passive inductor 806 may be placed in a smaller area within the interface device. In one example, the shape and position of the passive inductor 806 provide an inductive load close to the corresponding bumps and bump pads, increasing the efficiency of compensating for the capacitive load between the bumps and bump pads.

[0050] Figure 9 shows a portion of channel 900 in one or more examples. Channel 900 is configured similarly to channel 140 in Figures 1, 2 and 3. Channel 900 includes traces 902 and 904 connected to bump pads 916a and 916b. Channel 900 further includes a passive inductor 906 formed from traces 902 and 904. Passive inductor 906 is configured similarly to passive inductors 706 and 806 in Figures 7 and 8. Passive inductor 906 includes passive inductors 906a and 906b. Furthermore, the width of the traces 902 and 904 forming the passive inductor 906 is smaller than the width of the traces 902 and 904 outside the passive inductor 906. Furthermore, passive inductor 906 also includes an angled portion in which the distance between traces 902 and 904 is reduced. The passive inductive element 906 further includes one or more portions (e.g., 910 and 912) of traces 902 and 904 that extend perpendicular to path 908, with traces 902 and 904 including at least one change of direction. In addition, or alternatively, the traces may extend vertically and / or horizontally. Path 908 represents the direction of the shortest distance traces 902 and 904 travel to reach bump pads 916a and 916b. Portions 910 and 912 may have a waveform (e.g., a waveform), such as a sinusoidal or square waveform. Portions 910 and 912 of traces 902 and 904 include a plurality of extensions that extend perpendicular to path 908. In the example of Figure 9, portions 910 and 912 include eight extensions. In other examples, portions 910 and 912 of traces 902 and 904 include more or fewer than eight extensions that extend perpendicular to path 908. Furthermore, portions 910 and 912 include at least six changes of direction. In yet another example, portions 910 and 912 include more or fewer than six changes of direction. In one example, as shown in Figure 10, the passive inductor element 1006 includes portions 1010 and 1012 of traces 1002 and 1004 that include at least eight extensions that extend perpendicular to path 1008 and at least ten changes of direction.

[0051] The inductance of passive inductors 906 and 1006 is adjusted by changing the number of extensions within sections 910 and 912, or 1010 and 1012, the distance over which the extensions within sections 910 and 912, or 1010 and 1012 extend, and the width of traces 902 and 904, or 1002 and 1004. For example, by adjusting these features, the inductance of passive inductors 906 or 1006 can be increased or decreased. By forming passive inductors 906 and 1006 as described with respect to Figures 9 and 10, it is possible to form passive inductors 906 and 1006 within an interconnect device (e.g., a substrate, interposer, or one or more layers outside an IC chip), thereby reducing reflections and other interference in the transmitted data signal. In one example, the shape and position of the passive inductive elements 906 and 1006 provide an inductive load close to the corresponding bump and bump pad, thereby increasing the efficiency of compensating for the capacitive load between the bump and the bump pad.

[0052] Figure 11 shows a portion of channel 1100 in one or more examples. Channel 1100 is configured similarly to channel 140 in Figures 1, 2, and 3. Channel 1100 includes traces 1102 and 1104 connected to bump pads 1116a and 1116b. Channel 1100 further includes a passive inductor 1106 formed from traces 1102 and 1104. Passive inductor 1106 is configured similarly to passive inductors 706, 806, 906, and 1006 in Figures 7, 8, 9, and 10. Passive inductor 1106 includes passive inductors 1106a and 1106b. Furthermore, the widths of the traces 1102 and 1104 forming passive inductor 1106 are smaller than the widths of the traces 1102 and 1104 outside of passive inductor 1106. Furthermore, the passive inductive element 1106 also includes an angled portion in which the distance between traces 1102 and 1104 is reduced. The passive inductive element 1106 further includes an angled portion in which the distance between traces 1102 and 1104 is increased, and which is close to the bump pads 1116a and 1116b.

[0053] Traces 1102 and 1104 forming the passive inductor element 1106 include meandering paths. The meandering paths may extend horizontally and / or vertically within the interconnect device. Parts 1110 and 1112 of the passive inductor element 1106 include one or more of the following: (i) subparts having a waveform (e.g., a waveform having a sinusoidal or square waveform), (ii) at least one subpart having a direction opposite to the direction of adjacent subparts, and (iii) at least one subpart having a direction opposite to the direction between two adjacent subparts. In one example, different subparts of parts 1110 and 1112 have one or more of (i), (ii), and (iii).

[0054] The passive inductive element 1106 further includes one or more portions (e.g., 1110 and 1112) of the traces 1102 and 1104 that extend perpendicular to and parallel to the path 1108, with the traces 1102 and 1104 including at least one change of direction. The path 1108 represents the direction of the shortest distance that the traces 1102 and 1104 travel to reach the bump pads 1116a and 1116b. The portions 1110 and 1112 of the traces 1102 and 1104 include multiple extensions that extend perpendicular to the path 1108. As shown in Figure 11, portions 1110 and 1112 include two extensions that extend perpendicular to the path 1108. In other examples, portions 1110 and 1112 of traces 1102 and 1104 include more or fewer than two extensions that extend perpendicular to path 1108. Furthermore, as shown in Figure 11, each of portions 1110 and 1112 includes multiple extensions parallel to path 1108. In the example in Figure 11, each of portions 1110 and 1112 includes two extensions parallel to path 1108. In other examples, portions 1110 and 1112 include fewer than two or more extensions parallel to path 1108. Furthermore, the extensions that extend parallel to path 1108 extend away from and / or toward bump pads 1116a and 1116b. The extensions may extend the same distance parallel to path 1108, or one or more extensions may extend a shorter or longer distance parallel to path 1108 than another extension.

[0055] The inductance of the passive inductor 1106 is adjusted by changing the number of extensions within sections 1110 and 1112, the distance over which the extensions within sections 1110 and 1112 extend in one or more directions, and the widths of traces 1102 and 1104. For example, by adjusting these features, the inductance of the passive inductor 1106 can be increased or decreased. By forming the passive inductor 1106 as described with respect to Figure 11, it is possible to form the passive inductor 1106 within an interconnect device (e.g., a substrate, interposer, or one or more layers to an IC chip) to reduce reflections and other interference in the transmitted data signal. In one example, the shape and position of the passive inductor 1106 provide an inductive load close to the corresponding bumps and bump pads, increasing the efficiency of compensating for the capacitive load between the bumps and bump pads.

[0056] Figure 12 shows a portion of channel 1200 in one or more examples. Channel 1200 is configured similarly to channel 140 in Figures 1, 2, and 3. Channel 1200 includes traces 1202 and 1204 connected to bump pads 1216a and 1216b. Channel 1200 further includes a passive inductive element 1206 formed from traces 1202 and 1204. Furthermore, the passive inductive element 1206 includes passive inductors 1206a and 1206b. The passive inductive element 1206 is configured similarly to the passive inductive element 706. For example, the width of the traces 1202 and 1204 forming the passive inductive element 1206 is smaller than the width of the traces 1202 and 1204 outside the passive inductive element 1206. Furthermore, the passive inductive element 1206 includes portions of traces 1202, 1204 (e.g., portions 1210 and 1212) that at least partially surround the bump pads 1216a and 1216b. In one example, with respect to the passive inductive element 706, portions 1210 and 1212 surround more bump pads 1216a and 1216b than portions 730 and 732 surround. In one example, portions 1210 and 1212 completely surround the bump pads 1216a and 1216b. As shown in Figure 12, the shapes of portions 1210 and 1212 are the opposite of the shapes of portions 730 and 732 in Figure 7. In one example, portions 1210 and 1212 may be called helical or arc segments that rotate around their respective bump pads 1216a and 1216b.

[0057] Passive inductive elements (e.g., passive inductive element 142 in Figures 1, 2, and 3) may be formed by combining different features of passive inductive elements 700 to 1200. For example, a passive inductive element may include any combination of at least one portion that at least partially surrounds a bump pad, at least one portion having a waveform, at least one portion having a meandering path, a trace having a reduced width, a reduced distance between traces, and at least one change of direction. The inductance of a passive inductive element can be adjusted by changing the different features used to form the passive inductive element.

[0058] In the examples in Figures 7 to 12, each passive inductor is shown to include two different passive inductors formed from two different traces. In other examples, passive inductors may be formed from two or more passive inductors, each formed from fewer than two or more than two traces. For example, passive inductor 706 may be formed from passive inductor 706a or 706b, passive inductor 806 may be formed from passive inductor 806a or 806b, passive inductor 906 may be formed from passive inductor 906a or 906b, passive inductor 1006 may be formed from passive inductor 1006a or 1006b, passive inductor 1106 may be formed from passive inductor 1106a or 1106b, and / or passive inductor 1206 may be formed from passive inductor 1206a or 1206b.

[0059] Inductive elements within the IC die (e.g., on-die inductors) mitigate the effects corresponding to the capacitance of components within the IC die. Furthermore, passive inductive elements outside the IC die can be used to mitigate reflections of signals transmitted from the transmitter to the receiver. For example, passive inductive elements outside the IC die mitigate the effects of bump-to-bump pad capacitance. Passive inductors may be contained within one or more layers of one or more RDLs located outside but connected to the substrate, interposer, or IC die.

[0060] The above applies to specific examples, but other and further examples may be devised without departing from the basic scope, and the scope will be determined by the following "Claims".

Claims

1. Package device, A first transceiver including a first integrated circuit (IC) die and a transmitting circuit, A second transceiver including a second IC die and a receiving circuit coupled to the transmitting circuit via a channel, An interconnection device connected to the first IC die and the second IC die, wherein the interconnection device is A channel connecting the transmitting circuit to the receiving circuit, A passive inductive element is disposed outside the first IC die and the second IC die, and along the channel, Interconnected devices, Equipped with, The channel includes a first trace and a second trace, and the passive inductive element is formed by the first trace and the second trace. A package device in which the distance between the first trace and the second trace outside the passive inductive element is greater than the distance between the first trace and the second trace inside the passive inductive element.

2. The package device according to claim 1, wherein the interconnection device is a substrate, and the channel and the passive inductive element are arranged within the body of the substrate.

3. The package device according to claim 1, wherein the interconnection device comprises a plurality of layers, and the channel and the passive inductor are arranged within the plurality of layers.

4. The package device according to claim 1, wherein the interconnecting device is an interposer, and the channel and the passive inductive element are arranged within the body of the interposer.

5. The package device according to claim 1, wherein the second IC die includes a first bump pad connected to the first bump, the interconnection device includes a second bump pad connected to the first bump, and the passive inductive element is positioned in close proximity to the second bump pad.

6. The package device according to claim 1, wherein the first trace (a) at least partially surrounds the bump pad of the interconnect device, (b) is associated with a path, and the first trace includes a portion that includes one or more extensions extending perpendicular to the path, or (c) includes a portion that has a waveform.

7. An interconnection device, A channel configured to connect the transmitting circuit of a first integrated circuit (IC) die to the receiving circuit of a second IC die, wherein the interconnection device is connected to the first IC die and the second IC die, A passive inductive element is arranged adjacent to the second IC die along the channel, Equipped with, The channel includes a first trace and a second trace, and the passive inductive element is formed by the first trace and the second trace. An interconnect device in which the distance between the first trace and the second trace outside the passive inductive element is greater than the distance between the first trace and the second trace inside the passive inductive element.

8. It further includes the main unit and the first bump pad, The channel and the passive inductive element are arranged within the main body. The second IC die includes a second bump pad connected to the first bump pad via a bump, The interconnection device according to claim 7, wherein the passive inductive element is arranged in close proximity to the first bump pad.

9. It further comprises multiple layers and a first bump pad, The channel and the passive inductive element are arranged within the plurality of layers. The second IC die includes a second bump pad connected to the first bump pad via a bump, The interconnection device according to claim 7, wherein the passive inductive element is arranged in close proximity to the first bump pad.

10. The interconnect device according to claim 7, wherein the first trace includes a first portion outside the passive inductive element and a second portion inside the passive inductive element, and the width of the first portion of the first trace is greater than the width of the second portion of the first trace.

11. The first trace is associated with a path, and the first trace includes a portion that includes one or more extensions extending in a direction perpendicular to the path, The first trace includes a portion having a waveform, The interconnection device according to claim 7, which is at least one of the following.

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