Analog-to-digital converter system for switching operating modes
The ADC system efficiently switches between operating modes by using a controller to transmit configuration and calibration information, addressing the need for uninterrupted operation and reducing downtime.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- ANALOG DEVICES INC
- Filing Date
- 2024-11-15
- Publication Date
- 2026-07-23
AI Technical Summary
Existing analog-to-digital converter (ADC) systems face challenges in efficiently switching between operating modes without requiring power cycles or restarts, particularly when different hardware configurations and calibrations are needed.
An ADC system with hardware circuitry and a controller that allows switching between operating modes by transmitting configuration and calibration information to the hardware circuit, enabling it to operate in the new mode without power cycling, using a controller to manage the transition.
Enables seamless mode switching with reduced downtime and improved system continuity by allowing the ADC to transition between modes without power cycles, maintaining accurate and efficient operation.
Smart Images
Figure 0007894424000001 
Figure 0007894424000002 
Figure 0007894424000003
Abstract
Description
Technical Field
[0004] , , , , ,
[0003] , ,
[0001] Priority Claim This patent application claims priority to U.S. Provisional Patent Application No. 63 / 600,463 (Attorney Docket No. 3867.B86PRV), titled "MODE SWITCHING IN DATA CONVERSION SYSTEMS," filed on November 17, 2023, by Zakas et al., the entire disclosure of which is incorporated herein by reference.
[0002] The present disclosure relates to electronic devices, and more particularly, but not by way of limitation, to a system for switching the operating mode of an analog-to-digital converter (ADC). <00In one example, an analog-to-digital converter (ADC) system for switching between a first and a second operating mode may include hardware circuitry, where both the first and second operating modes may involve calibrated analog-to-digital conversion, and the hardware circuitry configuration for the second operating mode may differ from that of the first operating mode. The ADC system may also include a controller that can be configured to control the hardware circuitry and control the switching between the first and second operating modes in response to a command to switch from the first to the second operating mode. This controller may include transmitting configuration information for the second mode and calibration information for the second mode to the hardware circuitry, where the configuration information for the second mode may include values for configuring the hardware circuitry to operate in the second operating mode, and the calibration information for the second mode may include values for calibrating the ADC system while it is operating in the second operating mode.
[0005] In one example, a method for switching between a first and second operating mode of an analog-to-digital converter (ADC), where both the first and second operating modes may include calibrated analog-to-digital conversion, and the hardware circuit configuration for the second operating mode may differ from that of the first operating mode, may include transmitting configuration information for the second mode and calibration information for the second mode to the hardware circuit of the ADC. The configuration information for the second mode may include values for configuring the hardware circuit to operate in the second operating mode, and the calibration information for the second mode may include values for calibrating the ADC while it is operating in the second operating mode. The method may also include triggering the hardware circuit to start operating in the second operating mode.
[0006] For example, an analog-to-digital converter (ADC) system for switching between a first and a second operating mode may include hardware circuitry, where both the first and second operating modes may include calibrated analog-to-digital conversion, and the hardware circuitry configuration for the second operating mode may differ from that of the first operating mode. The ADC system may also include a controller that can be configured to control the hardware circuitry to switch between the first and second operating modes in response to a command to switch from the first to the second operating mode. This controller may include transmitting configuration information for the second mode and calibration information for the second mode to the hardware circuitry, where the configuration information for the second mode may include values for configuring the hardware circuitry to operate in the second operating mode, and the calibration information for the second mode may include values for calibrating the ADC system while operating in the second operating mode. The ADC system may also include a controller that can be configured to control the hardware circuitry to switch between the first and second operating modes in response to a command to switch from the first to the second operating mode. The hardware circuit may include a calibration storage register that can be configured to receive calibration information for a second mode, and a calibration operation register that can be configured to hold calibration information for an operating mode. [Brief explanation of the drawing]
[0007] In drawings, the figures may not be drawn to scale, and similar numbers may describe substantially the same components across one or more drawings. Similar numbers with different letter suffixes may represent different examples of substantially the same components. Drawings are illustrative and not limiting; they are for illustrative purposes only.
[0008] [Figure 1] A block diagram of an example of a part of an ADC system is shown. [Figure 2] A block diagram of an example of the hardware circuit is shown. [Figure 3] This shows a timing diagram of an example of the operating part of an ADC system. [Figure 4] A block diagram of an example of a part of an ADC system is shown. [Figure 5] This section provides an example of how to operate an ADC system. [Figure 6] This is a block diagram of an example of a machine part in which one or more parts of this disclosure may be implemented. [Modes for carrying out the invention]
[0009] The inventors have recognized, in particular, that it may be desirable for an ADC system to switch from one operating mode to another. For example, the second operating mode may have one or more characteristics that differ from those in the first operating mode (e.g., sampling rate, signal-to-noise ratio (SNR), spur position, power consumption). For this reason, it may be desirable to switch from the first operating mode to the second operating mode.
[0010] One approach allows an ADC system to switch modes by changing its hardware configuration and restarting the system. During the restart, data for operating the switched-to-mode can be generated. For example, the ADC system can be calibrated, and calibration information can be generated.
[0011] It may be desirable to switch from the first operating mode to the second operating mode within a specified time period, which may include a limited amount of time. For example, it may be desirable to switch from the first operating mode to the second operating mode without requiring one or more of the ADC system's power cycle or restart.
[0012] An ADC system can store information corresponding to two or more modes, which may include one or more of the following: mode configuration information, mode data (e.g., mode calibration data), or mode state information. When switching from a first mode to a second mode, the ADC system can transfer one or more of the mode data or mode state information to hardware circuitry, which can then eliminate the need to power cycle and / or restart the ADC system.
[0013] Figure 1 shows a block diagram of an example of a portion of the ADC system 100. In the example in Figure 1, the ADC system 100 may include hardware circuitry 102, firmware block 104, and controller 106. The ADC system 100 can be configured to switch between a first operating mode and a second operating mode.
[0014] In one example, one or more of the first or second operating modes may include a calibrated analog-to-digital conversion. For example, the ADC system 100 may be configured to perform an analog-to-digital conversion used to calibrate the ADC, such as during startup and / or initialization. The outputs from these calibrated analog-to-digital conversions may be used to adjust the ADC system 100, which may include adjusting the accuracy of the ADC system 100 (e.g., by generating calibration information). In one example, the outputs from these calibrated conversions do not need to be transmitted outside the ADC system 100 (e.g., the outputs may be used only internally). The calibrated analog-to-digital conversions may include one or more that occur after the calibration of the ADC system 100 and are output from the ADC system 100 or used for non-calibrated tasks (e.g., used by a separate system from the ADC system 100). For example, in the calibrated analog-to-digital conversion, the ADC system 100 can be used to measure the voltage signal (e.g., convert an analog voltage to a digital representation of this voltage), and this measured voltage can be sent to a spectrum analyzer to analyze the signal or signal component within the voltage signal.
[0015] The ADC system 100 can include any ADC style, such as one or more of delta-sigma, successive approximation, interleaving, residual generation, flash, or integration. For example, the ADC system 100 can include an interleaving ADC.
[0016] Hardware circuit 102 may include analog hardware circuit 108 and digital hardware circuit 110. Analog hardware circuit 108 can be configured to receive analog signals (e.g., voltage signals, current signals). Analog hardware circuit 108 can be configured to process the received analog signals in one or more ways (e.g., amplification, filtering, sampling). Analog hardware circuit 108 can be configured to pass a representation of the received analog signal to digital hardware circuit 110.
[0017] The digital hardware circuit 110 can be configured to convert a received representation of an analog signal into a digital representation of the analog signal. In one example, the operating modes of the hardware circuit 102 can be configurable. For example, the configuration of the hardware circuit 102 in a second operating mode can differ from the configuration of the hardware circuit 102 in a first operating mode. In one example, any part of the hardware circuit 102 can be configurable. The configuration of the hardware circuit 102 can include any parameters (e.g., configurable parameters) that can include one or more of the following: sampling rate, pre-processing configuration (e.g., amplification, filtering), or conversion configuration (e.g., random or pseudo-random vs. sequential), and post-processing configuration (e.g., amplification, filtering).
[0018] The digital hardware circuit 110 may include configuration operation information 128, calibration operation information 130, and state operation information 132. The configuration operation information 128 may include information that configures the hardware circuit 102 (e.g., the digital hardware circuit 110) to operate in a specified mode. For example, the digital hardware circuit 110 may include one or more registers configured to store digital configuration values (e.g., configuration operation registers that store the configuration operation information 128).
[0019] The calibration operation information 130 can include information used by the hardware circuit 102 (e.g., the digital hardware circuit 110) during operation, such as calibration values and / or other data (e.g., in a look-up table). The calibration operation information 130 can be stored in one or more registers (e.g., calibration operation registers) within the digital hardware circuit 110.
[0020] The state operation information 132 can include information used by the hardware circuit 102 (e.g., the digital hardware circuit 110) during operation, such as for determining the state of the hardware circuit 102 (e.g., determining where the hardware circuit 102 is in the sequence of operations). In one example, the state operation information 132 can be included in the calibration operation information 130. The state operation information 132 can be stored in one or more registers (e.g., state operation registers) within the digital hardware circuit 110.
[0021] The firmware block 104 can include one or more of instructions or other data (e.g., for operating the ADC system 100, for calibrating the ADC system 100, for configuring the ADC system 100). The firmware block 104 can include the first mode object 112 and the second mode object 114. The first mode object 112 can include information related to the first mode, which can include the configuration information 116 of the first mode, the calibration information 118 of the first mode, and the first mode state information 120. The second mode object 114 can include information related to the second mode, which can include the configuration information 122 of the second mode, the calibration information 124 of the second mode, and the second mode state information 126.
[0022] The controller 106 may include any hardware capable of executing instructions. For example, the controller 106 may be included in the firmware block 104. The controller 106 can be configured to control the hardware circuit 102, the firmware block 104, or both. The controller 106 may be configured to control switching between the first and second operating modes, such as in response to a command to switch from the first operating mode to the second operating mode (e.g., a command from a system outside the ADC system 100). For example, one or more of the configuration operation information 128, calibration operation information 130, or state operation information 132 may include information related to the first operating mode (e.g., from the first mode object 112). To switch to the second operating mode, it may be desirable to transfer one or more pieces of information from the second mode object 114 to the hardware circuit 102. For example, one or more of the configuration information 122 for the second mode, calibration information 124 for the second mode, or state information 126 for the second mode may be transferred to the hardware circuit 102. In one example, the controller 106 can control the ADC system 100 to transmit configuration information for a second mode and calibration information for a second mode to the hardware circuit, the configuration information for a second mode may include values that configure the hardware circuit 102 to operate in a second operating mode, and the calibration information for a second mode may include values that calibrate the ADC system 100 while it is operating in the second operating mode. In one example, the controller 106 may be configured to transmit state information to the hardware circuit 102. The first mode state information 120 may include values that program the state of the hardware circuit 102 state machine (e.g., a state machine that uses state operation information 132). For example, the controller 106 may be configured to transmit second mode state information 126 to state operation information 132.
[0023] After receiving information related to the second operation mode, the hardware circuit 102 may start operating in the second operation mode. In one example, the hardware circuit 102 may wait until a signal (e.g., a signal from the controller 106) triggers the hardware circuit 102 to start operating in the second operation mode. In one example, the second operation mode may be able to start operating without having to power cycle or restart the ADC system. This can reduce the length of time required to switch from the first operation mode to the second operation mode, reduce the length of time during which the ADC system 100 is not generating a usable output (e.g., calibrated analog-to-digital conversion), or both. This can then help improve the continuity or reduce the instability of the system in which the ADC system 100 is employed.
[0024] In one example, the controller 106 may be configured to operate in the second operation mode and configure the hardware circuit 102 to record calibration information 124 for the second mode, such as at startup. Alternatively or in addition, the controller 106 may be configured to operate in the first operation mode and configure the hardware circuit 102 to record calibration information 118 for the first mode, such as at startup. In this example, the ADC system 100 may place valid calibration data in one or more of the calibration information 118 for the first mode or the calibration information 124 for the second mode at startup, which can enable the ADC system 100 to switch between modes without requiring recalibration during operation.
[0025] For example, the ADC system 100 can repeatedly (for example, periodically) recalibrate its operating mode. This may include repeatedly updating the calibration operation information 130. The ADC system 100 can write this updated calibration operation information 130 to the corresponding operating mode. For example, when the first operating mode is in operation, the calibration operation information 130 can be written to the calibration information 118 for the first mode. When the second operating mode is in operation, the calibration operation information 130 can be written to the calibration information 124 for the second mode. This allows for repeated updates of the calibration information stored in the firmware of the operating mode.
[0026] In one example, an operating mode (e.g., a second operating mode) may not be used for a certain period of time, during which the stored calibration values may become outdated (e.g., the stored calibration values no longer provide the specified level of accuracy and / or precision due to changes in the hardware circuit 102 (e.g., drift)). In one example, the ADC system 100 can switch to an unused operating mode (e.g., a second operating mode), perform a calibration, and write the calibration values to the firmware (e.g., perform a calibration while operating in the second operating mode and write the values from the calibration operation information 130 to the calibration information 124 for the second mode). In one example, this can be done without using any of the outputs from the ADC system 100 while operating in the second operating mode in a post-calibration activity (e.g., no post-calibration analog-to-digital conversion occurs during the second operating mode). For example, the calibration values for the second operating mode may become outdated, for example, because the first operating mode is the desired operating mode for a specified period of time. The ADC system 100 can switch to a second operating mode (for example, during downtime of the first operating mode, such as when analog-to-digital conversion is not desired), update the calibration values for the second operating mode (for example, without using arbitrary values in post-calibration activities), and then return to the first operating mode to begin generating values for post-calibration activities (for example, after the downtime has ended).
[0027] For example, the ADC system 100 may include an interleaving ADC. The interleaving ADC may include two or more interleaving slices (e.g., each containing an ADC), which may operate in parallel, for example, with a timing offset. This can increase the sampling rate of the interleaving ADC. However, calibration information, such as that relating to timing mismatch, gain error, or offset difference, may be used to calibrate the interleaving ADC.
[0028] In an example where the ADC system 100 includes an interleaving ADC, the first operating mode may include a continuous operating mode. In continuous operating mode, interleaving slices can be sampled sequentially (for example, for an ADC operating on four interleaving slices, 1, 2, 3, 4, 1, 2, 3, 4, etc.). In one example, the second operating mode may include a random or pseudo-random operating mode (for example, interleaving slice sampling in a random manner or in a pseudo-random manner (for example, configured to appear random but following a specified order)).
[0029] The first operating mode (e.g., continuous operating mode) may have a higher signal-to-noise ratio than the second operating mode. The second operating mode (e.g., random or pseudo-random operating mode) may have a smaller spur in the operating spectrum (e.g., a frequency range with non-uniform gains) than the first operating mode. It may be desirable to operate in the first operating mode when a higher signal-to-noise ratio is specified, and to operate in the second operating mode when a smaller spur is desired, or both.
[0030] In one example, the first operating mode includes a continuous operating mode, and the second operating mode includes a continuous operating mode having a different number of interleaving slices than the first operating mode. In one example, the first operating mode may have more interleaving slices than the second operating mode. In this example, the first operating mode may have a higher sampling rate than the second operating mode. In this example, the second operating mode may have a higher signal-to-noise ratio than the first operating mode.
[0031] For example, the first operating mode may include, alternatively or in addition to, a different timing than the second operating mode, for instance, a different number of interleaving slices. This different timing may shift the position of one or more spars in the operating spectrum, which may make it desirable to select the operating mode based on the region of interest in the operating spectrum (e.g., selecting a mode with no or reduced spars in the region of interest).
[0032] For example, the first and second operating modes may have different levels of power consumption. For instance, the second mode may have lower power consumption than the first mode, possibly due to a lower sampling rate. This could make it desirable to switch to the second mode to save energy, for example, when the characteristics of the second mode are sufficient for the task (e.g., the higher sampling rate of the first mode may not be required for all tasks).
[0033] In one example, there may be any number of operating modes, including two, three, four, or five or more operating modes. Modes can be hardwired (for example, firmware block 104 does not need to be configurable after manufacturing and may have hardcoded operating modes, such as including some or all of the configuration information 116 for a first mode, which is read-only memory, or some or all of the calibration information 118 for a first mode, which is read-only memory, or both), or they can be configurable (for example, the information in the configuration information 116 for a first mode may be changed, such as before or during execution, or the information in the calibration information 118 for a first mode may be changed, or both), which can help enable the ADC system 100 to be configured to have a specified mode and / or specified calibration information (e.g., calibrated calibration information).
[0034] Figure 2 shows a block diagram of an example of a portion of the hardware circuitry 102 that may be included in the ADC system 100. In the example in Figure 2, the hardware circuitry 102 may include an operation register 220, a storage register 230, and a latch circuit 240.
[0035] The operation register 220 can store (for example, hold) information used by the operation mode. This may include one or more of the following: configuration operation information 128, calibration operation information 130, or state operation information 132.
[0036] The memory register 230 can store information received from the firmware block 104, such as information related to mode transitions (for example, information about the second operating mode when the ADC system 100 is operating in the first operating mode). The memory register 230 can store the transferred information until the controller 106 triggers the hardware circuit 102 to start operation in the second operating mode. The memory register 230 may contain one or more of the following: configuration storage information 202, calibration storage information 204, or state storage information 206.
[0037] The latch circuit 240 may be configured to write a value from the storage register 230 to the operation register 220, for example, in response to the controller 106 triggering the hardware circuit 102 to start operating in a second mode. The latch circuit 240 may include a configuration latch 208, a calibration latch 210, and a state latch 212.
[0038] In one example, the hardware circuit 102 includes a calibration storage register which can be configured to receive calibration information 124 for a second mode. The hardware circuit 102 may also include a calibration operation register which can be configured to hold calibration operation information 130 for an operating mode. The hardware circuit 102 may include latch circuits (e.g., calibration latch 210, latch circuit 240) which may be configured to write values from the calibration storage register to the calibration operation register, for example, when the controller triggers the hardware circuit 102 to start operating in a second operating mode.
[0039] Figure 3 shows a timing diagram of an example of the operating portion of the ADC system 100. Figure 3 shows that the transition from the first operating mode to the second operating mode can include a period 314 in which the first mode is operating, a period 322 in which the second mode is operating, and a transition state 318 (for example, when neither mode is operating). The mode transition can include a preparation stage 316, a transition stage 320, and a restart stage 324.
[0040] Figure 3 first shows that the ADC system 100 can operate in a first operating mode. At time 302, the ADC system 100 can begin preparing to switch modes. The operations performed in preparation stage 316 may include one or more of the following: pausing calibration, converting calibration coefficients to a stored format (e.g., lookup table values), writing stored values back to firmware block 104 (e.g., writing calibration operation information 130 to calibration information 118 for the first mode), or writing information from the second operating mode to the hardware circuit 102 (e.g., staging information, such as by writing to memory register 230). For example, before triggering the hardware circuit 102 to begin operating in the second mode, the controller 106 may consist of one or more of the following: pausing calibration in the first operating mode, or recording calibration information for the first mode, such as values to calibrate the ADC system while operating in the first operating mode. At time 304, preparation stage 316 may end.
[0041] At time 306, the transition stage 320 can be initiated. The actions performed in the transition stage 320 may include one or more of the following: latching staged information (e.g., transferring a value from the memory register 230 to the operation register 220 using the latch circuit 240), or writing a configuration to the hardware circuit 102 (e.g., writing configuration information 122 for the second mode to configuration operation information 128). For example, the hardware circuit 102 does not need to be configured to stage the configuration information; the configuration information may be written directly to the configuration operation information 128 during the transition stage 320. At time 308, the transition stage 320 can be terminated. The transition stage 320 may be initiated automatically following the preparation stage 316 (e.g., after a specified delay or without delay), or it may be triggered by the controller 106. In one example, the transition stage 320 may be initiated following the controller 106 triggering the hardware circuit 102 to start operating in the second operation mode (e.g., following the transmission of calibration information for the second mode).
[0042] At time 310, the restart stage 324 can be started. During the restart stage 324, calibration can be re-enabled. In one example, calibration can be automatically enabled during or at the end of the transition stage 320. In this example, the restart stage 324 can be omitted. The restart stage 324 can be completed at time 312.
[0043] In one example, one or more (e.g., some or all) of the registers in the hardware circuit 102 do not need to include a latch circuit. In this example, registers without latch circuits can be written directly when data is transferred, such as during the preparation stage 316 or the transition stage 320. In this example, the restart stage 324 can overlap with one or more of the transition stages 320 or transition states 318. For example, the ADC system 100 can continue to generate conversion data, which can be used by one or more systems. In one example, this data may have a specified level of precision that can be lower than a specified level of precision before and / or after a mode transition (e.g., so that one or more registers have values for a second operating mode while a first operating mode is still operating).
[0044] Figure 4 shows a block diagram of an example of a part of the ADC system 400. In one example, the ADC system 400 may be configured similarly to the ADC system 100. In one example, the ADC system 400 may differ in one or more ways.
[0045] Figure 4 shows that in the ADC system 400, the digital hardware circuit 110 may include a digital hardware circuit 402 for a first operating mode and a digital hardware circuit 404 for a second operating mode, and the analog hardware circuit 108 may include an analog hardware circuit 406 for a first operating mode and an analog hardware circuit 408 for a second operating mode, or both. In the example of Figure 4, some parts of the hardware circuit 102 can be duplicated, which can enable hardware circuits dedicated to either the first or second operating mode. For example, the digital hardware circuit 402 for the first operating mode and the digital hardware circuit 404 for the second operating mode can replace one or more of the configuration operation information 128 or the calibration operation information 130.
[0046] In this example, some of the information that was passed from the firmware block 104 to the digital hardware circuit 110 in the example of Figure 1 does not need to be passed. The digital hardware circuit 402 in the first operating mode and the analog hardware circuit 408 in the second operating mode can store mode-specific digital conversion information, which may include configuration information and data (e.g., calibration information). For example, the configuration information 116 for the first mode and the calibration information 118 for the first mode can be stored in the first operating mode digital hardware circuit 402, thereby eliminating the need to pass this information from the firmware block 104 to the hardware circuit 102. When the ADC system 400 switches from the first operating mode to the second operating mode, the hardware circuit 102 can start using the digital hardware circuit 404 and the analog hardware circuit 408 for the second operating mode, and can stop using the digital hardware circuit 402 and the analog hardware circuit 406 for the first operating mode, or both. However, the information in the digital hardware circuit 402 and / or the analog hardware circuit 406 of the first operating mode does not need to be overwritten, and the information in the digital hardware circuit 404 and / or the analog hardware circuit 408 of the second operating mode does not need to be transmitted from the firmware block 104, or both.
[0047] The analog hardware circuit 406 for the first operating mode and the analog hardware circuit 408 for the second operating mode may include mode-specific front-end circuits capable of performing one or more of sampling, filtering, or amplification. The analog hardware circuit 406 for the first operating mode may be directly linked to the digital hardware circuit 402 for the first operating mode. The analog hardware circuit 408 for the second operating mode may be directly linked to the digital hardware circuit 404 for the second operating mode.
[0048] The state operation information 132 can represent the current state of the digital hardware circuit 110. It may be desirable to hold only a single state operation information 132 (for example, since the digital hardware circuit 110 may be in only one state at a time, it may be beneficial to store and / or transmit an instruction for the current state from the firmware block 104). For example, even if the configuration registers and / or calibration registers may overlap for the first and second operating modes, one or more other parts of the digital hardware circuit 110 do not need to overlap and may be shared by the first and second operating modes.
[0049] When switching from the first operating mode to the second operating mode, the ADC system 400 may behave similarly to the ADC system 100. In one example, only state operation information 132 is written by the first mode object 112 or the second mode object 114. In one example, the operating digital hardware circuit 402 of the first operating mode or the operating digital hardware circuit 404 of the second operating mode can be selected using a "pointer" in the digital hardware circuit 110 (for example, one of the pointed-to digital hardware circuits 402 of the first operating mode or the operating digital hardware circuit 404 of the second operating mode is the one that operates). In one example, the operating analog hardware circuit 406 of the first operating mode or the operating analog hardware circuit 408 of the second operating mode can be selected using a "pointer" in the digital hardware circuit 110. In this way, configuration information and / or calibration information does not need to be passed from the firmware block 104 to switch modes.
[0050] In one example, hardware circuit 102 can periodically transmit information between the first mode object 112 and the digital hardware circuit 402 and / or the analog hardware circuit 406 of the first operating mode. In another example, hardware circuit 102 can periodically transmit information between the second mode object 114 and the digital hardware circuit 404 and / or the analog hardware circuit 408 of the second operating mode. For example, firmware block 104 can transmit information to digital hardware circuit 110 after the configuration of the first operating mode and / or the second operating mode has been specified.
[0051] Figure 5 shows an example of a portion of method 500 for operating an ADC system, such as ADC system 100. Method 500 may be a method for switching between a first operating mode and a second operating mode of an analog-to-digital converter (ADC). One or more of the first and second operating modes may include a calibrated analog-to-digital conversion. The hardware circuit configuration for the second operating mode may differ from the hardware circuit configuration for the first operating mode.
[0052] In step 502, configuration information for the second mode and / or calibration information for the second mode can be transmitted to the ADC hardware circuit. The configuration information for the second mode may include values for configuring the hardware circuit to operate in the second operating mode. The calibration information for the second mode may include values for calibrating the ADC while it is operating in the second operating mode. The hardware circuit may include hardware circuit 102. The configuration information for the second mode may be transmitted to configuration operation information 128. The calibration information for the second mode may be transmitted to calibration operation information 130.
[0053] In step 504, the hardware circuit can be triggered to start operating in the second operating mode. For example, a controller (e.g., controller 106) can trigger the hardware circuit 102 to start operating in the second operating mode. This may include sending the configuration information and calibration information for the second mode, and then waiting until a "switch" signal is received before triggering the hardware circuit and starting to operate in the second operating mode.
[0054] For example, calibration in the first operating mode can be paused, such as before switching to the second operating mode. Calibration information for the first mode can be recorded, including values for calibrating the ADC while operating in the first operating mode.
[0055] For example, data generated by the ADC while operating in the second operating mode can be discarded (e.g., not used by an external system or for post-calibration operation). Calibration in the second operating mode can be paused. Configuration information for the first mode and / or calibration information for the first mode can be transmitted to the hardware circuitry. The hardware circuitry can be triggered to start operating in the first operating mode.
[0056] For example, the ADC may include an interleaving ADC. The first operating mode may include a continuous operating mode. The second operating mode may include a random or pseudo-random operating mode. The method may switch to the second operating mode when an operating spectrum with smaller spars is specified. The method may switch to the first operating mode when a higher signal-to-noise ratio is specified.
[0057] The order of the steps shown is not intended to be restrictive to the order in which the steps are performed. In one example, two or more steps may be performed simultaneously, or at least partially simultaneously.
[0058] Figure 6 illustrates a block diagram of an exemplary machine 600 in which any one or more of the techniques (e.g., methodologies) discussed herein may be implemented. As described herein, the example may include, or be operated by, logic or several components or mechanisms within the machine 600. A circuit (e.g., a processing circuit) is a set of circuits implemented in the tangible entities of the machine 600, including hardware circuits (e.g., simple circuits, gates, logic, etc.). The membership of a circuit may be flexible over time. A circuit includes members that can perform specified operations, either individually or in combination, at the time of operation. In one example, the hardware circuit of a circuit may be designed immutably to perform a specific operation (e.g., hardwired). In one example, the hardware circuit of a circuit may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) that include a machine-readable medium that is physically modified (e.g., magnetic, electrical, movable arrangement of immutable mass particles, etc.) to encode instructions for a specific operation. When connecting physical components, the electrical properties underlying the hardware circuit components are changed, for example, from an insulator to a conductor, or vice versa. Instructions allow embedded hardware circuits (e.g., execution units or load mechanisms) to create members of the circuit within the hardware circuit via variable connections to perform specific parts of operation during operation. Thus, in one example, a machine-readable medium element is part of a circuit or is communicatively coupled to other components of the circuit when the device is operating. In one example, any one of the physical components may be used in two or more members of two or more circuits. For example, during operation, an execution unit may be used in a first circuit of a first circuit mechanism at one point and reused by a second circuit of the first circuit mechanism, or reused by a third circuit of a second circuit mechanism at a different point in time. Additional examples of these components relating to machine 600 are as follows:
[0059] In alternative examples, machine 600 may operate as a standalone device or be connected to other machines (e.g., networked). In a networked deployment, machine 600 may operate as a server machine, a client machine, or both in a server-client network environment. For example, machine 600 may function as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. Machine 600 may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, web appliance, network router, switch or bridge, or any machine capable of executing instructions (sequentially or otherwise) specifying actions to be performed by that machine. Furthermore, although only a single machine is illustrated, the term “machine” should also be interpreted to include any set of machines individually or collectively executing a set (or set) of instructions to implement one or more of the methodologies considered herein, such as cloud computing, software as a service (SaaS), and other computer cluster configurations.
[0060] Machine 600 may include a hardware circuit processor 602 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware circuit processor core, or any combination thereof), main memory 604, static memory (e.g., memory or storage for firmware, microcode, basic input / output (BIOS), and mass storage 608 (e.g., a hard drive, tape drive, flash storage, or other block device), some or all of which may communicate with each other via an interlink 630 (e.g., a bus). Machine 600 may also include a display unit 610, an alphanumeric input device 612 (e.g., a keyboard), and a user interface (UI) navigation device 6 14 may further include (e.g., a mouse). In one example, the display unit 610, input device 612, and UI navigation device 614 may be touchscreen displays. The machine 600 may additionally include a signal generating device 618 (e.g., a speaker), a network interface device 620, and one or more sensors 616 such as a Global Positioning System (GPS) sensor, compass, accelerometer, or other sensor. The machine 600 may include an output controller 628 for communicating with or controlling one or more peripheral devices (e.g., a printer, a card reader, etc.) via a serial (e.g., Universal Serial Bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near-field communication (NFC), etc.) connection).
[0061] The registers of processor 602, main memory 604, static memory 606, or mass storage 608 may be, or include, a machine-readable medium 622 in which one or more sets of data structures or instructions 624 (e.g., software) are stored, which are embodied or utilized by one or more of the technologies or functions described herein. The instructions 624 may also reside, all or at least partially, in the registers of processor 602, main memory 604, static memory 606, or mass storage 608 during their execution by machine 600. In one example, one or any combination of hardware circuitry processor 602, main memory 604, static memory 606, or mass storage 608 may constitute a machine-readable medium 622. Although machine-readable medium 622 is illustrated as a single medium, the term “machine-readable medium” may include one or more mediums configured to store one or more instructions 624 (e.g., centralized or distributed databases, and / or associated caches and servers).
[0062] The term “machine-readable medium” may include any medium capable of storing, encoding, or carrying instructions for execution by machine 600, causing machine 600 to perform one or more of the technologies of the Disclosure, or storing, encoding, or carrying data structures used by or associated with such instructions. Examples of non-limiting machine-readable mediums may include solid-state memory, optical media, magnetic media, and signals (e.g., radio frequency signals, other photon-based signals, audio signals, etc.). In one example, a non-transient machine-readable medium includes a machine-readable medium having a plurality of particles having an immutable (e.g., stationary) mass, and is therefore a composition of a substance. Thus, a non-transient machine-readable medium is a machine-readable medium that does not contain transient propagating signals. Specific examples of non-transient machine-readable mediums may include semiconductor memory devices (e.g., non-volatile memory such as electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and flash memory devices), magnetic disks such as internal hard disks and removable disks, magneto-optical disks, and CD-ROM and DVD-ROM disks.
[0063] For example, information stored on or otherwise provided on machine-readable medium 622 may represent instruction 624 itself or instruction 624 in a format from which instruction 624 can be derived. This format from which instruction 624 can be derived may include source code, encoded instructions (e.g., in a compressed or encrypted form), packaged instructions (e.g., divided into multiple packages), etc. Information representing instruction 624 in machine-readable medium 622 may be processed into instructions by a processing circuit to implement any of the operations considered herein. For example, deriving instruction 624 from information (e.g., processing by a processing circuit) may include compiling (e.g., from source code, object code, etc.), interpreting, reading, organizing (e.g., dynamically or statically linking), encoding, decoding, encrypting, decrypting, packaging, unpackaging, or otherwise manipulating the information into instruction 624.
[0064] For example, the derivation of instruction 624 may involve assembling, compiling, or interpreting information for creating instruction 624 from several intermediate or pre-processed formats provided by a machine-readable medium 622 (e.g., by a processing circuit). If the information is provided in multiple parts, it may be combined, unpacked, and modified to create instruction 624. For example, the information may be in multiple compressed source code packages (or object code, or binary executable code, etc.) on one or more remote servers. The source code packages may be encrypted in transit over the network, decrypted as needed, uncompressed, assembled (e.g., linked), compiled or interpreted on the local machine (e.g., into a library, a standalone executable, etc.), and executed by the local machine.
[0065] Instruction 624 may be further transmitted or received via the communication network 626 using a transmission medium through the network interface device 620, utilizing one of several transport protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.). Illustrative communication networks may include, among others, local area networks (LANs), wide area networks (WANs), packet data networks (e.g., the Internet), LoRa / LoRaWAN, or satellite communication networks, mobile phone networks (e.g., cellular networks such as those conforming to 3G, 4G LTE / LTE-A, or 5G standards), plain-old telephone (POTS) networks, and wireless data networks (e.g., Wi-Fi®, the IEEE 802.15.4 standard family, and the IEEE 802.11 family of standards known as peer-to-peer (P2P) networks). For example, the network interface device 620 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas for connecting to the communication network 626. For example, the network interface device 620 may include multiple antennas for wireless communication using at least one of the following technologies: single input multiple output (SIMO), multiple input multiple output (MIMO), or multiple input single output (MISO). The term “transmission medium” is considered to include any intangible medium capable of storing, encoding, or carrying instructions for execution by machine 600, and including digital or analog communication signals or other intangible mediums for facilitating communication of such software. The transmission medium is a machine-readable medium.
[0066] The following non-limiting embodiments will detail specific aspects of the subject matter, in particular, to solve the problems and provide the advantages discussed herein.
[0067] Examples: Embodiment 1 is an analog-to-digital converter (ADC) system for switching between a first operating mode and a second operating mode, wherein both the first and second operating modes include calibrated analog-to-digital conversion, the hardware circuit configuration of the second operating mode differs from the hardware circuit configuration of the first operating mode, the ADC system comprises a hardware circuit and a controller, the controller being configured to control the hardware circuit and control the switching between the first and second operating modes in response to a command to switch from the first operating mode to the second operating mode, and transmitting configuration information for the second operating mode and calibration information for the second mode to the hardware circuit, wherein the calibration information for the second operating mode includes values for configuring the hardware circuit to operate in the second operating mode, and the calibration information for the second operating mode includes values for calibrating the ADC system while operating in the second operating mode.
[0068] In Embodiment 2, the subject of Embodiment 1 optionally includes the configuration that, following the transmission of calibration information for the second mode, the controller is configured to trigger hardware circuitry to initiate operation in the second operating mode.
[0069] In Embodiment 3, the subject of Embodiment 2 optionally includes configuring the controller to pause the calibration of the first operating mode before triggering the hardware circuit to start operating in the second mode, and to record calibration information for the first mode, including values for calibrating the ADC system, while operating in the first operating mode.
[0070] In Embodiment 4, the subject of Embodiment 3 optionally includes a hardware circuit comprising: a calibration storage register configured to receive calibration information for a second mode; a calibration operation register configured to hold calibration information for an operating mode; and a latch circuit configured to write a value from the calibration storage register to the calibration operation register when a controller triggers the hardware circuit to start operating in the second operating mode.
[0071] In Example 5, one or more of the themes from Examples 2 to 4 optionally include a second operating mode in which the ADC system starts operating without requiring a power cycle or restart.
[0072] In Example 6, one or more of the themes from Examples 1 to 5 optionally include that the ADC system includes an interleaving ADC, a first operating mode includes a continuous operating mode, and a second operating mode includes a random or pseudo-random operating mode.
[0073] In Example 7, the subject of Example 6 optionally includes, in use, that the first operating mode has a higher signal-to-noise ratio than the second operating mode, and the second operating mode has smaller spars in the operating spectrum than the first operating mode.
[0074] In Example 8, one or more of the themes from Examples 1 to 7 optionally include an ADC system that includes an interleaving ADC, a first operating mode that includes a continuous operating mode, and a second operating mode that includes a continuous operating mode having a different number of interleaving slices than the first operating mode.
[0075] In Example 9, the subject of Example 8 optionally includes the first operating mode having more interleaving slices than the second operating mode, and the first operating mode having a higher sampling rate than the second operating mode.
[0076] In Example 10, the subject of Example 9 optionally includes the condition that the second operating mode has a higher signal-to-noise ratio than the first operating mode.
[0077] In Example 11, one or more of the themes from Examples 1 to 10 optionally include a controller configured to transmit state information to a hardware circuit, wherein the state information includes values for programming the state of the hardware circuit state machine.
[0078] In Example 12, one or more of the themes from Examples 1 to 11 optionally include being configured to, at startup, configure the controller to operate the hardware circuit in a second operating mode and record calibration information for the second mode, and configure the hardware circuit to operate in a first operating mode and record calibration information for the first mode.
[0079] Embodiment 13 is a method for switching between a first operating mode and a second operating mode of an analog-to-digital converter (ADC), wherein both the first and second operating modes include calibrated analog-to-digital conversion, the hardware circuit configuration of the second operating mode differs from the hardware circuit configuration of the first operating mode, the method comprising transmitting configuration information for the second mode and calibration information for the second mode to the hardware circuit of the ADC, wherein the configuration information for the second mode includes values for configuring the hardware circuit to operate in the second operating mode, and the calibration information for the second mode includes values for calibrating the ADC while it is operating in the second operating mode, and triggering the hardware circuit to start operating in the second mode.
[0080] In Example 14, the subject of Example 13 optionally includes, following the transmission of configuration information for the second mode and calibration information for the second mode, triggering a hardware circuit and waiting until a “switch” signal is received before initiating operation in the second operating mode.
[0081] In Example 15, one or more of the themes from Examples 13 to 14 optionally include pausing the calibration of the first operating mode and recording calibration information for the first mode, including values for calibrating the ADC while it is operating in the first operating mode.
[0082] In Example 16, the subject of Example 15 optionally includes discarding data generated by the ADC while operating in the second operating mode, pausing the calibration of the second operating mode, transmitting configuration information and calibration information of the first mode to the hardware circuit, and triggering the hardware circuit to start operating in the first operating mode.
[0083] In Example 17, one or more of the themes from Examples 13 to 16 optionally include the following: the ADC includes an interleaving ADC, the first operating mode includes a continuous operating mode, and the second operating mode includes a random or pseudo-random operating mode.
[0084] In Example 18, the subject of Example 17 optionally includes switching to a second operating mode when an operating spectrum with smaller spars is specified, and switching to a first operating mode when a higher signal-to-noise ratio is specified.
[0085] Embodiment 19 is an analog-to-digital converter (ADC) system for switching between a first operating mode and a second operating mode, wherein both the first and second operating modes include calibrated analog-to-digital conversion, the hardware circuit configuration of the second operating mode differs from the hardware circuit configuration of the first operating mode, the ADC system comprises a hardware circuit and a controller, the controller being configured to control the hardware circuit to switch from the first operating mode to the second operating mode in response to a command, and transmitting configuration information for the second mode and calibration information for the second mode to the hardware circuit, wherein the configuration information for the second mode includes values for configuring the hardware circuit to operate in the second operating mode, and the calibration information for the second mode includes values for calibrating the ADC system while operating in the second operating mode, the hardware circuit includes a calibration memory register configured to receive the calibration information for the second mode, and a calibration operation register configured to hold calibration information for the operating mode.
[0086] In Example 20, the subject of Example 19 is configured such that the controller transmits state information to a hardware circuit, optionally including that the state information includes values for programming the state of the hardware circuit state machine.
[0087] Example 21 is at least one machine-readable medium that, when executed by the processing circuit, contains instructions causing the processing circuit to perform an operation for any implementation of Examples 1 to 20.
[0088] Example 22 is an apparatus that includes means for mounting any of Examples 1 to 20.
[0089] Example 23 is a system for implementing any of Examples 1 to 20.
[0090] Example 24 is a method for implementing any of Examples 1 to 20.
[0091] Each of the above non-limiting embodiments may assert itself, be combined in various substitutions, or be combined with one or more other embodiments or other subjects described herein.
[0092] The above detailed description includes references to accompanying drawings that form part of the detailed description. The drawings illustrate specific examples that may be implemented. These embodiments are also referred to herein as “Examples.” Such examples may include elements in addition to those illustrated or described. However, the inventors also intend examples in which only these illustrated or described elements are provided. Furthermore, the inventors also intend examples (or one or more embodiments thereof) using any combination or permutation of these illustrated or described elements, with respect to a particular example (or one or more embodiments thereof) or to other examples (or one or more embodiments thereof) illustrated or described herein.
[0093] All publications, patents, and patent documents referenced herein are incorporated herein by reference in whole, as if they were individually incorporated by reference. In the event of any inconsistency in usage between this document and those documents incorporated by reference, the usage in the incorporated reference should be considered to complement the usage in this document, and in the event of any irreconcilable contradiction, the usage in this document shall prevail.
[0094] In this document, the terms “a” or “an” are used to include one or more, regardless of other examples or uses of “at least one” or “one or more,” as is common in patent documents. In this document, the terms “or” and “and / or” are used to refer to non-exclusive “or” such that “A or B” includes “A but not B,” “B but not A,” and “A and B.” In the attached claims, the terms “including” and “in which” are used as plain English equivalents of the terms “comprising” and “wherein,” respectively. Furthermore, in the following claims, the terms “including” and “comprising” are unrestrictive; that is, any system, device, article, or process containing elements in addition to those enumerated after such terms in a claim is still considered to be within the scope of that claim. Furthermore, in the following claims, terms such as “first,” “second,” and “third” are used merely as symbols and are not intended to impose numerical requirements on their respective subjects.
[0095] The term "about," as used herein, means approximately, in the region of, roughly, or around. When the term "about" is used in conjunction with a numerical range, it modifies that range by extending the upper and lower boundaries of the numerical value being described. Generally, the term "about" is used herein to modify a numerical value that is above or below the stated value with a 10% variance. In one aspect, the term "about" means plus or minus 10% of the numerical value of the number in which it is used. Thus, about 50% means the range of 45% to 55%. Numerical ranges enumerated herein by endpoints include all numbers and fractions contained within that range (for example, 1 to 5 includes 1, 1.5, 2, 2.75, 3, 3.90, 4, 4.24, and 5). Similarly, the numerical ranges enumerated herein by an endpoint include subranges that are contained within that range (for example, 1 to 5 includes 1 to 1.5, 1.5 to 2, 2 to 2.75, 2.75 to 3, 3 to 3.90, 3.90 to 4, 4 to 4.24, 4.24 to 5, 2 to 5, 3 to 5, 1 to 4, and 2 to 4).
[0096] Examples of methods described herein can be implemented in machine or computer, at least in part. Some examples may include computer-readable or machine-readable media encoded with instructions that can be operated to configure an electronic device to carry out the methods described in the above examples. Implementations of such methods may include code, such as microcode, assembly language code, high-level language code, etc. Such code may include computer-readable instructions for carrying out various methods. The code may form part of a computer program product. Such instructions may be read and executed by one or more processors, for example, to enable the performance of an operation including the method. Instructions may be in any preferred form, but are not limited to source code, compiled code, interpreted code, executable code, static code, dynamic code, etc.
[0097] Furthermore, in one example, the code may be explicitly stored on one or more volatile, non-temporary, or non-volatile tangible computer-readable media during execution or at some other point in time. Examples of these tangible computer-readable media include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact discs, digital video discs), magnetic cassettes, memory cards or sticks, random-access memory (RAM), and read-only memory (ROM).
[0098] The above description is intended to be illustrative and not restrictive. For example, the examples described above (or one or more of their embodiments) may be used in combination with each other. Other examples may be used by those skilled in the art, for example, by considering the above description. The abstract is submitted with the understanding that it is intended to allow the reader to quickly confirm the nature of the technical disclosure and is not to be used to interpret or limit the claims or their meaning. Also, in the forms for carrying out the invention described above, various features may be grouped together to streamline the disclosure. This should not be interpreted as meaning that any disclosed features not claimed are essential to any claim. Rather, the subject matter of the invention may lie in fewer features than all the features of a particular disclosed embodiment. Accordingly, the following claims are incorporated into the forms for carrying out the invention, and each claim stands independently as a separate embodiment. The scope of the embodiments should be determined by referring to the appended claims, along with the entire scope of equivalents to which such claims are entitled.
Claims
1. An analog-to-digital converter (ADC) system for switching between a first operating mode and a second operating mode, wherein both the first and second operating modes include calibrated analog-to-digital conversion, and the hardware circuit configuration of the second operating mode differs from the hardware circuit configuration of the first operating mode, and the ADC system Hardware circuitry and The system comprises a controller, wherein the controller is configured to control the hardware circuitry and, in response to a command to switch from the first operating mode to the second operating mode, control the switching between the first operating mode and the second operating mode. Transmitting configuration information for a second mode and calibration information for a second mode to the hardware circuit, wherein the configuration information for a second mode includes values for configuring the hardware circuit to operate in the second operating mode, and the calibration information for a second mode includes values for calibrating the ADC system while it is operating in the second operating mode. An ADC system that, when analog-to-digital conversion is not desired and the first operating mode is in downtime, switches to the second operating mode, updates the calibration information for the second operating mode, and then returns to the first operating mode after the downtime has ended.
2. Following the transmission of the calibration information for the second mode, the controller: The ADC system according to claim 1, configured to trigger the hardware circuit and start operating in the second operating mode.
3. Before the hardware circuit is triggered and operation begins in the second mode, the controller: Pausing the calibration of the first operating mode, The ADC system according to claim 2, configured to record calibration information for the first mode, including values for calibrating the ADC system, while operating in the first operating mode.
4. The aforementioned hardware circuit A calibration storage register configured to receive calibration information for the second mode described above, A calibration operation register configured to hold the calibration information for the operating mode, The ADC system according to claim 3, further comprising: a latch circuit configured to write the value from the calibration storage register to the calibration operation register when the controller triggers the hardware circuit to start operating in the second operating mode.
5. The ADC system according to claim 2, wherein the second operating mode starts operation without requiring the ADC system to be powered on or restarted.
6. The ADC system includes an interleaving ADC, The first operating mode includes a continuous operating mode, The ADC system according to claim 1, wherein the second operating mode includes a random or pseudo-random operating mode.
7. In use, The first operating mode has a higher signal-to-noise ratio than the second operating mode, The ADC system according to claim 6, wherein the second operating mode has smaller spurs in the operating spectrum than the first operating mode.
8. The ADC system includes an interleaving ADC, The first operating mode includes a continuous operating mode, The ADC system according to claim 1, wherein the second operating mode includes a continuous operating mode having a different number of interleaving slices than the first operating mode.
9. The first operating mode includes more interleaving slices than the second operating mode, The ADC system according to claim 8, wherein the first operating mode has a higher sampling rate than the second operating mode.
10. The ADC system according to claim 9, wherein the second operating mode has a higher signal-to-noise ratio than the first operating mode.
11. The aforementioned controller The ADC system according to claim 1, configured to transmit state information to the hardware circuit, wherein the state information includes values for programming the state of the hardware circuit state machine.
12. At startup, the controller The hardware circuit is configured to operate in the second operating mode and to record calibration information for the second mode. The ADC system according to claim 1, wherein the hardware circuit is configured to operate in the first operating mode and to record calibration information for the first mode.
13. A method for switching between a first operating mode and a second operating mode of an analog-to-digital converter (ADC), wherein both the first and second operating modes include calibrated analog-to-digital conversion, the hardware circuit configuration of the second operating mode differs from the hardware circuit configuration of the first operating mode, and the method Transmitting configuration information for a second mode and calibration information for a second mode to the hardware circuit of the ADC, wherein the configuration information for a second mode includes values for configuring the hardware circuit to operate in the second operating mode, and the calibration information for a second mode includes values for calibrating the ADC while it is operating in the second operating mode. A method comprising triggering the hardware circuit to start operation in the second operating mode, switching to the second operating mode and updating the calibration information of the second operating mode when analog-to-digital conversion is not desired and the first operating mode is in downtime, and then switching back to the first operating mode after the downtime has ended.
14. The method according to claim 13, comprising, following the transmission of the configuration information for the second mode and the calibration information for the second mode, triggering the hardware circuit and waiting until a “switch” signal is received before starting to operate in the second operating mode.
15. Pausing the calibration of the first operating mode, The method according to claim 13, comprising recording calibration information for a first mode, including a value for calibrating the ADC while it is operating in the first operating mode.
16. Discard the data generated by the ADC while operating in the second operating mode, Pausing the calibration of the second operating mode, Transmitting configuration information of the first mode and calibration information of the first mode to the hardware circuit, The method according to claim 15, comprising triggering the hardware circuit to start operation in the first operating mode.
17. The ADC includes an interleaving ADC, The first operating mode includes a continuous operating mode, The method according to claim 13, wherein the second operating mode includes a random or pseudo-random operating mode.
18. Switching to the second operating mode when an operating spectrum with smaller spars is specified, The method according to claim 17, comprising switching to the first operating mode when a higher signal-to-noise ratio is specified.
19. An analog-to-digital converter (ADC) system for switching between a first operating mode and a second operating mode, wherein both the first and second operating modes include calibrated analog-to-digital conversion, and the hardware circuit configuration of the second operating mode differs from the hardware circuit configuration of the first operating mode, and the ADC system Hardware circuitry and The system comprises a controller, the controller being configured to control the hardware circuitry and, in response to a command to switch from the first operating mode to the second operating mode, control the switching between the first operating mode and the second operating mode. Transmitting configuration information for a second mode and calibration information for a second mode to the hardware circuit, wherein the configuration information for a second mode includes values for configuring the hardware circuit to operate in the second operating mode, and the calibration information for a second mode includes values for calibrating the ADC system while it is operating in the second operating mode. When analog-to-digital conversion is not desired and the first operating mode is in downtime, the ADC system switches to the second operating mode and updates the calibration information for the second operating mode, and then, after the downtime ends, returns to the first operating mode. The aforementioned hardware circuit A calibration storage register configured to receive calibration information for the second mode described above, An ADC system including a calibration operation register configured to hold the calibration information for an operating mode.
20. The aforementioned controller The ADC system according to claim 19, configured to transmit state information to the hardware circuit, wherein the state information includes values for programming the state of the hardware circuit state machine.