Display panel and display device including the same

Abstract

To provide a display panel and a display device including the same.SOLUTION: Disclosed are a display panel including a plurality of pixels and a gate line and data line connected to the plurality of pixels, and a display device including the display panel. The plurality of pixels include: a 1-1th subpixel and a 1-2th subpixel of a first color; a 2-1th subpixel and a 2-2th subpixel of a second color; and a 3-1th subpixel and a 3-2th subpixel of a third color. The 2-1th subpixel and the 2-2th subpixel respectively include a luminous element and a compensation circuit, and the compensation circuit of the 2-1th subpixel and the compensation circuit of the 2-2th subpixel are connected to one data line.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present invention relates to a display panel and a display device including the same.

Background Art

[0002] An organic light-emitting display device causes an organic light-emitting diode (OLED) arranged for each pixel to emit light in accordance with an input video signal to reproduce an image. The organic light-emitting display device has a fast pixel response speed, high luminous efficiency, high brightness, and a large viewing angle, and can express a black gradation as complete black, so it has excellent contrast ratio and color reproducibility. Such an organic light-emitting display device does not require a backlight unit.

[0003] Recently, a micro display device that uses an LED (Light Emitting Diode), which is an inorganic light-emitting element, manufactured in a micro size of about 100 μm or less as a light-emitting element of a pixel has attracted attention as a next-generation display device. Since an LED is made of an inorganic substance, a separate encapsulation layer for protecting an organic substance from moisture is not required, and it has higher reliability and a longer lifespan than an OLED. In addition, an LED has a fast lighting speed, excellent luminous efficiency, and impact resistance.

[0004] In such a micro display device, since two LEDs are arranged in parallel in one subpixel, if a short circuit failure occurs in any one of them and it becomes a dark spot, there is a problem that the remaining LEDs also become dark spots.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The present invention provides a display panel and a display device including the same, in which even if any one light-emitting element among a plurality of subpixels becomes a dark spot, the remaining light-emitting elements can emit light.

[0006] Furthermore, the present invention provides a display panel and a display device including the same, which can repair light-emitting elements.

[0007] The problems addressed by the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0008] A display panel according to one feature of the present invention includes a plurality of pixels and gate lines and data lines connected to the plurality of pixels, wherein the plurality of pixels include a first-1 subpixel and a first-2 subpixel of the first color; a second-1 subpixel and a second-2 subpixel of the second color; and a third-1 subpixel and a third-2 subpixel of the third color, wherein the second-1 subpixel and the second-2 subpixel each include a light-emitting element and a compensation circuit, and the compensation circuit of the second-1 subpixel and the compensation circuit of the second-2 subpixel are connected to a single data line.

[0009] According to the present invention, even if one of the multiple subpixel light-emitting elements becomes dark, the remaining light-emitting elements can still emit light. Therefore, the number of darkened light-emitting elements in the display device can be reduced. Furthermore, low-power operation becomes possible.

[0010] Furthermore, by utilizing a pixel structure that facilitates dark-electrical improvement, it is possible to realize display panels that offer advantages in process optimization, high efficiency, high brightness, and long lifespan.

[0011] The effects of the present invention are not limited to those mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims. [Brief explanation of the drawing]

[0012] [Figure 1]Figure 1 is a block diagram schematically showing the configuration of a display device according to one embodiment of the present invention. [Figure 2] Figure 2 is a partial cross-sectional view showing pad electrodes and side wiring arranged around the outer casing of a display panel according to one embodiment of the present invention. [Figure 3] Figure 3 is a perspective view showing a tiling display device according to one embodiment of the present invention. [Figure 4] Figure 4 is a plan view showing the planar structure of a display panel according to one embodiment of the present invention. [Figure 5] Figure 5 is a cross-sectional view showing the cross-sectional structure of a display panel according to one embodiment of the present invention. [Figure 6] Figure 6 shows a pixel structure according to one embodiment of the present invention. [Figure 7] Figure 7 shows a red subpixel according to one embodiment of the present invention. [Figure 8] Figure 8 shows a green subpixel according to one embodiment of the present invention. [Figure 9] Figure 9 shows a blue subpixel according to one embodiment of the present invention. [Figure 10] Figure 10 shows the cathode electrodes of the red subpixel, green subpixel, and blue subpixel. [Figure 11] Figure 11 is a schematic circuit diagram showing a pixel circuit according to one embodiment of the present invention. [Figure 12] Figure 12 is a circuit diagram showing a pixel circuit according to another embodiment of the present invention. [Figure 13] Figure 13 is a waveform diagram of a pixel circuit according to another embodiment of the present invention. [Figure 14] Figure 14 shows a pixel where subpixels are connected in parallel. [Figure 15] Figure 15 shows the subpixels of Figure 14. [Figure 16] Figure 16 shows a method for repairing a display panel according to one embodiment of the present invention. [Figure 17]FIG. 17 is a diagram showing a method for repairing a display panel according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Advantages and features of the invention disclosed in this specification, and methods for achieving them, will become clear by referring to the embodiments described in detail below together with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but can be embodied in various different forms. Merely, the embodiments are provided so that the disclosure of the present invention is complete, and to fully inform those with ordinary knowledge in the technical field to which the present invention pertains of the scope of the invention. The present invention is only defined by the scope of the claims.

[0014] In explaining the present invention, when it is determined that a specific explanation of related known technologies will obscure the gist of the present invention, the detailed explanation thereof will be omitted.

[0015] When terms such as "comprising," "including," "having," "consisting of," etc., mentioned in this specification are used, unless "only" is used, other parts can be added. When a component is expressed in the singular, it can be interpreted as plural unless there are specifically explicit descriptions.

[0016] When the positional relationship and the mutual connection relationship between two components are described, such as "above," "on top of," "below," "on the side of," "connected or coupled (connect, couple)," "crossing," "intersecting," etc., unless there are mentions such as "immediately" or "directly," one or more other components can be interposed between those components.

[0017] When the temporal sequence relationship is described, such as "after," "subsequent to," "next," "before," etc., unless "immediately" or "directly" is used, it may not be continuous on the time axis.

[0018] While terms like "first," "second," etc., may be used to distinguish between components, the function and structure of these components are not restricted by the ordinal numbers preceding them or by the names of the components.

[0019] The following embodiments can be partially or entirely combined or linked with one another, allowing for various technical interlocking and driving mechanisms. Each embodiment can be implemented independently of the others, or they can be implemented together in a related manner.

[0020] In embodiments of the present invention, the pixel and display panel driving circuit include a transistor. The transistor is a three-electrode element including a gate, a source, and a drain. The source is the electrode that supplies carriers to the transistor. Within the transistor, carriers flow out from the source. The drain is the electrode through which carriers exit the transistor. In the transistor, the carrier flow is from the source to the drain. In the case of an n-channel transistor, since the carriers are electrons, the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain. In the n-channel transistor, the direction of current is from the drain to the source. In the case of a p-channel transistor, since the carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In the p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed depending on the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following explanation, the source and drain of the transistor will be referred to as the first and second electrodes.

[0021] The gate signal can swing between the gate-on voltage and the gate-off voltage. A transistor turns on in response to the gate-on voltage and turns off in response to the gate-off voltage. For an n-channel transistor, the gate-on voltage can be the gate-high voltage (VGH) and the gate-off voltage can be the gate-low voltage (VGL). For a p-channel transistor, the gate-on voltage can be the gate-low voltage (VGL) and the gate-off voltage can be the gate-high voltage (VGH).

[0022] In the embodiments of the present invention, the term "line" can be interpreted as a wire to which a signal or voltage is applied.

[0023] Terms used in embodiments of the present invention (including technical and scientific terms) may be interpreted as generally understood by a person of ordinary skill in the art to which the present invention pertains, unless otherwise clearly defined and described. Terms that are commonly used, such as those defined in dictionaries, may be interpreted in consideration of their meaning in the context of the relevant art.

[0024] Preferred embodiments of the present invention will be described in detail below with reference to the attached drawings.

[0025] Referring to Figure 1, the display device 100 includes a display panel PN in which multiple pixels are arranged in a display area AA, and a display panel driving circuit for driving the pixels.

[0026] The display panel PN may, but is not limited to, be a rectangular panel having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. A pixel contains multiple subpixels SP with different colors. In the display panel PN, the display area AA on which the input video is displayed may be the screen visible from the front of the display panel PN.

[0027] The display panel drive circuit includes a data drive unit DD, a gate drive unit GD, and a timing controller TC that controls the gate drive unit GD and the data drive unit DD.

[0028] The input image is displayed in the subpixels SP located in the display area AA of the display panel PN. Each subpixel SP includes a light-emitting element and a pixel circuit that drives the light-emitting element. The light-emitting element may be an LED (Light-emitting Diode) or a micro-LED (Micro Light-emitting Diode).

[0029] On the display panel PN, multiple gate lines SL and multiple data lines DL are arranged to intersect with each other. Each subpixel SP is connected to a gate line SL and a data line DL. Power supply wiring, which is omitted in Figure 1, may be connected to each subpixel SP. On the display panel PN, a non-display area NA may be located outside the display area AA.

[0030] The gate drive unit GD supplies a gate signal to the gate line SL in response to a gate control signal provided by the timing controller TC. The gate drive unit GD may be located in at least the non-display area NA of the display panel PN, or within the display area AA, as shown in Figure 1.

[0031] The data drive unit DD responds to the data control signal provided by the timing controller TC by converting the video data received from the timing controller TC into a gamma-compensated voltage and outputting a data voltage. The data voltage output from the data drive unit DD is supplied to the data line DL.

[0032] The timing controller TC aligns the video data input from an external source and supplies it to the data drive unit DD. Based on timing signals synchronized with the input video signal, such as a dot clock signal, a data enable signal, and horizontal / vertical synchronization signals, the timing controller TC can generate gate control signals and data control signals. The timing controller TC supplies the gate control signal to the gate drive unit GD and the data control signal to the data drive unit DD, thereby controlling the operating timing of the gate drive unit GD and the data drive unit DD.

[0033] The non-display area NA may contain link wiring and pad electrodes for transmitting signals to the subpixels SP of the display area AA. The non-display area NA may contain one or more of the following: a gate driver IC integrating the circuitry of the gate drive unit GD, and a data driver IC integrating the circuitry of the data drive unit DD. The non-display area NA may include the back of the display panel PN, i.e., the back without subpixels SP. The non-display area NA may be minimized to the point of being invisible when an image is displayed on the display panel PN.

[0034] The display panel drive circuit can be connected to the display panel PN in various ways to drive pixels. For example, the gate drive unit GD can be placed in the non-display area NA using the GIP (Gate In Panel) method, or it can be placed between subpixels SP in the display area AA using the GIA (Gate In Active Area) method. The data drive unit DD and timing controller TC are formed on a separate flexible film and PCB, and the terminals of the flexible film can be bonded to the pad electrodes formed in the non-display area NA of the display panel PN to electrically connect the data drive unit DD and timing controller TC to the display panel PN. The flexible film bonded to the display panel PN can be connected to a PCB (Printed Circuit Board) on which circuit elements are mounted and wiring is formed.

[0035] Side wiring can be formed on the outer side of the display panel PN to connect the signal wiring on the front of the display panel PN to the pad electrodes on the back of the display panel PN. This method of electrical connection between the front and back of the display panel PN via side wiring can minimize the non-display area NA visible from the front of the display panel PN. In Figure 2, "SRL" indicates the side wiring. When the gate drive unit GD, data drive unit DD, and timing controller TC are electrically connected to the display panel PN in the manner described above, a screen with virtually no bezel can be realized on the display panel PN.

[0036] Referring to Figure 2, the non-display area NA of the display panel PN has multiple pad electrodes arranged to transmit various signals to the subpixel SP. For example, the non-display area NA located on the front of the display panel PN may have a first pad electrode PAD1 that transmits signals to the subpixel SP. The non-display area NA located on the back of the display panel PN has a second pad electrode PAD2 that is electrically connected to circuit components such as a flexible film and PCB. The non-display area NA located on the front outer casing of the display panel PN where the image is displayed may be minimized by having only the pad area where the first pad electrode PAD1 is placed.

[0037] Various signal lines connected to the subpixel SP, such as gate line SL and data line DL, can extend into the non-display area NA and be electrically connected to the first pad electrode PAD1.

[0038] The display panel PN may include side wiring SRL located on the outer side of the display panel PN. The side wiring SRL can electrically connect a first pad electrode PAD1 located on the front outer casing of the display panel PN, which crosses the side of the display panel PN, to a second pad electrode PAD2 located on the rear outer casing of the display panel PN. Signals output from circuit components located on the rear of the display panel PN can be transmitted to the subpixel SP and gate drive unit GD in the display area AA through the second pad electrode PAD2, the side wiring SRL, and the first pad electrode PAD1. Thus, a signal transmission path can be formed across the front, side, and rear of the display panel PN's outer casing, minimizing the area of ​​the non-display area NA on the front of the display panel PN.

[0039] Multiple display modules can be combined on a plane to be realized as a large-screen tiling display device. Each display module can be realized as a single display device, and a combination of multiple display modules can be realized as a large-screen tiling display device. Each display module includes a single display panel PN, a drive circuit for the display panel PN, and circuit components and module cover members coupled to the back of the display panel PN.

[0040] Referring to Figure 3, the large-screen tiling display device TD includes multiple display modules arranged on the XY plane. Each display module includes a display panel PN that reproduces the input image. When the non-display area NA is minimized at the front outer casing of each display panel PN, a large-screen image can be reproduced between adjacent display panels PN without visible seams.

[0041] The display panels PN can be assembled on a plane such that the spacing D1 between the outermost pixel PX of one display panel PN and the outermost pixel PX of another display panel PN adjacent to that display panel PN is substantially the same as the spacing D2 between adjacent pixels PX within the display area AA of the display panel PN. As a result, the spacings D1 and D2 between pixels PX are the same across the entire display area of ​​the large screen of adjacent tiling display devices TD, and the seam area is not visible.

[0042] In a tiling display device TD, multiple display modules can share a single timing controller TC. The host system is connected to multiple timing controllers TC and can transmit video signals reproduced on all display panels PN that make up the large screen of the tiling display device TD to the timing controllers TC, thereby synchronizing the timing controllers TC.

[0043] Figure 4 is a schematic plan view showing the planar structure of a display panel according to one embodiment of the present invention.

[0044] Referring to Figure 4, the display panel PN includes a substrate SUBS on which the pixel array and gate drive unit GD circuits are arranged. The display panel PN may, but is not limited to, a rectangular panel having a length in the row direction (X-axis), a width in the column direction (Y-axis), and a thickness in the thickness direction (Z-axis).

[0045] A substrate (SUBS) may be an insulating substrate that supports components placed on top of a display device. A substrate (SUBS) may be a structure in which multiple substrates are stacked. A substrate (SUBS) may be made from glass, polymer resin, or plastic substrates.

[0046] On one side (or front) of the substrate SUBS, the display area AA may include multiple pixel areas UPA, multiple gate drive areas GA, and multiple pad areas PA1, PA2. One or more pixels PX may be placed in each pixel area UPA. The pixel areas UPA may be arranged along multiple row lines and multiple column lines. Each pixel PX includes multiple subpixels SP of different colors. Each subpixel SP includes a light-emitting element and a pixel circuit and can emit light independently. Subpixels SP may include, but are not limited to, red subpixels, blue subpixels, and green subpixels.

[0047] Multiple gate drive regions GA include the circuitry of gate drive units GD. The gate drive regions GA may be formed along the row and / or column directions between multiple pixel regions UPA. The gate drive units GD formed in the gate drive regions GA can provide gate signals to multiple gate lines SL. The gate drive regions GA may be positioned between adjacent pixel regions UPA in the row direction (X-axis).

[0048] The first pad area PA1 includes a plurality of first pad electrodes PAD1 arranged on the outer front surface of one side (or upper side) of the display panel PN. The first pad electrodes PAD1 can transmit various signals to various wirings extending in the column direction in the display area AA. The first pad electrodes PAD1 include a data pad DP connected to the data line DL, which transmits the data voltage from the data drive unit DD to the data line DL, and a gate pad GP connected to the gate drive unit GD, which transmits a clock signal, start signal, gate low voltage, gate high voltage, etc., to the gate drive unit GD for driving the gate drive unit GD. The clock signal, start signal, gate low voltage, gate high voltage, etc., for driving the gate drive unit GD can be generated from the timing controller TC and applied to the gate pad GP via a level shifter and PCB. The first pad electrodes PAD1 may include a plurality of power supply wirings to which a DC voltage (or constant voltage) is applied.

[0049] The first substrate SUBS1 of the display panel PN is connected to the gate pad GP and includes gate drive wiring connected in the column direction and a plurality of gate drive wirings GVL extending in the row direction. The column-direction gate drive wiring and the row-direction gate drive wiring GVL may be connected through contact holes that penetrate the insulating film. The gate drive wiring GVL transmits signals necessary for driving the gate drive units GD distributed in the gate drive region GA, such as clock signals, start signals, gate high voltage, and gate low voltage, to the circuits of the gate drive units GD.

[0050] The second pad region PA2 includes a plurality of second pad electrodes PAD2 located on the rear outer casing on the other side (or bottom side) of the display panel PN. The second pad region PA2 may include a plurality of low-potential power supply pads VP2.

[0051] A DC voltage applied from the power supply circuit (which is omitted in the drawing) to the power supply wiring can be output and applied to pads VP1 and VP2 connected to the power supply wiring via the PCB. The power supply circuit may be located on the PCB or control boards CTB1 and CTB2 on the back of the display panel PN and may be a DC-DC converter that converts the DC input voltage from the main power supply into a DC voltage suitable for driving the display panel PN.

[0052] The power pads VP1 and VP2 connected to the power wiring may include a plurality of high-potential power pads VP1 arranged on the first pad area PA1 to transmit a high-potential power supply voltage to the high-potential power supply wiring HL, and a plurality of low-potential power pads VP2 arranged on the second pad area PA2 to transmit a low-potential power supply voltage to the low-potential power supply wiring CL.

[0053] The data pad DP, which is connected one-to-one with the data line DL, may have a relatively narrow width, while the power pads VP1 and VP2 and the gate pad GP may have a relatively wide width. The low-potential power pad VP2 may have a wider width than the high-potential power pad VP1.

[0054] To minimize the non-display area (NA) of the outermost edge of the display panel PN, after the pixel array, wiring, and pads are formed on the front surface of the display panel PN substrate, the outermost portion outside the scribing line (SCL), indicated by the dotted line, may be removed to provide a substrate (SUBS) with minimized non-display area (NA). After the scribing process, the rough edges of the substrate (SUBS) outline may be ground or laser trimmed. Short pad electrodes (PAD1, PAD2) remain on the front surface of the thus reduced-size substrate (SUBS) outline.

[0055] The data line DL extends in the column direction (Y direction) on the first substrate SUBS and can be superimposed on the pixel region UPA. The data line DL supplies a data voltage to the pixel circuit of each subpixel SP. The gate line SL extends in the row direction (X direction) on the substrate SUBS of the display panel PN and can be superimposed on the pixel region UPA and the gate drive region GA. The gate line SL can cross the pixel region UPA and the gate drive region GA to supply a gate signal from the gate drive unit GD to the pixel circuit of each subpixel SP.

[0056] The high-potential power supply wiring VL1 extends in the column direction (Y direction), and at least one of these is connected in a mesh structure to the auxiliary high-potential power supply wiring AVL1, which extends in the row direction (X direction). The auxiliary high-potential power supply wiring AVL1 is connected to the subpixels SP arranged in the row direction (X direction). Therefore, the high-potential power supply voltage applied to the high-potential power supply wiring VL1 can be transmitted to the subpixels SP through the auxiliary high-potential power supply wiring AVL1.

[0057] Low-potential power supply wiring VL2 extends in the column direction (Y direction), and at least one of these can be connected in a mesh structure to auxiliary low-potential power supply wiring AVL2 which extends in the row direction (X direction). Auxiliary low-potential power supply wiring AVL2 is connected to subpixels SP arranged in the row direction (X direction). Thus, subpixels SP are connected to auxiliary high-potential power supply wiring AVL1 to which a low-potential power supply voltage is applied.

[0058] The mesh structure of the power wiring reduces the resistance of the power wiring, which can improve voltage drop in high-potential power supply voltages and reduce power supply voltage variations within the display area AA.

[0059] The substrate SUBS of the display panel PN may include one or more alignment keys AK1, AK2 positioned between the pixel regions UPA. The alignment keys AK1, AK2 may be used for alignment during the manufacturing process of the display panel PN. The first alignment key AK1 may be positioned in the gate drive region GA. The first alignment key AK1 may be used to check the alignment position of each light-emitting element. The first alignment key AK1 may be formed by a cross pattern, but is not limited to this. The second alignment key AK2 may be superimposed on a high-potential power supply wiring HL. The high-potential power supply wiring HL may include holes formed at the position where it is superimposed on the second alignment key AK2, so as to separate the second alignment key AK2 from the high-potential power supply wiring HL. The second alignment key AK2 may be used when aligning the display panel PN with a donor substrate. The donor substrate is an intermediate medium for mounting light-emitting elements on the substrate SUBS of the display panel PN. Multiple light-emitting elements manufactured on a semiconductor wafer are transported attached to a donor substrate, and the light-emitting elements attached to the donor substrate can be transferred onto the substrate SUBS. The second alignment key AK2 may be formed from a circular or annular pattern, but is not limited thereto.

[0060] Figure 5 is a cross-sectional view showing the cross-sectional structure of a display panel according to one embodiment of the present invention.

[0061] Referring to Figure 5, on the first substrate SUBS1, a pixel circuit for driving a light-emitting element ED is arranged for each of the multiple subpixels SP. The pixel circuit may include multiple thin-film transistors and one or more capacitors. For convenience of explanation, the driving element DT, first capacitor C1, and second capacitor C2 used in the pixel circuit are shown, but the display panel PN may include other circuit elements.

[0062] A pattern of a first metal layer may be arranged on the first substrate SUBS1. The pattern of the first metal layer may include a light-shielding layer BSM. The light-shielding layer BSM can block light incident on the active layer ACT of the drive element DT, thereby minimizing leakage current. The light-shielding layer BSM may be formed from an opaque conductive material, such as a metal like copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), or chromium (Cr), or from an alloy of these metals, or from a multilayer metal layer.

[0063] A buffer layer BUF may be placed on top of the light-shielding layer BSM. The buffer layer BUF can block the penetration of moisture or impurities through the first substrate SUBS1. The buffer layer BUF may be formed from silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer insulating layer.

[0064] A drive element DT, which includes an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE, may be arranged on a buffer layer BUF.

[0065] The active layer ACT may, but is not limited to, a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon. The gate insulating layer GI electrically insulates the active layer ACT from the gate electrode GE of the drive element DT. The gate insulating layer GI may be formed from silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer insulating layer.

[0066] A pattern of a second metal layer may be arranged on top of the gate insulating layer GI. The pattern of the second metal layer may include the gate electrode GE of the driving element DT. The second metal layer may be formed from copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or a multilayer metal layer.

[0067] A first interlayer insulating layer ILD1 and a second interlayer insulating layer ILD2 are arranged on the gate electrode GE. Contact holes are formed in the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 for the source electrode SE and drain electrode DE of the driving element DT to connect to the active layer ACT, respectively. The first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 may be formed from silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer insulating layer, respectively.

[0068] A pattern of a third metal layer may be arranged on top of the second interlayer insulating layer ILD2. The pattern of the third metal layer may include a source electrode SE and a drain electrode DE that are superimposed on the active layer ACT and connected to the active layer ACT through contact holes penetrating the interlayer insulating layers ILD1 and ILD2. The source electrode SE may be connected to the capacitors C1 and C2 and the first electrode E1 of the light-emitting element ED. The third metal layer may be formed from copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or a multilayer metal layer.

[0069] The first capacitor C1 includes a first capacitor electrode C1a and a second capacitor electrode C1b. The first capacitor electrode C1a may be formed from a pattern of a second metal layer placed on a gate insulating layer GI. The second capacitor electrode C1b is formed from a pattern of a fourth metal layer placed on a first interlayer insulating layer ILD1 and is superimposed on the first capacitor electrode C1a across the first interlayer insulating layer ILD1. The second capacitor electrode C1b may be connected to the source electrode SE of the driving element DT. The fourth metal layer may be formed from copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or a multilayer metal layer.

[0070] The second capacitor C2 includes a third capacitor electrode C2a superimposed on the first capacitor electrode C1a, with a buffer layer BUF and a gate insulating layer GI in between. The third capacitor electrode C2a may be formed from a pattern of a first metal layer disposed on the first substrate SUBS1.

[0071] The second capacitor C2 is electrically connected between the source electrode SE of the driving element DT and the light-emitting element ED, thereby increasing the capacitance of the light-emitting element ED and increasing the brightness when the light-emitting element ED emits light.

[0072] The first passivation layer PAS1 covers the pattern of the third metal layer and the second interlayer insulating layer ILD2 so as to cover the pattern of the third metal layer. The first passivation layer PAS1 may be formed from silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer insulating layer.

[0073] A first planarization layer PLN1 is placed on a first passivation layer PAS1. The first planarization layer PLN1 covers the first passivation layer PAS1 and planarizes the surface on which the light-emitting element is placed. The first planarization layer PLN1 may be a thick single or multilayer organic insulating layer made of benzocyclobutene or acrylic-based organic material.

[0074] A pattern of a fifth metal layer may be arranged on top of the first planarization layer PLN1. The pattern of the fifth metal layer may include a reflective layer RF. The reflective layer RF can be used as an electrode to connect the light-emitting element ED to the front side of the display panel PN to increase light efficiency, and to connect the light-emitting element ED to a pixel circuit or power supply wiring. The reflective layer RF can be electrically connected to the source electrode SE and first capacitor C1 of the driving element DT through a contact hole CH1 that penetrates the first planarization layer PLN1 and the first passivation layer PAS1. The reflective layer RF can also be electrically connected to the first electrode E1 of the light-emitting element ED through the anode electrode AND, or to the second electrode E2 of the light-emitting element ED and the high-potential power supply wiring HL. The fifth metal layer may be formed from a transparent electrode material such as silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), or ITO (Indium Tin Oxide), or from a multilayer metal layer.

[0075] The second passivation layer PAS2 covers the pattern of the fifth metal layer and the first planarization layer PLN1. The second passivation layer PAS2 may be formed from silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer insulating layer.

[0076] An adhesive layer AD is placed on the second passivation layer PAS2 to fix the light-emitting element ED. The adhesive layer AD may be formed from a photocurable resin that can be cured by light. The adhesive layer AD may be formed from an acrylic series of material containing a photosensitive agent, but is not limited to this. The adhesive layer AD may be formed over the entire surface of the first substrate SUBS1, excluding the pad regions PA1 and PA2 where the first pad electrodes PAD1 are placed.

[0077] A light-emitting element ED for each subpixel SP may be placed on the adhesive layer AD. The light-emitting element ED can emit light due to a current from the driving element DT. The light-emitting element ED may include red light-emitting elements (ED), green light-emitting elements (ED), and blue light-emitting elements (ED). The light-emitting element ED may be an LED (Light Emitting Diode) or a microLED.

[0078] Each of the light-emitting elements ED includes a first semiconductor pattern SEM1, a light-emitting layer EM, a second semiconductor pattern SEM2, a first electrode E1, and a second electrode E2.

[0079] A first semiconductor pattern SEM1 is placed on an adhesive layer AD, and a second semiconductor pattern SEM2 is placed on the first semiconductor pattern SEM1. The first semiconductor pattern SEM1 and the second semiconductor pattern SEM2 can be formed from semiconductor patterns obtained by doping a semiconductor material with n-type and p-type impurities. For example, the first semiconductor pattern SEM1 and the second semiconductor pattern SEM2 may each be layers in which a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs) is doped with n-type or p-type impurities. The p-type impurities may be magnesium, zinc (Zn), beryllium (Be), etc., and the n-type impurities may be silicon (Si), germanium, tin (Sn), etc., but are not limited to these.

[0080] A light-emitting layer EM is positioned between a first semiconductor pattern SEM1 and a second semiconductor pattern SEM2. The light-emitting layer EM can emit light by receiving holes and electrons from the first semiconductor pattern SEM1 and the second semiconductor pattern SEM2. The light-emitting layer EM may consist of a single layer or a multi-quantum well (MQW) structure, and may be formed from, for example, indium gallium nitride (InGaN) or gallium nitride (GaN).

[0081] A first electrode E1 is placed on a first semiconductor pattern SEM1. The first electrode E1 electrically connects the driving element DT to the first semiconductor pattern SEM1. The first semiconductor pattern SEM1 may be formed from a semiconductor layer doped with n-type impurities. The first electrode E1 may be the anode electrode of a light-emitting element ED, which is placed on the first semiconductor pattern SEM1 and electrically connected to the driving element DT and capacitors C1 and C2 via a reflective layer RF. The first electrode E1 may be placed on the upper surface of the first semiconductor layer SEM1. The first electrode E1 may be formed from a conductive material, such as a transparent conductive material like ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material like titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof.

[0082] A second electrode E2 is placed on the second semiconductor pattern SEM2. The second electrode E2 electrically connects the high-potential power supply wiring HL to the second semiconductor layer SEM2. The second semiconductor layer SEM2 may be formed from a semiconductor layer doped with p-type impurities. The second electrode E2 may be the cathode electrode of the light-emitting element ED. The second electrode E2 may be formed from a conductive material, such as a transparent conductive material like ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material like titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof.

[0083] The light-emitting element ED may include a sealing layer ENS. The sealing layer ENS covers the semiconductor patterns SEM1 and SEM2 and electrodes E1 and E2, protecting the light-emitting element ED. The sealing layer ENS and the third planarization layer PLN3 include contact holes that expose the first electrode E1 and the second electrode E2. The anode electrode AND is connected to the reflective layer RF through a first contact hole that penetrates the sealing layer ENS and the third planarization layer PLN3. The cathode electrode CAT is connected to the second electrode E2 through a second contact hole that penetrates the sealing layer ENS and the third planarization layer PLN3. On the other hand, a portion of the side surface of the first semiconductor pattern SEM1 may be exposed without the sealing layer ENS.

[0084] The second planarization layer PLN2 and the third planarization layer PLN3 may cover the adhesive layer AD and the light-emitting element ED. The second planarization layer PLN2 contacts the lower side edge of the light-emitting element ED to fix it in place. The third planarization layer PLN3 covers the light-emitting element ED on top of the second planarization layer PLN2. The third planarization layer PLN3 includes contact holes that expose the first electrode E1 and the second electrode E2 of the light-emitting element ED. The second planarization layer PLN2 and the third planarization layer PLN3 may be formed from a single or multilayer organic insulating material, such as a photoresist or an acrylic-based organic material.

[0085] A pattern of a sixth metal layer may be arranged on the third planarization layer PLN3. The sixth metal layer may include an anode electrode AND and a cathode electrode CAT. The anode electrode AND electrically connects the first electrode E1 of the light-emitting element ED to the reflective layer RF. The anode electrode AND may be connected to the first electrode E1 of the light-emitting element ED through contact holes penetrating the insulating layers PLN3 and ENS, and to the reflective layer RF through contact holes penetrating the insulating layers PAS2, AD, PLN2, and PLN3.

[0086] The cathode electrode CAT is connected to the second electrode E2 of the light-emitting element ED through a contact hole that penetrates the insulating layer PLN3, ENS. The cathode electrode CAT may be connected to the low-potential power supply wiring CL.

[0087] In the examples, the light-emitting element ED was shown to have a horizontal structure in which the electrodes are connected to the upper surfaces of the first semiconductor pattern SEM1 and the second semiconductor pattern SEM2, but it is not necessarily limited to this. Exemplarily, the light-emitting element ED may also have a vertical structure in which the anode electrode AND is located below the first semiconductor pattern SEM1.

[0088] A bank pattern BB may be placed on the second planarization layer PLN2. The bank pattern BB may be spaced at a certain distance from the light-emitting element ED. The bank pattern BB can cover a portion of the anode electrode AND present in the contact holes penetrating the insulating layers PLN2 and PLN3. The bank pattern BB can prevent optical crosstalk between subpixels SP and reduce color mixing between subpixels SP. For this purpose, the bank pattern BB may, but is not limited to, be formed from black resin.

[0089] The first protective layer CPA can cover the metal layer of the sixth metal layer, the bank pattern BB, the second planarization layer PLN2, and the third planarization layer PLN3. The first protective layer CPA can be formed from a single layer or multiple layers of insulating material such as translucent epoxy, silicon oxide (SiOx), or silicon nitride (SiNx).

[0090] Each of the first pad electrodes PAD1 located in the pad regions PA1 and PA2 of the first substrate SUBS1 may have a multilayer metal layer structure. For example, each of the first pad electrodes PAD1 may include a first pad metal layer PE1a, a second pad metal layer PE1b, and a third pad metal layer PE1c laminated on the outermost front surface of the first substrate SUBS1.

[0091] The pattern of the third metal layer placed on the second interlayer insulating layer ILD2 may further include a first pad metal layer PE1a. The first pad metal layer PE1a may be formed from the same metal as the source electrode SE and drain electrode DE of the drive element DT, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or a multilayer metal layer.

[0092] The pattern of the fifth metal layer placed on the first planarization layer PLN1 may further include a second pad metal layer PE1b. The second pad metal layer PE1b may be formed from the same metal as the reflective layer RF, for example, silver (Ag), aluminum (Al), molybdenum (Mo), or a multilayer metal layer.

[0093] The pattern of the sixth metal layer placed on the third planarization layer PLN3 may further include a third pad metal layer PE1c. The third pad metal layer PE1c may be formed from the same conductive material as the anode electrode AND and cathode electrode CAT, for example, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or from a multilayer metal layer.

[0094] A first metal layer ML1, a second metal layer ML2, and multiple insulating layers may be arranged beneath the first pad electrode PAD1. The height difference of the first pad electrode PAD1 can be adjusted by arranging the first metal layer ML1, the second metal layer ML2, and multiple insulating layers beneath the first pad electrode PAD1. For example, a buffer layer BUF, a gate insulating layer GI, a first metal layer ML1, a first interlayer insulating layer ILD1, and a second metal layer ML2 may be arranged sequentially between the first pad electrode PAD1 and the first substrate SUBS1. The pattern of the second metal layer arranged on the gate insulating layer GI may include the first metal layer ML1. The pattern of the fourth metal layer arranged on the first interlayer insulating layer ILD1 may include the second metal layer ML2. The multiple insulating layers and metal layers ML1, ML2 beneath the first pad electrode PAD1 are not limited to those shown in Figure 5.

[0095] A second substrate SUBS2 may be placed on the back of a first substrate SUBS1. A bonding layer BDL is placed between the first substrate SUBS1 and the second substrate SUBS2. The bonding layer BDL is cured through various curing methods to bond the first substrate SUBS1 and the second substrate SUBS2 together. The bonding layer BDL may be placed in only a portion of the area between the first substrate SUBS1 and the second substrate SUBS2, or it may be placed over the entire area. The first substrate SUBS1 and the second substrate SUBS2 may be simultaneously scribed and ground so that the sides of the first substrate SUBS1 and the second substrate SUBS2 become seamless.

[0096] Multiple second pad electrodes PAD2 may be arranged on the outermost back surface of the second substrate SUBS2. The second pad electrodes PAD2 are electrically connected to the side wiring SRL and the first pad electrode PAD1, and transmit signals from circuit components located on the back surface of the second substrate SUBS2 to the subpixel SP located on the top surface of the first substrate SUBS1.

[0097] Each of the second pad electrodes PAD2 may have a multilayer metal layer structure. For example, each of the second pad electrodes PAD2 may include a first pad metal layer PE2a, a second pad metal layer PE2b, and a third pad metal layer PE2c laminated on the outermost back surface of the second substrate SUBS2. The first and second pad metal layers PE2a and PE2b may be formed from copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or a multilayer metal layer, respectively. The third pad metal layer PE2c may be formed from a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

[0098] A second protective layer BCL may be placed on the back surface of the second substrate SUBS2. The second protective layer BCL can cover various wirings on the back surface of the second substrate SUBS2, excluding the second pad electrode PAD2. The second protective layer BCL may consist of an organic insulating material, for example, it may be formed from a benzocyclobutene or acrylic-based organic insulating material.

[0099] Multiple flexible films and circuit components such as PCBs can be arranged on the back side of the second substrate SUBS2. The output terminals of the flexible films are electrically connected to the second pad electrodes PAD2, and the input terminals of the flexible films are electrically connected to the output terminals of the PCB. Therefore, signals and voltages output from the PCB can be transmitted to the subpixel SP located on the front of the first substrate SUBS1 via the flexible films, the second pad electrodes PAD2, the side wiring SRL, multiple first pad electrodes PAD1, and the wiring connected to the first pad electrodes PAD1.

[0100] The side wiring SRL crosses the sides of the first substrate SUBS1 and the second substrate SUBS2, electrically connecting the first pad electrode PAD1 and the second pad electrode PAD2. The side wiring SRL can be formed on the sides of substrates SUBS1 and SUBS2 by a pad printing method using conductive ink, such as a conductive ink containing silver (Ag), copper (Cu), molybdenum (Mo), and chromium (Cr).

[0101] The side insulating layer SDI can cover the side wiring SRL formed on the top, sides, and back of the outermost layers of the first substrate SUBS1 and the second substrate SUBS2, which are bonded together. If the side wiring SRL is metal, ambient light may be reflected from the side wiring SRL, or light emitted from the light-emitting element ED may be reflected from the side wiring SRL and visible to the user. To improve image quality degradation due to such reflected light, the side insulating layer SDI may contain a black substance that absorbs ambient light. For example, the side insulating layer SDI can be formed on the outermost layers of the first substrate SUBS1 and the second substrate SUBS2 from black ink that can be applied by a printing method.

[0102] The protective layer (Seal) SS covers the side insulating layer SDI and can protect the display panel PN from external impacts, moisture, and oxygen. For example, the protective layer SS may consist of black ink, polyimide (PI), polyurethane (Polyurethane), epoxy (Epoxy), or acrylic (Acryl) series insulating materials. The protective layer SS may be a concept that includes the side insulating layer SDI. That is, the protective layer SS and the side insulating layer SDI may also consist of a single layer.

[0103] A cover film MF may cover the front surface of the first display panel PN. The cover film MF may be one or more of various functional films, such as shatterproof film, anti-glare film, anti-reflective film, low-reflective film, OLED Transmittance Controllable film, color difference compensation film, and polarizing plate. The shatterproof film prevents substrate fragments and particles from scattering when the display panel PN is damaged. The cover film MF may be cut and removed along a cutting line that overlaps with the protective layer SS, along with the outer edge portion of the protective layer SS, after the protective layer SS has been widely bonded to the front surface of the first substrate SUBS1. As a result, the exposed sides of the outermost edges of the cover film MF and protective layer SS may form a flush surface without any steps.

[0104] Figure 6 shows a pixel according to one embodiment of the present invention. Figure 7 shows a red subpixel according to one embodiment of the present invention. Figure 8 shows a green subpixel according to one embodiment of the present invention. Figure 9 shows a blue subpixel according to one embodiment of the present invention. Figure 10 shows the cathode electrodes of the red subpixel, green subpixel, and blue subpixel.

[0105] Referring to Figure 6, a pixel may contain six subpixels. Exemplarily, a pixel may contain two red subpixels R1 and R2, two green subpixels G1 and G2, and two blue subpixels B1 and B2. Each subpixel may comprise a pixel circuit including an emitting element and a compensation circuit. The compensation circuit is a circuit for compensating the threshold voltage of the driving element, and the pixel circuit may be a concept encompassing the emitting element, the driving element, and the compensation circuit. A subpixel comprising two emitting elements and one compensation circuit may be defined as a single subpixel.

[0106] According to the embodiment, each subpixel R1, R2, G1, G2, B1, B2 can be driven independently or simultaneously. Multiple subpixels R1, R2, G1, G2, B1, B2 can share a gate line and be driven simultaneously. However, this is not necessarily the only option; the gate line can consist of multiple lines, and a first pixel group R1, G1, B1 connected to a first gate line SCAN1 and a second pixel group R2, G2, B2 connected to a second gate line SCAN2 can be driven independently.

[0107] The two red subpixels R1 and R2 can be connected to data lines VdataR1 and VdataR2, respectively. In contrast, the two green subpixels G1 and G2 can share one data line VdataG, and the two blue subpixels B1 and B2 can share one data line VdataB. Thus, the number of data connections can be reduced.

[0108] Because the red subpixels R1 and R2 are relatively inefficient, their brightness is adjusted by driving them independently. On the other hand, the green subpixels G1 and G2 and the blue subpixels B1 and B2 are relatively efficient, so they can be emitted simultaneously using a single data line.

[0109] In this case, since two light-emitting elements are turned on simultaneously by a single data voltage, there is the advantage that the desired brightness can be output even if the data voltage is lowered. However, this is not necessarily the only option; the green subpixel and blue subpixel can also be driven independently by connecting separate data lines to each other.

[0110] Referring to Figure 7, the red subpixel may include a first red subpixel (subpixel 1-1) R1 and a second red subpixel (subpixel 1-2) R2. The first red subpixel R1 may include a first red light-emitting element ED11 and a first red compensation circuit PC11. The first red light-emitting element ED11 may be connected to an anode electrode AND connected to a high-potential power supply wiring HL and a cathode electrode CAT connected to a low-potential power supply wiring CL1. The first red compensation circuit PC11 may be connected between a first data line VdataR1 and a low-potential power supply wiring CL1.

[0111] The second red subpixel R2 may include a second red light-emitting element ED12 and a second red compensation circuit PC12. The second red light-emitting element ED12 may be connected to an anode electrode connected to a high-potential power supply wiring HL and a cathode electrode connected to a low-potential power supply wiring CL2. The second red compensation circuit PC12 may be connected between the second data line VdataR2 and the low-potential power supply wiring CL2.

[0112] In this embodiment, the first red subpixel R1 and the second red subpixel R2 are connected to the first data line VdataR1 and the second data line VdataR2, respectively, and can be driven independently. Therefore, if the voltage levels applied to the first data line VdataR1 and the second data line VdataR2 are adjusted to be different, the first red light-emitting element ED11 and the second red light-emitting element ED12 can emit light at different luminances. That is, the luminance of the first red light-emitting element ED11 and the second red light-emitting element ED12 can be controlled independently according to the overall luminance of the red light to be output from the pixel. Alternatively, the first red light-emitting element ED11 and the second red light-emitting element ED12 can be driven alternately. However, this is not necessarily the only option, and the first red subpixel R1 and the second red subpixel R2 can also be driven simultaneously by a single data line. Since the first red subpixel R1 and the second red subpixel R2 are composed of independent pixels, a short-circuit failure in either the first or second red subpixel R1 will not affect the other.

[0113] Referring to Figure 8, the green subpixel may include a first green subpixel (2-1 subpixel) G1 and a second green subpixel (2-2 subpixel) G2. The first green subpixel G1 may include a first green light-emitting element ED21 and a first green compensation circuit PC21. The first green light-emitting element ED21 may be connected to an anode electrode connected to a high-potential power supply wiring HL and a cathode electrode connected to a low-potential power supply wiring CL3. The first green compensation circuit PC21 may be connected between a third data line VdataG and the low-potential power supply wiring CL3.

[0114] The second green subpixel G2 may include a second green light-emitting element ED22 and a second green compensation circuit PC22. The second green light-emitting element ED22 may be connected to an anode electrode connected to a high-potential power supply wiring HL and a cathode electrode connected to a low-potential power supply wiring CL4. The second green compensation circuit PC22 may be connected between the third data line VdataG and the low-potential power supply wiring CL4.

[0115] According to the embodiment, the first green subpixel G1 and the second green subpixel G2 are commonly connected to the third data line VdataG, and can therefore be driven simultaneously. Consequently, the data voltage can be set relatively low. For example, if the data voltage to be applied to output the brightness of the green subpixel defined in the frame is 1V, even if the data voltage is reduced to 0.5V, the two green light-emitting elements will still emit light, and the desired brightness of green light can be output.

[0116] For example, in the case of a second pixel where either the first green subpixel G1 or the second green subpixel G2 is defective, the brightness must be adjusted using only one pixel. Therefore, twice the data voltage must be applied compared to the first pixel where both subpixels emit light, in order to adjust the brightness to the same level.

[0117] According to the embodiment, the anode electrode of the first green light-emitting element ED21 and the anode electrode of the second green light-emitting element ED22 are electrically isolated, and the cathode electrode of the first green light-emitting element ED21 and the cathode electrode of the second green light-emitting element ED22 can be electrically isolated. Therefore, even if a malfunction in the first green light-emitting element ED21 causes a short circuit between the high potential voltage VDD and the low potential voltage VSS, resulting in the first green light-emitting element ED21 becoming dark, it will not affect the adjacent second green light-emitting element ED22.

[0118] The failure of the first green light-emitting element ED21 could be due to a defect in the electrode pad, or it could be due to a defect in the semiconductor layer itself. In the case of micro-sized light-emitting diodes, their small size makes them vulnerable to static electricity, and because they are fabricated on a wafer at a micro-size and then transferred to a panel, the failure rate can be high due to a variety of causes.

[0119] Therefore, when the first green light-emitting element ED21 and the second green light-emitting element ED22 are connected in series or parallel, if a short-circuit failure occurs in either one of the light-emitting elements, causing it to become dark, the adjacent normal light-emitting elements may also become dark due to the short-circuit current flowing through them. However, according to this embodiment, since the anode electrode and cathode electrode of the first green light-emitting element ED21 and the second green light-emitting element ED22 are separated, even if a short-circuit failure occurs in either one of the light-emitting elements, it is possible to prevent the adjacent light-emitting elements from becoming dark. Therefore, the adjacent light-emitting elements can operate normally.

[0120] Referring to Figure 9, the blue subpixel may include a first blue subpixel (the 3-1st subpixel) B1 and a second blue subpixel (the 3-2nd subpixel) B2. The first blue subpixel B1 may include a first blue light-emitting element ED31 and a first blue compensation circuit PC31. The first blue light-emitting element ED31 may be connected to an anode electrode connected to a high-potential power supply wiring HL and a cathode electrode connected to a low-potential power supply wiring CL5. The first blue compensation circuit PC31 may be connected between the fourth data line VdataB and the low-potential power supply wiring CL5.

[0121] The second blue subpixel B2 may include a second blue light-emitting element ED32 and a second blue compensation circuit PC32. The second blue light-emitting element ED32 may be connected to an anode electrode connected to a high-potential power supply wiring HL and a cathode electrode connected to a low-potential power supply wiring CL6. The second blue compensation circuit PC32 may be connected between the fourth data line VdataB and the low-potential power supply wiring CL6.

[0122] According to the embodiment, the first blue subpixel B1 and the second blue subpixel B2 are commonly connected to the fourth data line VdataB, and can therefore be driven simultaneously. Consequently, the data voltage can be set lower than the voltage level required to illuminate one blue light-emitting element at a desired brightness.

[0123] For example, in the case of a third pixel where either the first blue subpixel B1 or the second blue subpixel B2 is defective, the brightness must be adjusted using only one pixel. Therefore, twice the data voltage must be applied compared to the first pixel where both subpixels are emitting light, in order to adjust the brightness to the same level.

[0124] Furthermore, the anode electrode of the first blue light-emitting element ED31 and the anode electrode of the second blue light-emitting element ED32 are electrically isolated, and the cathode electrode of the first blue light-emitting element ED31 and the cathode electrode of the second blue light-emitting element ED32 can be electrically isolated. Therefore, even if a short-circuit failure occurs in one of the light-emitting elements, it is possible to prevent the adjacent light-emitting elements from becoming dark.

[0125] Referring to Figure 10, within a pixel, the anode electrode AND1 of the first red subpixel R1, the anode electrode AND2 of the second red subpixel R2, the anode electrode AND3 of the first green subpixel G1, the anode electrode AND4 of the second green subpixel G2, the anode electrode AND5 of the first blue subpixel B1, and the anode electrode AND6 of the second blue subpixel B2 can each be electrically isolated.

[0126] Furthermore, the cathode electrodes CAT1 of the first red subpixel R1, CAT2 of the second red subpixel R2, CAT3 of the first green subpixel G1, CAT4 of the second green subpixel G2, CAT5 of the first blue subpixel B1, and CAT6 of the second blue subpixel B2 can each be electrically isolated.

[0127] Furthermore, the multiple high-potential power supply wires HL connected to each anode electrode AND1 to AND6 can be isolated from each other, and the multiple low-potential power supply wires CL connected to each cathode electrode CAT1 to CAT6 can also be isolated from each other. Therefore, a short-circuit failure in any one of the multiple subpixels can prevent the light-emitting elements of adjacent subpixels from becoming dark.

[0128] Figure 11 is a schematic circuit diagram showing a pixel circuit according to one embodiment of the present invention. Figure 12 is a schematic circuit diagram showing a pixel circuit according to one embodiment of the present invention.

[0129] Referring to Figure 11, the same color subpixels SP1 and SP2 each include a light-emitting element ED, a driving element DT, a first switching element M1, and a compensation circuit PC. The same color subpixels SP1 and SP2 may be green or blue subpixels.

[0130] Since the two subpixels SP1 and SP2 have the same structure, separated by the data line PL2 to which the data voltage Vdata is applied, the sign of the pixel circuit of each subpixel will be described using the same sign. In the following, the second subpixel SP2, located on the right, will be used as the reference.

[0131] The second subpixel SP2 may include a light-emitting element ED, a driving element DT, a first switching element M1, and a compensation circuit PC. The light-emitting element ED, the driving element DT, and the switching element M1 may be connected in series between a high potential voltage VDD and a low potential voltage VSS.

[0132] The driving element DT regulates the current flowing through the drain-source channel according to the gate-source voltage. The gate-source voltage of the driving element DT is variable according to the data voltage Vdata of the pixel data applied to the gate electrode of the driving element DT. Therefore, the current flowing through the driving element DT changes according to the data voltage Vdata. The light-emitting element ED can be driven by the current from the driving element DT to emit light. A capacitor C may be connected between the gate electrode of the driving element DT and the first electrode. Capacitor C is charged with the gate-source voltage of the driving element DT.

[0133] The driving element DT may be connected between the light-emitting element ED and the first switching element M1. In this case, the driving element DT includes a gate electrode to which the data voltage Vdata is applied, a first electrode connected to the cathode electrode of the light-emitting element ED, and a second electrode connected to the first electrode of the first switching element M1.

[0134] The first switch element M1 switches the current path between the high potential voltage VDD and the low potential voltage VSS. The first switch element M1 can be turned on in response to the gate-on voltage of one of the gate signals GATE1 and GATE2, and turned off in response to the gate-off voltage. When the first switch element M1 is turned on, the drive element DT and the light-emitting element ED are electrically connected, and current can be supplied to the light-emitting element ED. When the first switch element M1 is turned off, the current path between the high potential voltage VDD and the low potential voltage VSS is interrupted, and no current is supplied to the light-emitting element ED.

[0135] The first switching element M1 may be connected between the driving element DT and the cathode voltage VSS. In this case, the first switching element M1 includes a gate electrode connected to the first gate line, a first electrode connected to the second electrode of the driving element DT, and a second electrode connected to the node to which the cathode voltage VSS is applied.

[0136] The pixel circuit may further include a second switching element M2. The second switching element M2 is connected between the cathode electrode and the anode electrode of the light-emitting element ED and can be turned on in response to a gate signal applied through a compensation circuit. When the second switching element M2 is turned on, the cathode electrode and the anode electrode of the light-emitting element ED are short-circuited, and the light-emitting element ED does not emit light. The second switching element M2 can prevent the light-emitting element ED from emitting light when the pixel circuit is initialized and when the threshold voltage of the driving element DT is sampled. The second switching element M2 includes a gate electrode connected to a second gate line, a first electrode connected to the anode electrode of the light-emitting element ED, and a second electrode connected to the cathode electrode of the light-emitting element ED.

[0137] The first switch element M1 may be turned on in response to the gate-on voltage of the light emission signal and turned off in response to the gate-off voltage of the light emission signal, but is not limited to this. The second switch element M2 may be turned on in response to the gate-on voltage of the first scan signal and turned off in response to the gate-off voltage of the first scan signal, but is not limited to this.

[0138] The compensation circuit PC is connected to the data line to which the data voltage Vdata is applied, the gate line to which one or more scan signals SCAN1 and SCAN2 are applied, the gate electrode of the drive element DT, and the gate electrode of the first switch element M1. One or more scan signals SCAN1 and SCAN2 may be applied to the compensation circuit.

[0139] The compensation circuit uses multiple transistors to transmit the data voltage Vdata to the gate electrode of the driving element DT. The compensation circuit samples the threshold voltage of the driving element DT into capacitor C and compensates the gate voltage of the driving element DT by the threshold voltage of the driving element DT. The compensation circuit can compensate the threshold voltage of the driving element DT using a source follower or diode connection circuit.

[0140] Referring to Figure 12, the pixel circuit may include a driving element DT connected to the light-emitting element ED, a plurality of first switching elements M1 to M6, and a plurality of capacitors C1 to C3. The driving element DT and the plurality of first switching elements M1 to M6 may be P-channel transistors, but are not necessarily limited to them.

[0141] The driving element DT may have a gate electrode G connected to the first node n1, a source electrode S connected to the second node n2, and a drain electrode D connected to the third node n3.

[0142] The light-emitting element ED may be placed between the second node n2 and the high potential voltage VDD. The light-emitting element ED may be, but is not limited to, a micro-sized light-emitting diode. The source electrode S of the driving element DT may be connected to the cathode electrode of the light-emitting element ED.

[0143] The first switch element M1 can be connected between the third node n3 and the low potential voltage VSS. When the first switch element M1 is turned on in response to the gate-on voltage of the light-emitting signal EM, it can connect the third node n3 and the low potential voltage VSS.

[0144] The second switching element M2 is connected between the cathode electrode and the anode electrode of the light-emitting element ED and can be turned on by the gate-on voltage of the first scan signal SCAN1. When the second switching element M2 is turned on, the light-emitting element stops emitting light.

[0145] The third switch element M3 is connected between the reference voltage line PL1 and the fourth node n4, and when it is turned on in response to the gate-on voltage of the light emission signal EM, it can apply the reference voltage Vref to the fourth node n4.

[0146] The fourth switch element M4 is positioned between the third node n3 and the first node n1, and when turned on in response to the gate-on voltage of the first scan signal SCAN1, it can connect the third node n3 and the first node n1.

[0147] The fifth switch element M5 is positioned between the reference voltage line PL1 and the fifth node n5, and when turned on in response to the gate-on voltage of the second scan signal SCAN2, it can apply the reference voltage Vref to the fifth node n5.

[0148] The sixth switch element M6 is positioned between the data line PL2 and the fourth node n4, and when turned on in response to the gate-on voltage of the first scan signal SCAN1, it can apply the data voltage Vdata to the fourth node n4.

[0149] A first capacitor C1 may be placed between the first node n1 and the fourth node n4, a second capacitor C2 may be placed between the first node n1 and the second node n2, and a third capacitor C3 may be placed between the second capacitor C2 and the anode electrode of the light-emitting element ED. The threshold voltage and data voltage of the driving element may be stored in the second capacitor C2 and the third capacitor C3.

[0150] Referring to Figure 13, during the first initialization period INI1, the first scan signal SCAN1 may output a gate-off voltage VGH, and the second scan signal SCAN2 may output a gate-on voltage VGL. The fifth switch element M5 to which the second scan signal SCAN2 is applied may be turned on, and a reference voltage may be applied to the third node n3. The first node n1 maintains the reference voltage Vref that was applied during the emission period of the previous frame, and the third node n3 may have the reference voltage Vref applied.

[0151] During the second initialization period INI2, both the first scan signal SCAN1 and the second scan signal SCAN2 are output at the gate-on voltage VGL, so the second switch element M2, the fourth switch element M4, the fifth switch element M5, and the sixth switch element M6 can be turned on. Consequently, the data voltage Vdata is charged to the first node n1, the reference voltage Vref is charged to the first node n1, and the first capacitor C1 can be initialized. In addition, the gate electrode of the drive element DT can be initialized at the reference voltage Vref. At this time, the second switch element M2 is turned on, so the cathode electrode and anode electrode of the light-emitting element ED are short-circuited, and the light-emitting element ED may not emit light.

[0152] During the sampling period of SAM, the first scan signal SCAN1 is the gate-on voltage VGL and the second scan signal SCAN2 is the gate-off voltage VGH, so the sixth switch element M6, the fourth switch element M4, and the second switch element M2 can be turned on. Therefore, the first node n1 can store the VDD+Vth voltage.

[0153] During the hold period HOL, the first scan signal SCAN1, the second scan signal SCAN2, and the light emission signal EM are all at the gate off voltage VGH, so all switching elements can be turned off. Therefore, the VDD+Vth voltage can be maintained at the first node n1.

[0154] During the emission period EMI, the first scan signal SCAN1 and the second scan signal SCAN2 may have a gate-off voltage VGH, and the light emission signal EM may have a gate-on voltage VGL. The first switch element M1 and the third switch element M3 may be turned on. Therefore, a reference voltage Vref may be applied to the first node n1, and a voltage VDD + Vth - (Vdata - Vref) may be applied to the first node n1 by capacitor coupling.

[0155] The current Ids flowing through the drive element DT is k(lVgsl-lVthl) 2 It can be defined as follows: Therefore, k(VDD-VDD-Vth+Vdata-Vref+Vth) 2 Therefore, summarizing this, k(Vdata-Vref) 2 This can be simplified to the following: Therefore, the threshold voltage of the driving element can be compensated.

[0156] Figure 14 shows a pixel where subpixels are connected in parallel. Figure 15 shows the subpixels of Figure 14.

[0157] Referring to Figures 14 and 15, a pixel may consist of four subpixels R1, R2, G, and B. That is, a pixel may consist of a first red subpixel R1, a second red subpixel R2, a green subpixel G, and a blue subpixel B.

[0158] The first red subpixel R1 and the second red subpixel R2 may each comprise a light-emitting element ED and a compensation circuit PC, similar to the structure described in Figure 7. However, the green subpixel G may consist of two green light-emitting elements ED arranged in parallel, with the two green light-emitting elements ED sharing one compensation circuit PC. Similarly, the red subpixel R may consist of two red light-emitting elements ED arranged in parallel, with the two red light-emitting elements ED sharing one compensation circuit PC. Such a structure allows for a reduction in the number of compensation circuits and an increase in the aperture ratio.

[0159] However, since the two green light-emitting elements ED1 and ED2 are connected in parallel, if a short-circuit failure occurs in one of the light-emitting elements and causes it to become dark, the adjacent light-emitting elements will also be short-circuited and become dark. Consequently, in that pixel, both the green light-emitting elements ED1 and ED2 will become dark.

[0160] Figures 16 and 17 show the process of repairing subpixels.

[0161] Referring to Figure 16, multiple pixels may include a first pixel PIXEL(N) located on the first pixel line and a second pixel PIXEL(N+1) located on the second pixel line. The first pixel PIXEL(N) may include a first subpixel SP1 and a second subpixel SP2 of the same color, and the second pixel PIXEL(N+1) may include a third subpixel SP3 and a fourth subpixel SP4 of the same color. The first and second pixel lines may, but are not limited to, be adjacent in the column direction (Y-axis).

[0162] The first subpixel SP1, the second subpixel SP2, the third subpixel SP3, and the fourth subpixel SP4 may each comprise a light-emitting element ED, a compensation circuit PC, a high-potential power supply wiring HL, and a low-potential power supply wiring CL.

[0163] The first subpixel SP1 may be positioned so that it faces the third subpixel SP3 in the column direction, and the second subpixel SP2 may be positioned so that it faces the fourth subpixel SP4 in the column direction.

[0164] A low-potential power supply wire CL11 located in the first subpixel SP1 extends toward the third subpixel SP3, and a low-potential power supply wire CL13 located in the third subpixel SP3 may extend toward the first subpixel SP1. Also, a low-potential power supply wire CL12 located in the second subpixel SP2 extends toward the fourth subpixel SP4, and a low-potential power supply wire CL14 located in the fourth subpixel SP4 may extend toward the second subpixel SP2.

[0165] Welding sections WP may be formed at the ends of the low-potential power supply wiring CL11, CL12, CL13, and CL14 extending outside each subpixel. The welding sections WP include metal layers superimposed on each other with an insulating layer in between, and can be selectively joined during the welding process.

[0166] Referring to Figure 17, if a malfunction occurs in the compensation circuit PC of the fourth subpixel SP4, the welding portion WP of the low-potential power supply wiring CL14 of the fourth subpixel SP4 can be connected to the welding portion WP of the low-potential power supply wiring CL12 of the second subpixel SP2 to form a repair portion WP2. Therefore, in this case, in the fourth subpixel SP4, the welding portion WP can be connected after electrically separating the light-emitting element ED and the compensation circuit PC. With this configuration, if a malfunction occurs in the compensation circuit of each subpixel, it can be connected to the compensation circuit of an adjacent subpixel and operate normally.

[0167] A display panel and a display device including the same according to an embodiment of the present invention can be described as follows.

[0168] A display panel according to one embodiment of the present invention includes a plurality of pixels and gate lines and data lines connected to the plurality of pixels, wherein the plurality of pixels include a first-1 subpixel and a first-2 subpixel of the first color; a second-1 subpixel and a second-2 subpixel of the second color; and a third-1 subpixel and a third-2 subpixel of the third color, wherein the second-1 subpixel and the second-2 subpixel each include a light-emitting element and a compensation circuit, and the compensation circuit of the second-1 subpixel and the compensation circuit of the second-2 subpixel are connected to a single data line.

[0169] According to one or more embodiments of the present invention, the 1-1 subpixel may include a first compensation circuit connected to a first data line, and the 1-2 subpixel may include a second compensation circuit connected to a second data line.

[0170] According to one or more embodiments of the present invention, the 3-1 subpixel and the 3-2 subpixel each include a compensation circuit, and the compensation circuits of the 3-1 subpixel and the 3-2 subpixel can be coupled to a single data line.

[0171] According to one or more embodiments of the present invention, the first color may be red, the second color may be green, and the third color may be blue.

[0172] According to one or more embodiments of the present invention, the plurality of pixels may include a first pixel in which, when a data voltage is applied, all of the second-first subpixels and the second-second subpixels emit light, and a second pixel in which, when the data voltage is applied, only one of the second-first subpixels and the second-second subpixels emits light.

[0173] According to one or more embodiments of the present invention, the data voltage applied to the 2-1 subpixel and the 2-2 subpixel of the second pixel may be greater than the data voltage applied to the 2-1 subpixel and the 2-2 subpixel of the first pixel.

[0174] According to one or more embodiments of the present invention, the plurality of pixels may include a third pixel in which all of the 3-1 subpixels and the 3-2 subpixels emit light when a data voltage is applied, and a fourth pixel in which only one of the 3-1 subpixels and the 3-2 subpixels emits light when the data voltage is applied.

[0175] According to one or more embodiments of the present invention, the data voltage applied to the 3-1 and 3-2 subpixels of the 4th pixel may be greater than the data voltage applied to the 3-1 and 3-2 subpixels of the 3rd pixel.

[0176] According to one or more embodiments of the present invention, a first gate line connecting a 1-1 subpixel, a 2-1 subpixel, and a 3-1 subpixel may be included, and a second gate line connecting a 1-2 subpixel, a 2-2 subpixel, and a 3-2 subpixel may be included.

[0177] According to one or more embodiments of the present invention, the 1-1 to 3-2 subpixels each include an anode electrode and a cathode electrode for applying a voltage to the light-emitting element, the anode electrodes of the 1-1 to 3-2 subpixels are separated from each other, and the cathode electrodes of the 1-1 to 3-2 subpixels can be separated from each other.

[0178] According to one or more embodiments of the present invention, the compensation circuit for the second-first subpixel and the compensation circuit for the second-second subpixel may have the same structure.

[0179] According to one or more embodiments of the present invention, a plurality of pixels include a plurality of first pixels arranged in a first pixel line; and a plurality of second pixels arranged in a second pixel line adjacent to the first pixel line, wherein a 2-1 subpixel of the first pixel includes a first low-potential power supply wiring connected to a first cathode electrode, and a 2-1 subpixel of the second pixel includes a second low-potential power supply wiring connected to a second cathode electrode, the first low-potential power supply wiring extending toward the second cathode electrode, and the first low-potential power supply wiring and the second low-potential power supply wiring can be electrically connected.

[0180] According to one or more embodiments of the present invention, the second-first subpixel of the first pixel may be electrically connected to the compensation circuit of the second-first subpixel of the second pixel via a first low-potential power supply wiring.

[0181] According to one or more embodiments of the present invention, the first compensation circuit for the 1-1 subpixel is connected between the data trace and the low-voltage trace, and the second compensation circuit for the 1-2 subpixel may be connected between the data trace and the low-voltage trace.

[0182] A display device according to one embodiment of the present invention includes a display panel including a plurality of pixels and gate lines and data lines connected to the plurality of pixels; a gate drive unit connected to the gate lines; and a data drive unit connected to the data lines, wherein the plurality of pixels include a first-1 subpixel and a first-2 subpixel of the first color; a second-1 subpixel and a second-2 subpixel of the second color; and a third-1 subpixel and a third-2 subpixel of the third color, wherein the second-1 subpixel and the second-2 subpixel each include a light-emitting element and a compensation circuit, and the compensation circuit of the second-1 subpixel and the compensation circuit of the second-2 subpixel are connected to a single data line.

[0183] According to one or more embodiments of the present invention, the 1-1 subpixel may include a first compensation circuit connected to a first data line, and the 1-2 subpixel may include a second compensation circuit connected to a second data line.

[0184] According to one or more embodiments of the present invention, the 3-1 subpixel and the 3-2 subpixel each include a compensation circuit, and the compensation circuits of the 3-1 subpixel and the 3-2 subpixel can be coupled to a single data line.

[0185] According to one or more embodiments of the present invention, the first color may be red, the second color may be green, and the third color may be blue.

[0186] According to one or more embodiments of the present invention, the plurality of pixels may include a first pixel in which, when a data voltage is applied, all of the second-first subpixels and the second-second subpixels emit light, and a second pixel in which, when the data voltage is applied, only one of the second-first subpixels and the second-second subpixels emits light.

[0187] According to one or more embodiments of the present invention, the data voltage applied to the 2-1 subpixel and the 2-2 subpixel of the second pixel may be greater than the data voltage applied to the 2-1 subpixel and the 2-2 subpixel of the first pixel.

[0188] The display device according to the embodiment of the present invention is applicable to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, sliding devices, variable devices, electronic organizers, e-books, PMPs (portable multimedia players), PDAs (personal digital assistants), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbook computers, workstations, navigation systems, in-car navigation systems, vehicle display devices, vehicle devices, theater equipment, theater display devices, televisions, wallpaper devices, signage devices, game consoles, laptop computers, monitors, cameras, camcorders, and home appliances, etc.

[0189] The present invention described above is not limited to the embodiments and accompanying drawings, and it will be apparent to those with ordinary skill in the art to which the present invention pertains that various substitutions, modifications, and alterations are possible without departing from the technical spirit of the present invention. Therefore, the scope of the present invention is indicated by the claims described below, and all modified or altered forms derived from the meaning and scope of the claims, as well as equivalent concepts, should be interpreted as being included within the scope of the present invention. [Explanation of symbols]

[0190] R1: First red subpixel R2: Second red subpixel G1: First green subpixel G2: Second green subpixel B1: First blue subpixel B2: Second blue subpixel

Claims

1. Multiple pixels, Includes gate lines and data lines connected to the plurality of pixels, The aforementioned multiple pixels are, The first color's first-to-first subpixel and the first-to-second subpixel, The second color subpixels 2-1 and 2-2, and Including the third-1 and third-2 subpixels of the third color, The second-first subpixel and the second-second subpixel each include a light-emitting element and a compensation circuit, The compensation circuit for the second-first subpixel and the compensation circuit for the second-second subpixel are connected to a single data line. The 1-1 subpixel includes a first compensation circuit connected to the first data line, The first and second subpixels include a second compensation circuit connected to the second data line. The first compensation circuit for the 1-1 subpixel is connected between the first data line and the first low-voltage wiring, The second compensation circuit for the first and second subpixels is connected between the second data line and the second low-voltage wiring. Display panel.

2. The subpixel 3-1 and the subpixel 3-2 each include a compensation circuit. The display panel according to claim 1, wherein the compensation circuits for the third-first subpixel and the third-second subpixel are connected to a single data line.

3. The first color mentioned above is red. The aforementioned second color is green. The display panel according to claim 1, wherein the third color is blue.

4. The aforementioned multiple pixels are, When a data voltage is applied, the first pixel, and the subpixels 2-1 and 2-2, all emit light. The display panel according to claim 1, comprising a second pixel which, when the data voltage is applied, emits light only one of the second-first subpixel and the second-second subpixel.

5. The display panel according to claim 4, wherein the data voltage applied to the 2-1 subpixel and the 2-2 subpixel of the second pixel is greater than the data voltage applied to the 2-1 subpixel and the 2-2 subpixel of the first pixel.

6. The aforementioned multiple pixels are, When a data voltage is applied, the third pixel, and the subpixels 3-1 and 3-2, all emit light. The display panel according to claim 4, further comprising a fourth pixel which, when the data voltage is applied, emits light only one of the third-first subpixel and the third-second subpixel.

7. The display panel according to claim 6, wherein the data voltage applied to the 3-1 and 3-2 subpixels of the 4th pixel is greater than the data voltage applied to the 3-1 and 3-2 subpixels of the 3rd pixel.

8. The first gate line connects the 1st-1st subpixel, the 2nd-1st subpixel, and the 3rd-1st subpixel, and The display panel according to claim 1, comprising a second gate line connecting a first-to-second subpixel, a second-to-second subpixel, and a third-to-second subpixel.

9. Each of the first to third subpixels includes an anode electrode and a cathode electrode that apply a voltage to the light-emitting element. The anode electrodes of the 1-1 to 3-2 subpixels are separated from each other. The display panel according to claim 1, wherein the cathode electrodes of the 1-1 to 3-2 subpixels are separated from each other.

10. The display panel according to claim 1, wherein the compensation circuit for the second-first subpixel and the compensation circuit for the second-second subpixel have the same structure.

11. The aforementioned multiple pixels are, Multiple first pixels placed on the first pixel line; and, The first pixel line and the second pixel line adjacent to it include a plurality of second pixels, The second-first subpixel of the first pixel includes a first low-potential power supply wiring connected to the first cathode electrode of the second-first subpixel of the first pixel. The second-first subpixel of the second pixel includes a second low-potential power supply wiring connected to the second cathode electrode of the second-first subpixel of the second pixel, The first low-potential power supply wiring extends toward the second cathode electrode, The second low-potential power supply wiring extends toward the first cathode electrode, The display panel according to claim 1, wherein the first low-potential power supply wiring and the second low-potential power supply wiring are electrically connected to each other.

12. The display panel according to claim 11, wherein the second-first subpixel of the second pixel is electrically connected to the compensation circuit of the second-first subpixel of the first pixel by the first low-potential power supply wiring.

13. A display panel including multiple pixels and gate lines and data lines connected to the multiple pixels, A gate drive unit connected to the gate line, Includes a data drive unit connected to the aforementioned data line, Each of the aforementioned multiple pixels is, The first color's first-to-first subpixel and the first-to-second subpixel, The second color subpixels 2-1 and 2-2, and Including the third-1 and third-2 subpixels of the third color, The second-first subpixel and the second-second subpixel each include a light-emitting element and a compensation circuit, The compensation circuit for the second-first subpixel and the compensation circuit for the second-second subpixel are connected to a single data line. The 1-1 subpixel includes a first compensation circuit connected to the first data line, The first and second subpixels include a second compensation circuit connected to the second data line. The first compensation circuit for the 1-1 subpixel is connected between the first data line and the first low-voltage wiring, The second compensation circuit for the first and second subpixels is connected between the second data line and the second low-voltage wiring. Display device.

14. The subpixel 3-1 and the subpixel 3-2 each include a compensation circuit. The display device according to claim 13, wherein the compensation circuits for the third-first subpixel and the third-second subpixel are connected to a single data line.

15. The first color mentioned above is red. The aforementioned second color is green. The display device according to claim 13, wherein the third color is blue.

16. The aforementioned multiple pixels are, When a data voltage is applied, the first pixel, and the subpixels 2-1 and 2-2, all emit light. The display device according to claim 13, further comprising a second pixel which, when the data voltage is applied, emits light only one of the second-first subpixel and the second-second subpixel.

17. The display device according to claim 16, wherein the data voltage applied to the 2-1 subpixel and the 2-2 subpixel of the second pixel is greater than the data voltage applied to the 2-1 subpixel and the 2-2 subpixel of the first pixel.

Images