Encapsulation of ultra-miniature electronic assemblies

Abstract

To provide a microelectronic assembly and a method of forming the same that satisfy the demand for more compact physical arrangement of microelectronic elements such as integrated chips and dies.SOLUTION: In a microelectronic device 100, a metallic seal ring 302 can be formed surrounding a bonded joint of a cavity wafer 102 and a MEMS wafer 104, and can also be extended to seal a logic device 206 to the MEMS wafer 104. The metallic seal ring creates a hermetic seal around a periphery of microelectronic components (e.g., 102, 104, and 206), fully sealing joints between the components. The metallic seal ring can be located to seal any or all of the joints between the microelectronic components (e.g., 102, 104, and 206), as desired.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] (Priority Claim and Cross - Reference to Related Applications) This application claims the benefit of priority and priority and benefit of U.S. Patent Application No. 15 / 920,759, entitled "Sealing of Ultra - Small Electronic Assemblies", filed on March 14, 2018, and the benefit of 35 U.S.C.§119(e)(1) of U.S. Provisional Patent Application No. 62 / 474,478, entitled "Sealing of Ultra - Small Electronic Assemblies", filed on March 21, 2017, the entire contents of which are incorporated herein by reference.

[0002] (Field of the Invention) The following description relates to the processing of integrated circuits (ICs). More specifically, the following description relates to devices and techniques for processing IC dies and assemblies.

Background Art

[0003] The need for more compact physical arrangements of ultra - small electronic elements such as integrated chips and dies has been increasing further due to the rapid progress of portable electronic devices, the expansion of the Internet of Things, nanoscale integration, sub - wavelength optical integration, etc. As a mere example, a device commonly referred to as a "smartphone" integrates a high - performance data processor, memory, and accessory devices such as a global positioning system receiver, an electronic camera, various sensors, and a local area network connection, along with a high - resolution display and related image - processing chips, into the functionality of a mobile phone. Such a device can provide all the capabilities of full Internet connectivity, entertainment including full - resolution video, navigation, electronic banking, etc. within a pocket - sized device. Composite portable devices need to pack a large number of chips and dies into a small space.

[0004] Miniature electronic devices comprise a thin slab of semiconductor material such as silicon or gallium arsenide. Chips and dies are typically supplied as separate, pre-packaged units. In some unit designs, the die is mounted on a substrate or chip carrier, which is then mounted on a circuit panel such as a printed circuit board (PCB). Dies can be supplied in a package that facilitates handling of the die during manufacturing and when mounting it onto an external substrate. For example, many dies are supplied in packages suitable for surface mounting.

[0005] Numerous packages of this common type have been proposed for various applications. Most commonly, such packages include a dielectric element, usually referred to as a “chip carrier,” and have terminals formed as plated or etched metal structures on that dielectric. These terminals are typically connected to die contacts (e.g., bonding pads) by conductive features such as thin traces extending along the die carrier, and by thin leads or wires extending between the die contacts and the terminals or traces. In surface mount operation, the package can be mounted on a circuit board such that each terminal on the package aligns with a corresponding conductive pad on the circuit board. Solder or other bonding material is generally provided between the terminals and the conductive pads. The package can be permanently bonded in place by melting or “reflowing” the solder, or by heating the assembly to activate the bonding material in any other way.

[0006] Many packages contain solder blobs attached to the package terminals, typically in the form of solder balls with a diameter of approximately 0.02 mm to 0.8 mm (5 to 30 mils). Packages with arrays of solder balls protruding from their bottom surface (e.g., the surface opposite the front of the die) are usually referred to as ball grid array or "BGA" packages. Other packages, referred to as land grid array or "LGA" packages, are fixed to the substrate by thin layers or lands formed from solder. This type of package can be extremely compact. Certain packages, usually referred to as "chip-scale packages," occupy a circuit board area equal to, or only slightly larger than, the area of ​​the devices incorporated within the package. This scale is advantageous because it reduces the overall size of the assembly, allows for the use of short interconnects between various devices on the substrate, and subsequently limits signal propagation time between devices, thus facilitating high-speed operation of the assembly.

[0007] Semiconductor dies may also be provided in a “stacked” arrangement, for example, where one die is provided on a carrier and another die is mounted on top of the first die. These arrangements can enable the mounting of a number of different dies within a single footprint on a circuit board and can further facilitate high-speed operation by providing short interconnects between dies. Often, this interconnect distance can be slightly longer than the thickness of the die itself. To achieve interconnection within the stack of die packages, interconnection structures for mechanical and electrical connections may be provided on both sides (e.g., the surface) of each die package (perhaps excluding the top package). This is done, for example, by providing conductive pads or lands on both sides of the substrate on which the dies are mounted, and the pads are connected through the substrate by conductive vias, etc. Examples of stacked chip arrangements and interconnection structures are provided in U.S. Patent Publication No. 2010 / 0232129, the disclosure of which is incorporated herein by reference. In other embodiments, through-silicon vias (TSVs) are used for interconnection achieved within the stack of die packages. In some cases, dies or wafers may be bonded in a stacked configuration using a variety of bonding technologies, including direct dielectric bonding, non-adhesive technologies such as ZiBond®, or hybrid bonding technologies such as DBI®, both of which are available from Invensas Bonding Technologies, Inc. (formerly Ziptronix, Inc.), Xperi company (see, for example, U.S. Patents 6,864,585 and 7,485,968, which are incorporated herein by reference in their entirety).

[0008] Stacked die and wafer arrangements, including bonded configurations, can also be used to form assembled components such as microelectromechanical systems (MEMS) and sensors. See, for example, U.S. Patent No. 7,109,092, which is incorporated herein in whole. In many of these arrangements, it is desirable that the stacked die and wafer be sealed at their bonded surfaces, for example, to form a sensor cavity. In some cases, ensuring the reliability and longevity of such sealing can be a problem, particularly at the chip scale. [Brief explanation of the drawing]

[0009] Detailed explanations are provided with reference to the attached diagram. In the diagram, the leftmost digit of the reference number identifies the diagram in which the reference number first appears. The use of the same reference number in different diagrams indicates similar or identical items.

[0010] In this description, the devices and systems illustrated in the figures are shown as having a large number of components. Various implementations of the devices and / or systems described herein may include fewer components and remain within the scope of this disclosure. Alternatively, other implementations of the devices and / or systems may include additional components or various combinations of the components described and remain within the scope of this disclosure.

[0011] [Figure 1] (A) shows a cavity wafer bonded to a MEMS wafer using Zibond technology, and (B) shows a cavity wafer bonded to a MEMS wafer using Zibond technology in conjunction with DBI technology.

[0012] [Figure 2] This is a graphical flowchart illustrating an exemplary processing sequence for forming a stacked ultra-miniature electronic device.

[0013] [Figure 3](A) shows a plan view of an exemplary encapsulated ultra-small electronic device according to one embodiment. (B) shows a top view of an exemplary encapsulated ultra-small electronic device according to this embodiment. (C) shows an encapsulated multi-layer ultra-small electronic arrangement.

[0014] [Figure 4] An exemplary encapsulated ultra-small electronic device according to another embodiment is shown. In the example, two separate configurations of an exemplary encapsulation are illustrated.

[0015] [Figure 5] It is a graphical flow diagram illustrating an exemplary processing sequence for forming an encapsulated ultra-small electronic device according to one embodiment.

[0016] [Figure 6] Exemplary embodiments of encapsulations and encapsulated ultra-small electronic devices according to various embodiments are illustrated.

[0017] [Figure 7] Exemplary embodiments of encapsulations and encapsulated ultra-small electronic devices according to further embodiments are illustrated.

[0018] <偶 [Figure 8] It is a graphical flow diagram illustrating an exemplary processing sequence for forming an encapsulated ultra-small electronic device according to another embodiment.

[0019] [Figure 9] Exemplary embodiments of encapsulated ultra-small electronic devices according to various embodiments are illustrated.

[0020] [Figure 10] It is a graphical flow diagram illustrating an exemplary processing sequence for forming an encapsulated ultra-small electronic device according to further embodiments.

[0021] [Figure 11] Illustrative embodiments of a sealed ultra-small electronic device according to various embodiments are illustrated.

[0022] [Figure 12] FIG. is a graphical flow diagram illustrating an exemplary processing sequence for forming a sealed ultra-small electronic device according to additional embodiments.

[0023] [Figure 13] Illustrative embodiments of a sealed ultra-small electronic device according to various embodiments are illustrated. DETAILED DESCRIPTION

[0024] Overview

[0025] Various embodiments of techniques and devices for forming a sealing portion and a sealed ultra-small electronic device are disclosed. The sealing portion is disposed on a joined (e.g., bonded, connected, etc.) surface to seal (e.g., hermetically seal) the joined surface. The joined surface can be sealed to form, as part of the ultra-small electronic device, a sensor cavity or the like. For example, when a die having a recessed surface is joined to another die having a flat surface or a recessed surface, a cavity can be formed between the two dies. In some applications, it may be desirable to hermetically seal this cavity to maintain a specific vacuum level within the cavity and maintain a predetermined leakage rate.

[0026] The leakage rate of a sealed cavity can be examined as a function of the cavity volume. For example, if the cavity volume is 0.01 cc or less, the leakage rate should generally be less than 5E-8 atm-cc / sec of air for the cavity to be considered hermetically sealed. If the cavity volume is in the range of 0.01 to 0.4 cc, the leakage rate should be less than 1E-7, and if the volume is greater than 0.4 cc, the leakage rate should be less than 1E-6 for a hermetically sealed cavity (according to MIL-STD-883 Method 1014 and MIL-STD-750 Method 1071).

[0027] The integrity of the seal around the periphery of the die laminate can be crucial for maintaining the package's specific airtightness and low leak rate. Metals, ceramics, and glass are typical materials used to form seals and prevent water vapor or other gases (such as oxygen) from accessing components inside the package. A well-fabricated airtight seal with a sufficiently low leak rate can keep the inside of the package dry and moisture-free for many years.

[0028] The techniques disclosed herein include forming a seal of (e.g.) one or more metallic material at a joint (e.g., a joint line, seam, etc.) of at least two surfaces to seal the surfaces joined at the joint. In various embodiments, the metallic material may be deposited using electroless plating or the like. In some embodiments, the metallic material may be deposited directly on the joint or the joined surfaces around it. In other embodiments, one or more nonmetallic materials may be deposited on the joined surfaces, and the metallic material can be deposited on the nonmetallic material(s) to seal the joint. The seal may include a continuous seal ring fully formed around the joined die or wafer (e.g., the periphery of the device), or optionally one or more partial seals.

[0029] In various embodiments, the disclosed technology can be used to seal stacked and bonded dies and wafers using the "ZIBOND®" technology, thereby benefiting from additional sealing. For example, in Figure 1A, a cavity wafer 102 is bonded to a micro-electromechanical system (MEMS) wafer 104 (or any other wafer) using, for example, the ZIBOND® technology to form an ultra-small electronic device 100, such as a MEMS sensor device. The cavity wafer 102 (or die) may have one or more cavities or recesses of the same or different sizes. The particularly flat surfaces of the two wafers (102 and 104) are bonded together using a low-temperature covalent bond between two corresponding semiconductor and / or insulating layers. While the bond may be good, the sealing may not be sufficient as hermetically sealed, and the leakage rate may not be low enough for the application. Furthermore, the width of the bond line (P1) may not be optimal, as a relatively long bond line may unnecessarily increase the die size and reduce the number of dies manufactured per wafer.

[0030] In another example, as shown in Figure 1B, sealing can be improved by using Direct Bond Interconnect (DBI®) technology to form one or more metal-to-metal interconnects along the bonding seam. The metal lines 106 are deposited along each of the surfaces to be bonded so as to align with each other and form a metal-to-metal bond when set together using temperature and / or pressure. In some cases, the DBI lines 106 can help reduce the bond line width (P2) while improving the airtightness of the joint. However, the bond line width (P1) required to utilize the ZiBond method may not be sufficient for the application (for example, a bond line width of 100 microns using Zibond may be reduced to tens or even less than 10 microns using DBI, for example). Furthermore, such DBI bonding is not easy to achieve and can increase the complexity and cost of assembly.

[0031] Figure 2 is a graphical flowchart illustrating an exemplary processing sequence 200 for forming a stacked microelectronic device 100. Process 200 and the stacked microelectronic device 100 form the background for discussing various sealing techniques and devices. In various embodiments, process 200, as described with reference to Figure 2, may be modified to include techniques and devices for hermetically sealing the joined components at the joint. Figure 2 illustrates the process of a three-die stack to create a hermetically sealed cavity 202 between the top (and middle) and (middle and) bottom dies. However, as depicted in Figure 1, the stack may also include only two dies with a cavity 202 between them.

[0032] In Block 1, a recessed cavity wafer 102 is formed. Although one cavity 202 is shown in the example in Block 1, several such recessed cavities 202 may be effectively formed on the wafer (or die) 102, so that one or more cavities 202 of similar or different dimensions are formed at each die location. In Block 2, the cavity wafer 102 is bonded to a MEMS wafer 104 (or any other wafer or die) that encloses the cavity 202 internally. The cavity wafer 102 can be bonded to the MEMS wafer 104 using intimate surface bonding technology, e.g., ZIBOND® technology, so that an insulating surface (e.g., SiOx~SiOx, etc.) is bonded. In Block 3, the MEMS wafer 104 may be thinned and patterned to form standoffs. In Block 4, the metallization 204 can be added to the patterned surface of the MEMS wafer 104, including pads, contacts, traces, etc. In the alternative example, no metallization 204 is added to the surface of the MEMS wafer 104. In this embodiment, the miniature electronic device 100 can be attached to another device, such as a logic device wafer, for example, by using Zibond technology (e.g., SiOx-SiOx bonding) on ​​the bonding surface, or by using other bonding technology for dielectrics (polymer materials, e.g., die attach film or paste) on one or both of the bonded surfaces.

[0033] In block 5, an opening is formed in the MEMS wafer 104 to access the cavity 202, defining the properties of the microelectronic device 100 based on its application. In block 6, the microelectronic device 100 can be mounted on a logic device wafer (or die) 206 to provide logic / control (e.g.) for the microelectronic device 100. The metallized layer 204 conductive pads of the microelectronic device 100 are coupled to contacts 208 on the surface of the logic device 206. In block 7, a portion of the microelectronic device 100 (e.g., a portion of the cavity wafer 102) is removed (e.g., etched) to provide access to other conductive pads of the logic device wafer 206, etc. In some cases, the Zibond or DBI interface between the cavity wafer 102 and the MEMS wafer 104 may provide sufficient resistance to the flow of fluids such as gases and / or liquids. In other embodiments, one or more of the joint lines or connecting connections of the miniature electronic device 100 may be sealed for airtightness (e.g., predetermined resistance to the flow of fluids such as gases and / or liquids, and sufficiently low water vapor permeability, oxygen permeability, etc.), as discussed below. Example of an embodiment

[0034] To ensure a robust and hermetically sealed bond, the techniques disclosed herein include bonding the insulating surfaces of a wafer (e.g., 102 and 104) and then adding a metallic seal to the bond line to improve hermetically sealing, as will be further discussed below.

[0035] Figure 3 shows an exemplary embodiment for sealing a miniature electronic device 100, such as a miniature electronic device 100 formed with reference to Figure 2. As shown by the side view of the miniature electronic device 100 in Figure 3A and the top view in Figure 3B, the metal sealing ring 302 can be formed to surround the joint between the cavity wafer 102 and the MEMS wafer 104, and can also be extended to seal a logic device 206 to the MEMS wafer 104. The sealing ring 302 creates an hermetically sealed portion around the periphery of the miniature electronic components (e.g., 102, 104, and 206), completely sealing the joints between the components. The sealing ring 302 can be positioned to seal any or all of the joints between the miniature electronic components (e.g., 102, 104, and 206) as needed.

[0036] In various embodiments, the sealing ring 302 is made of a metallic material (i.e., a metal such as copper, e.g., an alloy, or a metallic composition). In some embodiments, two or more metallic materials may be used in layers (or other combinations) to form the sealing ring 302. In various embodiments, the sealing ring 302 is deposited using electroless plating, electrodeposition, mechanical printing, or various combinations thereof.

[0037] As shown in Figure 3C, multiple sealing rings 302 may be used to seal between multiple components (e.g., 102, 104, 206, and 304) at different stacking levels within the stacked microelectronic arrangement 300. The sealing rings 302 may be used at any or all levels of the stacked arrangement 300 as needed. Although a complete sealing ring 302 is discussed and illustrated, a partial sealing ring 302 may be used wherever desired to form a seal between a joint or microelectronic device (e.g., 100, 300) or components of an assembly (e.g., 102, 104, 206, and 304).

[0038] Figure 4 shows an exemplary sealed microelectronic device 100 using internal seals (e.g., 402 and 404) according to another embodiment. Instead of, or in addition to, the external seal ring 302 shown in Figure 3, the internal seals (e.g., 402 and 404) are formed after a channel 406 is formed (completely or partially) perforated, etched, or otherwise formed around the internal periphery of the joint components (e.g., 102, 104, and 206). Two distinct configurations of exemplary seals are shown in Figure 4, which are a filled seal 402 and a conformal seal 404. Both configurations are formed in the channel 406, perforated portion, etc., as will be discussed further below. The filled seal ring 402 forms an hermetically sealed portion of the joint by largely or completely filling the channel 406 or perforated cavity with one or more metallic materials. The conformal seal ring 404 forms an hermetically sealed portion by plating the walls of the channel 406 or cavity with one or more metallic materials. In various implementation configurations, two or more components (e.g., 102, 104, and 206) may be hermetically sealed using either the filled sealing portion 404 or the conformal sealing portion 406, as needed. In various embodiments, two (or more) components (e.g., 102, 104, and 206) may be sealed using multiple concentric sealing rings (e.g., 302, 402, and 404). The channel 406 may extend through component 104 to the interface with component 102, or it may extend within component 102, as shown.

[0039] Figure 5 is a graphical flowchart illustrating an exemplary processing sequence 500 for forming a sealed micro-electronic device 100 according to one embodiment using internal sealing sections (e.g., 402 and 404). In various embodiments, the process 500 described with reference to Figure 5 may be used to modify other assembly processes (e.g., process 200 mentioned in Figure 2) that involve joining micro-electronic components (e.g., 102, 104, 206, etc.) to include, if necessary, techniques and devices for hermetically sealing the micro-electronic components (e.g., 102, 104, 206, etc.) joined at the joint sections.

[0040] In block 1, a recessed cavity wafer 102 is formed. A channel 406 (or a "cavity ring" that partially or completely surrounds the cavity 202) is formed on the cavity-side surface of the wafer 102. The channel 406 may be formed by etching, perforating, or otherwise removing material from the surface of the wafer 102.

[0041] In block 2, the cavity wafer 102 is bonded to the MEMS wafer 104, which encloses the cavity 202 internally. The cavity wafer 102 can be bonded to the MEMS wafer 104 using an intimate surface bonding technique, such as ZIBOND® technology, where an insulating surface (e.g., SiOx~SiOx, etc.) is bonded. In another example, the cavity wafer 102 can be bonded to the MEMS wafer 104 using another dielectric bonding technique (e.g., a die attach film or paste, a polymer material such as silicon or epoxy, etc., which cannot provide and cannot improve or modify hermetic sealing).

[0042] In block 3, the MEMS wafer 104 may be thinned and patterned to form standoffs. In other cases, the standoffs are optional and do not have to be formed on the MEMS wafer 104. In such cases, the standoffs can be formed on the logic wafer 206 or created by any other material (e.g., die attach film or paste). In block 4, openings are formed in the MEMS wafer 104 to access the cavity 202, defining the characteristics of the microelectronic device 100 based on its application. Additionally, channels 406 are formed in the MEMS wafer 104 (and in some examples, in the cavity wafer 102) to form internal sealing portions (e.g., 402 and 404) and seal the joint between the cavity wafer 102 and the MEMS wafer 104. In some cases, the MEMS wafer 104 can be perforated to open up areas within the MEMS wafer 104 aligned with pre-formed cavity ring channels 406 in the cavity wafer 102. In an alternative case, the MEMS wafer 104 and the cavity wafer 102 can be drilled together to form a cavity ring channel 406 (for example, the channel 406 in the cavity wafer 102 is formed in this step while drilling the MEMS wafer 104, rather than being formed beforehand when bonding the cavity wafer 102 to the MEMS wafer 104).

[0043] In block 5, metallization 204 is added to the patterned surface of the MEMS wafer 104, including pads, contacts, traces, etc. The cavity ring channel 406 may also be metallized at this point. The channel 406 may be partially or completely filled / plated to form a filled sealing ring 402, or the walls of the channel 406 may be metallized / plated to form a conformal sealing ring 404. Either the filled sealing ring 402 or the conformal sealing ring 404 (either may be used) hermetically seals the joint between the cavity wafer 102 and the MEMS wafer 104.

[0044] In another example, after bonding, the MEMS wafer 104 and the cavity wafer 102 can be drilled together to form a cavity ring channel 406, which may be metallized, and then an opening to the cavity 202 is formed within the MEMS wafer 104.

[0045] In block 6, the miniature electronic device 100 may be mounted on a logic device 206 to provide logic / control (e.g.) for the miniature electronic device 100. Conductor pads of the metallized layer 204 of the miniature electronic device 100 can be coupled to contacts 208 on the surface of the logic device 206. In block 7, portions of the miniature electronic device 100 may be removed (e.g., by etching) to provide access to other conductor pads of the logic device 206, etc.

[0046] Figures 6A to 6E illustrate exemplary embodiments of the sealing portions 302, 402, and 404 and the sealed miniature electronic device 100 according to various embodiments. The first embodiment, illustrated in Figure 6A, shows an external sealing portion 302 implemented as described above with reference to Figures 3 and 4. Each sealing portion 302 forms a bead that covers one or more joints or connecting joints between itself and the miniature electronic components 102, 104, and 206 in order to hermetically seal the joints. The sealing portions 302 can be made of metal, alloy, or metal composite material, for example, a combination of two or more metals, a metallic glass composite material, a metallic ceramic composite material, etc.

[0047] A second embodiment, illustrated in Figure 6B, shows a sealing portion having a layered approach, where a polymer sealing portion 602 is first applied to the outside of the joint, and a metallic sealing portion 604 is deposited on top of the polymer sealing portion 602 to form an hermetically sealed seal. In an alternative implementation, multiple polymer materials forming one or more polymer sealing portions 602 and / or multiple metal layers forming one or more metallic sealing portions 604 may also be used to form a sealing ring.

[0048] A third embodiment, shown in Figure 6C, illustrates another external sealing ring 606 made of a sinterable conductive paste, frit-glass composite, or the like. Metal or glass components in the material of the deposited sealing portion 606 provide the desired hermetically sealed seal.

[0049] A fourth embodiment, illustrated in Figure 6D, shows internal sealing portions 402 and 404 as described above with reference to Figures 5 and 6. The channel 406 is formed in the cavity wafer 102, penetrating the MEMS wafer 104, and the channel 406 is plated from the MEMS wafer 104 side with a metallic material, either completely (e.g., 402), partially (not shown), or conformally (e.g., 404).

[0050] The fifth embodiment, shown in Figure 6E, illustrates an example in which a sealing ring (e.g., 404) is formed through multiple components (e.g., 102, 104, and 206). In this example, the logic wafer 206 (or similar) can be thinned and perforated, as can the MEMS wafer 104. For example, the logic wafer 206, MEMS wafer 104, and cavity wafer 102 may be joined in a process and then perforated together or in separate steps to align. By plating or filling the perforated channel 406 from the logic wafer 206 side, a sealing ring (e.g., 404) is formed extending from the logic wafer 206 through the MEMS wafer 104 and into the cavity wafer 102, hermetically sealing each of the joints and the spaces between the components (e.g., 102, 104, and 206). Alternatively, the sealing portion (e.g., 404) may extend through only a portion of the layers / components, as desired. In various embodiments, the metallization of the sealing portion (e.g., 402, 404) may be electrically continuous with or connected to one or more device pads for grounding or the like (it may also be electrically continuous with (e.g.) a ball terminal 608 on the package). Multiple types of metallization (conformal, nonformal) are shown in Figures 6D, 6E and elsewhere in this disclosure, but only a single type of metallization may be used at a time to obstruct fluid flow and thus form continuous or discontinuous shapes to improve airtightness.

[0051] Figures 7A–7D illustrate exemplary embodiments of the sealing portions 402 and 404 and the sealed microelectronic device 100 according to further embodiments. In one embodiment illustrated in Figure 7A, the embedded metal ring 702 is partially or completely embedded within the cavity wafer 102 (and / or MEMS wafer 104) and partially or completely surrounds the cavity 202. The embedded metal ring 702 may be positioned at or near the bonding line and can help seal the bonding joint between the cavity wafer 102 and the MEMS wafer 104. Vias (not shown for simplicity) may extend through the cavity wafer 102 and contact the metal ring 702. In another embodiment illustrated in Figure 7B, the microelectronic device 100 includes the embedded metal ring 702 that partially or completely surrounds the cavity 202, as described above with reference to Figures 5 and 6, and one or more internal sealing portions 402 and / or 404. The channel 406 is formed within the cavity wafer 102, penetrating the MEMS wafer 104 into the embedded metal ring 702, and the channel 406 is plated with a metallic material from the MEMS wafer 104 side, either completely (e.g., 402), partially (not shown), or conformally (e.g., 404).

[0052] As shown in Figure 7B, the internal seals 402 and / or 404 rest on (e.g., in contact with) the embedded metal ring 702. Figures 7C and 7D show close detail views of two (many) possible embodiments of this arrangement. For example, in Figure 7C, the channel 406 has a relatively rectangular cross-section, and in Figure 7D, the channel has a polygonal or other shaped cross-section (e.g., partially or completely elliptical, irregular, etc.). In various embodiments, the widths of the cross-sections of the channel 406 and the seals (402 and / or 404) that contact the embedded metal ring 702 are smaller than the width of the cross-section of the embedded metal ring 702 (e.g., 60% or less). The metal filler of the seal 404 may completely (as seen in Figure 7C) or partially (as seen in Figure 7D) line the inner wall of the channel 406 while in contact with (resting on) the embedded metal ring 702. In various embodiments, the shape of the channel 406 may be predetermined or may be a product of the drilling technique employed to form the channel 406.

[0053] Figure 8 is a graphical flowchart illustrating an exemplary processing sequence 800 for forming a sealed micro-electronic device 100 according to another embodiment using an internal sealing portion (e.g., 806). In various embodiments, the process 800 described with reference to Figure 8 may be used to modify other assembly processes (e.g., process 200 mentioned in Figure 2) that involve joining micro-electronic components (e.g., 102, 104, 206, etc.) to include, if necessary, techniques and devices for hermetically sealing micro-electronic components (e.g., 102, 104, 206, etc.) joined at the joint.

[0054] In block 1, a recessed cavity wafer 102 is formed and prepared for bonding to a second wafer 104. In various embodiments, the bonding surface of the second wafer 104 may include additional layers 802 such as an insulating layer, a dielectric layer, a semiconductor layer, a metal layer, and the like.

[0055] In block 2, the cavity wafer 102 is bonded to the second wafer 104, closing the cavity 202 internally. The cavity wafer 102 can be bonded to the second wafer 104 (and layer 802) using, for example, an intimate surface bonding technique such as ZIBOND® technology, to bond an insulating surface (e.g., SiOx~SiOx). In another example, the cavity wafer 102 can be bonded to the second wafer 104 using a different dielectric bonding technique (e.g., a die attach film or paste, a polymer material such as silicon or epoxy, which cannot provide and cannot improve or modify hermetic sealing).

[0056] In block 3, the cavity wafer 102 and / or the second wafer 104 can be thinned depending on the intended application. In block 4, a coating or layer 804, such as a dielectric layer, may be applied to the exposed surface of the cavity wafer 102. In block 5, one or more channels 406 (or a “cavity ring” that partially or completely surrounds the cavity 202) can be formed through portions of the cavity wafer 102 and the second wafer 104, and through one or both of the layers 802 and 804. The channels 406 may be formed by etching, drilling, or otherwise removing material from wafers 102 and 104, and may open to the outer surface of the cavity wafer 102 or the second wafer 104.

[0057] In block 6, the cavity ring channel 406 can be partially or completely filled / plated with a metallic material (e.g., copper) to form a filled sealing ring 806. The filled sealing ring 806 hermetically seals the joint between the cavity wafer 102 and the second wafer 104, sealing the cavity 202. In one configuration, the top exposed portion of the metal sealing ring 806 includes a redistribution layer (RDL).

[0058] Referring to Figures 9A–9C, several embodiments of the sealed microelectronic device 100 are illustrated as examples. Figure 9A shows a sealed microelectronic device 100 in which the bottom of one or more filled sealing rings 806 are disposed within a layer 802 (which may be, for example, a dielectric layer) and may or may not penetrate the second wafer 104. The opposite end of the filled sealing ring 806 (for example, at the top of the cavity wafer 102) is exposed and may be in contact with a metal layer for, for example, an electrical (and / or heat dissipation) function of the microelectronic device 100.

[0059] Figure 9B shows another sealed microelectronic device 100 in which the bottom of the packed sealing ring 806 is disposed within layer 802 (which may be, for example, a dielectric layer) and may or may not penetrate the second wafer 104. The top of the packed sealing ring 806 forms a redistribution layer (RDL) on a portion of the exposed surface of the cavity wafer 102. In an embodiment, the dielectric layer 804 is patterned such that the dielectric layer 804 does not cover one or more cavities 202. Figure 9C shows a further sealed microelectronic device 100 in which the bottom of the packed sealing ring 806 is disposed within layer 802 (which may be, for example, a dielectric layer) and may or may not penetrate the second wafer 104. The top of the packed sealing ring 806 forms a redistribution layer (RDL) on one or more portions of the exposed surface of the cavity wafer 102. In one embodiment, the dielectric layer 804 is patterned such that it covers one or more cavities 202, but a different layer 902 is arranged to cover the cavities 202. In various embodiments, the different layer 902 may include a substrate, a glass panel, a metal layer, and the like.

[0060] Figure 10 is a graphical flowchart illustrating an exemplary processing sequence 1000 for forming a sealed micro-electronic device 100 according to another embodiment using an internal sealing portion (e.g., 806). In various embodiments, the process 1000 described with reference to Figure 10 may be used to modify other assembly processes (e.g., process 200 mentioned in Figure 2) that involve joining micro-electronic components (e.g., 102, 104, 206, etc.) to include, if necessary, techniques and devices for hermetically sealing micro-electronic components (e.g., 102, 104, 206, etc.) joined at a joint.

[0061] In block 1, a recessed cavity wafer 102 is formed and prepared for bonding to a second wafer 104. In various embodiments, the bonding surface of the second wafer 104 may include additional layers 802 such as an insulating layer, a dielectric layer, a semiconductor layer, a metal layer, and the like.

[0062] In block 2, the cavity wafer 102 is bonded to the second wafer 104, closing the cavity 202 internally. The cavity wafer 102 can be bonded to the second wafer 104 (and layer 802) using, for example, an intimate surface bonding technique such as ZIBOND® technology, to bond an insulating surface (e.g., SiOx~SiOx). In another example, the cavity wafer 102 can be bonded to the second wafer 104 using a different dielectric bonding technique (e.g., a die attach film or paste, a polymer material such as silicon or epoxy, which cannot provide and cannot improve or modify hermetic sealing).

[0063] In block 3, the cavity wafer 102 and / or the second wafer 104 can be thinned depending on the intended application. Furthermore, the assembly featuring the cavity wafer 102 and the second wafer 104 may be inverted for processing from the second wafer 104 side. In block 4, a coating or layer 804, such as a dielectric layer, may be applied to the exposed surface of the second wafer 104. In block 5, one or more channels 406 (or a “cavity ring” that partially or completely surrounds the cavity 202) can be formed through portions of the second wafer 104, portions of the cavity wafer 102, and through one or both of the layers 802 and 804. The channels 406 may be formed by etching, drilling, or otherwise removing material from wafers 102 and 104 and may open to the outer surface of the second wafer 104 or the cavity wafer 102. As described above, the channel may extend only to the interface between wafer (or die) 102 and 104, or it may extend to one or more metallic features such as pads or vias on or within wafer 104.

[0064] In block 6, the cavity ring channel 406 can be partially or completely filled / plated with a metallic material (e.g., copper) to form a filled-seal ring 806. The filled-seal ring 806 hermetically seals the joint between the second wafer 104 and the cavity wafer 102, sealing the cavity 202. In one configuration, the top exposed portion of the metal sealing ring 806 may include a redistribution layer (RDL).

[0065] Referring to Figures 11A and 11B, embodiments of a sealed microelectronic device 100 are illustrated as examples. Figures 11A and 11B show a sealed microelectronic device 100, in which the bottom of a pack-seal ring 806 is disposed within a layer 802 (which may be, for example, a dielectric layer) and may or may not penetrate the cavity wafer 102. The opposite end of the pack-seal ring 806 (for example, at the top of a second wafer 104) is exposed and may contact a metal layer for, for example, the electrical function of the microelectronic device 100. In embodiments, the dielectric layer 804 is patterned such that the dielectric layer 804 does not cover one or more cavities 202, but a different layer 902 is arranged to cover the cavities 202. In various embodiments, the different layer 902 may include a substrate, a glass panel, a metal layer, and the like.

[0066] In various embodiments, as shown in Figures 11A and 11B, one or more cavities 202 extend into the second wafer 104 and the cavity wafer 102. A packing and sealing ring 806 hermetically seals the bonding portion between the second wafer 104 and the cavity wafer 102, thereby sealing the cavity 202. In addition, as shown in Figure 11B, a metal barrier layer 1102 may be applied into one or more of the cavities 202 to further seal one or more cavity portions 202. The metal barrier 1102 may be disposed on the sidewall or on the side, top, and bottom walls, partially or completely covering the inner surface of the cavity 202, as shown in Figure 11B. In one mounting configuration, the metal barrier 1102 may be applied to the inner surface of the cavity 202 before bonding the cavity wafer 102 to the second wafer 104. The bonding process, with or without heating annealing, may include metal-to-metal bonding (e.g., DBI) to bond a metal barrier 1102 located on the inner surface of a cavity wafer 102 to a metal barrier 1102 located on the inner surface of a second wafer 104, thereby forming a continuous metal sealing barrier 1102.

[0067] Figure 12 is a graphical flowchart illustrating an exemplary processing sequence 1200 for forming a sealed micro-electronic device 100 according to another embodiment using an internal sealing portion (e.g., 1202). In various embodiments, the process 1200 described with reference to Figure 12 may be used to modify other assembly processes (e.g., process 200 mentioned in Figure 2) that involve joining micro-electronic components (e.g., 102, 104, 206, etc.) to include, if necessary, techniques and devices for hermetically sealing micro-electronic components (e.g., 102, 104, 206, etc.) joined at a joint.

[0068] In block 1, a recessed cavity wafer 102 is formed and prepared for bonding to a second wafer 104 (which may or may not be a MEMS wafer). In various embodiments, the bonding surface of the second wafer 104 may include additional layers 802 such as an insulating layer, a dielectric layer, a semiconductor layer, a metal layer, and the like.

[0069] In block 2, the cavity wafer 102 is bonded to the second wafer 104, closing the cavity 202 internally. The cavity wafer 102 can be bonded to the second wafer 104 (and layer 802) using, for example, an intimate surface bonding technique such as ZIBOND® technology, to bond an insulating surface (e.g., SiOx~SiOx). In another example, the cavity wafer 102 can be bonded to the second wafer 104 using a different dielectric bonding technique (e.g., a die attach film or paste, a polymer material such as silicon or epoxy, which cannot provide and cannot improve or modify hermetic sealing).

[0070] In block 3, the cavity wafer 102 and / or the second wafer 104 can be thinned depending on the intended application. In block 4, a coating or layer 804, such as a dielectric layer, may be applied to the exposed surface of the cavity wafer 102. In block 5, one or more channels 406 (or a “cavity ring” that partially or completely surrounds the cavity 202) can be formed through portions of the cavity wafer 102 and the second wafer 104, and through one or both of the layers 802 and 804. The channels 406 may be formed by etching, drilling, or otherwise removing material from wafers 102 and 104, and may open to the outer surface of the cavity wafer 102 or the second wafer 104.

[0071] In block 6, the cavity ring channel 406 can be partially filled / plated with a metallic material (e.g., copper) to form a conformal sealing ring 1202. The sealing ring 1202 hermetically seals the joint between the cavity wafer 102 and the second wafer 104, sealing the cavity 202. In various embodiments, the channel 406 may be filled / plated to form a conformal sealing ring 1202, and the metallic layer 1204 is deposited on at least a portion of the exposed surface of the cavity wafer 102. Thus, in various embodiments, the channel 406 is filled in the same or a separate process as the deposition of the metallic layer 1204.

[0072] Referring to Figures 13A–13C, several embodiments of the sealed microelectronic device 100 are illustrated as examples. Figures 13A–13C show a sealed microelectronic device 100 in which a sealing ring 1202 is formed through a cavity layer 102, the bottom of which the sealing ring 1202 is disposed through a layer 802 (which may be, for example, a dielectric layer) and also penetrates a second wafer 104. Figures 13A and 13B show a partially filled sealing ring 1202 (for example, vacuum plated), and the embodiment shown in Figure 13B has a larger amount of metal in the partially filled sealing ring 1202 than the embodiment shown in Figure 13A. Annealing the substrate (bonded wafers 102 and 104) in a partially filled state at a temperature of 80–250C can increase the grain size of the plated metal (for example, 1202 and / or 1204). The process for generating enlarged particle sizes can reduce impurities in the metal layers of the sealing ring 1202 and / or metal layer 1204. In one configuration, the particles have an approximate (e.g., average) diameter greater than 10% of the width dimension of the channel 406.

[0073] Figure 13C shows a sealing ring 1202 fully filled within the channel 406. In some embodiments, the annealed metal of a partially filled sealing ring 1202, as shown in Figures 13A and 13B, can be added to or coated with an additional metal layer to form a fully filled sealing ring 1202. In one embodiment, the sealed microelectronic device 100 may be annealed again after the deposition of the additional metal layer. In some cases, CMP may be used before or after the final annealing to form a desired surface for the filled sealing ring 1202. For reliability, robustness, performance, etc., one or more additional materials may be provided to the unfilled portion of the sealing ring 1202 as needed.

[0074] The top (e.g., exposed) edge (e.g., of the top surface of the cavity wafer 102) of the filled sealing ring 1202 may be exposed and in contact with a metal layer for the electrical function of the miniature electronic device 100, for example, when bonded to another device.

[0075] The quantities of the sealing rings 302, 402, 404, 806, and 1202 shown in Figures 1-13 are for illustrative purposes and for discussion purposes only. In various embodiments, the sealed microelectronic device 100 or similar assemblies may include fewer or more quantities of the sealing rings 302, 402, 404, 806, and 1202, within the scope of this disclosure. Furthermore, various mounting configurations described herein can be combined to further improve conventional techniques for manufacturing MEMS devices. For example, although the sealing rings are shown extending from one side of the component to one surface, the sealing rings may be formed from both sides, in contact with each other, to form a metallic structure that extends completely through the sealed microelectronic device 100. conclusion

[0076] While the implementations of this disclosure have been described in language specific to structural features and / or methodological actions, it should be understood that the implementations are not necessarily limited to the specific features or actions described. Rather, specific features and actions are disclosed as representative forms of implementing the exemplary devices and technologies.

[0077] Each claim in this document constitutes a separate embodiment, and embodiments combining different claims and / or different embodiments are within the scope of this disclosure and will be apparent to those skilled in the art upon further examination of this disclosure.

Claims

1. A miniature electronic assembly, the miniature electronic assembly is A first miniature electronic component comprising a first insulator and a first surface having first conductive characteristics, A second miniature electronic component comprising a second surface including a second insulator and a second conductive feature, wherein the first surface is in contact with the second surface to form a joint, the joint including a dielectric-to-dielectric direct joint between the first insulator and the second insulator, and a metal-to-metal direct joint between the first conductive feature and the second conductive feature, A miniature electronic assembly further comprising a channel including a closed shape portion surrounding an internal region, wherein the height of the channel extends at least across the bonding portion, and a metallic material is disposed in the channel.

2. The miniature electronic assembly according to claim 1, wherein the channel extends through the thickness of the second miniature electronic component and partially extends through the first miniature electronic component.

3. The channel, at the bonding portion, is 1 × 10 per second. -6 atm・cm 3 The ultra-miniature electronic assembly according to claim 1, comprising a continuous channel including an airtight seal configured to prevent fluid leakage exceeding a certain limit.

4. The ultra-miniature electronic assembly according to claim 1, wherein the ultra-miniature electronic assembly comprises a micro-electromechanical system (MEMS) device.

5. The miniature electronic assembly according to claim 1, wherein the metallic material fills the channel at least partially or completely.

6. The miniature electronic assembly according to claim 1, wherein the channel includes a side wall, and the metallic material is located on the side wall.

7. The miniature electronic assembly according to claim 1, wherein the channel is arranged over the junction and around the first miniature electronic component and at least one of the first miniature electronic components.

8. A miniature electronic assembly, the miniature electronic assembly is A first miniature electronic component comprising a first insulator and a first surface having first conductive characteristics, A second miniature electronic component comprising a second insulator and a second surface having second conductive characteristics, The present invention includes a joint between the first surface and the second surface, wherein the first insulator is directly bonded to the second insulator, and the first conductive feature is directly bonded to the second conductive feature. A miniature electronic assembly further comprising channels arranged over the bonding portion, wherein the channels are continuous in an annular manner around the periphery of the bonding portion.

9. The miniature electronic assembly according to claim 8, wherein the channel seals the junction between the first miniature electronic component and the second miniature electronic component.

10. The miniature electronic assembly according to claim 8, further comprising a third miniature electronic component, wherein the third miniature electronic component is bonded to the second miniature electronic component such that the second miniature electronic component is positioned between the first miniature electronic component and the third miniature electronic component.

11. The miniature electronic assembly according to claim 10, wherein the third miniature electronic component is a logic device.

12. The miniature electronic assembly according to claim 11, wherein the first miniature electronic component includes a cavity die, and the second miniature electronic component includes a micro-electromechanical system (MEMS) die.

13. The miniature electronic assembly according to claim 8, wherein the channel comprises a polymer material and a metal layer.

14. The miniature electronic assembly according to claim 8, wherein the channel comprises a sinterable conductive paste or a frit glass composite.

15. A miniature electronic assembly, the miniature electronic assembly is A first miniature electronic component comprising a first insulator and a first surface having first conductive characteristics, A second miniature electronic component comprising a second insulator and a second surface having second conductive characteristics, The present invention includes a joint between the first surface and the second surface, wherein the first insulator is directly bonded to the second insulator, and the first conductive feature is directly bonded to the second conductive feature. A miniature electronic assembly further comprising a channel including an annular portion, the channel extending around the periphery of the first miniature electronic component, and the channel extending at least to the junction.

16. The miniature electronic assembly according to claim 15, wherein the channel includes a metallic material that seals the junction between the first miniature electronic component and the second miniature electronic component.

17. The miniature electronic assembly according to claim 15, wherein a metal material is disposed in the channel.

18. The channel, at the bonding portion, is 1 × 10 per second. -6 atm・cm 3 The ultra-miniature electronic assembly according to claim 17, comprising an airtight sealing portion for preventing fluid leakage exceeding a certain limit.

19. The miniature electronic assembly according to claim 15, wherein the channel includes a layer of metallic material arranged over the side walls of the channel.

20. The miniature electronic assembly according to claim 15, further comprising a third miniature electronic component, wherein the third miniature electronic component is bonded to the second miniature electronic component such that the second miniature electronic component is positioned between the first miniature electronic component and the third miniature electronic component.

21. A method for forming a miniature electronic assembly, The first bonding surface of a first ultra-miniature electronic component is bonded to the second bonding surface of a second ultra-miniature electronic component along the bonding joint, by directly bonding the first insulating surface of the first bonding surface to the second insulating surface of the second bonding surface without adhesive, such that a conformal joint is formed between the first insulating surface and the second insulating surface. After the bonding, a channel is formed from the outer surface of the first miniature electronic component opposite to the first bonding surface, at least to the bonding portion. A method comprising: placing a metallic material on at least the surface of the channel extending from the outer surface of the first miniature electronic component to at least the bonding portion.

22. The method according to claim 21, wherein forming the channel includes forming a channel that crosses the joint portion.

23. The method according to claim 21, further comprising attaching the second bonding surface of the second miniature electronic component to the third miniature electronic component after the bonding.

24. The method according to claim 21, wherein forming the channel includes exposing a metallic feature on or within the second miniature electronic component, and exposing the metallic material on at least the surface of the channel includes bringing the metallic material into contact with the metallic feature on or within the second miniature electronic component.

25. A miniature electronic assembly, the miniature electronic assembly is A first miniature electronic component having a first insulating surface, The present invention includes a second miniature electronic component having a second insulating surface, wherein the first insulating surface and the second insulating surface are directly joined to each other along a joint by a low-temperature covalent bond. A channel extending from the outer surface of the first miniature electronic component, opposite to the first insulating surface, to at least the junction, A miniature electronic assembly further comprising a metallic material disposed on at least the surface of the channel, wherein the metallic material extends from the outer surface of the first miniature electronic component to at least the junction.

26. The miniature electronic assembly according to claim 25, wherein the channel crosses the joint portion.

27. The miniature electronic assembly according to claim 25, wherein the channel extends from the outer surface of the first miniature electronic component to the semiconductor within the second miniature electronic component.

28. The miniature electronic assembly according to claim 27, wherein the channel is in contact with a semiconductor in the second miniature electronic component.

29. The metal material fills the channel, as described in claim 25, for the ultra-miniature electronic assembly.

30. A miniature electronic assembly, the miniature electronic assembly is The first insulating surface includes a first miniature electronic component bonded to the second insulating surface of a second miniature electronic component, and the first insulating surface and the second insulating surface form a bonded joint where the first insulating surface and the second insulating surface come into contact. A miniature electronic assembly further comprising a channel extending at least to the junction, the channel comprising a metallic material and sealing the junction between the first miniature electronic component and the second miniature electronic component, the channel being continuous within at least one periphery of the first miniature electronic component and the second miniature electronic component.

31. The channel, at the bonding portion, is 1 × 10 per second. -6 atm・cm 3 The miniature electronic assembly according to claim 30, comprising an airtight seal configured to prevent fluid leakage exceeding a certain limit.

32. The miniature electronic assembly according to claim 30, wherein the channel extends through the thickness of the second miniature electronic component and partially extends through the thickness of the first miniature electronic component.

33. The miniature electronic assembly according to claim 32, wherein the channel is filled with the metallic material.

34. The miniature electronic assembly according to claim 32, wherein the metal material is conformally arranged on the surface of the channel.

35. The miniature electronic assembly according to claim 32, further comprising a third miniature electronic component, wherein the third miniature electronic component is bonded to the second miniature electronic component such that the second miniature electronic component is positioned between the first miniature electronic component and the third miniature electronic component.

36. The miniature electronic assembly according to claim 35, wherein the first miniature electronic component is directly bonded to the second miniature electronic component by covalent bonding without adhesive, at room temperature, and the second miniature electronic component is directly bonded to the third miniature electronic component by covalent bonding without adhesive, at room temperature, and

37. A miniature electronic assembly, the miniature electronic assembly is The first miniature electronic component is bonded to the second insulating surface of the second miniature electronic component on the first insulating surface, the first insulating surface and the second insulating surface form a joint where they contact each other, and a direct bonding of dielectrics exists between the first insulating surface and the second insulating surface. A miniature electronic assembly further comprising a sealing portion disposed over the joint, the sealing portion comprising a metallic material, sealing the joint between the first miniature electronic component and the second miniature electronic component, and the sealing portion being continuous within at least one peripheral portion of the first miniature electronic component and the second miniature electronic component.

38. The miniature electronic assembly according to claim 37, wherein the sealing portion extends through the thickness of the second miniature electronic component and partially extends through the thickness of the first miniature electronic component.

39. The ultra-miniature electronic assembly according to claim 37, wherein the sealing portion is a filled sealing portion that is filled with the metal material.

40. The miniature electronic assembly according to claim 37, wherein the sealing portion is a conformal sealing portion having a layer of the metal material that extends through the thickness of the second miniature electronic component and conformally arranged on the surface of a channel that extends partially through the thickness of the first miniature electronic component.

41. The miniature electronic assembly according to claim 37, further comprising a direct metal-to-metal connection between the first miniature electronic component and the second miniature electronic component.

42. A miniature electronic assembly, the miniature electronic assembly is The first insulating surface includes a first miniature electronic component bonded to the second insulating surface of a second miniature electronic component, and the first insulating surface and the second insulating surface form a bonded joint where the first insulating surface and the second insulating surface come into contact. The channel further includes a channel extending at least to the joint, made of a metallic material, and sealing the joint between the first miniature electronic component and the second miniature electronic component, A miniature electronic assembly in which the first insulating surface is directly and conformally bonded to the second insulating surface by a room-temperature covalent bond without the use of adhesive.

43. The miniature electronic assembly according to claim 42, wherein the channel extends through the thickness of the second miniature electronic component and partially extends through the thickness of the first miniature electronic component.

44. The miniature electronic assembly according to claim 42, wherein the channel is filled with the metallic material.

45. The miniature electronic assembly according to claim 42, wherein the metal material is conformally arranged on the surface of the channel.

46. The miniature electronic assembly according to claim 42, further comprising a third miniature electronic component, wherein the third miniature electronic component is bonded to the second miniature electronic component such that the second miniature electronic component is positioned between the first miniature electronic component and the third miniature electronic component.

47. A joint structure, said joint structure is A first miniature electronic component comprising a first surface and a second surface opposite to the first surface, wherein the first surface includes a first dielectric and a first conductive feature, A second miniature electronic component including a third surface directly bonded to the first surface without an intervening adhesive to form a joint, A bonded structure comprising a channel extending through the bonded joint, wherein the channel extends continuously around an internal region of the bonded structure, the channel has sidewalls that are at least partially covered with metal, and the sidewalls extend from the second surface into the first miniature electronic component.

48. The joining structure according to claim 47, wherein the joining structure includes directly joined insulating materials, and the directly joined metal interconnecting portions are interconnected at the joining portion.

49. The bonding structure according to claim 47, wherein the bonding structure includes a sensor.

50. The bonding structure according to claim 47, wherein the channel partially extends into the second miniature electronic component.

51. A joint structure, said joint structure is A first miniature electronic component comprising a first surface and a second surface opposite to the first surface, wherein the first surface includes a first dielectric and a first conductive feature, A second miniature electronic component including a third surface directly bonded to the first surface without an intervening adhesive to form a joint, The junction structure includes a channel that extends at least partially around an internal region of the junction structure, the channel extending from the second surface through the first miniature electronic component, across the junction, and into at least a portion of the second miniature electronic component. A jointed structure further comprising a metallic material disposed on at least the channel surface.

52. The bonding structure according to claim 51, wherein the metal material partially fills the channel.

53. The joining structure according to claim 51, wherein the channel extends continuously around the internal region of the joining structure.

54. The joining structure according to claim 51, wherein the joining portion includes a directly joined insulating material, and the directly joined metal interconnection portions are interconnected at the joining portion.

55. A joint structure, said joint structure is A first miniature electronic component comprising a first surface, a second surface opposite to the first surface, and a side wall extending from the first surface to the second surface, A second miniature electronic component including a third surface directly bonded to the first surface without an intervening adhesive to form a joint, The joint structure includes a channel extending through the joint structure, the channel extending continuously around an internal region of the joint structure, and the channel having side walls extending from the second surface into the miniature electronic component. A joining structure, in which, when viewed in a lateral cross-section of the joining joint, metal exists between the side wall and the internal region at intervals of height between the joining joint and the second surface, such that the fluid moves from the side wall to the internal region without encountering the metal.

56. The joining structure according to claim 55, wherein the joining portion includes a directly joined insulating material, and directly joined metal interconnection portions are interconnected at the joining portion.

57. The bonding structure according to claim 55, wherein the channel passes through the first miniature electronic component, crosses the bonding portion, and extends into at least a portion of the second miniature electronic component.

58. A method for forming a joint structure, The first surface of the first miniature electronic component is directly bonded to the second miniature electronic component, After the direct bonding, the first miniature electronic component is thinned from the second surface opposite to the first surface, The thinned first miniature electronic component is provided with a channel extending from the second surface into the thinned first miniature electronic component, wherein the channel extends at least partially around the internal region of the bonding structure. A method further comprising providing a metallic material in the channel.

59. The method according to claim 58, wherein providing the channel includes providing a channel that extends continuously around the internal region.

60. The method according to claim 58, wherein providing the metal material includes at least partially covering the side wall of the channel with the metal material.

61. The method according to claim 58, wherein the direct joining includes directly joining the first insulating material of the first ultra-miniature electronic component to the second insulating material of the second ultra-miniature electronic component, and forming a metal-to-metal junction between the first ultra-miniature electronic component and the second ultra-miniature electronic component.

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