Field-effect transistor with at least partially embedded field plate
A partially embedded field plate in GaN-based HEMTs addresses the reliability issues of conventional designs, improving breakdown voltage and gain in high-power RF applications by minimizing parasitic capacitance.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- WOLFSPEED INC
- Filing Date
- 2025-02-07
- Publication Date
- 2026-07-23
AI Technical Summary
Narrow-bandgap semiconductor materials like silicon and gallium arsenide are unsuitable for high-power and high-frequency applications due to their small bandgap and breakdown voltage, while wide-bandgap materials like silicon carbide and group III nitrides offer improved performance but can exhibit poor reliability with conventional field plates, particularly in Class C operations.
The field plate is partially embedded within the dielectric layer and laterally spaced from the gate, connected to the source contact outside the active region, reducing gate-to-drain capacitance and improving reliability by minimizing overlapping parasitic capacitance.
This configuration enhances the breakdown voltage, linearity, and gain of GaN-based HEMTs, particularly in high-power RF applications, by reducing gate-to-drain capacitance and drain bias dependence.
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Abstract
Description
Technical Field
[0001] The present disclosure relates to transistor structures, and more particularly to electrolytic effect transistors including field plates.
Background Art
[0002] Narrow-bandgap semiconductor materials such as silicon (Si) and gallium arsenide (GaAs) are widely used in semiconductor devices for low-power applications and, in the case of Si, for low-frequency applications. However, these semiconductor materials have a relatively small bandgap (1.12 eV for Si and 1.42 eV for GaAs at room temperature) and a relatively small breakdown voltage, and thus may not be very suitable for high-power and / or high-frequency applications.
[0003] Due to the interest in high-power, high-temperature, and / or high-frequency applications and devices, wide-bandgap semiconductor materials such as silicon carbide (3.2 eV for 4H-SiC at room temperature) and group III nitrides (e.g., 3.36 eV for GaN at room temperature) have attracted attention. These materials can have a higher breakdown field strength and a higher electron saturation velocity than GaAs and Si.
[0004] Particularly interesting devices for high-power and / or high-frequency applications are high electron mobility transistors (HEMTs), also known as modulation doped field effect transistors (MODFETs). In HEMT devices, a two-dimensional electron gas (2DEG) can be formed at the hetero-junction of two semiconductor materials with different bandgap energies, where the material with the smaller bandgap has a higher electron affinity than the wide-bandgap material. The 2DEG is the accumulation layer of the undoped small-bandgap material and has a relatively high sheet electron concentration, e.g., 10
[0004] , , , , 13 , 2 carriers / cm 2It can contain sheet electron concentrations exceeding 2DEG. Furthermore, electrons originating from the wider bandgap semiconductor can transition to 2DEG, and relatively high electron mobility is possible due to reduced scattering of ionized impurities. This combination of relatively high carrier concentration and carrier mobility can give HEMTs relatively large transconductance, resulting in a performance advantage over metal-semiconductor field-effect transistors (MESFETS) for high-frequency applications.
[0005] HEMTs fabricated from gallium nitride / aluminum gallium nitride (GaN / AlGaN) material systems can generate large amounts of RF power due to a combination of material properties such as a relatively high dielectric breakdown field, a relatively wide band gap, a relatively large conduction band offset, and / or a relatively high saturation electron drift rate. The majority of electrons in 2DEG may be due to polarization in the AlGaN.
[0006] Field plates are used to improve the performance of GaN-based HEMTs at microwave frequencies, resulting in improved performance compared to devices without field plates. Many field-plate approaches involve connecting the field plate to the transistor's source, with the field plate placed on the drain side of the channel. This can lower the electric field on the gate-drain side of the transistor, thereby increasing the breakdown voltage and potentially reducing the high-field trapping effect. However, some transistors with gate-drain field plates may exhibit relatively poor reliability performance, particularly in Class C (or higher) operations where the electric field on the source side of the gate is critical.
[0007] Figure 1 shows a GaN-based HEMT 10 formed on a silicon carbide substrate 12. A GaN channel layer 16 is present on the substrate 12, and an AlGaN barrier layer 18 is present on the channel layer 16. A two-dimensional electron gas (2DEG) 20 is generated within the channel layer 16 adjacent to the barrier layer 18. A source contact 22 and a drain contact 24 are formed on the channel layer 16. The conductivity of the 2DEG 20 is modulated by applying a voltage to a gate 26 formed on the barrier layer 18 between the source contact 22 and the drain contact 24. As shown in Figure 1, the gate 26 may have a mushroom configuration or a T-top configuration in which the gate 26 contacts the barrier layer 18 in a relatively narrow contact region extending through the surface dielectric layer 25.
[0008] The HEMT10 includes a field plate 28 connected to the source contact 22. The field plate 28 is separated from the gate 26 by an interlayer dielectric layer 21 and separated from the barrier layer 18 by the interlayer dielectric layer 21 and the surface dielectric layer 25. The field plate 28 extends above the gate 26 and laterally toward the drain 24.
[0009] The field plate 28 is connected to the source contact 22. Connecting the field plate 28 to the source contact 22 reduces the gate-to-drain capacitance (Cgd), thereby increasing the gain of the device. In addition to reducing the gate-to-drain capacitance Cgd, the presence of the field plate 28 can improve the linearity of the device and / or reduce the drain bias dependence of the capacitance. GaN-based HEMTs generally exhibit good linearity, but further improvement may be desired in high-power RF applications. Furthermore, while the structure shown in Figure 1 can reduce the gate-to-drain capacitance Cgd compared to a structure without a field plate, the gate-to-drain capacitance Cgd may still be highly dependent on the bias of the drain contact 24. [Prior art documents] [Patent Documents]
[0010] [Patent Document 1] U.S. Patent No. 6,849,882 [Patent Document 2] U.S. Patent No. 7,230,284 [Patent Document 3] U.S. Patent No. 7,501,669 [Patent Document 4] U.S. Patent No. 7,126,426 [Patent Document 5] U.S. Patent No. 7,550,783 [Patent Document 6] U.S. Patent No. 7,573,078 [Patent Document 7] U.S. Patent Application Publication No. 2005 / 0253167 [Patent Document 8] U.S. Patent Application Publication No. 2006 / 0202272 Specification [Patent Document 9] U.S. Patent Application Publication No. 2008 / 0128752 [Patent Document 10] U.S. Patent Application Publication No. 2010 / 0276698 [Patent Document 11] U.S. Patent Application Publication No. 2012 / 0049973 [Patent Document 12] U.S. Patent Application Publication No. 2012 / 0194276 [Patent Document 13] U.S. Patent No. 9,847,411 [Overview of the Initiative] [Means for solving the problem]
[0011] Transistor elements according to some embodiments include a semiconductor layer, a surface dielectric layer on the semiconductor layer, and at least a portion of a gate on the surface dielectric layer. The surface dielectric layer contains an opening that is spaced laterally from the gate. The transistor element includes an interlayer dielectric layer on the surface dielectric layer and a field plate on the interlayer dielectric layer. The field plate is spaced laterally from the gate, and at least a portion of the field plate is located within the opening in the surface dielectric layer.
[0012] In some embodiments, the field plate includes a non-embedded portion extending over the semiconductor layer. The embedded portion of the field plate is spaced perpendicularly from the semiconductor layer by a shorter distance than the non-embedded portion is spaced perpendicularly from the semiconductor layer.
[0013] The interlayer dielectric layer extends into the opening in the surface dielectric layer. In some embodiments, the opening in the surface dielectric layer extends completely through the surface dielectric layer to expose the semiconductor layer. In some embodiments, the gate extends completely through the surface dielectric layer to contact the semiconductor layer.
[0014] The transistor element may further include source and drain contacts on a semiconductor layer, where the gate is located between the source and drain contacts. The non-embedded portion may include a drain-side wing extending along the semiconductor layer toward the drain contact. In some embodiments, the field plate includes a source-side wing extending along the semiconductor layer toward the source contact. The drain-side wing may have a width ranging from about 0 nm to about 500 nm. In some embodiments, the drain-side wing is spaced perpendicularly from the semiconductor layer by the combined thickness of the interlayer dielectric layer and the surface dielectric layer.
[0015] In some embodiments, the field plate is electrically connected to the source contact outside the active region of the transistor element. The electrical connection between the field plate and the source contact does not necessarily have to cross over the gate.
[0016] The transistor element may further include a second opening in the surface dielectric layer that is laterally spaced from the first opening. The embedded contact portion of the gate may extend through the second opening. The opening may have a chamfered or rounded edge.
[0017] In some embodiments, the embedded portion of the field plate is vertically spaced from the semiconductor layer by the thickness of the interlayer dielectric layer. The embedded portion of the field plate may be vertically spaced from the semiconductor layer by a distance of from about 60 nm to about 300 nm, in some embodiments by a distance of from about 100 nm to about 200 nm, and in still other embodiments by a distance of about 150 nm.
[0018] In some embodiments, the field plate is laterally spaced from the gate by the thickness of the interlayer dielectric layer. In some embodiments, the field plate is laterally spaced from the gate by a thickness of from about 200 nm to about 700 nm, and in still other embodiments by a thickness of from about 200 nm to about 400 nm.
[0019] The field plate may have an overall width from about 600 nm to about 1500 nm, and the embedded portion of the field plate may have a width from about 500 nm to about 900 nm. The opening may have a chamfered or rounded edge.
[0020] A method of forming a transistor element according to some embodiments includes forming a surface dielectric layer on a semiconductor layer, forming an opening in the surface dielectric layer, and forming a gate on the surface dielectric layer. The gate is laterally spaced from the opening. The method further includes forming an interlayer dielectric layer on the gate and the surface dielectric layer, the surface dielectric layer extending into the opening, and forming a field plate on the interlayer dielectric layer above the opening.
[0021] The method may further include the step of forming a second opening in a surface dielectric layer, wherein the first and second openings are spaced laterally apart from each other. A gate may be formed on the second opening, and the gate may include an embedded contact portion extending through the second opening. The embedded contact portion of the gate may be in contact with the semiconductor layer. The second opening may have chamfered or rounded edges.
[0022] The steps of forming the first and second openings include: forming a preliminary surface dielectric layer on a semiconductor layer; selectively etching the preliminary surface dielectric layer to form first and second holes within the preliminary surface dielectric layer; depositing a sacrificial dielectric layer on the semiconductor layer and the preliminary surface dielectric layer, wherein the sacrificial dielectric layer fills the first and second holes; and anisotropically etching the sacrificial dielectric layer to expose portions of the semiconductor layer within the first and second holes and to leave lateral portions of the sacrificial dielectric layer on the inner sidewalls of the first and second holes, wherein the preliminary surface dielectric layer and lateral portions define the surface dielectric layer.
[0023] The method further includes the step of forming source and drain contacts on a semiconductor layer, wherein the gate is located between the source and drain contacts, and the field plate may include a recessed portion above the opening and a drain-side wing extending over the semiconductor layer toward the drain contact.
[0024] The field plate may include a source-side wing that extends over the semiconductor layer toward the source contact.
[0025] The drain-side wing is spaced perpendicularly from the semiconductor layer by the combined thickness of the interlayer dielectric layer and the surface dielectric layer. The drain-side wing may have a width ranging from approximately 0 nm to approximately 500 nm. The embedded portion of the field plate may have a width ranging from approximately 500 nm to approximately 900 nm.
[0026] The method may further include the step of electrically connecting a field plate to a source contact outside the active region of a transistor element, wherein the electrical connection between the field plate and the source contact does not cross over the gate.
[0027] Transistor elements according to some embodiments include a semiconductor layer, a surface dielectric layer on the semiconductor layer, and at least a portion of a gate on the surface dielectric layer. The surface dielectric layer includes an opening therein that is laterally spaced from the gate. The transistor element further includes an interlayer dielectric layer on the surface dielectric layer having a recess above the opening, and at least a portion of a field plate within the recess.
[0028] The field plate may include a non-embedded portion extending over the semiconductor layer, where the portion of the field plate within the recess is separated perpendicularly from the semiconductor layer by a smaller distance than the non-embedded portion is separated perpendicularly from the semiconductor layer. [Brief explanation of the drawing]
[0029] [Figure 1] This is a cross-sectional view of a conventional transistor element, including the field plate. [Figure 2] This is a cross-sectional view of a transistor element, including a field plate according to several embodiments. [Figure 3A] This is a cross-sectional view of a transistor element, including a field plate according to yet another embodiment. [Figure 3B] This is a cross-sectional view of a transistor element, including a field plate according to yet another embodiment. [Figure 4A] This is a graph of the simulated Cgd for elements in several examples. [Figure 4B] This is a graph of the simulated drain-source capacitance Cds for elements in several embodiments. [Figure 5A]This is a cross-sectional view illustrating the operation for manufacturing a transistor element including a field plate according to several embodiments. [Figure 5B] This is a cross-sectional view illustrating the operation for manufacturing a transistor element including a field plate according to several embodiments. [Figure 5C] This is a cross-sectional view illustrating the operation for manufacturing a transistor element including a field plate according to several embodiments. [Figure 5D] This is a cross-sectional view illustrating the operation for manufacturing a transistor element including a field plate according to several embodiments. [Figure 5E] This is a cross-sectional view illustrating the operation for manufacturing a transistor element including a field plate according to several embodiments. [Figure 5F] This is a cross-sectional view illustrating the operation for manufacturing a transistor element including a field plate according to several embodiments. [Figure 5G] This is a cross-sectional view illustrating the operation for manufacturing a transistor element including a field plate according to several embodiments. [Figure 5H] This is a cross-sectional view illustrating the operation for manufacturing a transistor element including a field plate according to several embodiments. [Figure 6] This is a plan view of the conventional transistor structure outside the active region of the element. [Figure 7] This is a plan view of the transistor structure outside the active region of the element, according to several embodiments. [Figure 8] This block diagram shows the operation for forming a transistor element according to several embodiments. [Figure 9A] This is a schematic block diagram of a multi-stage amplifier circuit that can use an RF transistor amplifier incorporating transistor elements according to the embodiment. [Figure 9B]This is a schematic block diagram of a multi-stage amplifier circuit that can use an RF transistor amplifier incorporating transistor elements according to the embodiment. [Figure 9C] This is a schematic block diagram of a multi-stage amplifier circuit that can use an RF transistor amplifier incorporating transistor elements according to the embodiment. [Modes for carrying out the invention]
[0030] Next, embodiments of the concept of the present invention will be described in relation to the accompanying drawings. Some embodiments described herein provide a transistor element including a field plate which is automatically aligned with respect to the gate so as not to overlap with the gate in the vertical direction, and in some embodiments, is spaced laterally from the gate. In some embodiments, the field plate is embedded toward the barrier layer in the embedded region. In yet another embodiment, the field plate may be connected to a source outside the active region of the element by a non-crossing connection over the gate of the element.
[0031] In this specification, various elements may be described using ordinal numbers, such as 1st, 2nd, 3rd, etc., but it should be understood that these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, the 1st element may also be called the 2nd element, and similarly, the 2nd element may also be called the 1st element without departing from the scope of this disclosure.
[0032] Furthermore, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship between one element and another, as shown in the drawings. It should be understood that relative terms are intended to encompass different orientations of elements in addition to the orientation depicted in the drawings. For example, if an element is turned upside down in one of the drawings, a feature described as being on the "lower" side of the element will be oriented towards the "upper" side of that element. Thus, the exemplary term "lower" can describe both downward and upward orientations, depending on the specific orientation of the element. Similarly, if an element is turned upside down in one of the drawings, an element described as "below" or "below" other elements will be oriented above those other elements. Thus, the exemplary terms "downward" or "lower" can describe both upward and downward orientations.
[0033] The terms used in the description of the disclosure herein are intended solely to describe specific embodiments and are not intended to limit the disclosure. Where used in the description of the disclosure and the accompanying claims, the singular forms "an" and "the" are intended to include the plural form unless the context explicitly indicates otherwise. It should also be understood that the terms "and / or" as used herein refer to and encompass any and all possible combinations of one or more of the related enumerated items. Where used herein, the terms "comprise" and "comprising" indicate the presence of the described steps, operations, features, elements, and / or components, but do not preclude the presence or addition of one or more other steps, operations, features, elements, components, and / or groups thereof.
[0034] The embodiments of this disclosure are described herein with reference to schematic cross-sectional views of idealized embodiments of this disclosure. Therefore, variations from the shapes shown in the figures are to be expected, for example, as a result of manufacturing techniques and / or tolerances. Accordingly, the embodiments of this disclosure should not be construed as being limited to specific shapes of the regions shown herein, but should include, for example, deviations in shape resulting from manufacturing. The regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the elements, nor are they intended to limit the scope of the disclosure unless otherwise specified. Furthermore, for schematic reasons, lines that appear straight, horizontal, or vertical in the following drawings are often inclined, curved, non-horizontal, or non-vertical. Furthermore, it is understood that the thickness of the elements is schematic in nature.
[0035] Unless otherwise defined, all terms used in disclosing the embodiments of this disclosure, including technical and scientific terms, have the same meaning as commonly understood by those skilled in the art and are not necessarily limited to any specific definition known at the time of this disclosure. These terms may include equivalent terms created after such time. Furthermore, terms such as those defined in commonly used dictionaries should be understood to have meanings consistent with those in the context of this specification and the art.
[0036] Referring to Figure 2, transistor elements according to several embodiments are illustrated. In particular, Figure 2 shows a high electron mobility transistor 100 formed on a substrate 112. A channel layer 116 is formed on the substrate 112, and a barrier layer 118 is located on the channel layer 116.
[0037] Source contact 122 and drain contact 124 are formed on the channel layer 116. The gate 126 is formed on the barrier layer 118 between the source contact 122 and the drain contact 124. As shown in Figure 2, the gate 26 may have a mushroom configuration or a T-top configuration, in which the gate 126 contacts the barrier layer 118 in a relatively narrow contact area of the embedded contact portion 127 of the gate 126, and the embedded contact portion 127 extends through the surface dielectric layer 125 inside the gate opening 162 that passes through the surface dielectric layer 125.
[0038] The surface dielectric layer 125 also includes a field plate opening 164 that passes through the surface dielectric layer 125, exposing the barrier layer 118.
[0039] In some embodiments, the substrate 112 contains silicon carbide, the channel layer 116 contains GaN, and the barrier layer contains AlGaN. However, it will be understood that other materials or combinations of materials can also be used. Furthermore, the channel layer 116 and / or the barrier layer 118 may be Al x Ga 1-x It may include alloys such as N, where 0 ≤ x ≤ 1. Although a HEMT element is shown, it will be further understood that element 100 may be other types of transistor elements such as a metal-semiconductor field-effect transistor (MESFET), a junction field-effect transistor (JFET), or a metal oxide semiconductor field-effect transistor (MOSFET).
[0040] Element 100 includes a field plate 140 connected to the source contact 122 via a connection outside the active region of the element, as will be described later in relation to Figures 6 and 7. As will be described later, in some embodiments, the connection between the field plate 140 and the source contact 122 does not cross over the gate 126.
[0041] The field plate 140 is separated laterally from the gate 126 by the interlayer dielectric layer 121 and does not extend over or beyond the gate 126, as in the structure shown in Figure 1. This can result in insufficient step coverage and potential cracking of the metallization of the field plate. The field plate 140 is electrically connected to the source contact 122 outside the active region of the device (and outside the plane shown in Figure 2).
[0042] Similar to the gate 126, the field plate 140 may have a mushroom configuration or a T-top configuration, which is partially embedded and comprises a central recessed portion 144 and one or more wing portions extending laterally from the recessed portion 144. In the embodiment shown in Figure 2, the field plate 140 includes a source-side wing 146 extending laterally toward the source contact 122 and a drain-side wing 148 extending laterally toward the drain contact 124.
[0043] The field plate 140 is generally spaced perpendicularly from the barrier layer 118 by the interlayer dielectric layer 121 and the surface dielectric layer 125. The distance d2 between the wings of the field plate 140 and the barrier layer 118 is equal to the combined thickness of the interlayer dielectric layer 121 and the surface dielectric layer 125. The field plate 140 includes an embedded portion 144 above the field plate opening 164, and the embedded portion 144 is spaced perpendicularly from the barrier layer 118 within the region above the field plate opening 164 by a distance d1 equal only to the thickness of the interlayer dielectric layer 121.
[0044] The field plate 140 has a total width L1. The source-side wing 146 of the field plate 140 has a width L2, the embedded portion 144 of the field plate 140 has a width L3, and the drain-side wing 148 of the field plate 140 has a width L4. The embedded portion 144 of the field plate 140 is laterally spaced L5 from the gate 126, and the field plate 140 is laterally spaced L6 from the gate 126. By adjusting the distances d1, d2, and widths L1 to L6, several degrees of freedom are provided for modulating the gate-source capacitance and gate-drain capacitance of the element, as will be described below.
[0045] A passivation layer 132 is formed on the interlayer dielectric layer 121 and the field plate 140, and a field dielectric layer 134 is formed on the passivation layer 132. The passivation layer 132 may fill the gap between the field plate 140 and the gate 126 that is not filled by the interlayer dielectric layer 121.
[0046] The surface dielectric layer 125, interlayer dielectric layer 121, passivation layer 132, and field dielectric layer 134 may include one or more layers of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, or other atomic layer deposited films, or a multilayer insulating structure such as an oxide-nitride-oxide layer. In a particular embodiment, the surface dielectric layer 125 and interlayer dielectric layer 121 contain silicon nitride, the passivation layer 132 contains silicon oxynitride, and the field dielectric layer 134 contains silicon nitride.
[0047] Figure 3A shows a HEMT transistor element structure 200A according to yet another embodiment. Element 200 is similar to element 100 shown in Figure 2, with the same numbering referring to the same elements, except that element 200 does not include the source wing 146. That is, the distance L5 between the embedded portion 144 of the field plate 140 and the gate 126 defines the distance L6 between the field plate 140 and the gate 126, and the width L2 of the source wing 146 is zero.
[0048] By providing the embedded portion 144 of the field plate 140, the drain-source capacitance Cds and gate-train capacitance Cgd of the element change. In particular, by providing the embedded portion 144 of the field plate 140, it is possible to decrease the gate-drain capacitance Cgd of the element at a certain level of drain voltage, at the expense of increasing the drain-source capacitance Cds at low drain voltages.
[0049] Figure 3B shows a HEMT transistor element structure 200B according to yet another embodiment. Element 200 is similar to element 100 shown in Figure 2, with the same numbering referring to the same elements, except that element 200 does not include the source wing 146 or the drain wing 148. That is, the width L4 of the drain wing 148 is zero.
[0050] For example, Figure 4A is a graph of the simulated gate-drain capacitance Cgd for elements with a partially embedded field plate according to several embodiments, while Figure 4B is a graph of the simulated drain-source capacitance Cds for elements with a partially embedded field plate according to several embodiments. Referring to Figure 4A, simulated curves of the gate-drain capacitance Cgd are plotted for elements where the distance d1 between the embedded portion 144 of the field plate 140 and the barrier layer 118 is 200 nm (curve 402) and 150 nm (curve 404). The distance d1 between the embedded portion 144 of the field plate 140 and the barrier layer 118 is defined by the thickness of the interlayer dielectric layer 121.
[0051] In some embodiments, the distance d1 between the embedded portion 144 of the field plate 140 and the barrier layer 118 is approximately 60 nm to approximately 300 nm, and in some embodiments, it is between approximately 100 nm and 200 nm. As described herein, embedding a portion of the field plate 140 can reduce the gate-drain capacitance Cgd, which can improve the efficiency, linearity, gain, and / or bandwidth of amplifiers fabricated using this device. Furthermore, by using an etching process to form a field plate opening 164 in the surface dielectric layer 125 that defines the position of the embedded portion 144 of the field plate 140, precise control over the position of the embedded portion 144 is possible, thereby improving the process repeatability and manufacturability of the device while also providing more precise control over the electrical characteristics of the device.
[0052] Isolating the field plate 140 laterally from the gate 126 (for example, by not overlapping the field plate 140 and the gate 126) can reduce the gate-drain capacitance Cgd and / or drain-source capacitance Cds of the device by improving the field plate 140's ability to block the gate-to-drain feedback capacitance. In other words, overlapping the field plate 140 and the gate 126 can result in additional parasitic capacitance without any additional benefit.
[0053] As shown in Figure 4A, for drain voltages greater than 30V, particularly around 30-40V, the simulated device with a distance d1 of 150nm exhibits a lower gate-drain capacitance Cgd compared to the simulated device with a distance d1 of 200nm.
[0054] Referring to Figure 4B, the simulated device with a distance d1 of 150 nm exhibits an undesirably high drain-source capacitance Cds for drain voltages of less than approximately 30 V compared to the simulated device with a distance d1 of 200 nm. However, since the normal operating point of GaN-based HEMTs is a drain voltage of approximately 50 V, this increased drain-source capacitance Cds may not affect normal device operation.
[0055] Therefore, it is considered that laterally separating the field plate 140 from the gate 126 can improve the drain-source capacitance Cds while compromising the effect of the field plate 140 on the gate-drain capacitance Cgd. Thus, the distance of the gap L6 between the field plate 140 and the gate 126 (as shown in Figures 2 and 3) can be selected to reduce the gate-drain capacitance Cgd without adversely affecting the drain-source capacitance Cds. For example, in some embodiments, the gap L6 between the field plate 140 and the gate 126 may be between 0.2 microns and 0.7 microns. If the gap is less than 0.2 microns, reliability issues may arise, and if the gap exceeds 0.7 microns, the gate-drain capacitance Cgd may become undesirably high. In some embodiments, the gap L6 may be between approximately 0.2 microns and approximately 0.4 microns.
[0056] The overall width of the field plate 140 (L1 in Figures 2 and 3) may be approximately 0.6 microns to approximately 1.5 microns.
[0057] The width of the embedded portion 144 of the field plate 140 (L3 in Figures 2 and 3) may be approximately 0.5 microns to 0.9 microns.
[0058] In some embodiments, the gate opening 162 and the field plate opening 164 may be formed to have chamfered or rounded edges. Chamfering or rounding the edges of the gate opening 162 and the field plate opening 164 results in shapes corresponding to the embedded contact portion 127 of the gate 126 and the embedded portion 144 of the field plate 140, which helps to reduce field crowding around the gate 126 and the field plate 140.
[0059] The widths L2 and L4 of the source wing 146 and drain wing 148 of the field plate 140 may also affect the gate-drain capacitance Cgd and / or drain-source capacitance Cds of the element. The lengths of the wings 146 and 148 may involve a trade-off between the gate-drain capacitance Cgd and the drain-source capacitance Cds. For example, the drain wing 148 may decrease the gate-drain capacitance Cgd but increase the drain-source capacitance Cds. The drain wing 148 may have a length L4 between approximately zero and 0.5 microns (Figures 2 and 3). In particular, the drain wing 148 may have a length L4 of approximately 0.3 microns. The source wing 146 may have a length L2 between approximately zero and 0.3 microns (Figures 2 and 3). In particular, the source wing 146 may have a length L2 of zero microns.
[0060] Furthermore, because of the reduced parasitic capacitance, the field plate 140 does not need to handle the same high levels of current and may therefore be formed to have a smaller thickness than would otherwise be required.
[0061] Figures 5A to 5H are cross-sectional views illustrating the operation for manufacturing a transistor element including a field plate according to several embodiments.
[0062] Referring to Figure 5A, a substrate 112 is provided on which a channel layer 116 and a barrier layer 118 are formed. A preliminary surface dielectric layer 125' is formed on the barrier layer 118. A layer of photoresist 52 is formed on the preliminary surface dielectric layer 125' and patterned to form two holes 54 and 56 within it.
[0063] Referring to Figure 5B, the preliminary surface dielectric layer 125' is selectively etched through two holes 54, 56 using, for example, reactive ion etching or inductively coupled plasma, to form two corresponding holes 154, 156 inside.
[0064] Referring to Figure 5C, the sacrificial dielectric layer 165 is blanket-deposited on the preliminary surface dielectric layer 125' to fill the holes 154 and 156. The sacrificial dielectric layer 165 may be formed from the same material as the preliminary surface dielectric layer 125'. For example, both the sacrificial dielectric layer 165 and the preliminary surface dielectric layer 125' may be formed from silicon nitride.
[0065] Referring to Figure 5D, the sacrificial dielectric layer 165 is anisotropically etched using, for example, reactive ion etching or inductively coupled plasma 167 to remove portions of the sacrificial dielectric layer 165, except for the lateral portions 166 on the inner surface of the hole 154 of the preliminary surface dielectric layer 125' and the lateral portions 168 on the inner surface of the hole 156 of the preliminary surface dielectric layer 125', to form a gate opening 162 and a field plate opening 164 with rounded or chamfered edges, as shown in Figure 5E. Together with the lateral portions 166 and 168, the preliminary surface dielectric layer 125' forms the surface dielectric layer 125 on the barrier layer 118. With the lateral portions 166 present, the width of the gate opening 162 is approximately 250 nm.
[0066] Referring to Figure 5F, a metal such as gold is deposited and patterned on the surface dielectric layer 125 to form a mushroom gate or T-top gate 126. The embedded contact portion of the gate 126 extends through the gate opening 162 and contacts the barrier layer 118. Next, the interlayer dielectric layer 121 is blanket-deposited on the surface dielectric layer 125 and the gate 126. The interlayer dielectric layer 121 extends through the field plate opening 164 and contacts the barrier layer 118.
[0067] Referring to Figure 5G, a metal such as gold is then deposited on the interlayer dielectric layer 121 above the field plate opening 164 and patterned to form the field plate 140. The field plate 140 is separated from the barrier layer 118 by a distance d1 corresponding to the thickness of the interlayer dielectric layer 121 inside the field plate opening 164, and by a distance d2 corresponding to the sum of the thicknesses of the interlayer dielectric layer 121 and the surface dielectric layer 125 outside the field plate opening 164. The field plate 140 is laterally spaced from the gate 126 by a distance L6 approximately equal to the thickness of the interlayer dielectric layer 121. Thus, the field plate 140 is automatically aligned with respect to the gate 126 by a distance L6.
[0068] Referring to Figure 5H, a passivation layer 132, such as a silicon dioxide layer, is formed on the field plate 140 and the interlayer dielectric layer 121. Finally, a field dielectric layer 134, such as silicon nitride, is formed on the passivation layer 132.
[0069] As described above, to further reduce the gate-drain capacitance Cgd and / or drain-source capacitance Cds, the field plate 140 may be connected to the source contact 122 outside the active region of the element so that the connection does not cross over the gate metal. For example, Figure 6 is a plan view of a portion of a conventional transistor structure outside the active region 300 of the element, where the “active region of the element” generally refers to the region of the element where an electrical channel is formed between the source region and the drain region, and electrical conduction occurs through the channel layer 116 during the ON-state operation of the element. As shown in Figure 6, in a conventional element structure, the field plate 140 metallization crosses over the gate 126 metallization and contacts the source overmetallization 222. This arrangement can increase the gate-drain capacitance Cgd and / or drain-source capacitance Cds of the element.
[0070] Figure 7 is a plan view of a portion of the transistor structure in some embodiments, outside the active region 300 of the element. As shown in Figure 7, in some embodiments, the field plate 140 metallization extends around the distal end 126A of the gate 126 metallization (rather than crossing over the gate 126 metallization) and contacts the source overmetallization 222. This arrangement can reduce the gate-drain capacitance Cgd and / or drain-source capacitance Cds of the element.
[0071] Figure 8 is a block diagram illustrating the operation of forming a transistor element according to several embodiments. Referring to Figures 8 and 5A to 5H, a method for forming a transistor element according to several embodiments includes the steps of: forming a surface dielectric layer 125 on a semiconductor layer (block 802); forming an opening 164 within the surface dielectric layer (block 804); forming a gate 126 on the surface dielectric layer 125, wherein the gate is laterally spaced from the opening 164 (block 806); forming an interlayer dielectric layer 121 on the gate and the surface dielectric layer 125, wherein the surface dielectric layer extends into the opening 164 (block 808); and forming a field plate 140 on the interlayer dielectric layer 121 above the opening 164 (block 810).
[0072] The method further includes the step of forming a second opening in a surface dielectric layer, wherein the first and second openings are spaced laterally apart from each other. A gate is formed on the second opening, and the gate includes an embedded contact portion that passes through the second opening. The embedded contact portion of the gate may be in contact with a semiconductor layer.
[0073] This method may further include the step of forming a source contact and a drain contact on a semiconductor layer, wherein the gate is located between the source contact and the drain contact. The field plate may include a recessed portion above the opening and a drain-side wing extending over the semiconductor layer toward the drain contact. In some embodiments, the field plate includes a source-side wing extending over the semiconductor layer toward the source contact.
[0074] The embedded portion of the field plate may be spaced perpendicularly from the semiconductor layer by the thickness of the interlayer dielectric layer. In some embodiments, the embedded portion of the field plate may be spaced perpendicularly from the semiconductor layer by a distance of about 60 nm to about 300 nm, in some embodiments by a distance of about 100 nm to about 200 nm, and in some embodiments by a distance of about 150 nm.
[0075] The drain-side wing may be spaced perpendicularly from the semiconductor layer by the combined thickness of the interlayer dielectric layer and the surface dielectric layer. In some embodiments, the drain-side wing has a width of approximately 0 to 500 nm.
[0076] The field plate may be spaced laterally from the gate by the thickness of the interlayer dielectric layer. In some embodiments, the field plate is spaced laterally by a thickness of about 200 nm to about 700 nm, and in some further embodiments, by a thickness of about 200 nm to about 400 nm.
[0077] In some embodiments, the field plate has a total width of approximately 600 nm to approximately 1500 nm. In some embodiments, the embedded portion of the field plate has a width of approximately 500 nm to approximately 900 nm.
[0078] In some embodiments, the opening and / or the second opening have chamfered or rounded edges.
[0079] The steps of forming the first and second openings may include the steps of forming a preliminary surface dielectric layer on a semiconductor layer, selectively etching the preliminary surface dielectric layer to form the first and second holes within the preliminary surface dielectric layer, and depositing a sacrificial dielectric layer on the semiconductor layer and the preliminary surface dielectric layer, wherein the sacrificial dielectric layer fills the first and second holes. The sacrificial dielectric layer may be subjected to anisotropic etching in order to expose portions of the semiconductor layer within the first and second holes and to leave the lateral portions of the sacrificial dielectric layer on the inner sidewalls of the first and second holes.
[0080] This method may further include the step of connecting a field plate to a source contact outside the active region of a transistor element, wherein the electrical connection between the field plate and the source contact extends around the end of the gate and does not cross over the gate.
[0081] The transistor elements described herein can be used in amplifiers operating in a wide variety of different frequency bands. In some embodiments, an RF transistor amplifier incorporating such transistor elements can be configured to operate at frequencies above 1 GHz. In other embodiments, the RF transistor amplifier can be configured to operate at frequencies above 2.5 GHz. In yet another embodiment, the RF transistor amplifier can be configured to operate at frequencies above 3.1 GHz. In yet another embodiment, the RF transistor amplifier can be configured to operate at frequencies above 5 GHz. In some embodiments, the RF transistor amplifier can be configured to operate in at least one of the frequency bands of 2.5–2.7 GHz, 3.4–4.2 GHz, 5.1–5.8 GHz, 12–18 GHz, 18–27 GHz, 27–40 GHz, or 40–75 GHz, or sub-bands thereof.
[0082] While embodiments of the present invention have been discussed above in relation to HEMT devices, it will be understood that the inventive concepts described herein can be applied to other types of semiconductor devices such as MOSFETs, DMOS transistors, and / or laterally diffused MOS (LDMOS) transistors.
[0083] RF transistor amplifiers incorporating the transistor elements described herein can be used in standalone RF transistor amplifiers and / or multiple RF transistor amplifiers. Examples of how RF transistor amplifiers according to several embodiments can be used in applications involving multiple amplifiers are discussed with reference to Figures 9A-9C.
[0084] Referring to Figure 9A, the RF transistor amplifier 1000A is schematically illustrated, which includes a preamplifier 1010 and a main amplifier 1030 electrically connected in series. As shown in Figure 9A, the RF transistor amplifier 1000A includes an RF input 1001, a preamplifier 1010, an interstage impedance matching network 1020, a main amplifier 1030, and an RF output 1002. The interstage impedance matching network 1020 may include, for example, inductors and / or capacitors arranged in an optional, appropriate configuration to form a circuit that improves impedance matching between the output of the preamplifier 1010 and the input of the main amplifier 1030. Although not shown in Figure 9A, the RF transistor amplifier 1000A may further include an input matching network interposed between the RF input 1001 and the preamplifier 1010, and / or an output matching network interposed between the main amplifier 1030 and the RF output 1002. The RF transistor amplifier according to this embodiment may be used to implement either or both of the preamplifier 1010 and the main amplifier 1030.
[0085] Referring to Figure 9B, an RF transistor amplifier 1000B is schematically illustrated, which includes an RF input 1001, a pair of preamplifiers 1010-1 and 1010-2, a pair of interstage impedance matching networks 1020-1 and 1020-2, a pair of main amplifiers 1030-1 and 1030-2, and an RF output 1002. A splitter 1003 and a combiner 1004 are also provided. Preamplifier 1010-1 and main amplifier 1030-1 (which are electrically connected in series) are electrically connected in parallel with preamplifier 1010-2 and main amplifier 1030-2 (which are electrically connected in series). Similar to the RF transistor amplifier 1000A in Figure 9A, the RF transistor amplifier 1000B may further include an input matching network interposed between the RF input 1001 and preamplifiers 1010-1 and 1010-2, and / or an output matching network interposed between the main amplifiers 1030-1 and 1030-2 and the RF output 1002.
[0086] As shown in Figure 9C, RF transistor amplifiers according to some embodiments can also be used to implement Doherty amplifiers. As is known in the art, a Doherty amplifier circuit includes first and second (or higher) power-coupled amplifiers. The first amplifier is called the “main” amplifier or “carrier” amplifier, and the second amplifier is called the “peaking” amplifier. The biases of the two amplifiers may be different. For example, in one common Doherty amplifier implementation, the main amplifier may be a Class AB or Class B amplifier, while the peaking amplifier may be a Class C amplifier. Doherty amplifiers can operate more efficiently than balanced amplifiers when operating at power levels retreated from saturation. The RF signal input to the Doherty amplifier is split (e.g., using a quadrature coupler), and the outputs of the two amplifiers are coupled. The main amplifier is configured to turn on first (i.e., at a lower input power level), so that only the main amplifier operates at lower power levels. As the input power level increases towards saturation, the peaking amplifier is turned on, and the input RF signal is split between the main amplifier and the peaking amplifier.
[0087] As shown in Figure 9C, the DohertyRF transistor amplifier 1000C includes an RF input 1001, an input splitter 1003, a main amplifier 1040, a peaking amplifier 1050, an output combiner 1004, and an RF output 1002. The DohertyRF transistor amplifier 1000C includes a 90° transformer 1007 at the input of the peaking amplifier 1050 and a 90° transformer 1005 at the input of the main amplifier 1040, and may optionally include an input matching network and / or an output matching network (not shown). The main amplifier 1040 and / or the peaking amplifier 1050 can be implemented using any of the above-described RF transistor amplifiers according to the embodiment.
[0088] The RF transistor amplifiers according to the embodiments may be formed as discrete components or as part of a monolithic microwave integrated circuit (MMIC). An MMIC is an integrated circuit that operates on radio frequency and / or microwave frequency signals, in which all the circuits for a specific function are integrated on a single semiconductor chip. An example MMIC element is a transistor amplifier, including associated matching circuits, power supply networks, etc., all mounted on a common substrate. An MMIC transistor amplifier typically includes multiple unit cell HEMT transistors connected in parallel.
[0089] Many modifications are possible to the features of the above embodiment. Transistor structures having features that can be used in embodiments of the present invention are disclosed in the following generally assigned publications, the contents of which are fully incorporated herein by reference: U.S. Patent No. 6,849,882, Chavarkar et al., "Group-III Nitride Based High Electron Mobility Transistor (HEMT) With Barrier / Spacer Layer"; U.S. Patent No. 7,230,284, Parikh et al., "Insulating Gate AlGaN / GaN HEMT"; U.S. Patent No. 7,501,669, Parikh et al., "Wide Bandgap Transistor Devices With Field Plates"; U.S. Patent No. 7,126,426, Mishra et al., "Cascode Amplifier Structures Including Wide Bandgap Field Effect Transistor With Field Plates"; U.S. Patent No. 7,550,783, Wu et al., "Wide Bandgap HEMTs With Source Connected Field Plates"; U.S. Patent No. 7,573,078, Wu et al., "Wide "Bandgap Transistors With Multiple Field Plates"; U.S. Patent Application Publication No. 2005 / 0253167, Wu et al., "Wide Bandgap Field Effect Transistors With Source Connected Field Plates"; U.S. Patent Application Publication No. 2006 / 0202272, Wu et al., "Wide Bandgap Transistors With Gate-Source Field Plates"; U.S. Patent Application Publication No. 2008 / 0128752, Wu, "GaN Based HEMTs With Buried Field Plates";U.S. Patent Application Publication No. 2010 / 0276698, Moore et al., "Gate Electrodes For Millimeter-Wave Operation and Methods of Fabrication"; U.S. Patent Application Publication No. 2012 / 0049973, Smith, Jr. et al., "High Power Gallium Nitride Field Effect Transistor Switches"; U.S. Patent Application Publication No. 2012 / 0194276, Fisher, "Low Noise Amplifiers Including Group III Nitride Based High Electron Mobility Transistors"; and U.S. Patent No. 9,847,411, Sriram et al., "Recessed field plate transistor structures".
[0090] While embodiments of the concept of the present invention have been described in considerable detail with reference to their specific configurations, other versions are also possible. The field plate and gate can also have many different shapes and can be connected to the source contacts in various ways. Therefore, the spirit and scope of the present invention should not be limited to the specific embodiments described above.
Claims
1. A semiconductor structure comprising a channel layer and a barrier layer on the channel layer, wherein the barrier layer has a higher band gap than the channel layer, The source contact and drain contact on the semiconductor structure, The gate contact on the semiconductor structure between the source contact and the drain contact, A field plate on the semiconductor structure between the gate contact and the drain contact, wherein the field plate includes a field plate that is laterally offset from the gate contact by a certain distance and includes a first wing portion extending from the central portion of the field plate, An interlayer dielectric layer extending above the gate contact and below the field plate and A transistor element comprising, A transistor element in which the field plate is offset laterally from the gate contact by a distance defined by the vertical thickness of the interlayer dielectric layer.
2. The transistor element according to claim 1, wherein the distance is approximately 0.2 μm to 0.7 μm.
3. The transistor element according to claim 2, wherein the aforementioned distance is approximately 0.4 μm.
4. The transistor element according to claim 1, wherein the first wing portion of the field plate is the source-side wing portion.
5. The transistor element according to claim 4, wherein the field plate further comprises a drain-side wing portion.
6. The transistor element according to claim 1, wherein the first wing portion of the field plate is the drain-side wing portion.
7. The transistor element according to claim 1, wherein the central portion of the field plate is spaced a first distance from the barrier layer, and the first wing portion of the field plate is spaced a second distance longer than the first distance from the barrier layer.
8. The transistor element according to claim 1, wherein the gate contact includes a first wing portion extending from the central portion of the gate contact.
9. The transistor element according to claim 8, wherein the first wing portion of the gate contact is the drain-side wing portion.
10. The transistor element according to claim 9, wherein the gate contact further includes a source-side wing portion extending from the central portion of the gate contact.
11. The transistor element according to claim 1, further comprising a first insulating layer and a second insulating layer, wherein the first insulating layer and the second insulating layer are located between the barrier layer and the first wing portion of the field plate.
12. The transistor element according to claim 11, wherein the first insulating layer is located between the central portion of the field plate and the barrier layer, and the second insulating layer is not located between the central portion of the field plate and the barrier layer.
13. A step of forming a semiconductor structure including a channel layer and a barrier layer on the channel layer, wherein the barrier layer has a higher band gap than the channel layer, The steps of forming source contacts and drain contacts on the semiconductor structure, The steps include forming a gate contact on the semiconductor structure, The steps include forming an interlayer dielectric layer extending over the gate contact, A step of forming a field plate on the semiconductor structure between the gate contact and the drain contact, wherein the interlayer dielectric layer extends below the field plate, and A method for forming a transistor element, including, The field plate is spaced laterally from the gate contact by a distance determined by the vertical thickness of the interlayer dielectric layer. The method wherein the field plate includes a first wing portion extending from the central portion of the field plate.
14. The method according to claim 13, wherein the distance is approximately 0.2 μm to 0.7 μm.
15. The method according to claim 14, wherein the distance is approximately 0.4 μm.
16. The method according to claim 13, wherein the first wing portion of the field plate is the source-side wing portion.
17. The method according to claim 16, wherein the field plate further comprises a drain-side wing portion.
18. The method according to claim 13, wherein the first wing portion of the field plate is the drain-side wing portion.
19. The method according to claim 13, wherein the step of forming the gate contact includes the step of forming the gate contact such that it has a first wing portion extending from the central portion of the gate contact.
20. The method according to claim 19, wherein the first wing portion of the gate contact is the drain-side wing portion.
21. The method according to claim 20, wherein the gate contact further includes a source-side wing portion extending from the central portion of the gate contact.