Light-emitting diode (LED) chip and method for manufacturing a light-emitting diode (LED) chip

Abstract

A solid-state lighting device is disclosed that includes a light-emitting diode (LED) and a semitransparent metal layer deposited on the LED chip, capable of dimming the light output of the LED chip. The thickness of the semitransparent metal layer can be adjusted based on the desired dimming level. In embodiments, the metal layer is deposited on top of a passivation layer on the LED structure, such that the metal layer is not electrically coupled to the LED. The metal layer can additionally cover the mesa sidewalls of the LED structure. In other embodiments, the metal layer can be titanium, platinum, or other suitable metal. In embodiments, the metal layer can be deposited on the passivation layer, and the length of time the metal layer is deposited can be based on the amount of dimming desired.

Description

[Technical Field]

[0001]

[0001] This disclosure relates to a solid-state lighting device including a light-emitting diode (LED), and more particularly to a metal layer that dimmes the light emitted from an LED chip. [Background technology]

[0002]

[0002] Solid-state lighting devices such as light-emitting diodes (LEDs) are increasingly used in both consumer and commercial applications. Advances in LED technology have resulted in highly efficient, mechanically robust, and long-lasting light sources. Consequently, modern LEDs enable a variety of new display applications and are increasingly being used in general lighting applications, often replacing incandescent and fluorescent light sources.

[0003]

[0003] An LED is a solid-state device that converts electrical energy into light, and generally includes an active layer (or active region) of one or more semiconductor materials positioned between an n-type layer and a p-type layer doped on opposite sides. When a bias is applied to the entire doped layer, holes and electrons are injected into one or more active layers, where they recombine to produce light such as visible light or ultraviolet light. The active region can be made from, for example, silicon carbide, gallium nitride, gallium phosphide, aluminum nitride, and / or gallium arsenide-based materials, and / or organic semiconductor materials. The photons produced by the active region are emitted in all directions.

[0004]

[0004] As modern LED technology advances, there is a continuing need for improved LED and solid-state lighting devices that have desirable lighting characteristics and can overcome the challenges associated with conventional devices. [Overview of the Initiative] [Means for solving the problem]

[0005]

[0005] This disclosure relates to solid-state lighting devices including light-emitting diodes (LEDs), and more specifically to a semi-transparent metallic layer that can be deposited on an LED chip to dim the light output of the LED chip. The thickness of the semi-transparent metallic layer can be adjusted based on the desired dimming level. In embodiments, the metallic layer can be deposited on top of a passivation layer on the LED structure so that the metallic layer is not electrically coupled to the LED. In addition, the metallic layer can cover the mesa sidewall of the LED structure. In other embodiments, the metallic layer can be titanium, platinum, or other suitable metal. In embodiments, the metallic layer can be sputter-deposited on the passivation layer, and the length of time the metallic layer is sputter-deposited can be based on the desired dimming amount.

[0006]

[0006] In one embodiment, the LED chip is an active LED structure comprising an n-type layer, a p-type layer, and an active layer between the n-type layer and the p-type layer, forming a mesa with a mesa sidewall defining the periphery of the active LED structure; a metal layer that is partially transparent to the wavelength of light produced by the active LED structure; and a passivation layer located between the metal layer and the active LED structure, thereby electrically isolating the metal layer from the active LED structure.

[0007]

[0007] In another embodiment, the LED chip may include a carrier submount. The LED chip may also include an active LED structure bonded to the carrier submount, the active LED structure comprising an n-type layer, a p-type layer, and an active layer positioned between the n-type and p-type layers, and the active LED structure forming a mesa with mesa sidewalls defining the periphery of the active LED structure. The LED chip may also include a metal layer that is partially transparent to the wavelength of light produced by the active LED structure. The LED chip may also include a dielectric layer between the metal layer and the active LED structure, thereby electrically isolating the metal layer from the active LED structure.

[0008]

[0008] In another embodiment, a method for manufacturing an LED chip is disclosed. The method comprises forming an active LED structure on a carrier submount, the active LED structure comprising an n-type layer, a p-type layer, and an active layer between the n-type and p-type layers, and the active LED structure forms a mesa with mesa sidewalls defining the periphery of the active LED structure. The method may also comprise depositing a passivation layer on the active LED structure. The method may also comprise depositing a metal layer partially transparent to the wavelength of light produced by the active LED structure on the passivation layer, the metal layer being electrically isolated from the active LED structure, and the metal layer attenuating the light emitted by the active LED structure.

[0009]

[0009] In another embodiment, further advantages can be obtained by combining any of the above embodiments individually or together, and / or by combining the various individual embodiments and features described herein. Any of the various features and elements disclosed herein can be combined with one or more other disclosed features and elements unless otherwise indicated herein.

[0010]

[0010] Those skilled in the art will understand the scope of the present disclosure and its additional aspects after reading the following detailed description of preferred embodiments in conjunction with the accompanying drawings.

[0011] The accompanying drawings incorporated herein and forming part of herein illustrate several aspects of this disclosure and, together with the description, are useful in illustrating the principles of this disclosure. [Brief explanation of the drawing]

[0011] [Figure 1]

[0012] This is a generalized cross-sectional view of a light-emitting diode (LED) chip embodying a vertical chip structure according to one or more embodiments of the present disclosure. [Figure 2]

[0013] This is a cross-sectional view of an LED chip similar to the LED chip in Figure 1, further comprising a metal layer that dims the light emitted by the LED chip according to one or more embodiments of the present disclosure. [Figure 3]

[0014] This is a cross-sectional view of an LED chip which is a different embodiment of the LED chip shown in Figure 2 in accordance with one or more embodiments of the present disclosure. [Figure 4]

[0015] Figure 4A is a top view of a metal-less LED chip according to one or more embodiments of the present disclosure.

[0016] Figure 4B is a top view of an LED chip having a metal layer according to one or more embodiments of the present disclosure. [Figure 5]

[0017] This is a flowchart showing a method for manufacturing an LED chip having a metal layer according to one or more embodiments of the present disclosure. [Figure 6]

[0018] This graph shows experimental results illustrating the light transmittance as a function of the thickness of the metal layer according to one or more embodiments of this disclosure. [Modes for carrying out the invention]

[0012]

[0019] The embodiments described below provide the information necessary to enable those skilled in the art to carry out the embodiments and illustrate the best mode of carrying out the embodiments. By reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and recognize applications of these concepts not specifically addressed herein. It should be understood that these concepts and applications are included within the scope of this disclosure and the accompanying claims.

[0013]

[0020] In this specification, terms such as first, second, etc. may be used to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. The term "and / or" used herein includes any and all combinations of one or more of the associated listed items.

[0014]

[0021] When an element such as a layer, region, or substrate is said to be "on" or "extending on" another element, it will be understood that the element can be directly on or extending directly above the other element, or there may be intervening elements. In contrast, when an element is said to be "directly on" or "extending directly on" another element, there are no intervening elements. Similarly, when an element such as a layer, region, or substrate is said to be "on" or "extending on" another element, it will be understood that the element can be directly above or extending directly above the other element, or there may be intervening elements. In contrast, when an element is said to be "directly above" or "extending directly above" another element, there are no intervening elements. Also, when an element is said to be "connected" or "coupled" to another element, it will be understood that the element can be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is said to be "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0015]

[0022] Relative terms such as "under", "on", "above", "below", "horizontal", or "vertical" in this specification may be used to describe the relationship between one element, layer, or region and another element, layer, or region as illustrated in the figures. It will be understood that these terms, as well as the terms discussed above, are intended to encompass different orientations of the device in addition to the orientation shown in the figures.

[0016]

[0023] The terms used in this specification are for the purpose of describing particular embodiments only and are not intended to limit the disclosure. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Further, the terms "comprising", "comprises", "including", and / or "includes" as used herein specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0017]

[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Further, the terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0018]

[0025] Embodiments are described herein with reference to schematic drawings of embodiments of the present disclosure. Therefore, actual dimensions of layers and elements may differ, and variations from the exemplary shapes are expected, for example, as a result of manufacturing techniques and / or tolerances. For example, areas illustrated or described as squares or rectangles may have rounded or curved features, and areas illustrated as straight lines may have some irregularities. Thus, areas illustrated in the drawings are schematic, and the shapes of those areas are not intended to illustrate the exact shapes of areas in the device, nor are they intended to limit the scope of the disclosure. In addition, the size of structures or areas may be exaggerated in comparison to other structures or areas for illustrative purposes, and are therefore provided to illustrate a general structure of the subject matter of the present invention, and may or may not be drawn to scale. Elements common to both drawings may be indicated herein by common element numbers and may not be described again later.

[0019]

[0026] This disclosure relates to a solid-state lighting device including a light-emitting diode (LED), and more specifically, to a translucent metal layer deposited on an LED chip that can dim the light output of the LED chip. The thickness of the translucent metal layer can be adjusted based on the desired dimming level. In embodiments, the metal layer can be deposited on top of a passivation layer on the LED structure, thereby preventing the metal layer from being electrically coupled to the LED. In addition, the metal layer can cover the mesa sidewalls of the LED structure. In other embodiments, the metal layer can be titanium, platinum, or other suitable metals. In embodiments, the metal layer can be sputter-deposited on the passivation layer, and the length of time the metal layer is sputter-deposited can be based on the desired dimming amount.

[0020]

[0027] LED chips typically comprise an active LED structure or region, which may have many different semiconductor layers arranged in different ways. The manufacturing and operation of LEDs and their active structures are generally known in the art and will be briefly discussed herein. The layers of an active LED structure can be manufactured using known processes that have suitable processes, such as manufacturing using metal-organic chemical vapor deposition. The layers of an active LED structure may comprise many different layers, and generally may comprise an active layer sandwiched between an n-type epitaxial layer and a p-type epitaxial layer, all of which are doped on opposite sides and formed in a continuous manner on a growth substrate. Additional layers and elements may also be included in an active LED structure, but are not limited to, buffer layers, nucleation layers, superlattice structures, undoped layers, cladding layers, contact layers, current-spreading layers, light extraction layers, and elements. The active layer may comprise a single quantum well, multiple quantum wells, a double heterostructure, or a superlattice structure.

[0021]

[0028] Active LED structures can be fabricated from different material systems, some of which are Group III nitride-based. Group III nitrides refer to semiconductor compounds formed between nitrogen (N) and elements of Group III of the periodic table, typically aluminum (Al), gallium (Ga), and indium (In). Gallium nitride (GaN) is a common binary compound. Group III nitrides also refer to ternary and quaternary compounds such as aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN). In the case of Group III nitrides, silicon (Si) is a common n-type dopant, and magnesium (Mg) is a common p-type dopant. Therefore, the active layer, n-type layer, and p-type layer may include one or more layers of GaN, AlGaN, InGaN, and AlInGaN, either undoped or doped with Si or Mg, in the case of Group III nitride-based material systems. Other material systems include silicon carbide (SiC), organic semiconductor materials, and other III-V group systems such as gallium phosphide (GaP), gallium arsenide (GaAs), and related compounds.

[0022]

[0029] Active LED structures can be grown on growth substrates that can contain many materials, including sapphire, SiC, aluminum nitride (AlN), and GaN. A suitable substrate is the 4H polytype of SiC, but other SiC polytypes, including 3C, 6H, and 15R polytypes, can also be used. SiC has certain advantages, such as closer crystal lattice match with group III nitrides than other substrates, resulting in high-quality group III nitride films. SiC also has very high thermal conductivity, so the total power output of group III nitride devices on SiC is not limited by the thermal dissipation of the substrate. Sapphire is another common substrate for group III nitrides and also has certain advantages, such as low cost, established manufacturing processes, and excellent light-transmitting optical properties.

[0023]

[0030] Different embodiments of the active LED structure can emit light of different wavelengths depending on the composition of the active layer, n-type layer, and p-type layer. In certain embodiments, the active LED structure may emit blue light with a peak wavelength range of approximately 430 nanometers (nm) to 480 nm. In other embodiments, the active LED structure may emit green light with a peak wavelength range of 500 nm to 570 nm. In other embodiments, the active LED structure may emit red light with a peak wavelength range of 600 nm to 650 nm. In certain embodiments, the active LED structure may emit light with peak wavelengths in any region of the visible spectrum, for example, mainly in the range of 400 nm to 700 nm.

[0024]

[0031] In certain embodiments, an active LED structure may be configured to emit light outside the visible spectrum, including one or more portions of the ultraviolet (UV), infrared (IR), or near-IR spectrum. The UV spectrum is typically divided into three wavelength range categories, indicated by the letters A, B, and C. Thus, UV-A light is typically defined as a peak wavelength range of 315 nm to 400 nm, UV-B as a peak wavelength range of 280 nm to 315 nm, and UV-C as a peak wavelength range of 100 nm to 280 nm. UV LEDs are particularly important for use in applications related to the disinfection of microorganisms in air, water, and surfaces. For other applications, the UV LED may be provided with one or more emissive materials to provide an LED package with aggregated emission having a broad spectrum and improved color quality for visible light applications. The near-IR and / or IR wavelengths of the LED structures of this disclosure may have wavelengths greater than 700 nm, such as in the range of 750 nm to 1100 nm or more.

[0025]

[0032] An LED chip can be covered with one or more lumiphoric or other conversion materials such as phosphors, so that at least a portion of the light from the LED chip is absorbed by one or more phosphors and converted into one or more different wavelength spectra according to the characteristic emission from one or more phosphors. In some embodiments, the combination of an LED chip and one or more phosphors emits a combination of light that is generally white. One or more phosphors may be yellow (e.g., YAG:Ce), green (e.g., LuAg:Ce), and red (e.g., Ca i-x-y Sr x EU y The luminescent materials described herein may include AlSiN3) luminescent phosphors and combinations thereof. The luminescent materials described herein may be one or more of phosphors, scintillators, luminescent inks, quantum dot materials, day glow tapes, etc., or may include them. The luminescent materials may be provided by any suitable means, such as direct coating on one or more surfaces of LEDs, dispersion in an encapsulant material configured to cover one or more LEDs, and / or coating on one or more optical or support elements (e.g., by powder coating, inkjet printing, etc.). In certain embodiments, the luminescent materials may be down-converted or up-converted, and combinations of both down-converted and up-converted materials may be provided. In certain embodiments, multiple different (e.g., different compositions) luminescent materials arranged to produce different peak wavelengths may be arranged to receive light from one or more LED chips. In some embodiments, one or more phosphors may be a yellow phosphor (e.g., YAG:Ce), a green phosphor (e.g., LuAg:Ce), and a red phosphor (e.g., Ca i-x-y Sr x EU yThis may include AlSiN3) and combinations thereof. One or more light-emitting materials may be provided in various configurations on one or more parts of an LED chip and / or submount. In certain embodiments, one or more surfaces of an LED chip may be conformally coated with one or more light-emitting materials, while other surfaces of such an LED chip and / or associated submount may be free of light-emitting materials. In certain embodiments, the top surface of an LED chip may include light-emitting materials, while one or more sides of an LED chip may not. In certain embodiments, all or substantially all (e.g., not the contact definition surface or mounting surface) outer surfaces of an LED chip may be coated or covered with one or more light-emitting materials. In certain embodiments, one or more light-emitting materials may be distributed substantially uniformly on or over one or more surfaces of an LED chip. In other embodiments, one or more light-emitting materials may be distributed non-uniformly with respect to one or more of the material composition, concentration, and thickness of an LED chip. In certain embodiments, the filling density of one or more light-emitting materials may vary on or between one or more outer surfaces of an LED chip. In certain embodiments, one or more light-emitting materials may be patterned on one or more surfaces of an LED chip to include one or more stripes, dots, curves, or polygonal shapes. In certain embodiments, multiple light-emitting materials may be arranged on or in different separate regions or layers of the LED chip.

[0026]

[0033] Light emitted from the active layer or region of an LED chip can typically travel in various directions. For directional applications, internal mirrors or external reflective surfaces may be applied to redirect as much light as possible in the desired direction of emission. Internal mirrors may consist of one or more layers. Some multilayer mirrors include a metallic reflective layer and a dielectric reflective layer, with the dielectric reflective layer positioned between the metallic reflective layer and multiple semiconductor layers. Passivation layers are positioned between the metallic reflective layer and first and second electrical contacts, with the first electrical contacts positioned to communicate conductively with the first semiconductor layer and the second electrical contacts positioned to communicate conductively with the second semiconductor layer. In the case of single-layer or multilayer mirrors containing surfaces with reflectivity less than 100%, some light may be absorbed by the mirror. In addition, light redirected through the active LED structure may be absorbed by other layers or elements within the LED chip.

[0027]

[0034] As used herein, a layer or region of an emitting device may be considered “transparent” if at least 80% of the emitted light striking the layer or region passes through it. Furthermore, as used herein, a layer or region of an LED may be considered “reflective,” or embody a “mirror” or “reflector,” if at least 80% of the emitted light striking the layer or region is reflected. In some embodiments, the emitted light comprises visible light, such as blue and / or green LEDs, with or without the emitting material. In other embodiments, the emitted light may comprise invisible light. For example, in the case of GaN-based blue and / or green LEDs, silver (Ag) may be considered a reflective material (e.g., at least 80% reflectance). In the case of UV LEDs, suitable materials may be selected to provide a desired, in some embodiments, high reflectance, and / or, in some embodiments, low absorptance. In certain embodiments, a “light-transmitting” material may be configured to transmit at least 50% of the emitted light of a desired wavelength.

[0028]

[0035] This disclosure may be useful for LED chips having various shapes, such as vertical shapes. Vertical LED chips typically include anode and cathode connections on opposite sides or faces of the LED chip. In certain embodiments, vertical LED chips may also include a growth substrate positioned between the anode and cathode connections. In certain embodiments, the LED chip structure may include a carrier submount, where the growth substrate is removed. In yet other embodiments, any of the described principles may also be applicable to flip-chip structures, where the anode and cathode connections are made from the same side of the LED chip for flip-chip mounting to a different surface.

[0029]

[0036] Aspects of the present invention relate to solid-state lighting devices including light-emitting diodes (LEDs), and more particularly to translucent metal layers deposited on LED chips that can dim the light output of the LED chips. The metal layer can be translucent with respect to the wavelength of light emitted from the LED chip. Standard sapphire substitutes are often too bright and therefore difficult to meet the binning requirement. Since existing chip platforms can include titanium or other metal layers instead of etching passivation and texturing, this disclosure provides a solution for providing chips of varying brightness using the same chip platform. Different dimming levels can be provided by changing the thickness of the metal layer, so that various brightness requirements can be met with a single LED chip platform. Titanium or platinum metal layers can be used because the metal layer adheres well to the passivation layer and can withstand gold etchant while having the function of blocking light.

[0030]

[0037] Figure 1 is a generalized cross-sectional view of an LED chip 10 embodying a vertical chip structure according to the principles of this disclosure. The LED chip 10 includes an active LED structure 12 formed on a carrier submount 14. The active LED structure 12 generally refers to a portion of the LED chip 10 that includes semiconductor layers, such as an epitaxial semiconductor layer, which form a structure that generates light when electrically activated. The active LED structure 12 can be made of various materials, but a suitable material is silicon or doped silicon, which is formed on and supported by the carrier submount 14. In certain embodiments, the carrier submount 14 comprises a conductive material, and the carrier submount 14 becomes part of the conductive connection to the active LED structure 12. The active LED structure 12 may generally comprise a p-type layer 16, an n-type layer 18, and an active layer 20 positioned between the p-type layer 16 and the n-type layer 18. The active LED structure 12 may include, but is not limited to, many additional layers, such as buffer layers, nucleation layers, superlattice structures, undoped layers, cladding layers, contact layers, current diffusion layers, photoextraction layers, and elements. In addition, the active layer 20 may comprise a single quantum well, multiple quantum wells, a double heterostructure, or a superlattice structure. In Figure 1, the p-type layer 16 is positioned between the active layer 20 and the carrier submount 14 such that the p-type layer 16 is closer to the carrier submount 14 than the n-type layer 18. The active LED structure 12 can first be formed by epitaxially growing or depositing the n-type layer 18, the active layer 20, and the p-type layer 16 in sequence on a growth substrate. Next, the active LED structure 12 may be inverted and bonded to the carrier submount 14 via one or more bonding metals 22, and the growth substrate is removed. In this way, the top surface 18' of the n-type layer 18 forms the principal photoextraction surface of the LED chip 10. In certain embodiments, the top surface 18' may have a textured or patterned surface to improve light extraction. In other embodiments, the doping order may be reversed, so that the n-type layer 18 is positioned between the active layer 20 and the carrier submount 14. In embodiments, an outer layer 50 is applied onto the top surface 18' of the n-type layer 18 to cover and protect the top surface 18'.In an embodiment, the outer layer 50 can be a neutral dielectric material such as SiN, SiO2, or Al2O3, or other suitable passivation materials.

[0031]

[0038] The LED chip 10 may include a first reflective layer 24 provided on the p-type layer 16. In a particular embodiment, a current diffusion layer 26 may be provided between the p-type layer 16 and the first reflective layer 24. The current diffusion layer 26 may include a thin layer of a transparent conductive oxide such as indium tin oxide (ITO), or a thin metal layer such as platinum (Pt), although other materials may be used. The first reflective layer 24 may comprise many different materials, and preferably comprises a material that exhibits an index of refraction step with respect to the material of the active LED structure 12 and promotes total internal reflection (TIR) of the light generated from the active LED structure 12. The light undergoing TIR is redirected without undergoing absorption or loss, thereby contributing to the useful or desired light emission of the LED chip. In a particular embodiment, the first reflective layer 24 comprises a material having a refractive index lower than that of the material of the active LED structure 12. The first reflective layer 24 may comprise many different materials, such as those having a refractive index less than 2.3, less than 2.15, less than 2.0, less than 1.5. In a particular embodiment, the first reflective layer 24 comprises a dielectric material such as silicon dioxide (SiO2) and / or silicon nitride (SiN). SiN, SiN x , Si3N4, Si, germanium (Ge), SiO2, SiO x , titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), ITO, magnesium oxide (MgO xIt is understood that many dielectric materials can be used, such as GaN, zinc oxide (ZnO), and combinations thereof. In certain embodiments, the first reflective layer 24 may include multiple alternating layers of different dielectric materials, for example, alternating layers of SiO2 and SiN arranged symmetrically or asymmetrically. Some group III nitride materials, such as GaN, can have a refractive index of about 2.4, SiO2 can have a refractive index of about 1.48, and SiN can have a refractive index of about 1.9. In embodiments comprising an active LED structure 12 comprising GaN and a first reflective layer 24 comprising SiO2, a sufficient refractive index difference can be formed between the two to enable efficient TIR of light. The first reflective layer 24 may have different thicknesses depending on the type of material used, and in some embodiments, it has a thickness of at least 0.2 microns (μm). In some embodiments, the first reflective layer 24 may have a thickness in the range of 0.2 μm to 0.7 μm, and in some embodiments, the thickness may be about 0.5 μm.

[0032]

[0039] The LED chip 10 may further include a second reflective layer 28 positioned on the first reflective layer 24 such that the first reflective layer 24 is positioned between the active LED structure 12 and the second reflective layer 28. The second reflective layer 28 may include a metal layer configured to reflect light from the active LED structure 12 that can pass through the first reflective layer 24. The second reflective layer 28 may comprise many different materials such as Ag, gold (Au), Al, nickel (Ni), titanium (Ti), or combinations thereof. The second reflective layer 28 may have different thicknesses depending on the type of material used, and in some embodiments, it may have a thickness of at least 0.1 μm, or in a range including 0.1 μm to 0.7 μm, or in a range including 0.1 μm to 0.5 μm, or in a range including 0.1 μm to 0.3 μm. As illustrated, the second reflective layer 28 may include or form one or more reflective layer interconnects 30 that provide a conductive path through the first reflective layer 24. In this manner, one or more reflective layer interconnects 30 may extend across the entire thickness of the first reflective layer 24. In certain embodiments, the second reflective layer 28 is a metallic reflective layer, and the reflective layer interconnect 30 comprises reflective layer metallic vias. Thus, the first reflective layer 24, the second reflective layer 28, and the reflective layer interconnect 30 form a reflective structure for the LED chip 10 on the p-type layer 16. Thus, the reflective structure may comprise a dielectric reflective layer and a metallic reflective layer, as disclosed herein. In certain embodiments, the reflective layer interconnect 30 comprises the same material as the second reflective layer 28 and is formed simultaneously with the second reflective layer 28. In other embodiments, the reflective layer interconnect 30 may comprise a different material from the second reflective layer 28. Certain embodiments may also include adhesive layers 32 located at one or more interfaces between the first reflective layer 24 and the second reflective layer 28, and / or at the interface between the first reflective layer 24 and the current diffusion layer 26, which facilitate improved adhesion between them. The adhesive layer 32 contains titanium oxide (TiO, TiO2), titanium oxynitride (TiON, Ti x O y N), tantalum oxide (TaO, Ta2O5), tantalum oxynitride (TaON), aluminum oxide (AlO, Al x O yMany different materials can be used, such as ), or combinations thereof, but preferred materials are TiON, AlO, or Al x O y In certain embodiments, the adhesive layer is Al x O y It has the following characteristics: 1 ≤ x ≤ 4, 1 ≤ y ≤ 6. In a particular embodiment, the adhesive layer is Al at x=2, y=3. x O y , i.e., comprising Al2O3. The adhesive layer 32 can be deposited by electron beam deposition, which can provide a smooth, dense, continuous layer with no significant changes in surface morphology. The adhesive layer 32 can be deposited by sputtering, chemical vapor deposition, or plasma-enhanced chemical vapor deposition.

[0033]

[0040] The LED chip 10 may have a barrier layer 34 on the second reflective layer 28 to prevent the material of the second reflective layer 28, such as Ag, from migrating to other layers. By preventing this migration, the LED chip 10 can maintain efficient operation throughout its lifespan. The barrier layer 34 may comprise a conductive material, along with suitable materials including, but not limited to, Ti, Pt, Ni, Au, tungsten (W), and combinations or alloys thereof. In certain embodiments, the barrier layer 34 is positioned to extend laterally beyond a portion of the active LED structure 12 or beyond the peripheral boundary of the active LED structure 12 in order to provide an electrical connection to the p-contact 36. In this regard, the electrical path between the p-contact 36 and the p-type layer 16 may include the barrier layer 34, the second reflective layer 28, and the reflective layer interconnect 30. In other embodiments, the polarity may be reversed, the p-contact 36 may be replaced with an n-contact electrically coupled to the n-type layer 18, and the electrical connection to the p-type layer 16 may be made via a carrier submount 14. The passivation layer 38 is located on the barrier layer 34 and in any portion of the second reflective layer 28 that may not be covered by the barrier layer 34. The passivation layer 38 protects the LED chip 10, provides electrical insulation for the LED chip 10, and can comprise many different materials, including but not limited to dielectric materials containing silicon nitride. In certain embodiments, the passivation layer 38 is a single layer, while in other embodiments, the passivation layer 38 comprises multiple layers. In certain embodiments, the passivation layer 38 may also comprise an additional light-reflecting layer, as well as having one or more metal-containing intermediate layers positioned or embedded which can act as a crack stop layer against cracks that may propagate through the passivation layer 38.

[0034]

[0041] In Figure 1, the active LED structure 12 forms a first opening 40 or recess extending across a p-type layer 16, an active layer 20, and a portion of the n-type layer 18. The first opening 40 may be formed by a subtractive material process, such as etching, applied to the active LED structure 12 before bonding with the carrier submount 14. Hereinafter, the first opening 40 may also be referred to as the active LED structure opening. As illustrated, portions of the first reflective layer 24 and the adhesive layer 32 are arranged to cover the sidewalls of the p-type layer 16, the active layer 20, and the n-type layer 18 within the first opening 40. The passivation layer 38 extends along the first reflective layer 24 in the first opening 40 and is located on the surface of the n-type layer 18. The LED chip 10 further includes an n-contact metal layer 42 located across the LED chip 10 on the passivation layer 38. In the first opening 40, the n-contact metal layer 42 extends into the first opening 40 to form an n-contact interconnect 44, which may also be referred to as an n-contact via. In this way, the first opening 40 can be defined as a location where the n-contact metal layer 42, the n-contact interconnect 44, the passivation layer 38, and a portion of the first reflective layer 24 extend into the active LED structure 12. Thus, the n-contact metal layer 42 and the n-contact interconnect 44 can be formed integrally and can provide an electrical connection to the n-type layer 18 through the first opening 40. In other embodiments, the n-contact metal layer 42 and the n-contact interconnect 44 can be formed separately and may comprise the same or different materials. In certain embodiments, the n-contact metal layer 42 and the n-contact interconnect 44 comprise a single or multiple layers comprising a conductive metal such as one or more of Al, Ti, and their alloys.

[0035]

[0042] As illustrated, the p-contact 36 may be formed on the barrier layer 34, and one or more upper passivation layers 46-1, 46-2 may be provided on one or more top or side surfaces of the n-type layer 18 for additional electrical insulation. In Figure 1, the upper passivation layer 46-2 is positioned to cover the mesa sidewall 12' of the active LED structure 12. The upper passivation layers 46-1, 46-2 may comprise separate layers of continuous layers of a dielectric material such as silicon nitride. During the fabrication of the mesa of the active LED structure 12, an etching process is applied from the n-type layer 18 to the active LED structure 12. The etching process effectively forms the mesa sidewall 12' having an inclined surface along the periphery of the active LED structure 12.

[0036]

[0043] Figure 2 is a cross-sectional view of an LED chip 11, similar to the LED chip 10 in Figure 1, further including a metal layer 48 that dims the light emitted by the LED chip 11 according to one or more embodiments of the present disclosure.

[0037]

[0044] In Figure 1, the LED chip 10 has its upper passivation layers 46-1 and 46-2 etched away, exposing the n-type layer 18. The n-type layer is then textured to improve light extraction from the top surface 18'. However, in the embodiment of Figure 2, the LED chip 11 does not have its passivation layers 46-1 and 46-2 etched away; instead, an additional metal layer 48 is deposited on top of the passivation layer 46-2. Without textured surface, the light emitted by the LED chip 11 is reduced to a first stage, and then the light emitted by the LED chip 11, more specifically the light emitted by the active LED structure 12, can be further reduced by the metal layer 48, which can be semi-transparent or partially opaque. The metal layer 48 may be positioned to reduce the amount of light generated by the active LED structure 12 and escaping from the LED chip 11 by absorbing and / or internally reflecting some of the light from the active LED structure 12. The metal layer 48 can also cover the mesa sidewall 12'. In some embodiments, the metal layer 48 may have a variable thickness, such as a first thickness on top of the active LED structure 12 and a second thickness on the mesa sidewall 12'. The thickness of the metal layer 48 on the active LED structure 12 and the mesa sidewall 12' can be selected based on a desired light emission pattern or to adjust the overall dimming level of the metal layer 48. In other embodiments, the metal layer 48 may have a uniform thickness.

[0038]

[0045] In this embodiment, the metal layer 48 is at least one of titanium or platinum, which are metals that adhere well to the passivation layer 46-2 and have the ability to withstand gold etching solutions. The thickness of the metal layer 48 can be adjusted based on the desired light emission from the LED chip 11. A thicker metal layer 48 reduces, or dims, the light emitted from the LED chip 11 more than a thinner metal layer 48.

[0039]

[0046] In this embodiment, the metal layer 48 can be deposited on the passivation layer 46-2 by sputter deposition or other forms of physical vapor deposition such as cathode arc deposition, electron beam physical vapor deposition, evaporation deposition, close-space sublimation, pulsed laser deposition, or pulsed electron deposition. If the deposition rate is known, the thickness of the metal layer 48 can be determined by the duration of the deposition process.

[0040]

[0047] In this embodiment, the metal layer 48 is electrically insulated from or not electrically coupled to the active LED structure 12 by passivation layers 46-1 and 46-2, which are dielectric materials (e.g., silicon nitride).

[0041]

[0048] In the embodiment, the metal layer 48 can be patterned via a photomask so that it is not present in the street and pad areas of the LED chip 11. By keeping the metal layer 48 out of the street and pad areas of the LED chip 11, the metal layer 48 can be electrically isolated from the active LED structure 12 and from other components of the LED chip 11. The metal layer 48 can also be patterned and have a thickness that is variable across the top of the LED chip 11 in order to have adjustable brightness, adjustable light emission pattern, and / or adjustable emitter shape. In the embodiment, the metal layer 48 is deposited on a photoresist layer and the patterned metal layer 48 is formed after a photomask is applied.

[0042]

[0049] In the embodiment, the metal layer 48 may have an outer layer 50 coated on the metal layer to cover and protect the metal layer 48. In the embodiment, the outer layer 50 may be a neutral dielectric material such as SiN, SiO2, or Al2O3, or another suitable passivation material.

[0043]

[0050] As illustrated, the outer layer 50 may cover the metal layer 48 along the sidewall 12' and extend laterally beyond the metal layer 48 in order to electrically isolate the p-contact 36 from the metal layer 48. Thus, the metal layer 48 may be effectively embedded or surrounded by the dielectric material of the passivation layers 46-1, 46-2 and the outer layer 50, and as a result, the metal layer 48 is electrically isolated from the active LED structure 12. By covering the metal layer 48 with the outer layer 50, the metal layer 48 can be electrically and environmentally isolated from any additional layers that may be added to the LED chip 11 and / or from the environment surrounding the LED chip 11.

[0044]

[0051] Next, as shown in Figure 3, another embodiment of the LED chip 11 is illustrated in which the thickness of the metal layer 48 on the mesa sidewall 12' can differ from the thickness of the metal layer 48 on the upper surface of the active LED structure 12. For example, as shown in Figure 3, the metal layer 48 on the upper surface of the LED chip 11 is thicker than the metal layer 48 on the mesa sidewall 12'. In addition, in the embodiment illustrated in Figure 3, the metal layer 48 may have openings 49 to which a photomask is applied to create a pattern. The upper layer 50 can fill the openings 49 where the metal layer 48 is not present.

[0045]

[0052] Next, as shown in Figures 4A and 4B, top views of an LED chip (e.g., LED chip 11) without a metal layer (Figure 4A) and with a metal layer 48 (Figure 4B) are illustrated according to one or more embodiments of the present disclosure. In the embodiments, as shown in Figure 4B, the metal layer 48 can be patterned to include an opening 52 to prevent the metal layer 48 from covering the top pad or street area of ​​the LED chip 11.

[0046]

[0053] Next, as shown in Figure 5, a flowchart illustrating a method 500 for manufacturing an LED chip 11 having a metal layer 48 according to one or more embodiments of the present disclosure is provided.

[0047]

[0054] Method 500 can be started in step 502, where the method comprises forming an active LED structure 12 on a carrier submount 14, the active LED structure 12 comprising an n-type layer 18, a p-type layer 16, and an active layer 20 between the n-type layer 18 and the p-type layer 16, and the active LED structure 12 forms a mesa with mesa sidewalls 12' defining the periphery of the active LED structure 12.

[0048]

[0055] In step 504, the method may include depositing a passivation layer 46 on the active LED structure 12. In embodiments, the passivation layer 46 may be a dielectric such as silicon nitride.

[0049]

[0056] In step 506, the method may include depositing a partially transparent metal layer 48 on a passivation layer 46-2 with respect to the wavelength of light generated by the active LED structure 12, wherein the metal layer 48 is electrically isolated from the active LED structure 12 and attenuates the light emitted by the active LED structure 12. In embodiments, the metal layer 48 may be deposited by sputter deposition, and the length of time for depositing the metal layer 48 controls the thickness of the metal layer 48 and, consequently, the amount of attenuation provided by the metal layer 48. In other embodiments, other deposition techniques such as chemical vapor deposition or plasma-enhanced chemical vapor deposition are also possible. The metal layer 48 may also be deposited in a predetermined pattern or on a photoresist layer, and when a photomask is applied, a patterned metal layer 48 is formed.

[0050]

[0057] As shown in Figure 6, an example graph is provided illustrating experimental results showing light transmittance as a function of the thickness of the metal layer, according to one or more embodiments of the present disclosure.

[0051]

[0058] Graph 600 shows experimental result 602 illustrating the transmission percentage as a function of the thickness of the metal layer 48. In this example, the metal layer 48 is titanium, and it emits light at 451 nm. The thickness is in angstroms. The table on which Graph 600 is based is given in Table 1 below.

[0052] [Table 1]

[0053]

[0059] Any of the embodiments described herein, and / or any of the various individual embodiments and features described herein, may be combined for further advantages. Any of the various embodiments disclosed herein may be combined with one or more other disclosed embodiments unless otherwise indicated herein.

[0054]

[0060] Those skilled in the art will recognize improvements and modifications to preferred embodiments of this disclosure. All such improvements and modifications are considered to fall within the scope of the concepts and appended claims disclosed herein.

Claims

1. Light-emitting diode (LED) chip, An active LED structure comprising an n-type layer, a p-type layer, and an active layer between the n-type layer and the p-type layer, wherein the active LED structure forms a mesa having a mesa sidewall that defines the periphery of the active LED structure, A metal layer that is partially transparent to the wavelength of light generated by the aforementioned active LED structure, A passivation layer is located between the metal layer and the active LED structure, thereby electrically isolating the metal layer from the active LED structure. An LED chip comprising, wherein the first thickness of the metal layer on the upper part of the active LED structure is different from the second thickness of the metal layer on the mesa sidewall of the active LED structure.

2. The LED chip according to claim 1, wherein the mesa sidewall is covered by the passivation layer and the metal layer.

3. The LED chip according to claim 1, wherein the metal layer is configured to reduce the light emitted by the active LED structure.

4. The LED chip according to claim 3, wherein the amount of light attenuated by the metal layer corresponds to the thickness of the metal layer.

5. The LED chip according to claim 1, wherein the metal layer is at least one of titanium or platinum.

6. The LED chip according to claim 1, wherein the metal layer is sputter-deposited on the passivation layer.

7. The LED chip according to claim 1, wherein the metal layer is patterned in a predetermined pattern.

8. Light-emitting diode (LED) chip, Carrier submount and An active LED structure bonded to the carrier submount, comprising an n-type layer, a p-type layer, and an active layer disposed between the n-type layer and the p-type layer, forming a mesa with a mesa sidewall defining the periphery of the active LED structure, A metal layer that is partially transparent to the wavelength of light generated by the aforementioned active LED structure, A dielectric layer between the metal layer and the active LED structure, wherein the metal layer is electrically isolated from the active LED structure. An LED chip comprising, wherein the first thickness of the metal layer on the upper part of the active LED structure is different from the second thickness of the metal layer on the mesa sidewall of the active LED structure.

9. The LED chip according to claim 8, wherein the mesa sidewall is covered by the dielectric layer and the metal layer.

10. The LED chip according to claim 8, wherein the metal layer is configured to reduce the light emitted by the active LED structure.

11. The LED chip according to claim 10, wherein the amount of light attenuated by the metal layer corresponds to the thickness of the metal layer.

12. The LED chip according to claim 8, wherein the metal layer is at least one of titanium or platinum.

13. The LED chip according to claim 8, wherein the metal layer is sputter-deposited on the dielectric layer.

14. The LED chip according to claim 8, wherein the metal layer is patterned in a predetermined pattern.

15. The LED chip according to claim 8, wherein the dielectric layer is silicon nitride.

16. A method for manufacturing light-emitting diode (LED) chips, A step of forming an active LED structure on a carrier submount, wherein the active LED structure comprises an n-type layer, a p-type layer, and an active layer between the n-type layer and the p-type layer, and the active LED structure forms a mesa having a mesa sidewall defining the periphery of the active LED structure. The steps include depositing a passivation layer on the aforementioned active LED structure, A step of depositing a metal layer on a passivation layer that is partially transparent to the wavelength of light generated by the active LED structure, wherein the metal layer is electrically isolated from the active LED structure and is configured to reduce the light emitted by the active LED structure. A method comprising the above, wherein the first thickness of the metal layer on the upper part of the active LED structure is different from the second thickness of the metal layer on the mesa sidewall of the active LED structure.

17. The method according to claim 16, further comprising the step of depositing the metal layer to a predetermined thickness based on a predetermined light-reducing level.

18. The method according to claim 16, further comprising the step of depositing the metal layer in a predetermined pattern corresponding to the radiation pattern.

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